1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include "drm_crtc_helper.h"
40 static int i915_modeset __read_mostly
= -1;
41 module_param_named(modeset
, i915_modeset
, int, 0400);
42 MODULE_PARM_DESC(modeset
,
43 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
44 "1=on, -1=force vga console preference [default])");
46 unsigned int i915_fbpercrtc __always_unused
= 0;
47 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
49 int i915_panel_ignore_lid __read_mostly
= 0;
50 module_param_named(panel_ignore_lid
, i915_panel_ignore_lid
, int, 0600);
51 MODULE_PARM_DESC(panel_ignore_lid
,
52 "Override lid status (0=autodetect [default], 1=lid open, "
55 unsigned int i915_powersave __read_mostly
= 1;
56 module_param_named(powersave
, i915_powersave
, int, 0600);
57 MODULE_PARM_DESC(powersave
,
58 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60 unsigned int i915_semaphores __read_mostly
= 0;
61 module_param_named(semaphores
, i915_semaphores
, int, 0600);
62 MODULE_PARM_DESC(semaphores
,
63 "Use semaphores for inter-ring sync (default: false)");
65 unsigned int i915_enable_rc6 __read_mostly
= 0;
66 module_param_named(i915_enable_rc6
, i915_enable_rc6
, int, 0600);
67 MODULE_PARM_DESC(i915_enable_rc6
,
68 "Enable power-saving render C-state 6 (default: true)");
70 unsigned int i915_enable_fbc __read_mostly
= -1;
71 module_param_named(i915_enable_fbc
, i915_enable_fbc
, int, 0600);
72 MODULE_PARM_DESC(i915_enable_fbc
,
73 "Enable frame buffer compression for power savings "
74 "(default: -1 (use per-chip default))");
76 unsigned int i915_lvds_downclock __read_mostly
= 0;
77 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
78 MODULE_PARM_DESC(lvds_downclock
,
79 "Use panel (LVDS/eDP) downclocking for power savings "
82 unsigned int i915_panel_use_ssc __read_mostly
= 1;
83 module_param_named(lvds_use_ssc
, i915_panel_use_ssc
, int, 0600);
84 MODULE_PARM_DESC(lvds_use_ssc
,
85 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
88 int i915_vbt_sdvo_panel_type __read_mostly
= -1;
89 module_param_named(vbt_sdvo_panel_type
, i915_vbt_sdvo_panel_type
, int, 0600);
90 MODULE_PARM_DESC(vbt_sdvo_panel_type
,
91 "Override selection of SDVO panel mode in the VBT "
94 static bool i915_try_reset __read_mostly
= true;
95 module_param_named(reset
, i915_try_reset
, bool, 0600);
96 MODULE_PARM_DESC(reset
, "Attempt GPU resets (default: true)");
98 bool i915_enable_hangcheck __read_mostly
= true;
99 module_param_named(enable_hangcheck
, i915_enable_hangcheck
, bool, 0644);
100 MODULE_PARM_DESC(enable_hangcheck
,
101 "Periodically check GPU activity for detecting hangs. "
102 "WARNING: Disabling this can cause system wide hangs. "
105 static struct drm_driver driver
;
106 extern int intel_agp_enabled
;
108 #define INTEL_VGA_DEVICE(id, info) { \
109 .class = PCI_CLASS_DISPLAY_VGA << 8, \
110 .class_mask = 0xff0000, \
113 .subvendor = PCI_ANY_ID, \
114 .subdevice = PCI_ANY_ID, \
115 .driver_data = (unsigned long) info }
117 static const struct intel_device_info intel_i830_info
= {
118 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1,
119 .has_overlay
= 1, .overlay_needs_physical
= 1,
122 static const struct intel_device_info intel_845g_info
= {
124 .has_overlay
= 1, .overlay_needs_physical
= 1,
127 static const struct intel_device_info intel_i85x_info
= {
128 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1,
129 .cursor_needs_physical
= 1,
130 .has_overlay
= 1, .overlay_needs_physical
= 1,
133 static const struct intel_device_info intel_i865g_info
= {
135 .has_overlay
= 1, .overlay_needs_physical
= 1,
138 static const struct intel_device_info intel_i915g_info
= {
139 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1,
140 .has_overlay
= 1, .overlay_needs_physical
= 1,
142 static const struct intel_device_info intel_i915gm_info
= {
143 .gen
= 3, .is_mobile
= 1,
144 .cursor_needs_physical
= 1,
145 .has_overlay
= 1, .overlay_needs_physical
= 1,
148 static const struct intel_device_info intel_i945g_info
= {
149 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1,
150 .has_overlay
= 1, .overlay_needs_physical
= 1,
152 static const struct intel_device_info intel_i945gm_info
= {
153 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1,
154 .has_hotplug
= 1, .cursor_needs_physical
= 1,
155 .has_overlay
= 1, .overlay_needs_physical
= 1,
159 static const struct intel_device_info intel_i965g_info
= {
160 .gen
= 4, .is_broadwater
= 1,
165 static const struct intel_device_info intel_i965gm_info
= {
166 .gen
= 4, .is_crestline
= 1,
167 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
172 static const struct intel_device_info intel_g33_info
= {
173 .gen
= 3, .is_g33
= 1,
174 .need_gfx_hws
= 1, .has_hotplug
= 1,
178 static const struct intel_device_info intel_g45_info
= {
179 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1,
180 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
184 static const struct intel_device_info intel_gm45_info
= {
185 .gen
= 4, .is_g4x
= 1,
186 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
187 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
192 static const struct intel_device_info intel_pineview_info
= {
193 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1,
194 .need_gfx_hws
= 1, .has_hotplug
= 1,
198 static const struct intel_device_info intel_ironlake_d_info
= {
200 .need_gfx_hws
= 1, .has_pipe_cxsr
= 1, .has_hotplug
= 1,
204 static const struct intel_device_info intel_ironlake_m_info
= {
205 .gen
= 5, .is_mobile
= 1,
206 .need_gfx_hws
= 1, .has_hotplug
= 1,
211 static const struct intel_device_info intel_sandybridge_d_info
= {
213 .need_gfx_hws
= 1, .has_hotplug
= 1,
218 static const struct intel_device_info intel_sandybridge_m_info
= {
219 .gen
= 6, .is_mobile
= 1,
220 .need_gfx_hws
= 1, .has_hotplug
= 1,
226 static const struct intel_device_info intel_ivybridge_d_info
= {
227 .is_ivybridge
= 1, .gen
= 7,
228 .need_gfx_hws
= 1, .has_hotplug
= 1,
233 static const struct intel_device_info intel_ivybridge_m_info
= {
234 .is_ivybridge
= 1, .gen
= 7, .is_mobile
= 1,
235 .need_gfx_hws
= 1, .has_hotplug
= 1,
236 .has_fbc
= 0, /* FBC is not enabled on Ivybridge mobile yet */
241 static const struct pci_device_id pciidlist
[] = { /* aka */
242 INTEL_VGA_DEVICE(0x3577, &intel_i830_info
), /* I830_M */
243 INTEL_VGA_DEVICE(0x2562, &intel_845g_info
), /* 845_G */
244 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info
), /* I855_GM */
245 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info
),
246 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info
), /* I865_G */
247 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info
), /* I915_G */
248 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info
), /* E7221_G */
249 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info
), /* I915_GM */
250 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info
), /* I945_G */
251 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info
), /* I945_GM */
252 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info
), /* I945_GME */
253 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info
), /* I946_GZ */
254 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info
), /* G35_G */
255 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info
), /* I965_Q */
256 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info
), /* I965_G */
257 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info
), /* Q35_G */
258 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info
), /* G33_G */
259 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info
), /* Q33_G */
260 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info
), /* I965_GM */
261 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info
), /* I965_GME */
262 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info
), /* GM45_G */
263 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info
), /* IGD_E_G */
264 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info
), /* Q45_G */
265 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info
), /* G45_G */
266 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info
), /* G41_G */
267 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info
), /* B43_G */
268 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info
), /* B43_G.1 */
269 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info
),
270 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info
),
271 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info
),
272 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info
),
273 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info
),
274 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info
),
275 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info
),
276 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info
),
277 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info
),
278 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info
),
279 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info
),
280 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info
), /* GT1 mobile */
281 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info
), /* GT2 mobile */
282 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info
), /* GT1 desktop */
283 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info
), /* GT2 desktop */
284 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info
), /* GT1 server */
288 #if defined(CONFIG_DRM_I915_KMS)
289 MODULE_DEVICE_TABLE(pci
, pciidlist
);
292 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
293 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
294 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
295 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
297 void intel_detect_pch (struct drm_device
*dev
)
299 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
303 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
304 * make graphics device passthrough work easy for VMM, that only
305 * need to expose ISA bridge to let driver know the real hardware
306 * underneath. This is a requirement from virtualization team.
308 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
310 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
312 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
314 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
315 dev_priv
->pch_type
= PCH_IBX
;
316 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
317 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
318 dev_priv
->pch_type
= PCH_CPT
;
319 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
320 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
321 /* PantherPoint is CPT compatible */
322 dev_priv
->pch_type
= PCH_CPT
;
323 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
330 static void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
335 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1))
338 I915_WRITE_NOTRACE(FORCEWAKE
, 1);
339 POSTING_READ(FORCEWAKE
);
342 while (count
++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK
) & 1) == 0)
347 * Generally this is called implicitly by the register read function. However,
348 * if some sequence requires the GT to not power down then this function should
349 * be called at the beginning of the sequence followed by a call to
350 * gen6_gt_force_wake_put() at the end of the sequence.
352 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
)
354 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
356 /* Forcewake is atomic in case we get in here without the lock */
357 if (atomic_add_return(1, &dev_priv
->forcewake_count
) == 1)
358 __gen6_gt_force_wake_get(dev_priv
);
361 static void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
363 I915_WRITE_NOTRACE(FORCEWAKE
, 0);
364 POSTING_READ(FORCEWAKE
);
368 * see gen6_gt_force_wake_get()
370 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
)
372 WARN_ON(!mutex_is_locked(&dev_priv
->dev
->struct_mutex
));
374 if (atomic_dec_and_test(&dev_priv
->forcewake_count
))
375 __gen6_gt_force_wake_put(dev_priv
);
378 void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
)
380 if (dev_priv
->gt_fifo_count
< GT_FIFO_NUM_RESERVED_ENTRIES
) {
382 u32 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
383 while (fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
&& loop
--) {
385 fifo
= I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES
);
387 WARN_ON(loop
< 0 && fifo
<= GT_FIFO_NUM_RESERVED_ENTRIES
);
388 dev_priv
->gt_fifo_count
= fifo
;
390 dev_priv
->gt_fifo_count
--;
393 static int i915_drm_freeze(struct drm_device
*dev
)
395 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
397 drm_kms_helper_poll_disable(dev
);
399 pci_save_state(dev
->pdev
);
401 /* If KMS is active, we do the leavevt stuff here */
402 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
403 int error
= i915_gem_idle(dev
);
405 dev_err(&dev
->pdev
->dev
,
406 "GEM idle failed, resume might fail\n");
409 drm_irq_uninstall(dev
);
412 i915_save_state(dev
);
414 intel_opregion_fini(dev
);
416 /* Modeset on resume, not lid events */
417 dev_priv
->modeset_on_lid
= 0;
422 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
426 if (!dev
|| !dev
->dev_private
) {
427 DRM_ERROR("dev: %p\n", dev
);
428 DRM_ERROR("DRM not initialized, aborting suspend.\n");
432 if (state
.event
== PM_EVENT_PRETHAW
)
436 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
439 error
= i915_drm_freeze(dev
);
443 if (state
.event
== PM_EVENT_SUSPEND
) {
444 /* Shut down the device */
445 pci_disable_device(dev
->pdev
);
446 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
452 static int i915_drm_thaw(struct drm_device
*dev
)
454 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
457 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
458 mutex_lock(&dev
->struct_mutex
);
459 i915_gem_restore_gtt_mappings(dev
);
460 mutex_unlock(&dev
->struct_mutex
);
463 i915_restore_state(dev
);
464 intel_opregion_setup(dev
);
466 /* KMS EnterVT equivalent */
467 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
468 mutex_lock(&dev
->struct_mutex
);
469 dev_priv
->mm
.suspended
= 0;
471 error
= i915_gem_init_ringbuffer(dev
);
472 mutex_unlock(&dev
->struct_mutex
);
474 drm_mode_config_reset(dev
);
475 drm_irq_install(dev
);
477 /* Resume the modeset for every activated CRTC */
478 drm_helper_resume_force_mode(dev
);
480 if (IS_IRONLAKE_M(dev
))
481 ironlake_enable_rc6(dev
);
484 intel_opregion_init(dev
);
486 dev_priv
->modeset_on_lid
= 0;
491 int i915_resume(struct drm_device
*dev
)
495 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
498 if (pci_enable_device(dev
->pdev
))
501 pci_set_master(dev
->pdev
);
503 ret
= i915_drm_thaw(dev
);
507 drm_kms_helper_poll_enable(dev
);
511 static int i8xx_do_reset(struct drm_device
*dev
, u8 flags
)
513 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
518 I915_WRITE(D_STATE
, I915_READ(D_STATE
) | DSTATE_GFX_RESET_I830
);
519 POSTING_READ(D_STATE
);
521 if (IS_I830(dev
) || IS_845G(dev
)) {
522 I915_WRITE(DEBUG_RESET_I830
,
523 DEBUG_RESET_DISPLAY
|
526 POSTING_READ(DEBUG_RESET_I830
);
529 I915_WRITE(DEBUG_RESET_I830
, 0);
530 POSTING_READ(DEBUG_RESET_I830
);
535 I915_WRITE(D_STATE
, I915_READ(D_STATE
) & ~DSTATE_GFX_RESET_I830
);
536 POSTING_READ(D_STATE
);
541 static int i965_reset_complete(struct drm_device
*dev
)
544 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
548 static int i965_do_reset(struct drm_device
*dev
, u8 flags
)
553 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
554 * well as the reset bit (GR/bit 0). Setting the GR bit
555 * triggers the reset; when done, the hardware will clear it.
557 pci_read_config_byte(dev
->pdev
, I965_GDRST
, &gdrst
);
558 pci_write_config_byte(dev
->pdev
, I965_GDRST
, gdrst
| flags
| 0x1);
560 return wait_for(i965_reset_complete(dev
), 500);
563 static int ironlake_do_reset(struct drm_device
*dev
, u8 flags
)
565 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
566 u32 gdrst
= I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
);
567 I915_WRITE(MCHBAR_MIRROR_BASE
+ ILK_GDSR
, gdrst
| flags
| 0x1);
568 return wait_for(I915_READ(MCHBAR_MIRROR_BASE
+ ILK_GDSR
) & 0x1, 500);
571 static int gen6_do_reset(struct drm_device
*dev
, u8 flags
)
573 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
575 I915_WRITE(GEN6_GDRST
, GEN6_GRDOM_FULL
);
576 return wait_for((I915_READ(GEN6_GDRST
) & GEN6_GRDOM_FULL
) == 0, 500);
580 * i965_reset - reset chip after a hang
581 * @dev: drm device to reset
582 * @flags: reset domains
584 * Reset the chip. Useful if a hang is detected. Returns zero on successful
585 * reset or otherwise an error code.
587 * Procedure is fairly simple:
588 * - reset the chip using the reset reg
589 * - re-init context state
590 * - re-init hardware status page
591 * - re-init ring buffer
592 * - re-init interrupt state
595 int i915_reset(struct drm_device
*dev
, u8 flags
)
597 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
599 * We really should only reset the display subsystem if we actually
602 bool need_display
= true;
608 if (!mutex_trylock(&dev
->struct_mutex
))
614 if (get_seconds() - dev_priv
->last_gpu_reset
< 5) {
615 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
616 } else switch (INTEL_INFO(dev
)->gen
) {
619 ret
= gen6_do_reset(dev
, flags
);
620 /* If reset with a user forcewake, try to restore */
621 if (atomic_read(&dev_priv
->forcewake_count
))
622 __gen6_gt_force_wake_get(dev_priv
);
625 ret
= ironlake_do_reset(dev
, flags
);
628 ret
= i965_do_reset(dev
, flags
);
631 ret
= i8xx_do_reset(dev
, flags
);
634 dev_priv
->last_gpu_reset
= get_seconds();
636 DRM_ERROR("Failed to reset chip.\n");
637 mutex_unlock(&dev
->struct_mutex
);
641 /* Ok, now get things going again... */
644 * Everything depends on having the GTT running, so we need to start
645 * there. Fortunately we don't need to do this unless we reset the
646 * chip at a PCI level.
648 * Next we need to restore the context, but we don't use those
651 * Ring buffer needs to be re-initialized in the KMS case, or if X
652 * was running at the time of the reset (i.e. we weren't VT
655 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
656 !dev_priv
->mm
.suspended
) {
657 dev_priv
->mm
.suspended
= 0;
659 dev_priv
->ring
[RCS
].init(&dev_priv
->ring
[RCS
]);
661 dev_priv
->ring
[VCS
].init(&dev_priv
->ring
[VCS
]);
663 dev_priv
->ring
[BCS
].init(&dev_priv
->ring
[BCS
]);
665 mutex_unlock(&dev
->struct_mutex
);
666 drm_irq_uninstall(dev
);
667 drm_mode_config_reset(dev
);
668 drm_irq_install(dev
);
669 mutex_lock(&dev
->struct_mutex
);
672 mutex_unlock(&dev
->struct_mutex
);
675 * Perform a full modeset as on later generations, e.g. Ironlake, we may
676 * need to retrain the display link and cannot just restore the register
680 mutex_lock(&dev
->mode_config
.mutex
);
681 drm_helper_resume_force_mode(dev
);
682 mutex_unlock(&dev
->mode_config
.mutex
);
690 i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
692 /* Only bind to function 0 of the device. Early generations
693 * used function 1 as a placeholder for multi-head. This causes
694 * us confusion instead, especially on the systems where both
695 * functions have the same PCI-ID!
697 if (PCI_FUNC(pdev
->devfn
))
700 return drm_get_pci_dev(pdev
, ent
, &driver
);
704 i915_pci_remove(struct pci_dev
*pdev
)
706 struct drm_device
*dev
= pci_get_drvdata(pdev
);
711 static int i915_pm_suspend(struct device
*dev
)
713 struct pci_dev
*pdev
= to_pci_dev(dev
);
714 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
717 if (!drm_dev
|| !drm_dev
->dev_private
) {
718 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
722 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
725 error
= i915_drm_freeze(drm_dev
);
729 pci_disable_device(pdev
);
730 pci_set_power_state(pdev
, PCI_D3hot
);
735 static int i915_pm_resume(struct device
*dev
)
737 struct pci_dev
*pdev
= to_pci_dev(dev
);
738 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
740 return i915_resume(drm_dev
);
743 static int i915_pm_freeze(struct device
*dev
)
745 struct pci_dev
*pdev
= to_pci_dev(dev
);
746 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
748 if (!drm_dev
|| !drm_dev
->dev_private
) {
749 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
753 return i915_drm_freeze(drm_dev
);
756 static int i915_pm_thaw(struct device
*dev
)
758 struct pci_dev
*pdev
= to_pci_dev(dev
);
759 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
761 return i915_drm_thaw(drm_dev
);
764 static int i915_pm_poweroff(struct device
*dev
)
766 struct pci_dev
*pdev
= to_pci_dev(dev
);
767 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
769 return i915_drm_freeze(drm_dev
);
772 static const struct dev_pm_ops i915_pm_ops
= {
773 .suspend
= i915_pm_suspend
,
774 .resume
= i915_pm_resume
,
775 .freeze
= i915_pm_freeze
,
776 .thaw
= i915_pm_thaw
,
777 .poweroff
= i915_pm_poweroff
,
778 .restore
= i915_pm_resume
,
781 static struct vm_operations_struct i915_gem_vm_ops
= {
782 .fault
= i915_gem_fault
,
783 .open
= drm_gem_vm_open
,
784 .close
= drm_gem_vm_close
,
787 static struct drm_driver driver
= {
788 /* don't use mtrr's here, the Xserver or user space app should
789 * deal with them for intel hardware.
792 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
793 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
,
794 .load
= i915_driver_load
,
795 .unload
= i915_driver_unload
,
796 .open
= i915_driver_open
,
797 .lastclose
= i915_driver_lastclose
,
798 .preclose
= i915_driver_preclose
,
799 .postclose
= i915_driver_postclose
,
801 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
802 .suspend
= i915_suspend
,
803 .resume
= i915_resume
,
805 .device_is_agp
= i915_driver_device_is_agp
,
806 .reclaim_buffers
= drm_core_reclaim_buffers
,
807 .master_create
= i915_master_create
,
808 .master_destroy
= i915_master_destroy
,
809 #if defined(CONFIG_DEBUG_FS)
810 .debugfs_init
= i915_debugfs_init
,
811 .debugfs_cleanup
= i915_debugfs_cleanup
,
813 .gem_init_object
= i915_gem_init_object
,
814 .gem_free_object
= i915_gem_free_object
,
815 .gem_vm_ops
= &i915_gem_vm_ops
,
816 .dumb_create
= i915_gem_dumb_create
,
817 .dumb_map_offset
= i915_gem_mmap_gtt
,
818 .dumb_destroy
= i915_gem_dumb_destroy
,
819 .ioctls
= i915_ioctls
,
821 .owner
= THIS_MODULE
,
823 .release
= drm_release
,
824 .unlocked_ioctl
= drm_ioctl
,
825 .mmap
= drm_gem_mmap
,
827 .fasync
= drm_fasync
,
830 .compat_ioctl
= i915_compat_ioctl
,
832 .llseek
= noop_llseek
,
838 .major
= DRIVER_MAJOR
,
839 .minor
= DRIVER_MINOR
,
840 .patchlevel
= DRIVER_PATCHLEVEL
,
843 static struct pci_driver i915_pci_driver
= {
845 .id_table
= pciidlist
,
846 .probe
= i915_pci_probe
,
847 .remove
= i915_pci_remove
,
848 .driver
.pm
= &i915_pm_ops
,
851 static int __init
i915_init(void)
853 if (!intel_agp_enabled
) {
854 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
858 driver
.num_ioctls
= i915_max_ioctl
;
861 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
862 * explicitly disabled with the module pararmeter.
864 * Otherwise, just follow the parameter (defaulting to off).
866 * Allow optional vga_text_mode_force boot option to override
867 * the default behavior.
869 #if defined(CONFIG_DRM_I915_KMS)
870 if (i915_modeset
!= 0)
871 driver
.driver_features
|= DRIVER_MODESET
;
873 if (i915_modeset
== 1)
874 driver
.driver_features
|= DRIVER_MODESET
;
876 #ifdef CONFIG_VGA_CONSOLE
877 if (vgacon_text_force() && i915_modeset
== -1)
878 driver
.driver_features
&= ~DRIVER_MODESET
;
881 if (!(driver
.driver_features
& DRIVER_MODESET
))
882 driver
.get_vblank_timestamp
= NULL
;
884 return drm_pci_init(&driver
, &i915_pci_driver
);
887 static void __exit
i915_exit(void)
889 drm_pci_exit(&driver
, &i915_pci_driver
);
892 module_init(i915_init
);
893 module_exit(i915_exit
);
895 MODULE_AUTHOR(DRIVER_AUTHOR
);
896 MODULE_DESCRIPTION(DRIVER_DESC
);
897 MODULE_LICENSE("GPL and additional rights");