1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver
;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
51 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
52 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
54 #define GEN_CHV_PIPEOFFSETS \
55 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
56 CHV_PIPE_C_OFFSET }, \
57 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
58 CHV_TRANSCODER_C_OFFSET, }, \
59 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET, \
60 CHV_DPLL_C_OFFSET }, \
61 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET, \
62 CHV_DPLL_C_MD_OFFSET }, \
63 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
64 CHV_PALETTE_C_OFFSET }
66 #define CURSOR_OFFSETS \
67 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
69 #define IVB_CURSOR_OFFSETS \
70 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
72 static const struct intel_device_info intel_i830_info
= {
73 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
74 .has_overlay
= 1, .overlay_needs_physical
= 1,
75 .ring_mask
= RENDER_RING
,
76 GEN_DEFAULT_PIPEOFFSETS
,
80 static const struct intel_device_info intel_845g_info
= {
81 .gen
= 2, .num_pipes
= 1,
82 .has_overlay
= 1, .overlay_needs_physical
= 1,
83 .ring_mask
= RENDER_RING
,
84 GEN_DEFAULT_PIPEOFFSETS
,
88 static const struct intel_device_info intel_i85x_info
= {
89 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
90 .cursor_needs_physical
= 1,
91 .has_overlay
= 1, .overlay_needs_physical
= 1,
93 .ring_mask
= RENDER_RING
,
94 GEN_DEFAULT_PIPEOFFSETS
,
98 static const struct intel_device_info intel_i865g_info
= {
99 .gen
= 2, .num_pipes
= 1,
100 .has_overlay
= 1, .overlay_needs_physical
= 1,
101 .ring_mask
= RENDER_RING
,
102 GEN_DEFAULT_PIPEOFFSETS
,
106 static const struct intel_device_info intel_i915g_info
= {
107 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
108 .has_overlay
= 1, .overlay_needs_physical
= 1,
109 .ring_mask
= RENDER_RING
,
110 GEN_DEFAULT_PIPEOFFSETS
,
113 static const struct intel_device_info intel_i915gm_info
= {
114 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
115 .cursor_needs_physical
= 1,
116 .has_overlay
= 1, .overlay_needs_physical
= 1,
119 .ring_mask
= RENDER_RING
,
120 GEN_DEFAULT_PIPEOFFSETS
,
123 static const struct intel_device_info intel_i945g_info
= {
124 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
125 .has_overlay
= 1, .overlay_needs_physical
= 1,
126 .ring_mask
= RENDER_RING
,
127 GEN_DEFAULT_PIPEOFFSETS
,
130 static const struct intel_device_info intel_i945gm_info
= {
131 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
132 .has_hotplug
= 1, .cursor_needs_physical
= 1,
133 .has_overlay
= 1, .overlay_needs_physical
= 1,
136 .ring_mask
= RENDER_RING
,
137 GEN_DEFAULT_PIPEOFFSETS
,
141 static const struct intel_device_info intel_i965g_info
= {
142 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
145 .ring_mask
= RENDER_RING
,
146 GEN_DEFAULT_PIPEOFFSETS
,
150 static const struct intel_device_info intel_i965gm_info
= {
151 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
152 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
155 .ring_mask
= RENDER_RING
,
156 GEN_DEFAULT_PIPEOFFSETS
,
160 static const struct intel_device_info intel_g33_info
= {
161 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
162 .need_gfx_hws
= 1, .has_hotplug
= 1,
164 .ring_mask
= RENDER_RING
,
165 GEN_DEFAULT_PIPEOFFSETS
,
169 static const struct intel_device_info intel_g45_info
= {
170 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
171 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
172 .ring_mask
= RENDER_RING
| BSD_RING
,
173 GEN_DEFAULT_PIPEOFFSETS
,
177 static const struct intel_device_info intel_gm45_info
= {
178 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
179 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
180 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
182 .ring_mask
= RENDER_RING
| BSD_RING
,
183 GEN_DEFAULT_PIPEOFFSETS
,
187 static const struct intel_device_info intel_pineview_info
= {
188 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
189 .need_gfx_hws
= 1, .has_hotplug
= 1,
191 GEN_DEFAULT_PIPEOFFSETS
,
195 static const struct intel_device_info intel_ironlake_d_info
= {
196 .gen
= 5, .num_pipes
= 2,
197 .need_gfx_hws
= 1, .has_hotplug
= 1,
198 .ring_mask
= RENDER_RING
| BSD_RING
,
199 GEN_DEFAULT_PIPEOFFSETS
,
203 static const struct intel_device_info intel_ironlake_m_info
= {
204 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
205 .need_gfx_hws
= 1, .has_hotplug
= 1,
207 .ring_mask
= RENDER_RING
| BSD_RING
,
208 GEN_DEFAULT_PIPEOFFSETS
,
212 static const struct intel_device_info intel_sandybridge_d_info
= {
213 .gen
= 6, .num_pipes
= 2,
214 .need_gfx_hws
= 1, .has_hotplug
= 1,
216 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
218 GEN_DEFAULT_PIPEOFFSETS
,
222 static const struct intel_device_info intel_sandybridge_m_info
= {
223 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
224 .need_gfx_hws
= 1, .has_hotplug
= 1,
226 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
228 GEN_DEFAULT_PIPEOFFSETS
,
232 #define GEN7_FEATURES \
233 .gen = 7, .num_pipes = 3, \
234 .need_gfx_hws = 1, .has_hotplug = 1, \
236 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
239 static const struct intel_device_info intel_ivybridge_d_info
= {
242 GEN_DEFAULT_PIPEOFFSETS
,
246 static const struct intel_device_info intel_ivybridge_m_info
= {
250 GEN_DEFAULT_PIPEOFFSETS
,
254 static const struct intel_device_info intel_ivybridge_q_info
= {
257 .num_pipes
= 0, /* legal, last one wins */
258 GEN_DEFAULT_PIPEOFFSETS
,
262 static const struct intel_device_info intel_valleyview_m_info
= {
267 .display_mmio_offset
= VLV_DISPLAY_BASE
,
268 .has_fbc
= 0, /* legal, last one wins */
269 .has_llc
= 0, /* legal, last one wins */
270 GEN_DEFAULT_PIPEOFFSETS
,
274 static const struct intel_device_info intel_valleyview_d_info
= {
278 .display_mmio_offset
= VLV_DISPLAY_BASE
,
279 .has_fbc
= 0, /* legal, last one wins */
280 .has_llc
= 0, /* legal, last one wins */
281 GEN_DEFAULT_PIPEOFFSETS
,
285 static const struct intel_device_info intel_haswell_d_info
= {
290 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
291 GEN_DEFAULT_PIPEOFFSETS
,
295 static const struct intel_device_info intel_haswell_m_info
= {
301 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
302 GEN_DEFAULT_PIPEOFFSETS
,
306 static const struct intel_device_info intel_broadwell_d_info
= {
307 .gen
= 8, .num_pipes
= 3,
308 .need_gfx_hws
= 1, .has_hotplug
= 1,
309 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
313 GEN_DEFAULT_PIPEOFFSETS
,
317 static const struct intel_device_info intel_broadwell_m_info
= {
318 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
319 .need_gfx_hws
= 1, .has_hotplug
= 1,
320 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
324 GEN_DEFAULT_PIPEOFFSETS
,
328 static const struct intel_device_info intel_broadwell_gt3d_info
= {
329 .gen
= 8, .num_pipes
= 3,
330 .need_gfx_hws
= 1, .has_hotplug
= 1,
331 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
335 GEN_DEFAULT_PIPEOFFSETS
,
339 static const struct intel_device_info intel_broadwell_gt3m_info
= {
340 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
341 .need_gfx_hws
= 1, .has_hotplug
= 1,
342 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
346 GEN_DEFAULT_PIPEOFFSETS
,
350 static const struct intel_device_info intel_cherryview_info
= {
352 .gen
= 8, .num_pipes
= 3,
353 .need_gfx_hws
= 1, .has_hotplug
= 1,
354 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
356 .display_mmio_offset
= VLV_DISPLAY_BASE
,
362 * Make sure any device matches here are from most specific to most
363 * general. For example, since the Quanta match is based on the subsystem
364 * and subvendor IDs, we need it to come before the more general IVB
365 * PCI ID matches, otherwise we'll use the wrong info struct above.
367 #define INTEL_PCI_IDS \
368 INTEL_I830_IDS(&intel_i830_info), \
369 INTEL_I845G_IDS(&intel_845g_info), \
370 INTEL_I85X_IDS(&intel_i85x_info), \
371 INTEL_I865G_IDS(&intel_i865g_info), \
372 INTEL_I915G_IDS(&intel_i915g_info), \
373 INTEL_I915GM_IDS(&intel_i915gm_info), \
374 INTEL_I945G_IDS(&intel_i945g_info), \
375 INTEL_I945GM_IDS(&intel_i945gm_info), \
376 INTEL_I965G_IDS(&intel_i965g_info), \
377 INTEL_G33_IDS(&intel_g33_info), \
378 INTEL_I965GM_IDS(&intel_i965gm_info), \
379 INTEL_GM45_IDS(&intel_gm45_info), \
380 INTEL_G45_IDS(&intel_g45_info), \
381 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
382 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
383 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
384 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
385 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
386 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
387 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
388 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
389 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
390 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
391 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
392 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
393 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
394 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
395 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
396 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
397 INTEL_CHV_IDS(&intel_cherryview_info)
399 static const struct pci_device_id pciidlist
[] = { /* aka */
404 #if defined(CONFIG_DRM_I915_KMS)
405 MODULE_DEVICE_TABLE(pci
, pciidlist
);
408 void intel_detect_pch(struct drm_device
*dev
)
410 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
411 struct pci_dev
*pch
= NULL
;
413 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
414 * (which really amounts to a PCH but no South Display).
416 if (INTEL_INFO(dev
)->num_pipes
== 0) {
417 dev_priv
->pch_type
= PCH_NOP
;
422 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
423 * make graphics device passthrough work easy for VMM, that only
424 * need to expose ISA bridge to let driver know the real hardware
425 * underneath. This is a requirement from virtualization team.
427 * In some virtualized environments (e.g. XEN), there is irrelevant
428 * ISA bridge in the system. To work reliably, we should scan trhough
429 * all the ISA bridge devices and check for the first match, instead
430 * of only checking the first one.
432 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
433 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
434 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
435 dev_priv
->pch_id
= id
;
437 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
438 dev_priv
->pch_type
= PCH_IBX
;
439 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
440 WARN_ON(!IS_GEN5(dev
));
441 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
442 dev_priv
->pch_type
= PCH_CPT
;
443 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
444 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
445 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
446 /* PantherPoint is CPT compatible */
447 dev_priv
->pch_type
= PCH_CPT
;
448 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
449 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
450 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
451 dev_priv
->pch_type
= PCH_LPT
;
452 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
453 WARN_ON(!IS_HASWELL(dev
));
454 WARN_ON(IS_ULT(dev
));
455 } else if (IS_BROADWELL(dev
)) {
456 dev_priv
->pch_type
= PCH_LPT
;
458 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
459 DRM_DEBUG_KMS("This is Broadwell, assuming "
460 "LynxPoint LP PCH\n");
461 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
462 dev_priv
->pch_type
= PCH_LPT
;
463 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
464 WARN_ON(!IS_HASWELL(dev
));
465 WARN_ON(!IS_ULT(dev
));
473 DRM_DEBUG_KMS("No PCH found.\n");
478 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
480 if (INTEL_INFO(dev
)->gen
< 6)
483 if (i915
.semaphores
>= 0)
484 return i915
.semaphores
;
486 /* Until we get further testing... */
490 #ifdef CONFIG_INTEL_IOMMU
491 /* Enable semaphores on SNB when IO remapping is off */
492 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
499 static int i915_drm_freeze(struct drm_device
*dev
)
501 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
502 struct drm_crtc
*crtc
;
503 pci_power_t opregion_target_state
;
505 intel_runtime_pm_get(dev_priv
);
507 /* ignore lid events during suspend */
508 mutex_lock(&dev_priv
->modeset_restore_lock
);
509 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
510 mutex_unlock(&dev_priv
->modeset_restore_lock
);
512 /* We do a lot of poking in a lot of registers, make sure they work
514 intel_display_set_init_power(dev_priv
, true);
516 drm_kms_helper_poll_disable(dev
);
518 pci_save_state(dev
->pdev
);
520 /* If KMS is active, we do the leavevt stuff here */
521 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
524 error
= i915_gem_suspend(dev
);
526 dev_err(&dev
->pdev
->dev
,
527 "GEM idle failed, resume might fail\n");
531 drm_irq_uninstall(dev
);
532 dev_priv
->enable_hotplug_processing
= false;
534 intel_suspend_gt_powersave(dev
);
537 * Disable CRTCs directly since we want to preserve sw state
540 drm_modeset_lock_all(dev
);
541 for_each_crtc(dev
, crtc
) {
542 dev_priv
->display
.crtc_disable(crtc
);
544 drm_modeset_unlock_all(dev
);
546 intel_modeset_suspend_hw(dev
);
549 i915_gem_suspend_gtt_mappings(dev
);
551 i915_save_state(dev
);
553 if (acpi_target_system_state() >= ACPI_STATE_S3
)
554 opregion_target_state
= PCI_D3cold
;
556 opregion_target_state
= PCI_D1
;
557 intel_opregion_notify_adapter(dev
, opregion_target_state
);
559 intel_uncore_forcewake_reset(dev
, false);
560 intel_opregion_fini(dev
);
563 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
);
566 dev_priv
->suspend_count
++;
568 intel_display_set_init_power(dev_priv
, false);
573 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
577 if (!dev
|| !dev
->dev_private
) {
578 DRM_ERROR("dev: %p\n", dev
);
579 DRM_ERROR("DRM not initialized, aborting suspend.\n");
583 if (state
.event
== PM_EVENT_PRETHAW
)
587 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
590 error
= i915_drm_freeze(dev
);
594 if (state
.event
== PM_EVENT_SUSPEND
) {
595 /* Shut down the device */
596 pci_disable_device(dev
->pdev
);
597 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
603 void intel_console_resume(struct work_struct
*work
)
605 struct drm_i915_private
*dev_priv
=
606 container_of(work
, struct drm_i915_private
,
607 console_resume_work
);
608 struct drm_device
*dev
= dev_priv
->dev
;
611 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
615 static int i915_drm_thaw_early(struct drm_device
*dev
)
617 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
619 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
620 hsw_disable_pc8(dev_priv
);
622 intel_uncore_early_sanitize(dev
);
623 intel_uncore_sanitize(dev
);
624 intel_power_domains_init_hw(dev_priv
);
629 static int __i915_drm_thaw(struct drm_device
*dev
, bool restore_gtt_mappings
)
631 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
633 if (drm_core_check_feature(dev
, DRIVER_MODESET
) &&
634 restore_gtt_mappings
) {
635 mutex_lock(&dev
->struct_mutex
);
636 i915_gem_restore_gtt_mappings(dev
);
637 mutex_unlock(&dev
->struct_mutex
);
640 i915_restore_state(dev
);
641 intel_opregion_setup(dev
);
643 /* KMS EnterVT equivalent */
644 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
645 intel_init_pch_refclk(dev
);
646 drm_mode_config_reset(dev
);
648 mutex_lock(&dev
->struct_mutex
);
649 if (i915_gem_init_hw(dev
)) {
650 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
651 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
653 mutex_unlock(&dev
->struct_mutex
);
655 /* We need working interrupts for modeset enabling ... */
656 drm_irq_install(dev
, dev
->pdev
->irq
);
658 intel_modeset_init_hw(dev
);
660 drm_modeset_lock_all(dev
);
661 intel_modeset_setup_hw_state(dev
, true);
662 drm_modeset_unlock_all(dev
);
665 * ... but also need to make sure that hotplug processing
666 * doesn't cause havoc. Like in the driver load code we don't
667 * bother with the tiny race here where we might loose hotplug
671 dev_priv
->enable_hotplug_processing
= true;
672 /* Config may have changed between suspend and resume */
673 drm_helper_hpd_irq_event(dev
);
676 intel_opregion_init(dev
);
679 * The console lock can be pretty contented on resume due
680 * to all the printk activity. Try to keep it out of the hot
681 * path of resume if possible.
683 if (console_trylock()) {
684 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
687 schedule_work(&dev_priv
->console_resume_work
);
690 mutex_lock(&dev_priv
->modeset_restore_lock
);
691 dev_priv
->modeset_restore
= MODESET_DONE
;
692 mutex_unlock(&dev_priv
->modeset_restore_lock
);
694 intel_opregion_notify_adapter(dev
, PCI_D0
);
696 intel_runtime_pm_put(dev_priv
);
700 static int i915_drm_thaw(struct drm_device
*dev
)
702 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
703 i915_check_and_clear_faults(dev
);
705 return __i915_drm_thaw(dev
, true);
708 static int i915_resume_early(struct drm_device
*dev
)
710 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
714 * We have a resume ordering issue with the snd-hda driver also
715 * requiring our device to be power up. Due to the lack of a
716 * parent/child relationship we currently solve this with an early
719 * FIXME: This should be solved with a special hdmi sink device or
720 * similar so that power domains can be employed.
722 if (pci_enable_device(dev
->pdev
))
725 pci_set_master(dev
->pdev
);
727 return i915_drm_thaw_early(dev
);
730 int i915_resume(struct drm_device
*dev
)
732 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
736 * Platforms with opregion should have sane BIOS, older ones (gen3 and
737 * earlier) need to restore the GTT mappings since the BIOS might clear
738 * all our scratch PTEs.
740 ret
= __i915_drm_thaw(dev
, !dev_priv
->opregion
.header
);
744 drm_kms_helper_poll_enable(dev
);
748 static int i915_resume_legacy(struct drm_device
*dev
)
750 i915_resume_early(dev
);
757 * i915_reset - reset chip after a hang
758 * @dev: drm device to reset
760 * Reset the chip. Useful if a hang is detected. Returns zero on successful
761 * reset or otherwise an error code.
763 * Procedure is fairly simple:
764 * - reset the chip using the reset reg
765 * - re-init context state
766 * - re-init hardware status page
767 * - re-init ring buffer
768 * - re-init interrupt state
771 int i915_reset(struct drm_device
*dev
)
773 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
780 mutex_lock(&dev
->struct_mutex
);
784 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
786 ret
= intel_gpu_reset(dev
);
788 /* Also reset the gpu hangman. */
790 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
791 dev_priv
->gpu_error
.stop_rings
= 0;
792 if (ret
== -ENODEV
) {
793 DRM_INFO("Reset not implemented, but ignoring "
794 "error for simulated gpu hangs\n");
800 DRM_ERROR("Failed to reset chip: %i\n", ret
);
801 mutex_unlock(&dev
->struct_mutex
);
805 /* Ok, now get things going again... */
808 * Everything depends on having the GTT running, so we need to start
809 * there. Fortunately we don't need to do this unless we reset the
810 * chip at a PCI level.
812 * Next we need to restore the context, but we don't use those
815 * Ring buffer needs to be re-initialized in the KMS case, or if X
816 * was running at the time of the reset (i.e. we weren't VT
819 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
820 !dev_priv
->ums
.mm_suspended
) {
821 dev_priv
->ums
.mm_suspended
= 0;
823 ret
= i915_gem_init_hw(dev
);
824 mutex_unlock(&dev
->struct_mutex
);
826 DRM_ERROR("Failed hw init on reset %d\n", ret
);
831 * FIXME: This races pretty badly against concurrent holders of
832 * ring interrupts. This is possible since we've started to drop
833 * dev->struct_mutex in select places when waiting for the gpu.
837 * rps/rc6 re-init is necessary to restore state lost after the
838 * reset and the re-install of gt irqs. Skip for ironlake per
839 * previous concerns that it doesn't respond well to some forms
840 * of re-init after reset.
842 if (INTEL_INFO(dev
)->gen
> 5)
843 intel_reset_gt_powersave(dev
);
847 mutex_unlock(&dev
->struct_mutex
);
853 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
855 struct intel_device_info
*intel_info
=
856 (struct intel_device_info
*) ent
->driver_data
;
858 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
859 DRM_INFO("This hardware requires preliminary hardware support.\n"
860 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
864 /* Only bind to function 0 of the device. Early generations
865 * used function 1 as a placeholder for multi-head. This causes
866 * us confusion instead, especially on the systems where both
867 * functions have the same PCI-ID!
869 if (PCI_FUNC(pdev
->devfn
))
872 driver
.driver_features
&= ~(DRIVER_USE_AGP
);
874 return drm_get_pci_dev(pdev
, ent
, &driver
);
878 i915_pci_remove(struct pci_dev
*pdev
)
880 struct drm_device
*dev
= pci_get_drvdata(pdev
);
885 static int i915_pm_suspend(struct device
*dev
)
887 struct pci_dev
*pdev
= to_pci_dev(dev
);
888 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
890 if (!drm_dev
|| !drm_dev
->dev_private
) {
891 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
895 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
898 return i915_drm_freeze(drm_dev
);
901 static int i915_pm_suspend_late(struct device
*dev
)
903 struct pci_dev
*pdev
= to_pci_dev(dev
);
904 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
905 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
908 * We have a suspedn ordering issue with the snd-hda driver also
909 * requiring our device to be power up. Due to the lack of a
910 * parent/child relationship we currently solve this with an late
913 * FIXME: This should be solved with a special hdmi sink device or
914 * similar so that power domains can be employed.
916 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
919 if (IS_HASWELL(drm_dev
) || IS_BROADWELL(drm_dev
))
920 hsw_enable_pc8(dev_priv
);
922 pci_disable_device(pdev
);
923 pci_set_power_state(pdev
, PCI_D3hot
);
928 static int i915_pm_resume_early(struct device
*dev
)
930 struct pci_dev
*pdev
= to_pci_dev(dev
);
931 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
933 return i915_resume_early(drm_dev
);
936 static int i915_pm_resume(struct device
*dev
)
938 struct pci_dev
*pdev
= to_pci_dev(dev
);
939 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
941 return i915_resume(drm_dev
);
944 static int i915_pm_freeze(struct device
*dev
)
946 struct pci_dev
*pdev
= to_pci_dev(dev
);
947 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
949 if (!drm_dev
|| !drm_dev
->dev_private
) {
950 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
954 return i915_drm_freeze(drm_dev
);
957 static int i915_pm_thaw_early(struct device
*dev
)
959 struct pci_dev
*pdev
= to_pci_dev(dev
);
960 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
962 return i915_drm_thaw_early(drm_dev
);
965 static int i915_pm_thaw(struct device
*dev
)
967 struct pci_dev
*pdev
= to_pci_dev(dev
);
968 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
970 return i915_drm_thaw(drm_dev
);
973 static int i915_pm_poweroff(struct device
*dev
)
975 struct pci_dev
*pdev
= to_pci_dev(dev
);
976 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
978 return i915_drm_freeze(drm_dev
);
981 static int hsw_runtime_suspend(struct drm_i915_private
*dev_priv
)
983 hsw_enable_pc8(dev_priv
);
988 static int snb_runtime_resume(struct drm_i915_private
*dev_priv
)
990 struct drm_device
*dev
= dev_priv
->dev
;
992 intel_init_pch_refclk(dev
);
997 static int hsw_runtime_resume(struct drm_i915_private
*dev_priv
)
999 hsw_disable_pc8(dev_priv
);
1005 * Save all Gunit registers that may be lost after a D3 and a subsequent
1006 * S0i[R123] transition. The list of registers needing a save/restore is
1007 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1008 * registers in the following way:
1009 * - Driver: saved/restored by the driver
1010 * - Punit : saved/restored by the Punit firmware
1011 * - No, w/o marking: no need to save/restore, since the register is R/O or
1012 * used internally by the HW in a way that doesn't depend
1013 * keeping the content across a suspend/resume.
1014 * - Debug : used for debugging
1016 * We save/restore all registers marked with 'Driver', with the following
1018 * - Registers out of use, including also registers marked with 'Debug'.
1019 * These have no effect on the driver's operation, so we don't save/restore
1020 * them to reduce the overhead.
1021 * - Registers that are fully setup by an initialization function called from
1022 * the resume path. For example many clock gating and RPS/RC6 registers.
1023 * - Registers that provide the right functionality with their reset defaults.
1025 * TODO: Except for registers that based on the above 3 criteria can be safely
1026 * ignored, we save/restore all others, practically treating the HW context as
1027 * a black-box for the driver. Further investigation is needed to reduce the
1028 * saved/restored registers even further, by following the same 3 criteria.
1030 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1032 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1035 /* GAM 0x4000-0x4770 */
1036 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1037 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1038 s
->arb_mode
= I915_READ(ARB_MODE
);
1039 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1040 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1042 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1043 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS_BASE
+ i
* 4);
1045 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1046 s
->gfx_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1048 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1049 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1050 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1051 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1053 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1055 /* MBC 0x9024-0x91D0, 0x8500 */
1056 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1057 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1058 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1060 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1061 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1062 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1063 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1064 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1065 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1066 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1068 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1069 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1070 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1071 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1072 s
->ecobus
= I915_READ(ECOBUS
);
1073 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1074 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1075 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1076 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1077 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1078 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1080 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1081 s
->gt_imr
= I915_READ(GTIMR
);
1082 s
->gt_ier
= I915_READ(GTIER
);
1083 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1084 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1086 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1087 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH_BASE
+ i
* 4);
1089 /* GT SA CZ domain, 0x100000-0x138124 */
1090 s
->tilectl
= I915_READ(TILECTL
);
1091 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1092 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1093 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1094 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1096 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1097 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1098 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1099 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1102 * Not saving any of:
1103 * DFT, 0x9800-0x9EC0
1104 * SARB, 0xB000-0xB1FC
1105 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1110 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1112 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1116 /* GAM 0x4000-0x4770 */
1117 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1118 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1119 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1120 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1121 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1123 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1124 I915_WRITE(GEN7_LRA_LIMITS_BASE
+ i
* 4, s
->lra_limits
[i
]);
1126 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1127 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1129 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1130 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1131 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1132 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1134 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1136 /* MBC 0x9024-0x91D0, 0x8500 */
1137 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1138 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1139 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1141 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1142 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1143 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1144 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1145 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1146 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1147 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1149 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1150 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1151 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1152 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1153 I915_WRITE(ECOBUS
, s
->ecobus
);
1154 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1155 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1156 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1157 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1158 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1159 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1161 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1162 I915_WRITE(GTIMR
, s
->gt_imr
);
1163 I915_WRITE(GTIER
, s
->gt_ier
);
1164 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1165 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1167 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1168 I915_WRITE(GEN7_GT_SCRATCH_BASE
+ i
* 4, s
->gt_scratch
[i
]);
1170 /* GT SA CZ domain, 0x100000-0x138124 */
1171 I915_WRITE(TILECTL
, s
->tilectl
);
1172 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1174 * Preserve the GT allow wake and GFX force clock bit, they are not
1175 * be restored, as they are used to control the s0ix suspend/resume
1176 * sequence by the caller.
1178 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1179 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1180 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1181 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1183 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1184 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1185 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1186 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1188 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1190 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1191 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1192 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1193 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1196 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1201 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1202 WARN_ON(!!(val
& VLV_GFX_CLK_FORCE_ON_BIT
) == force_on
);
1204 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1205 /* Wait for a previous force-off to settle */
1207 err
= wait_for(!COND
, 20);
1209 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1210 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1215 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1216 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1218 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1219 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1224 err
= wait_for(COND
, 20);
1226 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1227 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1233 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1238 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1239 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1241 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1242 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1243 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1245 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1247 err
= wait_for(COND
, 1);
1249 DRM_ERROR("timeout disabling GT waking\n");
1254 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1261 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1262 val
= wait_for_on
? mask
: 0;
1263 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1267 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1268 wait_for_on
? "on" : "off",
1269 I915_READ(VLV_GTLC_PW_STATUS
));
1272 * RC6 transitioning can be delayed up to 2 msec (see
1273 * valleyview_enable_rps), use 3 msec for safety.
1275 err
= wait_for(COND
, 3);
1277 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1278 wait_for_on
? "on" : "off");
1284 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1286 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1289 DRM_ERROR("GT register access while GT waking disabled\n");
1290 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1293 static int vlv_runtime_suspend(struct drm_i915_private
*dev_priv
)
1299 * Bspec defines the following GT well on flags as debug only, so
1300 * don't treat them as hard failures.
1302 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1304 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1305 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1307 vlv_check_no_gt_access(dev_priv
);
1309 err
= vlv_force_gfx_clock(dev_priv
, true);
1313 err
= vlv_allow_gt_wake(dev_priv
, false);
1316 vlv_save_gunit_s0ix_state(dev_priv
);
1318 err
= vlv_force_gfx_clock(dev_priv
, false);
1325 /* For safety always re-enable waking and disable gfx clock forcing */
1326 vlv_allow_gt_wake(dev_priv
, true);
1328 vlv_force_gfx_clock(dev_priv
, false);
1333 static int vlv_runtime_resume(struct drm_i915_private
*dev_priv
)
1335 struct drm_device
*dev
= dev_priv
->dev
;
1340 * If any of the steps fail just try to continue, that's the best we
1341 * can do at this point. Return the first error code (which will also
1342 * leave RPM permanently disabled).
1344 ret
= vlv_force_gfx_clock(dev_priv
, true);
1346 vlv_restore_gunit_s0ix_state(dev_priv
);
1348 err
= vlv_allow_gt_wake(dev_priv
, true);
1352 err
= vlv_force_gfx_clock(dev_priv
, false);
1356 vlv_check_no_gt_access(dev_priv
);
1358 intel_init_clock_gating(dev
);
1359 i915_gem_restore_fences(dev
);
1364 static int intel_runtime_suspend(struct device
*device
)
1366 struct pci_dev
*pdev
= to_pci_dev(device
);
1367 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1368 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1371 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1374 WARN_ON(!HAS_RUNTIME_PM(dev
));
1375 assert_force_wake_inactive(dev_priv
);
1377 DRM_DEBUG_KMS("Suspending device\n");
1380 * We could deadlock here in case another thread holding struct_mutex
1381 * calls RPM suspend concurrently, since the RPM suspend will wait
1382 * first for this RPM suspend to finish. In this case the concurrent
1383 * RPM resume will be followed by its RPM suspend counterpart. Still
1384 * for consistency return -EAGAIN, which will reschedule this suspend.
1386 if (!mutex_trylock(&dev
->struct_mutex
)) {
1387 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1389 * Bump the expiration timestamp, otherwise the suspend won't
1392 pm_runtime_mark_last_busy(device
);
1397 * We are safe here against re-faults, since the fault handler takes
1400 i915_gem_release_all_mmaps(dev_priv
);
1401 mutex_unlock(&dev
->struct_mutex
);
1404 * rps.work can't be rearmed here, since we get here only after making
1405 * sure the GPU is idle and the RPS freq is set to the minimum. See
1406 * intel_mark_idle().
1408 cancel_work_sync(&dev_priv
->rps
.work
);
1409 intel_runtime_pm_disable_interrupts(dev
);
1413 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1414 ret
= hsw_runtime_suspend(dev_priv
);
1415 } else if (IS_VALLEYVIEW(dev
)) {
1416 ret
= vlv_runtime_suspend(dev_priv
);
1423 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1424 intel_runtime_pm_restore_interrupts(dev
);
1429 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
1430 dev_priv
->pm
.suspended
= true;
1433 * current versions of firmware which depend on this opregion
1434 * notification have repurposed the D1 definition to mean
1435 * "runtime suspended" vs. what you would normally expect (D3)
1436 * to distinguish it from notifications that might be sent
1437 * via the suspend path.
1439 intel_opregion_notify_adapter(dev
, PCI_D1
);
1441 DRM_DEBUG_KMS("Device suspended\n");
1445 static int intel_runtime_resume(struct device
*device
)
1447 struct pci_dev
*pdev
= to_pci_dev(device
);
1448 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1452 WARN_ON(!HAS_RUNTIME_PM(dev
));
1454 DRM_DEBUG_KMS("Resuming device\n");
1456 intel_opregion_notify_adapter(dev
, PCI_D0
);
1457 dev_priv
->pm
.suspended
= false;
1460 ret
= snb_runtime_resume(dev_priv
);
1461 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1462 ret
= hsw_runtime_resume(dev_priv
);
1463 } else if (IS_VALLEYVIEW(dev
)) {
1464 ret
= vlv_runtime_resume(dev_priv
);
1471 * No point of rolling back things in case of an error, as the best
1472 * we can do is to hope that things will still work (and disable RPM).
1474 i915_gem_init_swizzling(dev
);
1475 gen6_update_ring_freq(dev
);
1477 intel_runtime_pm_restore_interrupts(dev
);
1478 intel_reset_gt_powersave(dev
);
1481 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1483 DRM_DEBUG_KMS("Device resumed\n");
1488 static const struct dev_pm_ops i915_pm_ops
= {
1489 .suspend
= i915_pm_suspend
,
1490 .suspend_late
= i915_pm_suspend_late
,
1491 .resume_early
= i915_pm_resume_early
,
1492 .resume
= i915_pm_resume
,
1493 .freeze
= i915_pm_freeze
,
1494 .thaw_early
= i915_pm_thaw_early
,
1495 .thaw
= i915_pm_thaw
,
1496 .poweroff
= i915_pm_poweroff
,
1497 .restore_early
= i915_pm_resume_early
,
1498 .restore
= i915_pm_resume
,
1499 .runtime_suspend
= intel_runtime_suspend
,
1500 .runtime_resume
= intel_runtime_resume
,
1503 static const struct vm_operations_struct i915_gem_vm_ops
= {
1504 .fault
= i915_gem_fault
,
1505 .open
= drm_gem_vm_open
,
1506 .close
= drm_gem_vm_close
,
1509 static const struct file_operations i915_driver_fops
= {
1510 .owner
= THIS_MODULE
,
1512 .release
= drm_release
,
1513 .unlocked_ioctl
= drm_ioctl
,
1514 .mmap
= drm_gem_mmap
,
1517 #ifdef CONFIG_COMPAT
1518 .compat_ioctl
= i915_compat_ioctl
,
1520 .llseek
= noop_llseek
,
1523 static struct drm_driver driver
= {
1524 /* Don't use MTRRs here; the Xserver or userspace app should
1525 * deal with them for Intel hardware.
1529 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1531 .load
= i915_driver_load
,
1532 .unload
= i915_driver_unload
,
1533 .open
= i915_driver_open
,
1534 .lastclose
= i915_driver_lastclose
,
1535 .preclose
= i915_driver_preclose
,
1536 .postclose
= i915_driver_postclose
,
1538 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1539 .suspend
= i915_suspend
,
1540 .resume
= i915_resume_legacy
,
1542 .device_is_agp
= i915_driver_device_is_agp
,
1543 .master_create
= i915_master_create
,
1544 .master_destroy
= i915_master_destroy
,
1545 #if defined(CONFIG_DEBUG_FS)
1546 .debugfs_init
= i915_debugfs_init
,
1547 .debugfs_cleanup
= i915_debugfs_cleanup
,
1549 .gem_free_object
= i915_gem_free_object
,
1550 .gem_vm_ops
= &i915_gem_vm_ops
,
1552 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1553 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1554 .gem_prime_export
= i915_gem_prime_export
,
1555 .gem_prime_import
= i915_gem_prime_import
,
1557 .dumb_create
= i915_gem_dumb_create
,
1558 .dumb_map_offset
= i915_gem_mmap_gtt
,
1559 .dumb_destroy
= drm_gem_dumb_destroy
,
1560 .ioctls
= i915_ioctls
,
1561 .fops
= &i915_driver_fops
,
1562 .name
= DRIVER_NAME
,
1563 .desc
= DRIVER_DESC
,
1564 .date
= DRIVER_DATE
,
1565 .major
= DRIVER_MAJOR
,
1566 .minor
= DRIVER_MINOR
,
1567 .patchlevel
= DRIVER_PATCHLEVEL
,
1570 static struct pci_driver i915_pci_driver
= {
1571 .name
= DRIVER_NAME
,
1572 .id_table
= pciidlist
,
1573 .probe
= i915_pci_probe
,
1574 .remove
= i915_pci_remove
,
1575 .driver
.pm
= &i915_pm_ops
,
1578 static int __init
i915_init(void)
1580 driver
.num_ioctls
= i915_max_ioctl
;
1583 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1584 * explicitly disabled with the module pararmeter.
1586 * Otherwise, just follow the parameter (defaulting to off).
1588 * Allow optional vga_text_mode_force boot option to override
1589 * the default behavior.
1591 #if defined(CONFIG_DRM_I915_KMS)
1592 if (i915
.modeset
!= 0)
1593 driver
.driver_features
|= DRIVER_MODESET
;
1595 if (i915
.modeset
== 1)
1596 driver
.driver_features
|= DRIVER_MODESET
;
1598 #ifdef CONFIG_VGA_CONSOLE
1599 if (vgacon_text_force() && i915
.modeset
== -1)
1600 driver
.driver_features
&= ~DRIVER_MODESET
;
1603 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1604 driver
.get_vblank_timestamp
= NULL
;
1605 #ifndef CONFIG_DRM_I915_UMS
1606 /* Silently fail loading to not upset userspace. */
1607 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1612 return drm_pci_init(&driver
, &i915_pci_driver
);
1615 static void __exit
i915_exit(void)
1617 #ifndef CONFIG_DRM_I915_UMS
1618 if (!(driver
.driver_features
& DRIVER_MODESET
))
1619 return; /* Never loaded a driver. */
1622 drm_pci_exit(&driver
, &i915_pci_driver
);
1625 module_init(i915_init
);
1626 module_exit(i915_exit
);
1628 MODULE_AUTHOR(DRIVER_AUTHOR
);
1629 MODULE_DESCRIPTION(DRIVER_DESC
);
1630 MODULE_LICENSE("GPL and additional rights");