1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <linux/vga_switcheroo.h>
42 #include <drm/drm_crtc_helper.h>
44 static struct drm_driver driver
;
46 #define GEN_DEFAULT_PIPEOFFSETS \
47 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
48 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
49 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
50 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
51 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
53 #define GEN_CHV_PIPEOFFSETS \
54 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
55 CHV_PIPE_C_OFFSET }, \
56 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
57 CHV_TRANSCODER_C_OFFSET, }, \
58 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
59 CHV_PALETTE_C_OFFSET }
61 #define CURSOR_OFFSETS \
62 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
64 #define IVB_CURSOR_OFFSETS \
65 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
68 .color = { .degamma_lut_size = 512, .gamma_lut_size = 512 }
70 .color = { .degamma_lut_size = 65, .gamma_lut_size = 257 }
72 static const struct intel_device_info intel_i830_info
= {
73 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
74 .has_overlay
= 1, .overlay_needs_physical
= 1,
75 .ring_mask
= RENDER_RING
,
76 GEN_DEFAULT_PIPEOFFSETS
,
80 static const struct intel_device_info intel_845g_info
= {
81 .gen
= 2, .num_pipes
= 1,
82 .has_overlay
= 1, .overlay_needs_physical
= 1,
83 .ring_mask
= RENDER_RING
,
84 GEN_DEFAULT_PIPEOFFSETS
,
88 static const struct intel_device_info intel_i85x_info
= {
89 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
90 .cursor_needs_physical
= 1,
91 .has_overlay
= 1, .overlay_needs_physical
= 1,
93 .ring_mask
= RENDER_RING
,
94 GEN_DEFAULT_PIPEOFFSETS
,
98 static const struct intel_device_info intel_i865g_info
= {
99 .gen
= 2, .num_pipes
= 1,
100 .has_overlay
= 1, .overlay_needs_physical
= 1,
101 .ring_mask
= RENDER_RING
,
102 GEN_DEFAULT_PIPEOFFSETS
,
106 static const struct intel_device_info intel_i915g_info
= {
107 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
108 .has_overlay
= 1, .overlay_needs_physical
= 1,
109 .ring_mask
= RENDER_RING
,
110 GEN_DEFAULT_PIPEOFFSETS
,
113 static const struct intel_device_info intel_i915gm_info
= {
114 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
115 .cursor_needs_physical
= 1,
116 .has_overlay
= 1, .overlay_needs_physical
= 1,
119 .ring_mask
= RENDER_RING
,
120 GEN_DEFAULT_PIPEOFFSETS
,
123 static const struct intel_device_info intel_i945g_info
= {
124 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
125 .has_overlay
= 1, .overlay_needs_physical
= 1,
126 .ring_mask
= RENDER_RING
,
127 GEN_DEFAULT_PIPEOFFSETS
,
130 static const struct intel_device_info intel_i945gm_info
= {
131 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
132 .has_hotplug
= 1, .cursor_needs_physical
= 1,
133 .has_overlay
= 1, .overlay_needs_physical
= 1,
136 .ring_mask
= RENDER_RING
,
137 GEN_DEFAULT_PIPEOFFSETS
,
141 static const struct intel_device_info intel_i965g_info
= {
142 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
145 .ring_mask
= RENDER_RING
,
146 GEN_DEFAULT_PIPEOFFSETS
,
150 static const struct intel_device_info intel_i965gm_info
= {
151 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
152 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
155 .ring_mask
= RENDER_RING
,
156 GEN_DEFAULT_PIPEOFFSETS
,
160 static const struct intel_device_info intel_g33_info
= {
161 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
162 .need_gfx_hws
= 1, .has_hotplug
= 1,
164 .ring_mask
= RENDER_RING
,
165 GEN_DEFAULT_PIPEOFFSETS
,
169 static const struct intel_device_info intel_g45_info
= {
170 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
171 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
172 .ring_mask
= RENDER_RING
| BSD_RING
,
173 GEN_DEFAULT_PIPEOFFSETS
,
177 static const struct intel_device_info intel_gm45_info
= {
178 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
179 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
180 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
182 .ring_mask
= RENDER_RING
| BSD_RING
,
183 GEN_DEFAULT_PIPEOFFSETS
,
187 static const struct intel_device_info intel_pineview_info
= {
188 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
189 .need_gfx_hws
= 1, .has_hotplug
= 1,
191 GEN_DEFAULT_PIPEOFFSETS
,
195 static const struct intel_device_info intel_ironlake_d_info
= {
196 .gen
= 5, .num_pipes
= 2,
197 .need_gfx_hws
= 1, .has_hotplug
= 1,
198 .ring_mask
= RENDER_RING
| BSD_RING
,
199 GEN_DEFAULT_PIPEOFFSETS
,
203 static const struct intel_device_info intel_ironlake_m_info
= {
204 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
205 .need_gfx_hws
= 1, .has_hotplug
= 1,
207 .ring_mask
= RENDER_RING
| BSD_RING
,
208 GEN_DEFAULT_PIPEOFFSETS
,
212 static const struct intel_device_info intel_sandybridge_d_info
= {
213 .gen
= 6, .num_pipes
= 2,
214 .need_gfx_hws
= 1, .has_hotplug
= 1,
216 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
218 GEN_DEFAULT_PIPEOFFSETS
,
222 static const struct intel_device_info intel_sandybridge_m_info
= {
223 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
224 .need_gfx_hws
= 1, .has_hotplug
= 1,
226 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
228 GEN_DEFAULT_PIPEOFFSETS
,
232 #define GEN7_FEATURES \
233 .gen = 7, .num_pipes = 3, \
234 .need_gfx_hws = 1, .has_hotplug = 1, \
236 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
238 GEN_DEFAULT_PIPEOFFSETS, \
241 static const struct intel_device_info intel_ivybridge_d_info
= {
246 static const struct intel_device_info intel_ivybridge_m_info
= {
252 static const struct intel_device_info intel_ivybridge_q_info
= {
255 .num_pipes
= 0, /* legal, last one wins */
258 #define VLV_FEATURES \
259 .gen = 7, .num_pipes = 2, \
260 .need_gfx_hws = 1, .has_hotplug = 1, \
261 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
262 .display_mmio_offset = VLV_DISPLAY_BASE, \
263 GEN_DEFAULT_PIPEOFFSETS, \
266 static const struct intel_device_info intel_valleyview_m_info
= {
272 static const struct intel_device_info intel_valleyview_d_info
= {
277 #define HSW_FEATURES \
279 .ring_mask = RENDER_RING | BSD_RING | BLT_RING | VEBOX_RING, \
283 static const struct intel_device_info intel_haswell_d_info
= {
288 static const struct intel_device_info intel_haswell_m_info
= {
294 #define BDW_FEATURES \
298 static const struct intel_device_info intel_broadwell_d_info
= {
303 static const struct intel_device_info intel_broadwell_m_info
= {
305 .gen
= 8, .is_mobile
= 1,
308 static const struct intel_device_info intel_broadwell_gt3d_info
= {
311 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
314 static const struct intel_device_info intel_broadwell_gt3m_info
= {
316 .gen
= 8, .is_mobile
= 1,
317 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
320 static const struct intel_device_info intel_cherryview_info
= {
321 .gen
= 8, .num_pipes
= 3,
322 .need_gfx_hws
= 1, .has_hotplug
= 1,
323 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
325 .display_mmio_offset
= VLV_DISPLAY_BASE
,
331 static const struct intel_device_info intel_skylake_info
= {
337 static const struct intel_device_info intel_skylake_gt3_info
= {
341 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
344 static const struct intel_device_info intel_broxton_info
= {
348 .need_gfx_hws
= 1, .has_hotplug
= 1,
349 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
354 GEN_DEFAULT_PIPEOFFSETS
,
359 static const struct intel_device_info intel_kabylake_info
= {
365 static const struct intel_device_info intel_kabylake_gt3_info
= {
369 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
373 * Make sure any device matches here are from most specific to most
374 * general. For example, since the Quanta match is based on the subsystem
375 * and subvendor IDs, we need it to come before the more general IVB
376 * PCI ID matches, otherwise we'll use the wrong info struct above.
378 static const struct pci_device_id pciidlist
[] = {
379 INTEL_I830_IDS(&intel_i830_info
),
380 INTEL_I845G_IDS(&intel_845g_info
),
381 INTEL_I85X_IDS(&intel_i85x_info
),
382 INTEL_I865G_IDS(&intel_i865g_info
),
383 INTEL_I915G_IDS(&intel_i915g_info
),
384 INTEL_I915GM_IDS(&intel_i915gm_info
),
385 INTEL_I945G_IDS(&intel_i945g_info
),
386 INTEL_I945GM_IDS(&intel_i945gm_info
),
387 INTEL_I965G_IDS(&intel_i965g_info
),
388 INTEL_G33_IDS(&intel_g33_info
),
389 INTEL_I965GM_IDS(&intel_i965gm_info
),
390 INTEL_GM45_IDS(&intel_gm45_info
),
391 INTEL_G45_IDS(&intel_g45_info
),
392 INTEL_PINEVIEW_IDS(&intel_pineview_info
),
393 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info
),
394 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info
),
395 INTEL_SNB_D_IDS(&intel_sandybridge_d_info
),
396 INTEL_SNB_M_IDS(&intel_sandybridge_m_info
),
397 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info
), /* must be first IVB */
398 INTEL_IVB_M_IDS(&intel_ivybridge_m_info
),
399 INTEL_IVB_D_IDS(&intel_ivybridge_d_info
),
400 INTEL_HSW_D_IDS(&intel_haswell_d_info
),
401 INTEL_HSW_M_IDS(&intel_haswell_m_info
),
402 INTEL_VLV_M_IDS(&intel_valleyview_m_info
),
403 INTEL_VLV_D_IDS(&intel_valleyview_d_info
),
404 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info
),
405 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info
),
406 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info
),
407 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info
),
408 INTEL_CHV_IDS(&intel_cherryview_info
),
409 INTEL_SKL_GT1_IDS(&intel_skylake_info
),
410 INTEL_SKL_GT2_IDS(&intel_skylake_info
),
411 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info
),
412 INTEL_SKL_GT4_IDS(&intel_skylake_gt3_info
),
413 INTEL_BXT_IDS(&intel_broxton_info
),
414 INTEL_KBL_GT1_IDS(&intel_kabylake_info
),
415 INTEL_KBL_GT2_IDS(&intel_kabylake_info
),
416 INTEL_KBL_GT3_IDS(&intel_kabylake_gt3_info
),
417 INTEL_KBL_GT4_IDS(&intel_kabylake_gt3_info
),
421 MODULE_DEVICE_TABLE(pci
, pciidlist
);
423 static enum intel_pch
intel_virt_detect_pch(struct drm_device
*dev
)
425 enum intel_pch ret
= PCH_NOP
;
428 * In a virtualized passthrough environment we can be in a
429 * setup where the ISA bridge is not able to be passed through.
430 * In this case, a south bridge can be emulated and we have to
431 * make an educated guess as to which PCH is really there.
436 DRM_DEBUG_KMS("Assuming Ibex Peak PCH\n");
437 } else if (IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)) {
439 DRM_DEBUG_KMS("Assuming CouarPoint PCH\n");
440 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
442 DRM_DEBUG_KMS("Assuming LynxPoint PCH\n");
443 } else if (IS_SKYLAKE(dev
) || IS_KABYLAKE(dev
)) {
445 DRM_DEBUG_KMS("Assuming SunrisePoint PCH\n");
451 void intel_detect_pch(struct drm_device
*dev
)
453 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
454 struct pci_dev
*pch
= NULL
;
456 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
457 * (which really amounts to a PCH but no South Display).
459 if (INTEL_INFO(dev
)->num_pipes
== 0) {
460 dev_priv
->pch_type
= PCH_NOP
;
465 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
466 * make graphics device passthrough work easy for VMM, that only
467 * need to expose ISA bridge to let driver know the real hardware
468 * underneath. This is a requirement from virtualization team.
470 * In some virtualized environments (e.g. XEN), there is irrelevant
471 * ISA bridge in the system. To work reliably, we should scan trhough
472 * all the ISA bridge devices and check for the first match, instead
473 * of only checking the first one.
475 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
476 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
477 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
478 dev_priv
->pch_id
= id
;
480 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
481 dev_priv
->pch_type
= PCH_IBX
;
482 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
483 WARN_ON(!IS_GEN5(dev
));
484 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
485 dev_priv
->pch_type
= PCH_CPT
;
486 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
487 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
488 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
489 /* PantherPoint is CPT compatible */
490 dev_priv
->pch_type
= PCH_CPT
;
491 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
492 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
493 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
494 dev_priv
->pch_type
= PCH_LPT
;
495 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
496 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
497 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
498 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
499 dev_priv
->pch_type
= PCH_LPT
;
500 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
501 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
502 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
503 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
504 dev_priv
->pch_type
= PCH_SPT
;
505 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
506 WARN_ON(!IS_SKYLAKE(dev
) &&
508 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
509 dev_priv
->pch_type
= PCH_SPT
;
510 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
511 WARN_ON(!IS_SKYLAKE(dev
) &&
513 } else if ((id
== INTEL_PCH_P2X_DEVICE_ID_TYPE
) ||
514 (id
== INTEL_PCH_P3X_DEVICE_ID_TYPE
) ||
515 ((id
== INTEL_PCH_QEMU_DEVICE_ID_TYPE
) &&
516 pch
->subsystem_vendor
== 0x1af4 &&
517 pch
->subsystem_device
== 0x1100)) {
518 dev_priv
->pch_type
= intel_virt_detect_pch(dev
);
526 DRM_DEBUG_KMS("No PCH found.\n");
531 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
533 if (INTEL_INFO(dev
)->gen
< 6)
536 if (i915
.semaphores
>= 0)
537 return i915
.semaphores
;
539 /* TODO: make semaphores and Execlists play nicely together */
540 if (i915
.enable_execlists
)
543 /* Until we get further testing... */
547 #ifdef CONFIG_INTEL_IOMMU
548 /* Enable semaphores on SNB when IO remapping is off */
549 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
556 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
558 struct drm_device
*dev
= dev_priv
->dev
;
559 struct intel_encoder
*encoder
;
561 drm_modeset_lock_all(dev
);
562 for_each_intel_encoder(dev
, encoder
)
563 if (encoder
->suspend
)
564 encoder
->suspend(encoder
);
565 drm_modeset_unlock_all(dev
);
568 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
570 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
);
572 static bool suspend_to_idle(struct drm_i915_private
*dev_priv
)
574 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
575 if (acpi_target_system_state() < ACPI_STATE_S3
)
581 static int i915_drm_suspend(struct drm_device
*dev
)
583 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
584 pci_power_t opregion_target_state
;
587 /* ignore lid events during suspend */
588 mutex_lock(&dev_priv
->modeset_restore_lock
);
589 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
590 mutex_unlock(&dev_priv
->modeset_restore_lock
);
592 disable_rpm_wakeref_asserts(dev_priv
);
594 /* We do a lot of poking in a lot of registers, make sure they work
596 intel_display_set_init_power(dev_priv
, true);
598 drm_kms_helper_poll_disable(dev
);
600 pci_save_state(dev
->pdev
);
602 error
= i915_gem_suspend(dev
);
604 dev_err(&dev
->pdev
->dev
,
605 "GEM idle failed, resume might fail\n");
609 intel_guc_suspend(dev
);
611 intel_suspend_gt_powersave(dev
);
613 intel_display_suspend(dev
);
615 intel_dp_mst_suspend(dev
);
617 intel_runtime_pm_disable_interrupts(dev_priv
);
618 intel_hpd_cancel_work(dev_priv
);
620 intel_suspend_encoders(dev_priv
);
622 intel_suspend_hw(dev
);
624 i915_gem_suspend_gtt_mappings(dev
);
626 i915_save_state(dev
);
628 opregion_target_state
= suspend_to_idle(dev_priv
) ? PCI_D1
: PCI_D3cold
;
629 intel_opregion_notify_adapter(dev
, opregion_target_state
);
631 intel_uncore_forcewake_reset(dev
, false);
632 intel_opregion_fini(dev
);
634 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
636 dev_priv
->suspend_count
++;
638 intel_display_set_init_power(dev_priv
, false);
640 intel_csr_ucode_suspend(dev_priv
);
643 enable_rpm_wakeref_asserts(dev_priv
);
648 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
650 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
654 disable_rpm_wakeref_asserts(dev_priv
);
656 fw_csr
= !IS_BROXTON(dev_priv
) &&
657 suspend_to_idle(dev_priv
) && dev_priv
->csr
.dmc_payload
;
659 * In case of firmware assisted context save/restore don't manually
660 * deinit the power domains. This also means the CSR/DMC firmware will
661 * stay active, it will power down any HW resources as required and
662 * also enable deeper system power states that would be blocked if the
663 * firmware was inactive.
666 intel_power_domains_suspend(dev_priv
);
669 if (IS_BROXTON(dev_priv
))
670 bxt_enable_dc9(dev_priv
);
671 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
672 hsw_enable_pc8(dev_priv
);
673 else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
674 ret
= vlv_suspend_complete(dev_priv
);
677 DRM_ERROR("Suspend complete failed: %d\n", ret
);
679 intel_power_domains_init_hw(dev_priv
, true);
684 pci_disable_device(drm_dev
->pdev
);
686 * During hibernation on some platforms the BIOS may try to access
687 * the device even though it's already in D3 and hang the machine. So
688 * leave the device in D0 on those platforms and hope the BIOS will
689 * power down the device properly. The issue was seen on multiple old
690 * GENs with different BIOS vendors, so having an explicit blacklist
691 * is inpractical; apply the workaround on everything pre GEN6. The
692 * platforms where the issue was seen:
693 * Lenovo Thinkpad X301, X61s, X60, T60, X41
697 if (!(hibernation
&& INTEL_INFO(dev_priv
)->gen
< 6))
698 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
700 dev_priv
->suspended_to_idle
= suspend_to_idle(dev_priv
);
703 enable_rpm_wakeref_asserts(dev_priv
);
708 int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
)
712 if (!dev
|| !dev
->dev_private
) {
713 DRM_ERROR("dev: %p\n", dev
);
714 DRM_ERROR("DRM not initialized, aborting suspend.\n");
718 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
719 state
.event
!= PM_EVENT_FREEZE
))
722 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
725 error
= i915_drm_suspend(dev
);
729 return i915_drm_suspend_late(dev
, false);
732 static int i915_drm_resume(struct drm_device
*dev
)
734 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
736 disable_rpm_wakeref_asserts(dev_priv
);
738 intel_csr_ucode_resume(dev_priv
);
740 mutex_lock(&dev
->struct_mutex
);
741 i915_gem_restore_gtt_mappings(dev
);
742 mutex_unlock(&dev
->struct_mutex
);
744 i915_restore_state(dev
);
745 intel_opregion_setup(dev
);
747 intel_init_pch_refclk(dev
);
748 drm_mode_config_reset(dev
);
751 * Interrupts have to be enabled before any batches are run. If not the
752 * GPU will hang. i915_gem_init_hw() will initiate batches to
753 * update/restore the context.
755 * Modeset enabling in intel_modeset_init_hw() also needs working
758 intel_runtime_pm_enable_interrupts(dev_priv
);
760 mutex_lock(&dev
->struct_mutex
);
761 if (i915_gem_init_hw(dev
)) {
762 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
763 atomic_or(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
765 mutex_unlock(&dev
->struct_mutex
);
767 intel_guc_resume(dev
);
769 intel_modeset_init_hw(dev
);
771 spin_lock_irq(&dev_priv
->irq_lock
);
772 if (dev_priv
->display
.hpd_irq_setup
)
773 dev_priv
->display
.hpd_irq_setup(dev
);
774 spin_unlock_irq(&dev_priv
->irq_lock
);
776 intel_dp_mst_resume(dev
);
778 intel_display_resume(dev
);
781 * ... but also need to make sure that hotplug processing
782 * doesn't cause havoc. Like in the driver load code we don't
783 * bother with the tiny race here where we might loose hotplug
786 intel_hpd_init(dev_priv
);
787 /* Config may have changed between suspend and resume */
788 drm_helper_hpd_irq_event(dev
);
790 intel_opregion_init(dev
);
792 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
794 mutex_lock(&dev_priv
->modeset_restore_lock
);
795 dev_priv
->modeset_restore
= MODESET_DONE
;
796 mutex_unlock(&dev_priv
->modeset_restore_lock
);
798 intel_opregion_notify_adapter(dev
, PCI_D0
);
800 drm_kms_helper_poll_enable(dev
);
802 enable_rpm_wakeref_asserts(dev_priv
);
807 static int i915_drm_resume_early(struct drm_device
*dev
)
809 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
813 * We have a resume ordering issue with the snd-hda driver also
814 * requiring our device to be power up. Due to the lack of a
815 * parent/child relationship we currently solve this with an early
818 * FIXME: This should be solved with a special hdmi sink device or
819 * similar so that power domains can be employed.
823 * Note that we need to set the power state explicitly, since we
824 * powered off the device during freeze and the PCI core won't power
825 * it back up for us during thaw. Powering off the device during
826 * freeze is not a hard requirement though, and during the
827 * suspend/resume phases the PCI core makes sure we get here with the
828 * device powered on. So in case we change our freeze logic and keep
829 * the device powered we can also remove the following set power state
832 ret
= pci_set_power_state(dev
->pdev
, PCI_D0
);
834 DRM_ERROR("failed to set PCI D0 power state (%d)\n", ret
);
839 * Note that pci_enable_device() first enables any parent bridge
840 * device and only then sets the power state for this device. The
841 * bridge enabling is a nop though, since bridge devices are resumed
842 * first. The order of enabling power and enabling the device is
843 * imposed by the PCI core as described above, so here we preserve the
844 * same order for the freeze/thaw phases.
846 * TODO: eventually we should remove pci_disable_device() /
847 * pci_enable_enable_device() from suspend/resume. Due to how they
848 * depend on the device enable refcount we can't anyway depend on them
849 * disabling/enabling the device.
851 if (pci_enable_device(dev
->pdev
)) {
856 pci_set_master(dev
->pdev
);
858 disable_rpm_wakeref_asserts(dev_priv
);
860 if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
))
861 ret
= vlv_resume_prepare(dev_priv
, false);
863 DRM_ERROR("Resume prepare failed: %d, continuing anyway\n",
866 intel_uncore_early_sanitize(dev
, true);
868 if (IS_BROXTON(dev
)) {
869 if (!dev_priv
->suspended_to_idle
)
870 gen9_sanitize_dc_state(dev_priv
);
871 bxt_disable_dc9(dev_priv
);
872 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
873 hsw_disable_pc8(dev_priv
);
876 intel_uncore_sanitize(dev
);
878 if (IS_BROXTON(dev_priv
) ||
879 !(dev_priv
->suspended_to_idle
&& dev_priv
->csr
.dmc_payload
))
880 intel_power_domains_init_hw(dev_priv
, true);
882 enable_rpm_wakeref_asserts(dev_priv
);
885 dev_priv
->suspended_to_idle
= false;
890 int i915_resume_switcheroo(struct drm_device
*dev
)
894 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
897 ret
= i915_drm_resume_early(dev
);
901 return i915_drm_resume(dev
);
905 * i915_reset - reset chip after a hang
906 * @dev: drm device to reset
908 * Reset the chip. Useful if a hang is detected. Returns zero on successful
909 * reset or otherwise an error code.
911 * Procedure is fairly simple:
912 * - reset the chip using the reset reg
913 * - re-init context state
914 * - re-init hardware status page
915 * - re-init ring buffer
916 * - re-init interrupt state
919 int i915_reset(struct drm_device
*dev
)
921 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
922 struct i915_gpu_error
*error
= &dev_priv
->gpu_error
;
923 unsigned reset_counter
;
926 intel_reset_gt_powersave(dev
);
928 mutex_lock(&dev
->struct_mutex
);
930 /* Clear any previous failed attempts at recovery. Time to try again. */
931 atomic_andnot(I915_WEDGED
, &error
->reset_counter
);
933 /* Clear the reset-in-progress flag and increment the reset epoch. */
934 reset_counter
= atomic_inc_return(&error
->reset_counter
);
935 if (WARN_ON(__i915_reset_in_progress(reset_counter
))) {
942 ret
= intel_gpu_reset(dev
, ALL_ENGINES
);
944 /* Also reset the gpu hangman. */
945 if (error
->stop_rings
!= 0) {
946 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
947 error
->stop_rings
= 0;
948 if (ret
== -ENODEV
) {
949 DRM_INFO("Reset not implemented, but ignoring "
950 "error for simulated gpu hangs\n");
955 if (i915_stop_ring_allow_warn(dev_priv
))
956 pr_notice("drm/i915: Resetting chip after gpu hang\n");
960 DRM_ERROR("Failed to reset chip: %i\n", ret
);
962 DRM_DEBUG_DRIVER("GPU reset disabled\n");
966 intel_overlay_reset(dev_priv
);
968 /* Ok, now get things going again... */
971 * Everything depends on having the GTT running, so we need to start
972 * there. Fortunately we don't need to do this unless we reset the
973 * chip at a PCI level.
975 * Next we need to restore the context, but we don't use those
978 * Ring buffer needs to be re-initialized in the KMS case, or if X
979 * was running at the time of the reset (i.e. we weren't VT
982 ret
= i915_gem_init_hw(dev
);
984 DRM_ERROR("Failed hw init on reset %d\n", ret
);
988 mutex_unlock(&dev
->struct_mutex
);
991 * rps/rc6 re-init is necessary to restore state lost after the
992 * reset and the re-install of gt irqs. Skip for ironlake per
993 * previous concerns that it doesn't respond well to some forms
994 * of re-init after reset.
996 if (INTEL_INFO(dev
)->gen
> 5)
997 intel_enable_gt_powersave(dev
);
1002 atomic_or(I915_WEDGED
, &error
->reset_counter
);
1003 mutex_unlock(&dev
->struct_mutex
);
1007 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
1009 struct intel_device_info
*intel_info
=
1010 (struct intel_device_info
*) ent
->driver_data
;
1012 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
1013 DRM_INFO("This hardware requires preliminary hardware support.\n"
1014 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
1018 /* Only bind to function 0 of the device. Early generations
1019 * used function 1 as a placeholder for multi-head. This causes
1020 * us confusion instead, especially on the systems where both
1021 * functions have the same PCI-ID!
1023 if (PCI_FUNC(pdev
->devfn
))
1026 if (vga_switcheroo_client_probe_defer(pdev
))
1027 return -EPROBE_DEFER
;
1029 return drm_get_pci_dev(pdev
, ent
, &driver
);
1033 i915_pci_remove(struct pci_dev
*pdev
)
1035 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1040 static int i915_pm_suspend(struct device
*dev
)
1042 struct pci_dev
*pdev
= to_pci_dev(dev
);
1043 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
1045 if (!drm_dev
|| !drm_dev
->dev_private
) {
1046 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
1050 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1053 return i915_drm_suspend(drm_dev
);
1056 static int i915_pm_suspend_late(struct device
*dev
)
1058 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1061 * We have a suspend ordering issue with the snd-hda driver also
1062 * requiring our device to be power up. Due to the lack of a
1063 * parent/child relationship we currently solve this with an late
1066 * FIXME: This should be solved with a special hdmi sink device or
1067 * similar so that power domains can be employed.
1069 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1072 return i915_drm_suspend_late(drm_dev
, false);
1075 static int i915_pm_poweroff_late(struct device
*dev
)
1077 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1079 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1082 return i915_drm_suspend_late(drm_dev
, true);
1085 static int i915_pm_resume_early(struct device
*dev
)
1087 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1089 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1092 return i915_drm_resume_early(drm_dev
);
1095 static int i915_pm_resume(struct device
*dev
)
1097 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1099 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1102 return i915_drm_resume(drm_dev
);
1106 * Save all Gunit registers that may be lost after a D3 and a subsequent
1107 * S0i[R123] transition. The list of registers needing a save/restore is
1108 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1109 * registers in the following way:
1110 * - Driver: saved/restored by the driver
1111 * - Punit : saved/restored by the Punit firmware
1112 * - No, w/o marking: no need to save/restore, since the register is R/O or
1113 * used internally by the HW in a way that doesn't depend
1114 * keeping the content across a suspend/resume.
1115 * - Debug : used for debugging
1117 * We save/restore all registers marked with 'Driver', with the following
1119 * - Registers out of use, including also registers marked with 'Debug'.
1120 * These have no effect on the driver's operation, so we don't save/restore
1121 * them to reduce the overhead.
1122 * - Registers that are fully setup by an initialization function called from
1123 * the resume path. For example many clock gating and RPS/RC6 registers.
1124 * - Registers that provide the right functionality with their reset defaults.
1126 * TODO: Except for registers that based on the above 3 criteria can be safely
1127 * ignored, we save/restore all others, practically treating the HW context as
1128 * a black-box for the driver. Further investigation is needed to reduce the
1129 * saved/restored registers even further, by following the same 3 criteria.
1131 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1133 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1136 /* GAM 0x4000-0x4770 */
1137 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1138 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1139 s
->arb_mode
= I915_READ(ARB_MODE
);
1140 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1141 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1143 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1144 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS(i
));
1146 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1147 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1149 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1150 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1151 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1152 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1154 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1156 /* MBC 0x9024-0x91D0, 0x8500 */
1157 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1158 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1159 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1161 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1162 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1163 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1164 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1165 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1166 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1167 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1169 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1170 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1171 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1172 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1173 s
->ecobus
= I915_READ(ECOBUS
);
1174 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1175 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1176 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1177 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1178 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1179 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1181 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1182 s
->gt_imr
= I915_READ(GTIMR
);
1183 s
->gt_ier
= I915_READ(GTIER
);
1184 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1185 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1187 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1188 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH(i
));
1190 /* GT SA CZ domain, 0x100000-0x138124 */
1191 s
->tilectl
= I915_READ(TILECTL
);
1192 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1193 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1194 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1195 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1197 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1198 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1199 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1200 s
->pcbr
= I915_READ(VLV_PCBR
);
1201 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1204 * Not saving any of:
1205 * DFT, 0x9800-0x9EC0
1206 * SARB, 0xB000-0xB1FC
1207 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1212 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1214 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1218 /* GAM 0x4000-0x4770 */
1219 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1220 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1221 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1222 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1223 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1225 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1226 I915_WRITE(GEN7_LRA_LIMITS(i
), s
->lra_limits
[i
]);
1228 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1229 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1231 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1232 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1233 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1234 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1236 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1238 /* MBC 0x9024-0x91D0, 0x8500 */
1239 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1240 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1241 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1243 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1244 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1245 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1246 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1247 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1248 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1249 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1251 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1252 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1253 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1254 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1255 I915_WRITE(ECOBUS
, s
->ecobus
);
1256 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1257 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1258 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1259 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1260 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1261 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1263 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1264 I915_WRITE(GTIMR
, s
->gt_imr
);
1265 I915_WRITE(GTIER
, s
->gt_ier
);
1266 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1267 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1269 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1270 I915_WRITE(GEN7_GT_SCRATCH(i
), s
->gt_scratch
[i
]);
1272 /* GT SA CZ domain, 0x100000-0x138124 */
1273 I915_WRITE(TILECTL
, s
->tilectl
);
1274 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1276 * Preserve the GT allow wake and GFX force clock bit, they are not
1277 * be restored, as they are used to control the s0ix suspend/resume
1278 * sequence by the caller.
1280 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1281 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1282 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1283 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1285 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1286 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1287 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1288 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1290 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1292 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1293 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1294 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1295 I915_WRITE(VLV_PCBR
, s
->pcbr
);
1296 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1299 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1304 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1306 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1307 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1309 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1310 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1315 err
= wait_for(COND
, 20);
1317 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1318 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1324 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1329 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1330 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1332 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1333 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1334 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1336 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1338 err
= wait_for(COND
, 1);
1340 DRM_ERROR("timeout disabling GT waking\n");
1345 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1352 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1353 val
= wait_for_on
? mask
: 0;
1354 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1358 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1360 I915_READ(VLV_GTLC_PW_STATUS
));
1363 * RC6 transitioning can be delayed up to 2 msec (see
1364 * valleyview_enable_rps), use 3 msec for safety.
1366 err
= wait_for(COND
, 3);
1368 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1369 onoff(wait_for_on
));
1375 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1377 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1380 DRM_DEBUG_DRIVER("GT register access while GT waking disabled\n");
1381 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1384 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1390 * Bspec defines the following GT well on flags as debug only, so
1391 * don't treat them as hard failures.
1393 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1395 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1396 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1398 vlv_check_no_gt_access(dev_priv
);
1400 err
= vlv_force_gfx_clock(dev_priv
, true);
1404 err
= vlv_allow_gt_wake(dev_priv
, false);
1408 if (!IS_CHERRYVIEW(dev_priv
))
1409 vlv_save_gunit_s0ix_state(dev_priv
);
1411 err
= vlv_force_gfx_clock(dev_priv
, false);
1418 /* For safety always re-enable waking and disable gfx clock forcing */
1419 vlv_allow_gt_wake(dev_priv
, true);
1421 vlv_force_gfx_clock(dev_priv
, false);
1426 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1429 struct drm_device
*dev
= dev_priv
->dev
;
1434 * If any of the steps fail just try to continue, that's the best we
1435 * can do at this point. Return the first error code (which will also
1436 * leave RPM permanently disabled).
1438 ret
= vlv_force_gfx_clock(dev_priv
, true);
1440 if (!IS_CHERRYVIEW(dev_priv
))
1441 vlv_restore_gunit_s0ix_state(dev_priv
);
1443 err
= vlv_allow_gt_wake(dev_priv
, true);
1447 err
= vlv_force_gfx_clock(dev_priv
, false);
1451 vlv_check_no_gt_access(dev_priv
);
1454 intel_init_clock_gating(dev
);
1455 i915_gem_restore_fences(dev
);
1461 static int intel_runtime_suspend(struct device
*device
)
1463 struct pci_dev
*pdev
= to_pci_dev(device
);
1464 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1465 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1468 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1471 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1474 DRM_DEBUG_KMS("Suspending device\n");
1477 * We could deadlock here in case another thread holding struct_mutex
1478 * calls RPM suspend concurrently, since the RPM suspend will wait
1479 * first for this RPM suspend to finish. In this case the concurrent
1480 * RPM resume will be followed by its RPM suspend counterpart. Still
1481 * for consistency return -EAGAIN, which will reschedule this suspend.
1483 if (!mutex_trylock(&dev
->struct_mutex
)) {
1484 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1486 * Bump the expiration timestamp, otherwise the suspend won't
1489 pm_runtime_mark_last_busy(device
);
1494 disable_rpm_wakeref_asserts(dev_priv
);
1497 * We are safe here against re-faults, since the fault handler takes
1500 i915_gem_release_all_mmaps(dev_priv
);
1501 mutex_unlock(&dev
->struct_mutex
);
1503 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1505 intel_guc_suspend(dev
);
1507 intel_suspend_gt_powersave(dev
);
1508 intel_runtime_pm_disable_interrupts(dev_priv
);
1511 if (IS_BROXTON(dev_priv
)) {
1512 bxt_display_core_uninit(dev_priv
);
1513 bxt_enable_dc9(dev_priv
);
1514 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1515 hsw_enable_pc8(dev_priv
);
1516 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1517 ret
= vlv_suspend_complete(dev_priv
);
1521 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1522 intel_runtime_pm_enable_interrupts(dev_priv
);
1524 enable_rpm_wakeref_asserts(dev_priv
);
1529 intel_uncore_forcewake_reset(dev
, false);
1531 enable_rpm_wakeref_asserts(dev_priv
);
1532 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1534 if (intel_uncore_arm_unclaimed_mmio_detection(dev_priv
))
1535 DRM_ERROR("Unclaimed access detected prior to suspending\n");
1537 dev_priv
->pm
.suspended
= true;
1540 * FIXME: We really should find a document that references the arguments
1543 if (IS_BROADWELL(dev
)) {
1545 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1546 * being detected, and the call we do at intel_runtime_resume()
1547 * won't be able to restore them. Since PCI_D3hot matches the
1548 * actual specification and appears to be working, use it.
1550 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1553 * current versions of firmware which depend on this opregion
1554 * notification have repurposed the D1 definition to mean
1555 * "runtime suspended" vs. what you would normally expect (D3)
1556 * to distinguish it from notifications that might be sent via
1559 intel_opregion_notify_adapter(dev
, PCI_D1
);
1562 assert_forcewakes_inactive(dev_priv
);
1564 DRM_DEBUG_KMS("Device suspended\n");
1568 static int intel_runtime_resume(struct device
*device
)
1570 struct pci_dev
*pdev
= to_pci_dev(device
);
1571 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1572 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1575 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1578 DRM_DEBUG_KMS("Resuming device\n");
1580 WARN_ON_ONCE(atomic_read(&dev_priv
->pm
.wakeref_count
));
1581 disable_rpm_wakeref_asserts(dev_priv
);
1583 intel_opregion_notify_adapter(dev
, PCI_D0
);
1584 dev_priv
->pm
.suspended
= false;
1585 if (intel_uncore_unclaimed_mmio(dev_priv
))
1586 DRM_DEBUG_DRIVER("Unclaimed access during suspend, bios?\n");
1588 intel_guc_resume(dev
);
1590 if (IS_GEN6(dev_priv
))
1591 intel_init_pch_refclk(dev
);
1593 if (IS_BROXTON(dev
)) {
1594 bxt_disable_dc9(dev_priv
);
1595 bxt_display_core_init(dev_priv
, true);
1596 if (dev_priv
->csr
.dmc_payload
&&
1597 (dev_priv
->csr
.allowed_dc_mask
& DC_STATE_EN_UPTO_DC5
))
1598 gen9_enable_dc5(dev_priv
);
1599 } else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
)) {
1600 hsw_disable_pc8(dev_priv
);
1601 } else if (IS_VALLEYVIEW(dev_priv
) || IS_CHERRYVIEW(dev_priv
)) {
1602 ret
= vlv_resume_prepare(dev_priv
, true);
1606 * No point of rolling back things in case of an error, as the best
1607 * we can do is to hope that things will still work (and disable RPM).
1609 i915_gem_init_swizzling(dev
);
1610 gen6_update_ring_freq(dev
);
1612 intel_runtime_pm_enable_interrupts(dev_priv
);
1615 * On VLV/CHV display interrupts are part of the display
1616 * power well, so hpd is reinitialized from there. For
1617 * everyone else do it here.
1619 if (!IS_VALLEYVIEW(dev_priv
) && !IS_CHERRYVIEW(dev_priv
))
1620 intel_hpd_init(dev_priv
);
1622 intel_enable_gt_powersave(dev
);
1624 enable_rpm_wakeref_asserts(dev_priv
);
1627 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1629 DRM_DEBUG_KMS("Device resumed\n");
1634 static const struct dev_pm_ops i915_pm_ops
= {
1636 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1639 .suspend
= i915_pm_suspend
,
1640 .suspend_late
= i915_pm_suspend_late
,
1641 .resume_early
= i915_pm_resume_early
,
1642 .resume
= i915_pm_resume
,
1646 * @freeze, @freeze_late : called (1) before creating the
1647 * hibernation image [PMSG_FREEZE] and
1648 * (2) after rebooting, before restoring
1649 * the image [PMSG_QUIESCE]
1650 * @thaw, @thaw_early : called (1) after creating the hibernation
1651 * image, before writing it [PMSG_THAW]
1652 * and (2) after failing to create or
1653 * restore the image [PMSG_RECOVER]
1654 * @poweroff, @poweroff_late: called after writing the hibernation
1655 * image, before rebooting [PMSG_HIBERNATE]
1656 * @restore, @restore_early : called after rebooting and restoring the
1657 * hibernation image [PMSG_RESTORE]
1659 .freeze
= i915_pm_suspend
,
1660 .freeze_late
= i915_pm_suspend_late
,
1661 .thaw_early
= i915_pm_resume_early
,
1662 .thaw
= i915_pm_resume
,
1663 .poweroff
= i915_pm_suspend
,
1664 .poweroff_late
= i915_pm_poweroff_late
,
1665 .restore_early
= i915_pm_resume_early
,
1666 .restore
= i915_pm_resume
,
1668 /* S0ix (via runtime suspend) event handlers */
1669 .runtime_suspend
= intel_runtime_suspend
,
1670 .runtime_resume
= intel_runtime_resume
,
1673 static const struct vm_operations_struct i915_gem_vm_ops
= {
1674 .fault
= i915_gem_fault
,
1675 .open
= drm_gem_vm_open
,
1676 .close
= drm_gem_vm_close
,
1679 static const struct file_operations i915_driver_fops
= {
1680 .owner
= THIS_MODULE
,
1682 .release
= drm_release
,
1683 .unlocked_ioctl
= drm_ioctl
,
1684 .mmap
= drm_gem_mmap
,
1687 #ifdef CONFIG_COMPAT
1688 .compat_ioctl
= i915_compat_ioctl
,
1690 .llseek
= noop_llseek
,
1693 static struct drm_driver driver
= {
1694 /* Don't use MTRRs here; the Xserver or userspace app should
1695 * deal with them for Intel hardware.
1698 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1699 DRIVER_RENDER
| DRIVER_MODESET
,
1700 .load
= i915_driver_load
,
1701 .unload
= i915_driver_unload
,
1702 .open
= i915_driver_open
,
1703 .lastclose
= i915_driver_lastclose
,
1704 .preclose
= i915_driver_preclose
,
1705 .postclose
= i915_driver_postclose
,
1706 .set_busid
= drm_pci_set_busid
,
1708 #if defined(CONFIG_DEBUG_FS)
1709 .debugfs_init
= i915_debugfs_init
,
1710 .debugfs_cleanup
= i915_debugfs_cleanup
,
1712 .gem_free_object
= i915_gem_free_object
,
1713 .gem_vm_ops
= &i915_gem_vm_ops
,
1715 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1716 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1717 .gem_prime_export
= i915_gem_prime_export
,
1718 .gem_prime_import
= i915_gem_prime_import
,
1720 .dumb_create
= i915_gem_dumb_create
,
1721 .dumb_map_offset
= i915_gem_mmap_gtt
,
1722 .dumb_destroy
= drm_gem_dumb_destroy
,
1723 .ioctls
= i915_ioctls
,
1724 .fops
= &i915_driver_fops
,
1725 .name
= DRIVER_NAME
,
1726 .desc
= DRIVER_DESC
,
1727 .date
= DRIVER_DATE
,
1728 .major
= DRIVER_MAJOR
,
1729 .minor
= DRIVER_MINOR
,
1730 .patchlevel
= DRIVER_PATCHLEVEL
,
1733 static struct pci_driver i915_pci_driver
= {
1734 .name
= DRIVER_NAME
,
1735 .id_table
= pciidlist
,
1736 .probe
= i915_pci_probe
,
1737 .remove
= i915_pci_remove
,
1738 .driver
.pm
= &i915_pm_ops
,
1741 static int __init
i915_init(void)
1743 driver
.num_ioctls
= i915_max_ioctl
;
1746 * Enable KMS by default, unless explicitly overriden by
1747 * either the i915.modeset prarameter or by the
1748 * vga_text_mode_force boot option.
1751 if (i915
.modeset
== 0)
1752 driver
.driver_features
&= ~DRIVER_MODESET
;
1754 if (vgacon_text_force() && i915
.modeset
== -1)
1755 driver
.driver_features
&= ~DRIVER_MODESET
;
1757 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1758 /* Silently fail loading to not upset userspace. */
1759 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1763 if (i915
.nuclear_pageflip
)
1764 driver
.driver_features
|= DRIVER_ATOMIC
;
1766 return drm_pci_init(&driver
, &i915_pci_driver
);
1769 static void __exit
i915_exit(void)
1771 if (!(driver
.driver_features
& DRIVER_MODESET
))
1772 return; /* Never loaded a driver. */
1774 drm_pci_exit(&driver
, &i915_pci_driver
);
1777 module_init(i915_init
);
1778 module_exit(i915_exit
);
1780 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1781 MODULE_AUTHOR("Intel Corporation");
1783 MODULE_DESCRIPTION(DRIVER_DESC
);
1784 MODULE_LICENSE("GPL and additional rights");