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drm/i915: info level for simulated gpu hang dmesg notice
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.c
1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #include <linux/device.h>
31 #include <drm/drmP.h>
32 #include <drm/i915_drm.h>
33 #include "i915_drv.h"
34 #include "i915_trace.h"
35 #include "intel_drv.h"
36
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
40
41 static int i915_modeset __read_mostly = -1;
42 module_param_named(modeset, i915_modeset, int, 0400);
43 MODULE_PARM_DESC(modeset,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
46
47 unsigned int i915_fbpercrtc __always_unused = 0;
48 module_param_named(fbpercrtc, i915_fbpercrtc, int, 0400);
49
50 int i915_panel_ignore_lid __read_mostly = 1;
51 module_param_named(panel_ignore_lid, i915_panel_ignore_lid, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
55
56 unsigned int i915_powersave __read_mostly = 1;
57 module_param_named(powersave, i915_powersave, int, 0600);
58 MODULE_PARM_DESC(powersave,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
60
61 int i915_semaphores __read_mostly = -1;
62 module_param_named(semaphores, i915_semaphores, int, 0600);
63 MODULE_PARM_DESC(semaphores,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
65
66 int i915_enable_rc6 __read_mostly = -1;
67 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
74
75 int i915_enable_fbc __read_mostly = -1;
76 module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
80
81 unsigned int i915_lvds_downclock __read_mostly = 0;
82 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock,
84 "Use panel (LVDS/eDP) downclocking for power savings "
85 "(default: false)");
86
87 int i915_lvds_channel_mode __read_mostly;
88 module_param_named(lvds_channel_mode, i915_lvds_channel_mode, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
92
93 int i915_panel_use_ssc __read_mostly = -1;
94 module_param_named(lvds_use_ssc, i915_panel_use_ssc, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
98
99 int i915_vbt_sdvo_panel_type __read_mostly = -1;
100 module_param_named(vbt_sdvo_panel_type, i915_vbt_sdvo_panel_type, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
104
105 static bool i915_try_reset __read_mostly = true;
106 module_param_named(reset, i915_try_reset, bool, 0600);
107 MODULE_PARM_DESC(reset, "Attempt GPU resets (default: true)");
108
109 bool i915_enable_hangcheck __read_mostly = true;
110 module_param_named(enable_hangcheck, i915_enable_hangcheck, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
114 "(default: true)");
115
116 int i915_enable_ppgtt __read_mostly = -1;
117 module_param_named(i915_enable_ppgtt, i915_enable_ppgtt, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt,
119 "Enable PPGTT (default: true)");
120
121 unsigned int i915_preliminary_hw_support __read_mostly = 0;
122 module_param_named(preliminary_hw_support, i915_preliminary_hw_support, int, 0600);
123 MODULE_PARM_DESC(preliminary_hw_support,
124 "Enable preliminary hardware support. (default: false)");
125
126 int i915_disable_power_well __read_mostly = 0;
127 module_param_named(disable_power_well, i915_disable_power_well, int, 0600);
128 MODULE_PARM_DESC(disable_power_well,
129 "Disable the power well when possible (default: false)");
130
131 static struct drm_driver driver;
132 extern int intel_agp_enabled;
133
134 #define INTEL_VGA_DEVICE(id, info) { \
135 .class = PCI_BASE_CLASS_DISPLAY << 16, \
136 .class_mask = 0xff0000, \
137 .vendor = 0x8086, \
138 .device = id, \
139 .subvendor = PCI_ANY_ID, \
140 .subdevice = PCI_ANY_ID, \
141 .driver_data = (unsigned long) info }
142
143 static const struct intel_device_info intel_i830_info = {
144 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1, .num_pipes = 2,
145 .has_overlay = 1, .overlay_needs_physical = 1,
146 };
147
148 static const struct intel_device_info intel_845g_info = {
149 .gen = 2, .num_pipes = 1,
150 .has_overlay = 1, .overlay_needs_physical = 1,
151 };
152
153 static const struct intel_device_info intel_i85x_info = {
154 .gen = 2, .is_i85x = 1, .is_mobile = 1, .num_pipes = 2,
155 .cursor_needs_physical = 1,
156 .has_overlay = 1, .overlay_needs_physical = 1,
157 };
158
159 static const struct intel_device_info intel_i865g_info = {
160 .gen = 2, .num_pipes = 1,
161 .has_overlay = 1, .overlay_needs_physical = 1,
162 };
163
164 static const struct intel_device_info intel_i915g_info = {
165 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1, .num_pipes = 2,
166 .has_overlay = 1, .overlay_needs_physical = 1,
167 };
168 static const struct intel_device_info intel_i915gm_info = {
169 .gen = 3, .is_mobile = 1, .num_pipes = 2,
170 .cursor_needs_physical = 1,
171 .has_overlay = 1, .overlay_needs_physical = 1,
172 .supports_tv = 1,
173 };
174 static const struct intel_device_info intel_i945g_info = {
175 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1, .num_pipes = 2,
176 .has_overlay = 1, .overlay_needs_physical = 1,
177 };
178 static const struct intel_device_info intel_i945gm_info = {
179 .gen = 3, .is_i945gm = 1, .is_mobile = 1, .num_pipes = 2,
180 .has_hotplug = 1, .cursor_needs_physical = 1,
181 .has_overlay = 1, .overlay_needs_physical = 1,
182 .supports_tv = 1,
183 };
184
185 static const struct intel_device_info intel_i965g_info = {
186 .gen = 4, .is_broadwater = 1, .num_pipes = 2,
187 .has_hotplug = 1,
188 .has_overlay = 1,
189 };
190
191 static const struct intel_device_info intel_i965gm_info = {
192 .gen = 4, .is_crestline = 1, .num_pipes = 2,
193 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
194 .has_overlay = 1,
195 .supports_tv = 1,
196 };
197
198 static const struct intel_device_info intel_g33_info = {
199 .gen = 3, .is_g33 = 1, .num_pipes = 2,
200 .need_gfx_hws = 1, .has_hotplug = 1,
201 .has_overlay = 1,
202 };
203
204 static const struct intel_device_info intel_g45_info = {
205 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1, .num_pipes = 2,
206 .has_pipe_cxsr = 1, .has_hotplug = 1,
207 .has_bsd_ring = 1,
208 };
209
210 static const struct intel_device_info intel_gm45_info = {
211 .gen = 4, .is_g4x = 1, .num_pipes = 2,
212 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
213 .has_pipe_cxsr = 1, .has_hotplug = 1,
214 .supports_tv = 1,
215 .has_bsd_ring = 1,
216 };
217
218 static const struct intel_device_info intel_pineview_info = {
219 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1, .num_pipes = 2,
220 .need_gfx_hws = 1, .has_hotplug = 1,
221 .has_overlay = 1,
222 };
223
224 static const struct intel_device_info intel_ironlake_d_info = {
225 .gen = 5, .num_pipes = 2,
226 .need_gfx_hws = 1, .has_hotplug = 1,
227 .has_bsd_ring = 1,
228 };
229
230 static const struct intel_device_info intel_ironlake_m_info = {
231 .gen = 5, .is_mobile = 1, .num_pipes = 2,
232 .need_gfx_hws = 1, .has_hotplug = 1,
233 .has_fbc = 1,
234 .has_bsd_ring = 1,
235 };
236
237 static const struct intel_device_info intel_sandybridge_d_info = {
238 .gen = 6, .num_pipes = 2,
239 .need_gfx_hws = 1, .has_hotplug = 1,
240 .has_bsd_ring = 1,
241 .has_blt_ring = 1,
242 .has_llc = 1,
243 .has_force_wake = 1,
244 };
245
246 static const struct intel_device_info intel_sandybridge_m_info = {
247 .gen = 6, .is_mobile = 1, .num_pipes = 2,
248 .need_gfx_hws = 1, .has_hotplug = 1,
249 .has_fbc = 1,
250 .has_bsd_ring = 1,
251 .has_blt_ring = 1,
252 .has_llc = 1,
253 .has_force_wake = 1,
254 };
255
256 #define GEN7_FEATURES \
257 .gen = 7, .num_pipes = 3, \
258 .need_gfx_hws = 1, .has_hotplug = 1, \
259 .has_bsd_ring = 1, \
260 .has_blt_ring = 1, \
261 .has_llc = 1, \
262 .has_force_wake = 1
263
264 static const struct intel_device_info intel_ivybridge_d_info = {
265 GEN7_FEATURES,
266 .is_ivybridge = 1,
267 };
268
269 static const struct intel_device_info intel_ivybridge_m_info = {
270 GEN7_FEATURES,
271 .is_ivybridge = 1,
272 .is_mobile = 1,
273 };
274
275 static const struct intel_device_info intel_valleyview_m_info = {
276 GEN7_FEATURES,
277 .is_mobile = 1,
278 .num_pipes = 2,
279 .is_valleyview = 1,
280 .display_mmio_offset = VLV_DISPLAY_BASE,
281 };
282
283 static const struct intel_device_info intel_valleyview_d_info = {
284 GEN7_FEATURES,
285 .num_pipes = 2,
286 .is_valleyview = 1,
287 .display_mmio_offset = VLV_DISPLAY_BASE,
288 };
289
290 static const struct intel_device_info intel_haswell_d_info = {
291 GEN7_FEATURES,
292 .is_haswell = 1,
293 };
294
295 static const struct intel_device_info intel_haswell_m_info = {
296 GEN7_FEATURES,
297 .is_haswell = 1,
298 .is_mobile = 1,
299 };
300
301 static const struct pci_device_id pciidlist[] = { /* aka */
302 INTEL_VGA_DEVICE(0x3577, &intel_i830_info), /* I830_M */
303 INTEL_VGA_DEVICE(0x2562, &intel_845g_info), /* 845_G */
304 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info), /* I855_GM */
305 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
306 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info), /* I865_G */
307 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info), /* I915_G */
308 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info), /* E7221_G */
309 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info), /* I915_GM */
310 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info), /* I945_G */
311 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info), /* I945_GM */
312 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info), /* I945_GME */
313 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info), /* I946_GZ */
314 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info), /* G35_G */
315 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info), /* I965_Q */
316 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info), /* I965_G */
317 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info), /* Q35_G */
318 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info), /* G33_G */
319 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info), /* Q33_G */
320 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info), /* I965_GM */
321 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info), /* I965_GME */
322 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info), /* GM45_G */
323 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info), /* IGD_E_G */
324 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info), /* Q45_G */
325 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info), /* G45_G */
326 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info), /* G41_G */
327 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info), /* B43_G */
328 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info), /* B43_G.1 */
329 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
330 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
331 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
332 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
333 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
334 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
335 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
336 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
337 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
338 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
339 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
340 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
341 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
342 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
343 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
344 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
345 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
346 INTEL_VGA_DEVICE(0x0402, &intel_haswell_d_info), /* GT1 desktop */
347 INTEL_VGA_DEVICE(0x0412, &intel_haswell_d_info), /* GT2 desktop */
348 INTEL_VGA_DEVICE(0x0422, &intel_haswell_d_info), /* GT2 desktop */
349 INTEL_VGA_DEVICE(0x040a, &intel_haswell_d_info), /* GT1 server */
350 INTEL_VGA_DEVICE(0x041a, &intel_haswell_d_info), /* GT2 server */
351 INTEL_VGA_DEVICE(0x042a, &intel_haswell_d_info), /* GT2 server */
352 INTEL_VGA_DEVICE(0x0406, &intel_haswell_m_info), /* GT1 mobile */
353 INTEL_VGA_DEVICE(0x0416, &intel_haswell_m_info), /* GT2 mobile */
354 INTEL_VGA_DEVICE(0x0426, &intel_haswell_m_info), /* GT2 mobile */
355 INTEL_VGA_DEVICE(0x0C02, &intel_haswell_d_info), /* SDV GT1 desktop */
356 INTEL_VGA_DEVICE(0x0C12, &intel_haswell_d_info), /* SDV GT2 desktop */
357 INTEL_VGA_DEVICE(0x0C22, &intel_haswell_d_info), /* SDV GT2 desktop */
358 INTEL_VGA_DEVICE(0x0C0A, &intel_haswell_d_info), /* SDV GT1 server */
359 INTEL_VGA_DEVICE(0x0C1A, &intel_haswell_d_info), /* SDV GT2 server */
360 INTEL_VGA_DEVICE(0x0C2A, &intel_haswell_d_info), /* SDV GT2 server */
361 INTEL_VGA_DEVICE(0x0C06, &intel_haswell_m_info), /* SDV GT1 mobile */
362 INTEL_VGA_DEVICE(0x0C16, &intel_haswell_m_info), /* SDV GT2 mobile */
363 INTEL_VGA_DEVICE(0x0C26, &intel_haswell_m_info), /* SDV GT2 mobile */
364 INTEL_VGA_DEVICE(0x0A02, &intel_haswell_d_info), /* ULT GT1 desktop */
365 INTEL_VGA_DEVICE(0x0A12, &intel_haswell_d_info), /* ULT GT2 desktop */
366 INTEL_VGA_DEVICE(0x0A22, &intel_haswell_d_info), /* ULT GT2 desktop */
367 INTEL_VGA_DEVICE(0x0A0A, &intel_haswell_d_info), /* ULT GT1 server */
368 INTEL_VGA_DEVICE(0x0A1A, &intel_haswell_d_info), /* ULT GT2 server */
369 INTEL_VGA_DEVICE(0x0A2A, &intel_haswell_d_info), /* ULT GT2 server */
370 INTEL_VGA_DEVICE(0x0A06, &intel_haswell_m_info), /* ULT GT1 mobile */
371 INTEL_VGA_DEVICE(0x0A16, &intel_haswell_m_info), /* ULT GT2 mobile */
372 INTEL_VGA_DEVICE(0x0A26, &intel_haswell_m_info), /* ULT GT2 mobile */
373 INTEL_VGA_DEVICE(0x0D02, &intel_haswell_d_info), /* CRW GT1 desktop */
374 INTEL_VGA_DEVICE(0x0D12, &intel_haswell_d_info), /* CRW GT2 desktop */
375 INTEL_VGA_DEVICE(0x0D22, &intel_haswell_d_info), /* CRW GT2 desktop */
376 INTEL_VGA_DEVICE(0x0D0A, &intel_haswell_d_info), /* CRW GT1 server */
377 INTEL_VGA_DEVICE(0x0D1A, &intel_haswell_d_info), /* CRW GT2 server */
378 INTEL_VGA_DEVICE(0x0D2A, &intel_haswell_d_info), /* CRW GT2 server */
379 INTEL_VGA_DEVICE(0x0D06, &intel_haswell_m_info), /* CRW GT1 mobile */
380 INTEL_VGA_DEVICE(0x0D16, &intel_haswell_m_info), /* CRW GT2 mobile */
381 INTEL_VGA_DEVICE(0x0D26, &intel_haswell_m_info), /* CRW GT2 mobile */
382 INTEL_VGA_DEVICE(0x0f30, &intel_valleyview_m_info),
383 INTEL_VGA_DEVICE(0x0f31, &intel_valleyview_m_info),
384 INTEL_VGA_DEVICE(0x0f32, &intel_valleyview_m_info),
385 INTEL_VGA_DEVICE(0x0f33, &intel_valleyview_m_info),
386 INTEL_VGA_DEVICE(0x0157, &intel_valleyview_m_info),
387 INTEL_VGA_DEVICE(0x0155, &intel_valleyview_d_info),
388 {0, 0, 0}
389 };
390
391 #if defined(CONFIG_DRM_I915_KMS)
392 MODULE_DEVICE_TABLE(pci, pciidlist);
393 #endif
394
395 void intel_detect_pch(struct drm_device *dev)
396 {
397 struct drm_i915_private *dev_priv = dev->dev_private;
398 struct pci_dev *pch;
399
400 /*
401 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
402 * make graphics device passthrough work easy for VMM, that only
403 * need to expose ISA bridge to let driver know the real hardware
404 * underneath. This is a requirement from virtualization team.
405 */
406 pch = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
407 if (pch) {
408 if (pch->vendor == PCI_VENDOR_ID_INTEL) {
409 unsigned short id;
410 id = pch->device & INTEL_PCH_DEVICE_ID_MASK;
411 dev_priv->pch_id = id;
412
413 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
414 dev_priv->pch_type = PCH_IBX;
415 dev_priv->num_pch_pll = 2;
416 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
417 WARN_ON(!IS_GEN5(dev));
418 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
419 dev_priv->pch_type = PCH_CPT;
420 dev_priv->num_pch_pll = 2;
421 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
422 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
423 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
424 /* PantherPoint is CPT compatible */
425 dev_priv->pch_type = PCH_CPT;
426 dev_priv->num_pch_pll = 2;
427 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
428 WARN_ON(!(IS_GEN6(dev) || IS_IVYBRIDGE(dev)));
429 } else if (id == INTEL_PCH_LPT_DEVICE_ID_TYPE) {
430 dev_priv->pch_type = PCH_LPT;
431 dev_priv->num_pch_pll = 0;
432 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
433 WARN_ON(!IS_HASWELL(dev));
434 } else if (id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
435 dev_priv->pch_type = PCH_LPT;
436 dev_priv->num_pch_pll = 0;
437 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
438 WARN_ON(!IS_HASWELL(dev));
439 }
440 BUG_ON(dev_priv->num_pch_pll > I915_NUM_PLLS);
441 }
442 pci_dev_put(pch);
443 }
444 }
445
446 bool i915_semaphore_is_enabled(struct drm_device *dev)
447 {
448 if (INTEL_INFO(dev)->gen < 6)
449 return 0;
450
451 if (i915_semaphores >= 0)
452 return i915_semaphores;
453
454 #ifdef CONFIG_INTEL_IOMMU
455 /* Enable semaphores on SNB when IO remapping is off */
456 if (INTEL_INFO(dev)->gen == 6 && intel_iommu_gfx_mapped)
457 return false;
458 #endif
459
460 return 1;
461 }
462
463 static int i915_drm_freeze(struct drm_device *dev)
464 {
465 struct drm_i915_private *dev_priv = dev->dev_private;
466 struct drm_crtc *crtc;
467
468 /* ignore lid events during suspend */
469 mutex_lock(&dev_priv->modeset_restore_lock);
470 dev_priv->modeset_restore = MODESET_SUSPENDED;
471 mutex_unlock(&dev_priv->modeset_restore_lock);
472
473 intel_set_power_well(dev, true);
474
475 drm_kms_helper_poll_disable(dev);
476
477 pci_save_state(dev->pdev);
478
479 /* If KMS is active, we do the leavevt stuff here */
480 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
481 int error = i915_gem_idle(dev);
482 if (error) {
483 dev_err(&dev->pdev->dev,
484 "GEM idle failed, resume might fail\n");
485 return error;
486 }
487
488 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
489
490 drm_irq_uninstall(dev);
491 dev_priv->enable_hotplug_processing = false;
492 /*
493 * Disable CRTCs directly since we want to preserve sw state
494 * for _thaw.
495 */
496 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
497 dev_priv->display.crtc_disable(crtc);
498 }
499
500 i915_save_state(dev);
501
502 intel_opregion_fini(dev);
503
504 console_lock();
505 intel_fbdev_set_suspend(dev, 1);
506 console_unlock();
507
508 return 0;
509 }
510
511 int i915_suspend(struct drm_device *dev, pm_message_t state)
512 {
513 int error;
514
515 if (!dev || !dev->dev_private) {
516 DRM_ERROR("dev: %p\n", dev);
517 DRM_ERROR("DRM not initialized, aborting suspend.\n");
518 return -ENODEV;
519 }
520
521 if (state.event == PM_EVENT_PRETHAW)
522 return 0;
523
524
525 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
526 return 0;
527
528 error = i915_drm_freeze(dev);
529 if (error)
530 return error;
531
532 if (state.event == PM_EVENT_SUSPEND) {
533 /* Shut down the device */
534 pci_disable_device(dev->pdev);
535 pci_set_power_state(dev->pdev, PCI_D3hot);
536 }
537
538 return 0;
539 }
540
541 void intel_console_resume(struct work_struct *work)
542 {
543 struct drm_i915_private *dev_priv =
544 container_of(work, struct drm_i915_private,
545 console_resume_work);
546 struct drm_device *dev = dev_priv->dev;
547
548 console_lock();
549 intel_fbdev_set_suspend(dev, 0);
550 console_unlock();
551 }
552
553 static void intel_resume_hotplug(struct drm_device *dev)
554 {
555 struct drm_mode_config *mode_config = &dev->mode_config;
556 struct intel_encoder *encoder;
557
558 mutex_lock(&mode_config->mutex);
559 DRM_DEBUG_KMS("running encoder hotplug functions\n");
560
561 list_for_each_entry(encoder, &mode_config->encoder_list, base.head)
562 if (encoder->hot_plug)
563 encoder->hot_plug(encoder);
564
565 mutex_unlock(&mode_config->mutex);
566
567 /* Just fire off a uevent and let userspace tell us what to do */
568 drm_helper_hpd_irq_event(dev);
569 }
570
571 static int __i915_drm_thaw(struct drm_device *dev)
572 {
573 struct drm_i915_private *dev_priv = dev->dev_private;
574 int error = 0;
575
576 i915_restore_state(dev);
577 intel_opregion_setup(dev);
578
579 /* KMS EnterVT equivalent */
580 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
581 intel_init_pch_refclk(dev);
582
583 mutex_lock(&dev->struct_mutex);
584 dev_priv->mm.suspended = 0;
585
586 error = i915_gem_init_hw(dev);
587 mutex_unlock(&dev->struct_mutex);
588
589 /* We need working interrupts for modeset enabling ... */
590 drm_irq_install(dev);
591
592 intel_modeset_init_hw(dev);
593
594 drm_modeset_lock_all(dev);
595 intel_modeset_setup_hw_state(dev, true);
596 drm_modeset_unlock_all(dev);
597
598 /*
599 * ... but also need to make sure that hotplug processing
600 * doesn't cause havoc. Like in the driver load code we don't
601 * bother with the tiny race here where we might loose hotplug
602 * notifications.
603 * */
604 intel_hpd_init(dev);
605 dev_priv->enable_hotplug_processing = true;
606 /* Config may have changed between suspend and resume */
607 intel_resume_hotplug(dev);
608 }
609
610 intel_opregion_init(dev);
611
612 /*
613 * The console lock can be pretty contented on resume due
614 * to all the printk activity. Try to keep it out of the hot
615 * path of resume if possible.
616 */
617 if (console_trylock()) {
618 intel_fbdev_set_suspend(dev, 0);
619 console_unlock();
620 } else {
621 schedule_work(&dev_priv->console_resume_work);
622 }
623
624 mutex_lock(&dev_priv->modeset_restore_lock);
625 dev_priv->modeset_restore = MODESET_DONE;
626 mutex_unlock(&dev_priv->modeset_restore_lock);
627 return error;
628 }
629
630 static int i915_drm_thaw(struct drm_device *dev)
631 {
632 int error = 0;
633
634 intel_gt_reset(dev);
635
636 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
637 mutex_lock(&dev->struct_mutex);
638 i915_gem_restore_gtt_mappings(dev);
639 mutex_unlock(&dev->struct_mutex);
640 }
641
642 __i915_drm_thaw(dev);
643
644 return error;
645 }
646
647 int i915_resume(struct drm_device *dev)
648 {
649 struct drm_i915_private *dev_priv = dev->dev_private;
650 int ret;
651
652 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
653 return 0;
654
655 if (pci_enable_device(dev->pdev))
656 return -EIO;
657
658 pci_set_master(dev->pdev);
659
660 intel_gt_reset(dev);
661
662 /*
663 * Platforms with opregion should have sane BIOS, older ones (gen3 and
664 * earlier) need this since the BIOS might clear all our scratch PTEs.
665 */
666 if (drm_core_check_feature(dev, DRIVER_MODESET) &&
667 !dev_priv->opregion.header) {
668 mutex_lock(&dev->struct_mutex);
669 i915_gem_restore_gtt_mappings(dev);
670 mutex_unlock(&dev->struct_mutex);
671 }
672
673 ret = __i915_drm_thaw(dev);
674 if (ret)
675 return ret;
676
677 drm_kms_helper_poll_enable(dev);
678 return 0;
679 }
680
681 static int i8xx_do_reset(struct drm_device *dev)
682 {
683 struct drm_i915_private *dev_priv = dev->dev_private;
684
685 if (IS_I85X(dev))
686 return -ENODEV;
687
688 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
689 POSTING_READ(D_STATE);
690
691 if (IS_I830(dev) || IS_845G(dev)) {
692 I915_WRITE(DEBUG_RESET_I830,
693 DEBUG_RESET_DISPLAY |
694 DEBUG_RESET_RENDER |
695 DEBUG_RESET_FULL);
696 POSTING_READ(DEBUG_RESET_I830);
697 msleep(1);
698
699 I915_WRITE(DEBUG_RESET_I830, 0);
700 POSTING_READ(DEBUG_RESET_I830);
701 }
702
703 msleep(1);
704
705 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
706 POSTING_READ(D_STATE);
707
708 return 0;
709 }
710
711 static int i965_reset_complete(struct drm_device *dev)
712 {
713 u8 gdrst;
714 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
715 return (gdrst & GRDOM_RESET_ENABLE) == 0;
716 }
717
718 static int i965_do_reset(struct drm_device *dev)
719 {
720 int ret;
721 u8 gdrst;
722
723 /*
724 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
725 * well as the reset bit (GR/bit 0). Setting the GR bit
726 * triggers the reset; when done, the hardware will clear it.
727 */
728 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
729 pci_write_config_byte(dev->pdev, I965_GDRST,
730 gdrst | GRDOM_RENDER |
731 GRDOM_RESET_ENABLE);
732 ret = wait_for(i965_reset_complete(dev), 500);
733 if (ret)
734 return ret;
735
736 /* We can't reset render&media without also resetting display ... */
737 pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst);
738 pci_write_config_byte(dev->pdev, I965_GDRST,
739 gdrst | GRDOM_MEDIA |
740 GRDOM_RESET_ENABLE);
741
742 return wait_for(i965_reset_complete(dev), 500);
743 }
744
745 static int ironlake_do_reset(struct drm_device *dev)
746 {
747 struct drm_i915_private *dev_priv = dev->dev_private;
748 u32 gdrst;
749 int ret;
750
751 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
752 gdrst &= ~GRDOM_MASK;
753 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
754 gdrst | GRDOM_RENDER | GRDOM_RESET_ENABLE);
755 ret = wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
756 if (ret)
757 return ret;
758
759 /* We can't reset render&media without also resetting display ... */
760 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
761 gdrst &= ~GRDOM_MASK;
762 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR,
763 gdrst | GRDOM_MEDIA | GRDOM_RESET_ENABLE);
764 return wait_for(I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1, 500);
765 }
766
767 static int gen6_do_reset(struct drm_device *dev)
768 {
769 struct drm_i915_private *dev_priv = dev->dev_private;
770 int ret;
771 unsigned long irqflags;
772
773 /* Hold gt_lock across reset to prevent any register access
774 * with forcewake not set correctly
775 */
776 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
777
778 /* Reset the chip */
779
780 /* GEN6_GDRST is not in the gt power well, no need to check
781 * for fifo space for the write or forcewake the chip for
782 * the read
783 */
784 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
785
786 /* Spin waiting for the device to ack the reset request */
787 ret = wait_for((I915_READ_NOTRACE(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500);
788
789 /* If reset with a user forcewake, try to restore, otherwise turn it off */
790 if (dev_priv->forcewake_count)
791 dev_priv->gt.force_wake_get(dev_priv);
792 else
793 dev_priv->gt.force_wake_put(dev_priv);
794
795 /* Restore fifo count */
796 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
797
798 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
799 return ret;
800 }
801
802 int intel_gpu_reset(struct drm_device *dev)
803 {
804 struct drm_i915_private *dev_priv = dev->dev_private;
805 int ret = -ENODEV;
806
807 switch (INTEL_INFO(dev)->gen) {
808 case 7:
809 case 6:
810 ret = gen6_do_reset(dev);
811 break;
812 case 5:
813 ret = ironlake_do_reset(dev);
814 break;
815 case 4:
816 ret = i965_do_reset(dev);
817 break;
818 case 2:
819 ret = i8xx_do_reset(dev);
820 break;
821 }
822
823 /* Also reset the gpu hangman. */
824 if (dev_priv->gpu_error.stop_rings) {
825 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
826 dev_priv->gpu_error.stop_rings = 0;
827 if (ret == -ENODEV) {
828 DRM_ERROR("Reset not implemented, but ignoring "
829 "error for simulated gpu hangs\n");
830 ret = 0;
831 }
832 }
833
834 return ret;
835 }
836
837 /**
838 * i915_reset - reset chip after a hang
839 * @dev: drm device to reset
840 *
841 * Reset the chip. Useful if a hang is detected. Returns zero on successful
842 * reset or otherwise an error code.
843 *
844 * Procedure is fairly simple:
845 * - reset the chip using the reset reg
846 * - re-init context state
847 * - re-init hardware status page
848 * - re-init ring buffer
849 * - re-init interrupt state
850 * - re-init display
851 */
852 int i915_reset(struct drm_device *dev)
853 {
854 drm_i915_private_t *dev_priv = dev->dev_private;
855 int ret;
856
857 if (!i915_try_reset)
858 return 0;
859
860 mutex_lock(&dev->struct_mutex);
861
862 i915_gem_reset(dev);
863
864 ret = -ENODEV;
865 if (get_seconds() - dev_priv->gpu_error.last_reset < 5)
866 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
867 else
868 ret = intel_gpu_reset(dev);
869
870 dev_priv->gpu_error.last_reset = get_seconds();
871 if (ret) {
872 DRM_ERROR("Failed to reset chip.\n");
873 mutex_unlock(&dev->struct_mutex);
874 return ret;
875 }
876
877 /* Ok, now get things going again... */
878
879 /*
880 * Everything depends on having the GTT running, so we need to start
881 * there. Fortunately we don't need to do this unless we reset the
882 * chip at a PCI level.
883 *
884 * Next we need to restore the context, but we don't use those
885 * yet either...
886 *
887 * Ring buffer needs to be re-initialized in the KMS case, or if X
888 * was running at the time of the reset (i.e. we weren't VT
889 * switched away).
890 */
891 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
892 !dev_priv->mm.suspended) {
893 struct intel_ring_buffer *ring;
894 int i;
895
896 dev_priv->mm.suspended = 0;
897
898 i915_gem_init_swizzling(dev);
899
900 for_each_ring(ring, dev_priv, i)
901 ring->init(ring);
902
903 i915_gem_context_init(dev);
904 i915_gem_init_ppgtt(dev);
905
906 /*
907 * It would make sense to re-init all the other hw state, at
908 * least the rps/rc6/emon init done within modeset_init_hw. For
909 * some unknown reason, this blows up my ilk, so don't.
910 */
911
912 mutex_unlock(&dev->struct_mutex);
913
914 drm_irq_uninstall(dev);
915 drm_irq_install(dev);
916 intel_hpd_init(dev);
917 } else {
918 mutex_unlock(&dev->struct_mutex);
919 }
920
921 return 0;
922 }
923
924 static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
925 {
926 struct intel_device_info *intel_info =
927 (struct intel_device_info *) ent->driver_data;
928
929 if (intel_info->is_valleyview)
930 if(!i915_preliminary_hw_support) {
931 DRM_ERROR("Preliminary hardware support disabled\n");
932 return -ENODEV;
933 }
934
935 /* Only bind to function 0 of the device. Early generations
936 * used function 1 as a placeholder for multi-head. This causes
937 * us confusion instead, especially on the systems where both
938 * functions have the same PCI-ID!
939 */
940 if (PCI_FUNC(pdev->devfn))
941 return -ENODEV;
942
943 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
944 * implementation for gen3 (and only gen3) that used legacy drm maps
945 * (gasp!) to share buffers between X and the client. Hence we need to
946 * keep around the fake agp stuff for gen3, even when kms is enabled. */
947 if (intel_info->gen != 3) {
948 driver.driver_features &=
949 ~(DRIVER_USE_AGP | DRIVER_REQUIRE_AGP);
950 } else if (!intel_agp_enabled) {
951 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
952 return -ENODEV;
953 }
954
955 return drm_get_pci_dev(pdev, ent, &driver);
956 }
957
958 static void
959 i915_pci_remove(struct pci_dev *pdev)
960 {
961 struct drm_device *dev = pci_get_drvdata(pdev);
962
963 drm_put_dev(dev);
964 }
965
966 static int i915_pm_suspend(struct device *dev)
967 {
968 struct pci_dev *pdev = to_pci_dev(dev);
969 struct drm_device *drm_dev = pci_get_drvdata(pdev);
970 int error;
971
972 if (!drm_dev || !drm_dev->dev_private) {
973 dev_err(dev, "DRM not initialized, aborting suspend.\n");
974 return -ENODEV;
975 }
976
977 if (drm_dev->switch_power_state == DRM_SWITCH_POWER_OFF)
978 return 0;
979
980 error = i915_drm_freeze(drm_dev);
981 if (error)
982 return error;
983
984 pci_disable_device(pdev);
985 pci_set_power_state(pdev, PCI_D3hot);
986
987 return 0;
988 }
989
990 static int i915_pm_resume(struct device *dev)
991 {
992 struct pci_dev *pdev = to_pci_dev(dev);
993 struct drm_device *drm_dev = pci_get_drvdata(pdev);
994
995 return i915_resume(drm_dev);
996 }
997
998 static int i915_pm_freeze(struct device *dev)
999 {
1000 struct pci_dev *pdev = to_pci_dev(dev);
1001 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1002
1003 if (!drm_dev || !drm_dev->dev_private) {
1004 dev_err(dev, "DRM not initialized, aborting suspend.\n");
1005 return -ENODEV;
1006 }
1007
1008 return i915_drm_freeze(drm_dev);
1009 }
1010
1011 static int i915_pm_thaw(struct device *dev)
1012 {
1013 struct pci_dev *pdev = to_pci_dev(dev);
1014 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1015
1016 return i915_drm_thaw(drm_dev);
1017 }
1018
1019 static int i915_pm_poweroff(struct device *dev)
1020 {
1021 struct pci_dev *pdev = to_pci_dev(dev);
1022 struct drm_device *drm_dev = pci_get_drvdata(pdev);
1023
1024 return i915_drm_freeze(drm_dev);
1025 }
1026
1027 static const struct dev_pm_ops i915_pm_ops = {
1028 .suspend = i915_pm_suspend,
1029 .resume = i915_pm_resume,
1030 .freeze = i915_pm_freeze,
1031 .thaw = i915_pm_thaw,
1032 .poweroff = i915_pm_poweroff,
1033 .restore = i915_pm_resume,
1034 };
1035
1036 static const struct vm_operations_struct i915_gem_vm_ops = {
1037 .fault = i915_gem_fault,
1038 .open = drm_gem_vm_open,
1039 .close = drm_gem_vm_close,
1040 };
1041
1042 static const struct file_operations i915_driver_fops = {
1043 .owner = THIS_MODULE,
1044 .open = drm_open,
1045 .release = drm_release,
1046 .unlocked_ioctl = drm_ioctl,
1047 .mmap = drm_gem_mmap,
1048 .poll = drm_poll,
1049 .fasync = drm_fasync,
1050 .read = drm_read,
1051 #ifdef CONFIG_COMPAT
1052 .compat_ioctl = i915_compat_ioctl,
1053 #endif
1054 .llseek = noop_llseek,
1055 };
1056
1057 static struct drm_driver driver = {
1058 /* Don't use MTRRs here; the Xserver or userspace app should
1059 * deal with them for Intel hardware.
1060 */
1061 .driver_features =
1062 DRIVER_USE_AGP | DRIVER_REQUIRE_AGP | /* DRIVER_USE_MTRR |*/
1063 DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM | DRIVER_PRIME,
1064 .load = i915_driver_load,
1065 .unload = i915_driver_unload,
1066 .open = i915_driver_open,
1067 .lastclose = i915_driver_lastclose,
1068 .preclose = i915_driver_preclose,
1069 .postclose = i915_driver_postclose,
1070
1071 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1072 .suspend = i915_suspend,
1073 .resume = i915_resume,
1074
1075 .device_is_agp = i915_driver_device_is_agp,
1076 .master_create = i915_master_create,
1077 .master_destroy = i915_master_destroy,
1078 #if defined(CONFIG_DEBUG_FS)
1079 .debugfs_init = i915_debugfs_init,
1080 .debugfs_cleanup = i915_debugfs_cleanup,
1081 #endif
1082 .gem_init_object = i915_gem_init_object,
1083 .gem_free_object = i915_gem_free_object,
1084 .gem_vm_ops = &i915_gem_vm_ops,
1085
1086 .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1087 .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1088 .gem_prime_export = i915_gem_prime_export,
1089 .gem_prime_import = i915_gem_prime_import,
1090
1091 .dumb_create = i915_gem_dumb_create,
1092 .dumb_map_offset = i915_gem_mmap_gtt,
1093 .dumb_destroy = i915_gem_dumb_destroy,
1094 .ioctls = i915_ioctls,
1095 .fops = &i915_driver_fops,
1096 .name = DRIVER_NAME,
1097 .desc = DRIVER_DESC,
1098 .date = DRIVER_DATE,
1099 .major = DRIVER_MAJOR,
1100 .minor = DRIVER_MINOR,
1101 .patchlevel = DRIVER_PATCHLEVEL,
1102 };
1103
1104 static struct pci_driver i915_pci_driver = {
1105 .name = DRIVER_NAME,
1106 .id_table = pciidlist,
1107 .probe = i915_pci_probe,
1108 .remove = i915_pci_remove,
1109 .driver.pm = &i915_pm_ops,
1110 };
1111
1112 static int __init i915_init(void)
1113 {
1114 driver.num_ioctls = i915_max_ioctl;
1115
1116 /*
1117 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1118 * explicitly disabled with the module pararmeter.
1119 *
1120 * Otherwise, just follow the parameter (defaulting to off).
1121 *
1122 * Allow optional vga_text_mode_force boot option to override
1123 * the default behavior.
1124 */
1125 #if defined(CONFIG_DRM_I915_KMS)
1126 if (i915_modeset != 0)
1127 driver.driver_features |= DRIVER_MODESET;
1128 #endif
1129 if (i915_modeset == 1)
1130 driver.driver_features |= DRIVER_MODESET;
1131
1132 #ifdef CONFIG_VGA_CONSOLE
1133 if (vgacon_text_force() && i915_modeset == -1)
1134 driver.driver_features &= ~DRIVER_MODESET;
1135 #endif
1136
1137 if (!(driver.driver_features & DRIVER_MODESET))
1138 driver.get_vblank_timestamp = NULL;
1139
1140 return drm_pci_init(&driver, &i915_pci_driver);
1141 }
1142
1143 static void __exit i915_exit(void)
1144 {
1145 drm_pci_exit(&driver, &i915_pci_driver);
1146 }
1147
1148 module_init(i915_init);
1149 module_exit(i915_exit);
1150
1151 MODULE_AUTHOR(DRIVER_AUTHOR);
1152 MODULE_DESCRIPTION(DRIVER_DESC);
1153 MODULE_LICENSE("GPL and additional rights");
1154
1155 /* We give fast paths for the really cool registers */
1156 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1157 ((HAS_FORCE_WAKE((dev_priv)->dev)) && \
1158 ((reg) < 0x40000) && \
1159 ((reg) != FORCEWAKE))
1160 static void
1161 ilk_dummy_write(struct drm_i915_private *dev_priv)
1162 {
1163 /* WaIssueDummyWriteToWakeupFromRC6: Issue a dummy write to wake up the
1164 * chip from rc6 before touching it for real. MI_MODE is masked, hence
1165 * harmless to write 0 into. */
1166 I915_WRITE_NOTRACE(MI_MODE, 0);
1167 }
1168
1169 static void
1170 hsw_unclaimed_reg_clear(struct drm_i915_private *dev_priv, u32 reg)
1171 {
1172 if (IS_HASWELL(dev_priv->dev) &&
1173 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1174 DRM_ERROR("Unknown unclaimed register before writing to %x\n",
1175 reg);
1176 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1177 }
1178 }
1179
1180 static void
1181 hsw_unclaimed_reg_check(struct drm_i915_private *dev_priv, u32 reg)
1182 {
1183 if (IS_HASWELL(dev_priv->dev) &&
1184 (I915_READ_NOTRACE(FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) {
1185 DRM_ERROR("Unclaimed write to %x\n", reg);
1186 I915_WRITE_NOTRACE(FPGA_DBG, FPGA_DBG_RM_NOCLAIM);
1187 }
1188 }
1189
1190 #define __i915_read(x, y) \
1191 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1192 u##x val = 0; \
1193 if (IS_GEN5(dev_priv->dev)) \
1194 ilk_dummy_write(dev_priv); \
1195 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1196 unsigned long irqflags; \
1197 spin_lock_irqsave(&dev_priv->gt_lock, irqflags); \
1198 if (dev_priv->forcewake_count == 0) \
1199 dev_priv->gt.force_wake_get(dev_priv); \
1200 val = read##y(dev_priv->regs + reg); \
1201 if (dev_priv->forcewake_count == 0) \
1202 dev_priv->gt.force_wake_put(dev_priv); \
1203 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags); \
1204 } else { \
1205 val = read##y(dev_priv->regs + reg); \
1206 } \
1207 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1208 return val; \
1209 }
1210
1211 __i915_read(8, b)
1212 __i915_read(16, w)
1213 __i915_read(32, l)
1214 __i915_read(64, q)
1215 #undef __i915_read
1216
1217 #define __i915_write(x, y) \
1218 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1219 u32 __fifo_ret = 0; \
1220 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1221 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1222 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
1223 } \
1224 if (IS_GEN5(dev_priv->dev)) \
1225 ilk_dummy_write(dev_priv); \
1226 hsw_unclaimed_reg_clear(dev_priv, reg); \
1227 write##y(val, dev_priv->regs + reg); \
1228 if (unlikely(__fifo_ret)) { \
1229 gen6_gt_check_fifodbg(dev_priv); \
1230 } \
1231 hsw_unclaimed_reg_check(dev_priv, reg); \
1232 }
1233 __i915_write(8, b)
1234 __i915_write(16, w)
1235 __i915_write(32, l)
1236 __i915_write(64, q)
1237 #undef __i915_write
1238
1239 static const struct register_whitelist {
1240 uint64_t offset;
1241 uint32_t size;
1242 uint32_t gen_bitmask; /* support gens, 0x10 for 4, 0x30 for 4 and 5, etc. */
1243 } whitelist[] = {
1244 { RING_TIMESTAMP(RENDER_RING_BASE), 8, 0xF0 },
1245 };
1246
1247 int i915_reg_read_ioctl(struct drm_device *dev,
1248 void *data, struct drm_file *file)
1249 {
1250 struct drm_i915_private *dev_priv = dev->dev_private;
1251 struct drm_i915_reg_read *reg = data;
1252 struct register_whitelist const *entry = whitelist;
1253 int i;
1254
1255 for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) {
1256 if (entry->offset == reg->offset &&
1257 (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask))
1258 break;
1259 }
1260
1261 if (i == ARRAY_SIZE(whitelist))
1262 return -EINVAL;
1263
1264 switch (entry->size) {
1265 case 8:
1266 reg->val = I915_READ64(reg->offset);
1267 break;
1268 case 4:
1269 reg->val = I915_READ(reg->offset);
1270 break;
1271 case 2:
1272 reg->val = I915_READ16(reg->offset);
1273 break;
1274 case 1:
1275 reg->val = I915_READ8(reg->offset);
1276 break;
1277 default:
1278 WARN_ON(1);
1279 return -EINVAL;
1280 }
1281
1282 return 0;
1283 }
Linux kernel - Deliverables
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