1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver
;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info
= {
67 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
68 .has_overlay
= 1, .overlay_needs_physical
= 1,
69 .ring_mask
= RENDER_RING
,
70 GEN_DEFAULT_PIPEOFFSETS
,
74 static const struct intel_device_info intel_845g_info
= {
75 .gen
= 2, .num_pipes
= 1,
76 .has_overlay
= 1, .overlay_needs_physical
= 1,
77 .ring_mask
= RENDER_RING
,
78 GEN_DEFAULT_PIPEOFFSETS
,
82 static const struct intel_device_info intel_i85x_info
= {
83 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
84 .cursor_needs_physical
= 1,
85 .has_overlay
= 1, .overlay_needs_physical
= 1,
87 .ring_mask
= RENDER_RING
,
88 GEN_DEFAULT_PIPEOFFSETS
,
92 static const struct intel_device_info intel_i865g_info
= {
93 .gen
= 2, .num_pipes
= 1,
94 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 .ring_mask
= RENDER_RING
,
96 GEN_DEFAULT_PIPEOFFSETS
,
100 static const struct intel_device_info intel_i915g_info
= {
101 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
102 .has_overlay
= 1, .overlay_needs_physical
= 1,
103 .ring_mask
= RENDER_RING
,
104 GEN_DEFAULT_PIPEOFFSETS
,
107 static const struct intel_device_info intel_i915gm_info
= {
108 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
109 .cursor_needs_physical
= 1,
110 .has_overlay
= 1, .overlay_needs_physical
= 1,
113 .ring_mask
= RENDER_RING
,
114 GEN_DEFAULT_PIPEOFFSETS
,
117 static const struct intel_device_info intel_i945g_info
= {
118 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
119 .has_overlay
= 1, .overlay_needs_physical
= 1,
120 .ring_mask
= RENDER_RING
,
121 GEN_DEFAULT_PIPEOFFSETS
,
124 static const struct intel_device_info intel_i945gm_info
= {
125 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
126 .has_hotplug
= 1, .cursor_needs_physical
= 1,
127 .has_overlay
= 1, .overlay_needs_physical
= 1,
130 .ring_mask
= RENDER_RING
,
131 GEN_DEFAULT_PIPEOFFSETS
,
135 static const struct intel_device_info intel_i965g_info
= {
136 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
139 .ring_mask
= RENDER_RING
,
140 GEN_DEFAULT_PIPEOFFSETS
,
144 static const struct intel_device_info intel_i965gm_info
= {
145 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
146 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
149 .ring_mask
= RENDER_RING
,
150 GEN_DEFAULT_PIPEOFFSETS
,
154 static const struct intel_device_info intel_g33_info
= {
155 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
156 .need_gfx_hws
= 1, .has_hotplug
= 1,
158 .ring_mask
= RENDER_RING
,
159 GEN_DEFAULT_PIPEOFFSETS
,
163 static const struct intel_device_info intel_g45_info
= {
164 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
165 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
166 .ring_mask
= RENDER_RING
| BSD_RING
,
167 GEN_DEFAULT_PIPEOFFSETS
,
171 static const struct intel_device_info intel_gm45_info
= {
172 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
173 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
174 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
176 .ring_mask
= RENDER_RING
| BSD_RING
,
177 GEN_DEFAULT_PIPEOFFSETS
,
181 static const struct intel_device_info intel_pineview_info
= {
182 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
183 .need_gfx_hws
= 1, .has_hotplug
= 1,
185 GEN_DEFAULT_PIPEOFFSETS
,
189 static const struct intel_device_info intel_ironlake_d_info
= {
190 .gen
= 5, .num_pipes
= 2,
191 .need_gfx_hws
= 1, .has_hotplug
= 1,
192 .ring_mask
= RENDER_RING
| BSD_RING
,
193 GEN_DEFAULT_PIPEOFFSETS
,
197 static const struct intel_device_info intel_ironlake_m_info
= {
198 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
199 .need_gfx_hws
= 1, .has_hotplug
= 1,
201 .ring_mask
= RENDER_RING
| BSD_RING
,
202 GEN_DEFAULT_PIPEOFFSETS
,
206 static const struct intel_device_info intel_sandybridge_d_info
= {
207 .gen
= 6, .num_pipes
= 2,
208 .need_gfx_hws
= 1, .has_hotplug
= 1,
210 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
212 GEN_DEFAULT_PIPEOFFSETS
,
216 static const struct intel_device_info intel_sandybridge_m_info
= {
217 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
218 .need_gfx_hws
= 1, .has_hotplug
= 1,
220 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
222 GEN_DEFAULT_PIPEOFFSETS
,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
233 static const struct intel_device_info intel_ivybridge_d_info
= {
236 GEN_DEFAULT_PIPEOFFSETS
,
240 static const struct intel_device_info intel_ivybridge_m_info
= {
244 GEN_DEFAULT_PIPEOFFSETS
,
248 static const struct intel_device_info intel_ivybridge_q_info
= {
251 .num_pipes
= 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS
,
256 static const struct intel_device_info intel_valleyview_m_info
= {
261 .display_mmio_offset
= VLV_DISPLAY_BASE
,
262 .has_fbc
= 0, /* legal, last one wins */
263 .has_llc
= 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS
,
268 static const struct intel_device_info intel_valleyview_d_info
= {
272 .display_mmio_offset
= VLV_DISPLAY_BASE
,
273 .has_fbc
= 0, /* legal, last one wins */
274 .has_llc
= 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS
,
279 static const struct intel_device_info intel_haswell_d_info
= {
284 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
285 GEN_DEFAULT_PIPEOFFSETS
,
289 static const struct intel_device_info intel_haswell_m_info
= {
295 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
296 GEN_DEFAULT_PIPEOFFSETS
,
300 static const struct intel_device_info intel_broadwell_d_info
= {
301 .gen
= 8, .num_pipes
= 3,
302 .need_gfx_hws
= 1, .has_hotplug
= 1,
303 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
308 GEN_DEFAULT_PIPEOFFSETS
,
312 static const struct intel_device_info intel_broadwell_m_info
= {
313 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
314 .need_gfx_hws
= 1, .has_hotplug
= 1,
315 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
320 GEN_DEFAULT_PIPEOFFSETS
,
324 static const struct intel_device_info intel_broadwell_gt3d_info
= {
325 .gen
= 8, .num_pipes
= 3,
326 .need_gfx_hws
= 1, .has_hotplug
= 1,
327 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
332 GEN_DEFAULT_PIPEOFFSETS
,
336 static const struct intel_device_info intel_broadwell_gt3m_info
= {
337 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
338 .need_gfx_hws
= 1, .has_hotplug
= 1,
339 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
344 GEN_DEFAULT_PIPEOFFSETS
,
348 static const struct intel_device_info intel_cherryview_info
= {
349 .gen
= 8, .num_pipes
= 3,
350 .need_gfx_hws
= 1, .has_hotplug
= 1,
351 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
353 .display_mmio_offset
= VLV_DISPLAY_BASE
,
358 static const struct intel_device_info intel_skylake_info
= {
361 .gen
= 9, .num_pipes
= 3,
362 .need_gfx_hws
= 1, .has_hotplug
= 1,
363 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
367 GEN_DEFAULT_PIPEOFFSETS
,
371 static const struct intel_device_info intel_skylake_gt3_info
= {
374 .gen
= 9, .num_pipes
= 3,
375 .need_gfx_hws
= 1, .has_hotplug
= 1,
376 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
380 GEN_DEFAULT_PIPEOFFSETS
,
385 * Make sure any device matches here are from most specific to most
386 * general. For example, since the Quanta match is based on the subsystem
387 * and subvendor IDs, we need it to come before the more general IVB
388 * PCI ID matches, otherwise we'll use the wrong info struct above.
390 #define INTEL_PCI_IDS \
391 INTEL_I830_IDS(&intel_i830_info), \
392 INTEL_I845G_IDS(&intel_845g_info), \
393 INTEL_I85X_IDS(&intel_i85x_info), \
394 INTEL_I865G_IDS(&intel_i865g_info), \
395 INTEL_I915G_IDS(&intel_i915g_info), \
396 INTEL_I915GM_IDS(&intel_i915gm_info), \
397 INTEL_I945G_IDS(&intel_i945g_info), \
398 INTEL_I945GM_IDS(&intel_i945gm_info), \
399 INTEL_I965G_IDS(&intel_i965g_info), \
400 INTEL_G33_IDS(&intel_g33_info), \
401 INTEL_I965GM_IDS(&intel_i965gm_info), \
402 INTEL_GM45_IDS(&intel_gm45_info), \
403 INTEL_G45_IDS(&intel_g45_info), \
404 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
405 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
406 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
407 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
408 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
409 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
410 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
411 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
412 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
413 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
414 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
415 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
416 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
417 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
418 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
419 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
420 INTEL_CHV_IDS(&intel_cherryview_info), \
421 INTEL_SKL_GT1_IDS(&intel_skylake_info), \
422 INTEL_SKL_GT2_IDS(&intel_skylake_info), \
423 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info) \
425 static const struct pci_device_id pciidlist[] = { /* aka */
430 #if defined(CONFIG_DRM_I915_KMS)
431 MODULE_DEVICE_TABLE(pci
, pciidlist
);
434 void intel_detect_pch(struct drm_device
*dev
)
436 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
437 struct pci_dev
*pch
= NULL
;
439 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
440 * (which really amounts to a PCH but no South Display).
442 if (INTEL_INFO(dev
)->num_pipes
== 0) {
443 dev_priv
->pch_type
= PCH_NOP
;
448 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
449 * make graphics device passthrough work easy for VMM, that only
450 * need to expose ISA bridge to let driver know the real hardware
451 * underneath. This is a requirement from virtualization team.
453 * In some virtualized environments (e.g. XEN), there is irrelevant
454 * ISA bridge in the system. To work reliably, we should scan trhough
455 * all the ISA bridge devices and check for the first match, instead
456 * of only checking the first one.
458 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
459 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
460 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
461 dev_priv
->pch_id
= id
;
463 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
464 dev_priv
->pch_type
= PCH_IBX
;
465 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
466 WARN_ON(!IS_GEN5(dev
));
467 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
468 dev_priv
->pch_type
= PCH_CPT
;
469 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
470 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
471 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
472 /* PantherPoint is CPT compatible */
473 dev_priv
->pch_type
= PCH_CPT
;
474 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
475 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
476 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
477 dev_priv
->pch_type
= PCH_LPT
;
478 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
479 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
480 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
481 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
482 dev_priv
->pch_type
= PCH_LPT
;
483 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
484 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
485 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
486 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
487 dev_priv
->pch_type
= PCH_SPT
;
488 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
489 WARN_ON(!IS_SKYLAKE(dev
));
490 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
491 dev_priv
->pch_type
= PCH_SPT
;
492 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
493 WARN_ON(!IS_SKYLAKE(dev
));
501 DRM_DEBUG_KMS("No PCH found.\n");
506 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
508 if (INTEL_INFO(dev
)->gen
< 6)
511 if (i915
.semaphores
>= 0)
512 return i915
.semaphores
;
514 /* TODO: make semaphores and Execlists play nicely together */
515 if (i915
.enable_execlists
)
518 /* Until we get further testing... */
522 #ifdef CONFIG_INTEL_IOMMU
523 /* Enable semaphores on SNB when IO remapping is off */
524 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
531 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
)
533 spin_lock_irq(&dev_priv
->irq_lock
);
535 dev_priv
->long_hpd_port_mask
= 0;
536 dev_priv
->short_hpd_port_mask
= 0;
537 dev_priv
->hpd_event_bits
= 0;
539 spin_unlock_irq(&dev_priv
->irq_lock
);
541 cancel_work_sync(&dev_priv
->dig_port_work
);
542 cancel_work_sync(&dev_priv
->hotplug_work
);
543 cancel_delayed_work_sync(&dev_priv
->hotplug_reenable_work
);
546 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
548 struct drm_device
*dev
= dev_priv
->dev
;
549 struct drm_encoder
*encoder
;
551 drm_modeset_lock_all(dev
);
552 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
553 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
555 if (intel_encoder
->suspend
)
556 intel_encoder
->suspend(intel_encoder
);
558 drm_modeset_unlock_all(dev
);
561 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
);
562 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
565 static int i915_drm_suspend(struct drm_device
*dev
)
567 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
568 struct drm_crtc
*crtc
;
569 pci_power_t opregion_target_state
;
572 /* ignore lid events during suspend */
573 mutex_lock(&dev_priv
->modeset_restore_lock
);
574 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
575 mutex_unlock(&dev_priv
->modeset_restore_lock
);
577 /* We do a lot of poking in a lot of registers, make sure they work
579 intel_display_set_init_power(dev_priv
, true);
581 drm_kms_helper_poll_disable(dev
);
583 pci_save_state(dev
->pdev
);
585 error
= i915_gem_suspend(dev
);
587 dev_err(&dev
->pdev
->dev
,
588 "GEM idle failed, resume might fail\n");
592 intel_suspend_gt_powersave(dev
);
595 * Disable CRTCs directly since we want to preserve sw state
596 * for _thaw. Also, power gate the CRTC power wells.
598 drm_modeset_lock_all(dev
);
599 for_each_crtc(dev
, crtc
)
600 intel_crtc_control(crtc
, false);
601 drm_modeset_unlock_all(dev
);
603 intel_dp_mst_suspend(dev
);
605 intel_runtime_pm_disable_interrupts(dev_priv
);
606 intel_hpd_cancel_work(dev_priv
);
608 intel_suspend_encoders(dev_priv
);
610 intel_suspend_hw(dev
);
612 i915_gem_suspend_gtt_mappings(dev
);
614 i915_save_state(dev
);
616 opregion_target_state
= PCI_D3cold
;
617 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
618 if (acpi_target_system_state() < ACPI_STATE_S3
)
619 opregion_target_state
= PCI_D1
;
621 intel_opregion_notify_adapter(dev
, opregion_target_state
);
623 intel_uncore_forcewake_reset(dev
, false);
624 intel_opregion_fini(dev
);
626 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
628 dev_priv
->suspend_count
++;
630 intel_display_set_init_power(dev_priv
, false);
635 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
637 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
640 ret
= intel_suspend_complete(dev_priv
);
643 DRM_ERROR("Suspend complete failed: %d\n", ret
);
648 pci_disable_device(drm_dev
->pdev
);
650 * During hibernation on some GEN4 platforms the BIOS may try to access
651 * the device even though it's already in D3 and hang the machine. So
652 * leave the device in D0 on those platforms and hope the BIOS will
653 * power down the device properly. Platforms where this was seen:
654 * Lenovo Thinkpad X301, X61s
657 drm_dev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_LENOVO
&&
658 INTEL_INFO(dev_priv
)->gen
== 4))
659 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
664 int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
)
668 if (!dev
|| !dev
->dev_private
) {
669 DRM_ERROR("dev: %p\n", dev
);
670 DRM_ERROR("DRM not initialized, aborting suspend.\n");
674 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
675 state
.event
!= PM_EVENT_FREEZE
))
678 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
681 error
= i915_drm_suspend(dev
);
685 return i915_drm_suspend_late(dev
, false);
688 static int i915_drm_resume(struct drm_device
*dev
)
690 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
692 mutex_lock(&dev
->struct_mutex
);
693 i915_gem_restore_gtt_mappings(dev
);
694 mutex_unlock(&dev
->struct_mutex
);
696 i915_restore_state(dev
);
697 intel_opregion_setup(dev
);
699 intel_init_pch_refclk(dev
);
700 drm_mode_config_reset(dev
);
703 * Interrupts have to be enabled before any batches are run. If not the
704 * GPU will hang. i915_gem_init_hw() will initiate batches to
705 * update/restore the context.
707 * Modeset enabling in intel_modeset_init_hw() also needs working
710 intel_runtime_pm_enable_interrupts(dev_priv
);
712 mutex_lock(&dev
->struct_mutex
);
713 if (i915_gem_init_hw(dev
)) {
714 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
715 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
717 mutex_unlock(&dev
->struct_mutex
);
719 intel_modeset_init_hw(dev
);
721 spin_lock_irq(&dev_priv
->irq_lock
);
722 if (dev_priv
->display
.hpd_irq_setup
)
723 dev_priv
->display
.hpd_irq_setup(dev
);
724 spin_unlock_irq(&dev_priv
->irq_lock
);
726 drm_modeset_lock_all(dev
);
727 intel_modeset_setup_hw_state(dev
, true);
728 drm_modeset_unlock_all(dev
);
730 intel_dp_mst_resume(dev
);
733 * ... but also need to make sure that hotplug processing
734 * doesn't cause havoc. Like in the driver load code we don't
735 * bother with the tiny race here where we might loose hotplug
738 intel_hpd_init(dev_priv
);
739 /* Config may have changed between suspend and resume */
740 drm_helper_hpd_irq_event(dev
);
742 intel_opregion_init(dev
);
744 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
746 mutex_lock(&dev_priv
->modeset_restore_lock
);
747 dev_priv
->modeset_restore
= MODESET_DONE
;
748 mutex_unlock(&dev_priv
->modeset_restore_lock
);
750 intel_opregion_notify_adapter(dev
, PCI_D0
);
752 drm_kms_helper_poll_enable(dev
);
757 static int i915_drm_resume_early(struct drm_device
*dev
)
759 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
763 * We have a resume ordering issue with the snd-hda driver also
764 * requiring our device to be power up. Due to the lack of a
765 * parent/child relationship we currently solve this with an early
768 * FIXME: This should be solved with a special hdmi sink device or
769 * similar so that power domains can be employed.
771 if (pci_enable_device(dev
->pdev
))
774 pci_set_master(dev
->pdev
);
776 if (IS_VALLEYVIEW(dev_priv
))
777 ret
= vlv_resume_prepare(dev_priv
, false);
779 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret
);
781 intel_uncore_early_sanitize(dev
, true);
783 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
784 hsw_disable_pc8(dev_priv
);
786 intel_uncore_sanitize(dev
);
787 intel_power_domains_init_hw(dev_priv
);
792 int i915_resume_legacy(struct drm_device
*dev
)
796 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
799 ret
= i915_drm_resume_early(dev
);
803 return i915_drm_resume(dev
);
807 * i915_reset - reset chip after a hang
808 * @dev: drm device to reset
810 * Reset the chip. Useful if a hang is detected. Returns zero on successful
811 * reset or otherwise an error code.
813 * Procedure is fairly simple:
814 * - reset the chip using the reset reg
815 * - re-init context state
816 * - re-init hardware status page
817 * - re-init ring buffer
818 * - re-init interrupt state
821 int i915_reset(struct drm_device
*dev
)
823 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
830 intel_reset_gt_powersave(dev
);
832 mutex_lock(&dev
->struct_mutex
);
836 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
838 ret
= intel_gpu_reset(dev
);
840 /* Also reset the gpu hangman. */
842 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
843 dev_priv
->gpu_error
.stop_rings
= 0;
844 if (ret
== -ENODEV
) {
845 DRM_INFO("Reset not implemented, but ignoring "
846 "error for simulated gpu hangs\n");
851 if (i915_stop_ring_allow_warn(dev_priv
))
852 pr_notice("drm/i915: Resetting chip after gpu hang\n");
855 DRM_ERROR("Failed to reset chip: %i\n", ret
);
856 mutex_unlock(&dev
->struct_mutex
);
860 intel_overlay_reset(dev_priv
);
862 /* Ok, now get things going again... */
865 * Everything depends on having the GTT running, so we need to start
866 * there. Fortunately we don't need to do this unless we reset the
867 * chip at a PCI level.
869 * Next we need to restore the context, but we don't use those
872 * Ring buffer needs to be re-initialized in the KMS case, or if X
873 * was running at the time of the reset (i.e. we weren't VT
877 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
878 dev_priv
->gpu_error
.reload_in_reset
= true;
880 ret
= i915_gem_init_hw(dev
);
882 dev_priv
->gpu_error
.reload_in_reset
= false;
884 mutex_unlock(&dev
->struct_mutex
);
886 DRM_ERROR("Failed hw init on reset %d\n", ret
);
891 * rps/rc6 re-init is necessary to restore state lost after the
892 * reset and the re-install of gt irqs. Skip for ironlake per
893 * previous concerns that it doesn't respond well to some forms
894 * of re-init after reset.
896 if (INTEL_INFO(dev
)->gen
> 5)
897 intel_enable_gt_powersave(dev
);
902 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
904 struct intel_device_info
*intel_info
=
905 (struct intel_device_info
*) ent
->driver_data
;
907 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
908 DRM_INFO("This hardware requires preliminary hardware support.\n"
909 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
913 /* Only bind to function 0 of the device. Early generations
914 * used function 1 as a placeholder for multi-head. This causes
915 * us confusion instead, especially on the systems where both
916 * functions have the same PCI-ID!
918 if (PCI_FUNC(pdev
->devfn
))
921 driver
.driver_features
&= ~(DRIVER_USE_AGP
);
923 return drm_get_pci_dev(pdev
, ent
, &driver
);
927 i915_pci_remove(struct pci_dev
*pdev
)
929 struct drm_device
*dev
= pci_get_drvdata(pdev
);
934 static int i915_pm_suspend(struct device
*dev
)
936 struct pci_dev
*pdev
= to_pci_dev(dev
);
937 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
939 if (!drm_dev
|| !drm_dev
->dev_private
) {
940 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
944 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
947 return i915_drm_suspend(drm_dev
);
950 static int i915_pm_suspend_late(struct device
*dev
)
952 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
955 * We have a suspedn ordering issue with the snd-hda driver also
956 * requiring our device to be power up. Due to the lack of a
957 * parent/child relationship we currently solve this with an late
960 * FIXME: This should be solved with a special hdmi sink device or
961 * similar so that power domains can be employed.
963 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
966 return i915_drm_suspend_late(drm_dev
, false);
969 static int i915_pm_poweroff_late(struct device
*dev
)
971 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
973 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
976 return i915_drm_suspend_late(drm_dev
, true);
979 static int i915_pm_resume_early(struct device
*dev
)
981 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
983 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
986 return i915_drm_resume_early(drm_dev
);
989 static int i915_pm_resume(struct device
*dev
)
991 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
993 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
996 return i915_drm_resume(drm_dev
);
999 static int hsw_suspend_complete(struct drm_i915_private
*dev_priv
)
1001 hsw_enable_pc8(dev_priv
);
1007 * Save all Gunit registers that may be lost after a D3 and a subsequent
1008 * S0i[R123] transition. The list of registers needing a save/restore is
1009 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1010 * registers in the following way:
1011 * - Driver: saved/restored by the driver
1012 * - Punit : saved/restored by the Punit firmware
1013 * - No, w/o marking: no need to save/restore, since the register is R/O or
1014 * used internally by the HW in a way that doesn't depend
1015 * keeping the content across a suspend/resume.
1016 * - Debug : used for debugging
1018 * We save/restore all registers marked with 'Driver', with the following
1020 * - Registers out of use, including also registers marked with 'Debug'.
1021 * These have no effect on the driver's operation, so we don't save/restore
1022 * them to reduce the overhead.
1023 * - Registers that are fully setup by an initialization function called from
1024 * the resume path. For example many clock gating and RPS/RC6 registers.
1025 * - Registers that provide the right functionality with their reset defaults.
1027 * TODO: Except for registers that based on the above 3 criteria can be safely
1028 * ignored, we save/restore all others, practically treating the HW context as
1029 * a black-box for the driver. Further investigation is needed to reduce the
1030 * saved/restored registers even further, by following the same 3 criteria.
1032 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1034 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1037 /* GAM 0x4000-0x4770 */
1038 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1039 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1040 s
->arb_mode
= I915_READ(ARB_MODE
);
1041 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1042 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1044 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1045 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS_BASE
+ i
* 4);
1047 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1048 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1050 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1051 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1052 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1053 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1055 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1057 /* MBC 0x9024-0x91D0, 0x8500 */
1058 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1059 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1060 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1062 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1063 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1064 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1065 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1066 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1067 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1068 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1070 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1071 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1072 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1073 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1074 s
->ecobus
= I915_READ(ECOBUS
);
1075 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1076 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1077 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1078 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1079 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1080 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1082 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1083 s
->gt_imr
= I915_READ(GTIMR
);
1084 s
->gt_ier
= I915_READ(GTIER
);
1085 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1086 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1088 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1089 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH_BASE
+ i
* 4);
1091 /* GT SA CZ domain, 0x100000-0x138124 */
1092 s
->tilectl
= I915_READ(TILECTL
);
1093 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1094 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1095 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1096 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1098 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1099 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1100 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1101 s
->pcbr
= I915_READ(VLV_PCBR
);
1102 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1105 * Not saving any of:
1106 * DFT, 0x9800-0x9EC0
1107 * SARB, 0xB000-0xB1FC
1108 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1113 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1115 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1119 /* GAM 0x4000-0x4770 */
1120 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1121 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1122 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1123 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1124 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1126 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1127 I915_WRITE(GEN7_LRA_LIMITS_BASE
+ i
* 4, s
->lra_limits
[i
]);
1129 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1130 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1132 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1133 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1134 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1135 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1137 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1139 /* MBC 0x9024-0x91D0, 0x8500 */
1140 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1141 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1142 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1144 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1145 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1146 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1147 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1148 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1149 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1150 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1152 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1153 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1154 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1155 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1156 I915_WRITE(ECOBUS
, s
->ecobus
);
1157 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1158 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1159 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1160 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1161 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1162 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1164 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1165 I915_WRITE(GTIMR
, s
->gt_imr
);
1166 I915_WRITE(GTIER
, s
->gt_ier
);
1167 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1168 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1170 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1171 I915_WRITE(GEN7_GT_SCRATCH_BASE
+ i
* 4, s
->gt_scratch
[i
]);
1173 /* GT SA CZ domain, 0x100000-0x138124 */
1174 I915_WRITE(TILECTL
, s
->tilectl
);
1175 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1177 * Preserve the GT allow wake and GFX force clock bit, they are not
1178 * be restored, as they are used to control the s0ix suspend/resume
1179 * sequence by the caller.
1181 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1182 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1183 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1184 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1186 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1187 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1188 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1189 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1191 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1193 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1194 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1195 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1196 I915_WRITE(VLV_PCBR
, s
->pcbr
);
1197 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1200 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1205 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1207 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1208 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1210 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1211 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1216 err
= wait_for(COND
, 20);
1218 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1219 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1225 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1230 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1231 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1233 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1234 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1235 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1237 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1239 err
= wait_for(COND
, 1);
1241 DRM_ERROR("timeout disabling GT waking\n");
1246 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1253 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1254 val
= wait_for_on
? mask
: 0;
1255 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1259 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1260 wait_for_on
? "on" : "off",
1261 I915_READ(VLV_GTLC_PW_STATUS
));
1264 * RC6 transitioning can be delayed up to 2 msec (see
1265 * valleyview_enable_rps), use 3 msec for safety.
1267 err
= wait_for(COND
, 3);
1269 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1270 wait_for_on
? "on" : "off");
1276 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1278 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1281 DRM_ERROR("GT register access while GT waking disabled\n");
1282 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1285 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1291 * Bspec defines the following GT well on flags as debug only, so
1292 * don't treat them as hard failures.
1294 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1296 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1297 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1299 vlv_check_no_gt_access(dev_priv
);
1301 err
= vlv_force_gfx_clock(dev_priv
, true);
1305 err
= vlv_allow_gt_wake(dev_priv
, false);
1309 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1310 vlv_save_gunit_s0ix_state(dev_priv
);
1312 err
= vlv_force_gfx_clock(dev_priv
, false);
1319 /* For safety always re-enable waking and disable gfx clock forcing */
1320 vlv_allow_gt_wake(dev_priv
, true);
1322 vlv_force_gfx_clock(dev_priv
, false);
1327 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1330 struct drm_device
*dev
= dev_priv
->dev
;
1335 * If any of the steps fail just try to continue, that's the best we
1336 * can do at this point. Return the first error code (which will also
1337 * leave RPM permanently disabled).
1339 ret
= vlv_force_gfx_clock(dev_priv
, true);
1341 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1342 vlv_restore_gunit_s0ix_state(dev_priv
);
1344 err
= vlv_allow_gt_wake(dev_priv
, true);
1348 err
= vlv_force_gfx_clock(dev_priv
, false);
1352 vlv_check_no_gt_access(dev_priv
);
1355 intel_init_clock_gating(dev
);
1356 i915_gem_restore_fences(dev
);
1362 static int intel_runtime_suspend(struct device
*device
)
1364 struct pci_dev
*pdev
= to_pci_dev(device
);
1365 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1366 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1369 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1372 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1375 DRM_DEBUG_KMS("Suspending device\n");
1378 * We could deadlock here in case another thread holding struct_mutex
1379 * calls RPM suspend concurrently, since the RPM suspend will wait
1380 * first for this RPM suspend to finish. In this case the concurrent
1381 * RPM resume will be followed by its RPM suspend counterpart. Still
1382 * for consistency return -EAGAIN, which will reschedule this suspend.
1384 if (!mutex_trylock(&dev
->struct_mutex
)) {
1385 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1387 * Bump the expiration timestamp, otherwise the suspend won't
1390 pm_runtime_mark_last_busy(device
);
1395 * We are safe here against re-faults, since the fault handler takes
1398 i915_gem_release_all_mmaps(dev_priv
);
1399 mutex_unlock(&dev
->struct_mutex
);
1401 intel_suspend_gt_powersave(dev
);
1402 intel_runtime_pm_disable_interrupts(dev_priv
);
1404 ret
= intel_suspend_complete(dev_priv
);
1406 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1407 intel_runtime_pm_enable_interrupts(dev_priv
);
1412 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1413 intel_uncore_forcewake_reset(dev
, false);
1414 dev_priv
->pm
.suspended
= true;
1417 * FIXME: We really should find a document that references the arguments
1420 if (IS_HASWELL(dev
)) {
1422 * current versions of firmware which depend on this opregion
1423 * notification have repurposed the D1 definition to mean
1424 * "runtime suspended" vs. what you would normally expect (D3)
1425 * to distinguish it from notifications that might be sent via
1428 intel_opregion_notify_adapter(dev
, PCI_D1
);
1431 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1432 * being detected, and the call we do at intel_runtime_resume()
1433 * won't be able to restore them. Since PCI_D3hot matches the
1434 * actual specification and appears to be working, use it. Let's
1435 * assume the other non-Haswell platforms will stay the same as
1438 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1441 assert_forcewakes_inactive(dev_priv
);
1443 DRM_DEBUG_KMS("Device suspended\n");
1447 static int intel_runtime_resume(struct device
*device
)
1449 struct pci_dev
*pdev
= to_pci_dev(device
);
1450 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1451 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1454 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1457 DRM_DEBUG_KMS("Resuming device\n");
1459 intel_opregion_notify_adapter(dev
, PCI_D0
);
1460 dev_priv
->pm
.suspended
= false;
1462 if (IS_GEN6(dev_priv
))
1463 intel_init_pch_refclk(dev
);
1464 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1465 hsw_disable_pc8(dev_priv
);
1466 else if (IS_VALLEYVIEW(dev_priv
))
1467 ret
= vlv_resume_prepare(dev_priv
, true);
1470 * No point of rolling back things in case of an error, as the best
1471 * we can do is to hope that things will still work (and disable RPM).
1473 i915_gem_init_swizzling(dev
);
1474 gen6_update_ring_freq(dev
);
1476 intel_runtime_pm_enable_interrupts(dev_priv
);
1477 intel_enable_gt_powersave(dev
);
1480 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1482 DRM_DEBUG_KMS("Device resumed\n");
1488 * This function implements common functionality of runtime and system
1491 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
)
1493 struct drm_device
*dev
= dev_priv
->dev
;
1496 if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1497 ret
= hsw_suspend_complete(dev_priv
);
1498 else if (IS_VALLEYVIEW(dev
))
1499 ret
= vlv_suspend_complete(dev_priv
);
1506 static const struct dev_pm_ops i915_pm_ops
= {
1508 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1511 .suspend
= i915_pm_suspend
,
1512 .suspend_late
= i915_pm_suspend_late
,
1513 .resume_early
= i915_pm_resume_early
,
1514 .resume
= i915_pm_resume
,
1518 * @freeze, @freeze_late : called (1) before creating the
1519 * hibernation image [PMSG_FREEZE] and
1520 * (2) after rebooting, before restoring
1521 * the image [PMSG_QUIESCE]
1522 * @thaw, @thaw_early : called (1) after creating the hibernation
1523 * image, before writing it [PMSG_THAW]
1524 * and (2) after failing to create or
1525 * restore the image [PMSG_RECOVER]
1526 * @poweroff, @poweroff_late: called after writing the hibernation
1527 * image, before rebooting [PMSG_HIBERNATE]
1528 * @restore, @restore_early : called after rebooting and restoring the
1529 * hibernation image [PMSG_RESTORE]
1531 .freeze
= i915_pm_suspend
,
1532 .freeze_late
= i915_pm_suspend_late
,
1533 .thaw_early
= i915_pm_resume_early
,
1534 .thaw
= i915_pm_resume
,
1535 .poweroff
= i915_pm_suspend
,
1536 .poweroff_late
= i915_pm_poweroff_late
,
1537 .restore_early
= i915_pm_resume_early
,
1538 .restore
= i915_pm_resume
,
1540 /* S0ix (via runtime suspend) event handlers */
1541 .runtime_suspend
= intel_runtime_suspend
,
1542 .runtime_resume
= intel_runtime_resume
,
1545 static const struct vm_operations_struct i915_gem_vm_ops
= {
1546 .fault
= i915_gem_fault
,
1547 .open
= drm_gem_vm_open
,
1548 .close
= drm_gem_vm_close
,
1551 static const struct file_operations i915_driver_fops
= {
1552 .owner
= THIS_MODULE
,
1554 .release
= drm_release
,
1555 .unlocked_ioctl
= drm_ioctl
,
1556 .mmap
= drm_gem_mmap
,
1559 #ifdef CONFIG_COMPAT
1560 .compat_ioctl
= i915_compat_ioctl
,
1562 .llseek
= noop_llseek
,
1565 static struct drm_driver driver
= {
1566 /* Don't use MTRRs here; the Xserver or userspace app should
1567 * deal with them for Intel hardware.
1571 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1573 .load
= i915_driver_load
,
1574 .unload
= i915_driver_unload
,
1575 .open
= i915_driver_open
,
1576 .lastclose
= i915_driver_lastclose
,
1577 .preclose
= i915_driver_preclose
,
1578 .postclose
= i915_driver_postclose
,
1579 .set_busid
= drm_pci_set_busid
,
1581 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1582 .suspend
= i915_suspend_legacy
,
1583 .resume
= i915_resume_legacy
,
1585 .device_is_agp
= i915_driver_device_is_agp
,
1586 #if defined(CONFIG_DEBUG_FS)
1587 .debugfs_init
= i915_debugfs_init
,
1588 .debugfs_cleanup
= i915_debugfs_cleanup
,
1590 .gem_free_object
= i915_gem_free_object
,
1591 .gem_vm_ops
= &i915_gem_vm_ops
,
1593 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1594 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1595 .gem_prime_export
= i915_gem_prime_export
,
1596 .gem_prime_import
= i915_gem_prime_import
,
1598 .dumb_create
= i915_gem_dumb_create
,
1599 .dumb_map_offset
= i915_gem_mmap_gtt
,
1600 .dumb_destroy
= drm_gem_dumb_destroy
,
1601 .ioctls
= i915_ioctls
,
1602 .fops
= &i915_driver_fops
,
1603 .name
= DRIVER_NAME
,
1604 .desc
= DRIVER_DESC
,
1605 .date
= DRIVER_DATE
,
1606 .major
= DRIVER_MAJOR
,
1607 .minor
= DRIVER_MINOR
,
1608 .patchlevel
= DRIVER_PATCHLEVEL
,
1611 static struct pci_driver i915_pci_driver
= {
1612 .name
= DRIVER_NAME
,
1613 .id_table
= pciidlist
,
1614 .probe
= i915_pci_probe
,
1615 .remove
= i915_pci_remove
,
1616 .driver
.pm
= &i915_pm_ops
,
1619 static int __init
i915_init(void)
1621 driver
.num_ioctls
= i915_max_ioctl
;
1624 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1625 * explicitly disabled with the module pararmeter.
1627 * Otherwise, just follow the parameter (defaulting to off).
1629 * Allow optional vga_text_mode_force boot option to override
1630 * the default behavior.
1632 #if defined(CONFIG_DRM_I915_KMS)
1633 if (i915
.modeset
!= 0)
1634 driver
.driver_features
|= DRIVER_MODESET
;
1636 if (i915
.modeset
== 1)
1637 driver
.driver_features
|= DRIVER_MODESET
;
1639 #ifdef CONFIG_VGA_CONSOLE
1640 if (vgacon_text_force() && i915
.modeset
== -1)
1641 driver
.driver_features
&= ~DRIVER_MODESET
;
1644 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1645 driver
.get_vblank_timestamp
= NULL
;
1646 /* Silently fail loading to not upset userspace. */
1647 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1652 * FIXME: Note that we're lying to the DRM core here so that we can get access
1653 * to the atomic ioctl and the atomic properties. Only plane operations on
1654 * a single CRTC will actually work.
1656 if (i915
.nuclear_pageflip
)
1657 driver
.driver_features
|= DRIVER_ATOMIC
;
1659 return drm_pci_init(&driver
, &i915_pci_driver
);
1662 static void __exit
i915_exit(void)
1664 if (!(driver
.driver_features
& DRIVER_MODESET
))
1665 return; /* Never loaded a driver. */
1667 drm_pci_exit(&driver
, &i915_pci_driver
);
1670 module_init(i915_init
);
1671 module_exit(i915_exit
);
1673 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1674 MODULE_AUTHOR("Intel Corporation");
1676 MODULE_DESCRIPTION(DRIVER_DESC
);
1677 MODULE_LICENSE("GPL and additional rights");