1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
31 #include <linux/acpi.h>
33 #include <drm/i915_drm.h>
35 #include "i915_trace.h"
36 #include "intel_drv.h"
38 #include <linux/console.h>
39 #include <linux/module.h>
40 #include <linux/pm_runtime.h>
41 #include <drm/drm_crtc_helper.h>
43 static struct drm_driver driver
;
45 #define GEN_DEFAULT_PIPEOFFSETS \
46 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
47 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
48 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
49 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
52 #define GEN_CHV_PIPEOFFSETS \
53 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
54 CHV_PIPE_C_OFFSET }, \
55 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
56 CHV_TRANSCODER_C_OFFSET, }, \
57 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET, \
58 CHV_PALETTE_C_OFFSET }
60 #define CURSOR_OFFSETS \
61 .cursor_offsets = { CURSOR_A_OFFSET, CURSOR_B_OFFSET, CHV_CURSOR_C_OFFSET }
63 #define IVB_CURSOR_OFFSETS \
64 .cursor_offsets = { CURSOR_A_OFFSET, IVB_CURSOR_B_OFFSET, IVB_CURSOR_C_OFFSET }
66 static const struct intel_device_info intel_i830_info
= {
67 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
68 .has_overlay
= 1, .overlay_needs_physical
= 1,
69 .ring_mask
= RENDER_RING
,
70 GEN_DEFAULT_PIPEOFFSETS
,
74 static const struct intel_device_info intel_845g_info
= {
75 .gen
= 2, .num_pipes
= 1,
76 .has_overlay
= 1, .overlay_needs_physical
= 1,
77 .ring_mask
= RENDER_RING
,
78 GEN_DEFAULT_PIPEOFFSETS
,
82 static const struct intel_device_info intel_i85x_info
= {
83 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
84 .cursor_needs_physical
= 1,
85 .has_overlay
= 1, .overlay_needs_physical
= 1,
87 .ring_mask
= RENDER_RING
,
88 GEN_DEFAULT_PIPEOFFSETS
,
92 static const struct intel_device_info intel_i865g_info
= {
93 .gen
= 2, .num_pipes
= 1,
94 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 .ring_mask
= RENDER_RING
,
96 GEN_DEFAULT_PIPEOFFSETS
,
100 static const struct intel_device_info intel_i915g_info
= {
101 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
102 .has_overlay
= 1, .overlay_needs_physical
= 1,
103 .ring_mask
= RENDER_RING
,
104 GEN_DEFAULT_PIPEOFFSETS
,
107 static const struct intel_device_info intel_i915gm_info
= {
108 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
109 .cursor_needs_physical
= 1,
110 .has_overlay
= 1, .overlay_needs_physical
= 1,
113 .ring_mask
= RENDER_RING
,
114 GEN_DEFAULT_PIPEOFFSETS
,
117 static const struct intel_device_info intel_i945g_info
= {
118 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
119 .has_overlay
= 1, .overlay_needs_physical
= 1,
120 .ring_mask
= RENDER_RING
,
121 GEN_DEFAULT_PIPEOFFSETS
,
124 static const struct intel_device_info intel_i945gm_info
= {
125 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
126 .has_hotplug
= 1, .cursor_needs_physical
= 1,
127 .has_overlay
= 1, .overlay_needs_physical
= 1,
130 .ring_mask
= RENDER_RING
,
131 GEN_DEFAULT_PIPEOFFSETS
,
135 static const struct intel_device_info intel_i965g_info
= {
136 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
139 .ring_mask
= RENDER_RING
,
140 GEN_DEFAULT_PIPEOFFSETS
,
144 static const struct intel_device_info intel_i965gm_info
= {
145 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
146 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
149 .ring_mask
= RENDER_RING
,
150 GEN_DEFAULT_PIPEOFFSETS
,
154 static const struct intel_device_info intel_g33_info
= {
155 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
156 .need_gfx_hws
= 1, .has_hotplug
= 1,
158 .ring_mask
= RENDER_RING
,
159 GEN_DEFAULT_PIPEOFFSETS
,
163 static const struct intel_device_info intel_g45_info
= {
164 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
165 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
166 .ring_mask
= RENDER_RING
| BSD_RING
,
167 GEN_DEFAULT_PIPEOFFSETS
,
171 static const struct intel_device_info intel_gm45_info
= {
172 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
173 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
174 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
176 .ring_mask
= RENDER_RING
| BSD_RING
,
177 GEN_DEFAULT_PIPEOFFSETS
,
181 static const struct intel_device_info intel_pineview_info
= {
182 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
183 .need_gfx_hws
= 1, .has_hotplug
= 1,
185 GEN_DEFAULT_PIPEOFFSETS
,
189 static const struct intel_device_info intel_ironlake_d_info
= {
190 .gen
= 5, .num_pipes
= 2,
191 .need_gfx_hws
= 1, .has_hotplug
= 1,
192 .ring_mask
= RENDER_RING
| BSD_RING
,
193 GEN_DEFAULT_PIPEOFFSETS
,
197 static const struct intel_device_info intel_ironlake_m_info
= {
198 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
199 .need_gfx_hws
= 1, .has_hotplug
= 1,
201 .ring_mask
= RENDER_RING
| BSD_RING
,
202 GEN_DEFAULT_PIPEOFFSETS
,
206 static const struct intel_device_info intel_sandybridge_d_info
= {
207 .gen
= 6, .num_pipes
= 2,
208 .need_gfx_hws
= 1, .has_hotplug
= 1,
210 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
212 GEN_DEFAULT_PIPEOFFSETS
,
216 static const struct intel_device_info intel_sandybridge_m_info
= {
217 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
218 .need_gfx_hws
= 1, .has_hotplug
= 1,
220 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
222 GEN_DEFAULT_PIPEOFFSETS
,
226 #define GEN7_FEATURES \
227 .gen = 7, .num_pipes = 3, \
228 .need_gfx_hws = 1, .has_hotplug = 1, \
230 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
233 static const struct intel_device_info intel_ivybridge_d_info
= {
236 GEN_DEFAULT_PIPEOFFSETS
,
240 static const struct intel_device_info intel_ivybridge_m_info
= {
244 GEN_DEFAULT_PIPEOFFSETS
,
248 static const struct intel_device_info intel_ivybridge_q_info
= {
251 .num_pipes
= 0, /* legal, last one wins */
252 GEN_DEFAULT_PIPEOFFSETS
,
256 static const struct intel_device_info intel_valleyview_m_info
= {
261 .display_mmio_offset
= VLV_DISPLAY_BASE
,
262 .has_fbc
= 0, /* legal, last one wins */
263 .has_llc
= 0, /* legal, last one wins */
264 GEN_DEFAULT_PIPEOFFSETS
,
268 static const struct intel_device_info intel_valleyview_d_info
= {
272 .display_mmio_offset
= VLV_DISPLAY_BASE
,
273 .has_fbc
= 0, /* legal, last one wins */
274 .has_llc
= 0, /* legal, last one wins */
275 GEN_DEFAULT_PIPEOFFSETS
,
279 static const struct intel_device_info intel_haswell_d_info
= {
284 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
285 GEN_DEFAULT_PIPEOFFSETS
,
289 static const struct intel_device_info intel_haswell_m_info
= {
295 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
296 GEN_DEFAULT_PIPEOFFSETS
,
300 static const struct intel_device_info intel_broadwell_d_info
= {
301 .gen
= 8, .num_pipes
= 3,
302 .need_gfx_hws
= 1, .has_hotplug
= 1,
303 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
308 GEN_DEFAULT_PIPEOFFSETS
,
312 static const struct intel_device_info intel_broadwell_m_info
= {
313 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
314 .need_gfx_hws
= 1, .has_hotplug
= 1,
315 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
320 GEN_DEFAULT_PIPEOFFSETS
,
324 static const struct intel_device_info intel_broadwell_gt3d_info
= {
325 .gen
= 8, .num_pipes
= 3,
326 .need_gfx_hws
= 1, .has_hotplug
= 1,
327 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
332 GEN_DEFAULT_PIPEOFFSETS
,
336 static const struct intel_device_info intel_broadwell_gt3m_info
= {
337 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
338 .need_gfx_hws
= 1, .has_hotplug
= 1,
339 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
344 GEN_DEFAULT_PIPEOFFSETS
,
348 static const struct intel_device_info intel_cherryview_info
= {
349 .gen
= 8, .num_pipes
= 3,
350 .need_gfx_hws
= 1, .has_hotplug
= 1,
351 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
353 .display_mmio_offset
= VLV_DISPLAY_BASE
,
358 static const struct intel_device_info intel_skylake_info
= {
361 .gen
= 9, .num_pipes
= 3,
362 .need_gfx_hws
= 1, .has_hotplug
= 1,
363 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
367 GEN_DEFAULT_PIPEOFFSETS
,
371 static const struct intel_device_info intel_skylake_gt3_info
= {
374 .gen
= 9, .num_pipes
= 3,
375 .need_gfx_hws
= 1, .has_hotplug
= 1,
376 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
380 GEN_DEFAULT_PIPEOFFSETS
,
384 static const struct intel_device_info intel_broxton_info
= {
387 .need_gfx_hws
= 1, .has_hotplug
= 1,
388 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
392 GEN_DEFAULT_PIPEOFFSETS
,
397 * Make sure any device matches here are from most specific to most
398 * general. For example, since the Quanta match is based on the subsystem
399 * and subvendor IDs, we need it to come before the more general IVB
400 * PCI ID matches, otherwise we'll use the wrong info struct above.
402 #define INTEL_PCI_IDS \
403 INTEL_I830_IDS(&intel_i830_info), \
404 INTEL_I845G_IDS(&intel_845g_info), \
405 INTEL_I85X_IDS(&intel_i85x_info), \
406 INTEL_I865G_IDS(&intel_i865g_info), \
407 INTEL_I915G_IDS(&intel_i915g_info), \
408 INTEL_I915GM_IDS(&intel_i915gm_info), \
409 INTEL_I945G_IDS(&intel_i945g_info), \
410 INTEL_I945GM_IDS(&intel_i945gm_info), \
411 INTEL_I965G_IDS(&intel_i965g_info), \
412 INTEL_G33_IDS(&intel_g33_info), \
413 INTEL_I965GM_IDS(&intel_i965gm_info), \
414 INTEL_GM45_IDS(&intel_gm45_info), \
415 INTEL_G45_IDS(&intel_g45_info), \
416 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
417 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
418 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
419 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
420 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
421 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
422 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
423 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
424 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
425 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
426 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
427 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
428 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
429 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
430 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
431 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info), \
432 INTEL_CHV_IDS(&intel_cherryview_info), \
433 INTEL_SKL_GT1_IDS(&intel_skylake_info), \
434 INTEL_SKL_GT2_IDS(&intel_skylake_info), \
435 INTEL_SKL_GT3_IDS(&intel_skylake_gt3_info), \
436 INTEL_BXT_IDS(&intel_broxton_info)
438 static const struct pci_device_id pciidlist
[] = { /* aka */
443 #if defined(CONFIG_DRM_I915_KMS)
444 MODULE_DEVICE_TABLE(pci
, pciidlist
);
447 void intel_detect_pch(struct drm_device
*dev
)
449 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
450 struct pci_dev
*pch
= NULL
;
452 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
453 * (which really amounts to a PCH but no South Display).
455 if (INTEL_INFO(dev
)->num_pipes
== 0) {
456 dev_priv
->pch_type
= PCH_NOP
;
461 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
462 * make graphics device passthrough work easy for VMM, that only
463 * need to expose ISA bridge to let driver know the real hardware
464 * underneath. This is a requirement from virtualization team.
466 * In some virtualized environments (e.g. XEN), there is irrelevant
467 * ISA bridge in the system. To work reliably, we should scan trhough
468 * all the ISA bridge devices and check for the first match, instead
469 * of only checking the first one.
471 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
472 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
473 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
474 dev_priv
->pch_id
= id
;
476 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
477 dev_priv
->pch_type
= PCH_IBX
;
478 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
479 WARN_ON(!IS_GEN5(dev
));
480 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
481 dev_priv
->pch_type
= PCH_CPT
;
482 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
483 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
484 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
485 /* PantherPoint is CPT compatible */
486 dev_priv
->pch_type
= PCH_CPT
;
487 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
488 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
489 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
490 dev_priv
->pch_type
= PCH_LPT
;
491 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
492 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
493 WARN_ON(IS_HSW_ULT(dev
) || IS_BDW_ULT(dev
));
494 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
495 dev_priv
->pch_type
= PCH_LPT
;
496 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
497 WARN_ON(!IS_HASWELL(dev
) && !IS_BROADWELL(dev
));
498 WARN_ON(!IS_HSW_ULT(dev
) && !IS_BDW_ULT(dev
));
499 } else if (id
== INTEL_PCH_SPT_DEVICE_ID_TYPE
) {
500 dev_priv
->pch_type
= PCH_SPT
;
501 DRM_DEBUG_KMS("Found SunrisePoint PCH\n");
502 WARN_ON(!IS_SKYLAKE(dev
));
503 } else if (id
== INTEL_PCH_SPT_LP_DEVICE_ID_TYPE
) {
504 dev_priv
->pch_type
= PCH_SPT
;
505 DRM_DEBUG_KMS("Found SunrisePoint LP PCH\n");
506 WARN_ON(!IS_SKYLAKE(dev
));
514 DRM_DEBUG_KMS("No PCH found.\n");
519 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
521 if (INTEL_INFO(dev
)->gen
< 6)
524 if (i915
.semaphores
>= 0)
525 return i915
.semaphores
;
527 /* TODO: make semaphores and Execlists play nicely together */
528 if (i915
.enable_execlists
)
531 /* Until we get further testing... */
535 #ifdef CONFIG_INTEL_IOMMU
536 /* Enable semaphores on SNB when IO remapping is off */
537 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
544 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
)
546 spin_lock_irq(&dev_priv
->irq_lock
);
548 dev_priv
->long_hpd_port_mask
= 0;
549 dev_priv
->short_hpd_port_mask
= 0;
550 dev_priv
->hpd_event_bits
= 0;
552 spin_unlock_irq(&dev_priv
->irq_lock
);
554 cancel_work_sync(&dev_priv
->dig_port_work
);
555 cancel_work_sync(&dev_priv
->hotplug_work
);
556 cancel_delayed_work_sync(&dev_priv
->hotplug_reenable_work
);
559 void i915_firmware_load_error_print(const char *fw_path
, int err
)
561 DRM_ERROR("failed to load firmware %s (%d)\n", fw_path
, err
);
564 * If the reason is not known assume -ENOENT since that's the most
565 * usual failure mode.
570 if (!(IS_BUILTIN(CONFIG_DRM_I915
) && err
== -ENOENT
))
574 "The driver is built-in, so to load the firmware you need to\n"
575 "include it either in the kernel (see CONFIG_EXTRA_FIRMWARE) or\n"
576 "in your initrd/initramfs image.\n");
579 static void intel_suspend_encoders(struct drm_i915_private
*dev_priv
)
581 struct drm_device
*dev
= dev_priv
->dev
;
582 struct drm_encoder
*encoder
;
584 drm_modeset_lock_all(dev
);
585 list_for_each_entry(encoder
, &dev
->mode_config
.encoder_list
, head
) {
586 struct intel_encoder
*intel_encoder
= to_intel_encoder(encoder
);
588 if (intel_encoder
->suspend
)
589 intel_encoder
->suspend(intel_encoder
);
591 drm_modeset_unlock_all(dev
);
594 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
);
595 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
597 static int skl_resume_prepare(struct drm_i915_private
*dev_priv
);
600 static int i915_drm_suspend(struct drm_device
*dev
)
602 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
603 struct drm_crtc
*crtc
;
604 pci_power_t opregion_target_state
;
607 /* ignore lid events during suspend */
608 mutex_lock(&dev_priv
->modeset_restore_lock
);
609 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
610 mutex_unlock(&dev_priv
->modeset_restore_lock
);
612 /* We do a lot of poking in a lot of registers, make sure they work
614 intel_display_set_init_power(dev_priv
, true);
616 drm_kms_helper_poll_disable(dev
);
618 pci_save_state(dev
->pdev
);
620 error
= i915_gem_suspend(dev
);
622 dev_err(&dev
->pdev
->dev
,
623 "GEM idle failed, resume might fail\n");
627 intel_suspend_gt_powersave(dev
);
630 * Disable CRTCs directly since we want to preserve sw state
631 * for _thaw. Also, power gate the CRTC power wells.
633 drm_modeset_lock_all(dev
);
634 for_each_crtc(dev
, crtc
)
635 intel_crtc_control(crtc
, false);
636 drm_modeset_unlock_all(dev
);
638 intel_dp_mst_suspend(dev
);
640 intel_runtime_pm_disable_interrupts(dev_priv
);
641 intel_hpd_cancel_work(dev_priv
);
643 intel_suspend_encoders(dev_priv
);
645 intel_suspend_hw(dev
);
647 i915_gem_suspend_gtt_mappings(dev
);
649 i915_save_state(dev
);
651 opregion_target_state
= PCI_D3cold
;
652 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
653 if (acpi_target_system_state() < ACPI_STATE_S3
)
654 opregion_target_state
= PCI_D1
;
656 intel_opregion_notify_adapter(dev
, opregion_target_state
);
658 intel_uncore_forcewake_reset(dev
, false);
659 intel_opregion_fini(dev
);
661 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
, true);
663 dev_priv
->suspend_count
++;
665 intel_display_set_init_power(dev_priv
, false);
670 static int i915_drm_suspend_late(struct drm_device
*drm_dev
, bool hibernation
)
672 struct drm_i915_private
*dev_priv
= drm_dev
->dev_private
;
675 ret
= intel_suspend_complete(dev_priv
);
678 DRM_ERROR("Suspend complete failed: %d\n", ret
);
683 pci_disable_device(drm_dev
->pdev
);
685 * During hibernation on some GEN4 platforms the BIOS may try to access
686 * the device even though it's already in D3 and hang the machine. So
687 * leave the device in D0 on those platforms and hope the BIOS will
688 * power down the device properly. Platforms where this was seen:
689 * Lenovo Thinkpad X301, X61s
692 drm_dev
->pdev
->subsystem_vendor
== PCI_VENDOR_ID_LENOVO
&&
693 INTEL_INFO(dev_priv
)->gen
== 4))
694 pci_set_power_state(drm_dev
->pdev
, PCI_D3hot
);
699 int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
)
703 if (!dev
|| !dev
->dev_private
) {
704 DRM_ERROR("dev: %p\n", dev
);
705 DRM_ERROR("DRM not initialized, aborting suspend.\n");
709 if (WARN_ON_ONCE(state
.event
!= PM_EVENT_SUSPEND
&&
710 state
.event
!= PM_EVENT_FREEZE
))
713 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
716 error
= i915_drm_suspend(dev
);
720 return i915_drm_suspend_late(dev
, false);
723 static int i915_drm_resume(struct drm_device
*dev
)
725 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
727 mutex_lock(&dev
->struct_mutex
);
728 i915_gem_restore_gtt_mappings(dev
);
729 mutex_unlock(&dev
->struct_mutex
);
731 i915_restore_state(dev
);
732 intel_opregion_setup(dev
);
734 intel_init_pch_refclk(dev
);
735 drm_mode_config_reset(dev
);
737 mutex_lock(&dev
->struct_mutex
);
738 if (i915_gem_init_hw(dev
)) {
739 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
740 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
742 mutex_unlock(&dev
->struct_mutex
);
744 /* We need working interrupts for modeset enabling ... */
745 intel_runtime_pm_enable_interrupts(dev_priv
);
747 intel_modeset_init_hw(dev
);
749 spin_lock_irq(&dev_priv
->irq_lock
);
750 if (dev_priv
->display
.hpd_irq_setup
)
751 dev_priv
->display
.hpd_irq_setup(dev
);
752 spin_unlock_irq(&dev_priv
->irq_lock
);
754 drm_modeset_lock_all(dev
);
755 intel_modeset_setup_hw_state(dev
, true);
756 drm_modeset_unlock_all(dev
);
758 intel_dp_mst_resume(dev
);
761 * ... but also need to make sure that hotplug processing
762 * doesn't cause havoc. Like in the driver load code we don't
763 * bother with the tiny race here where we might loose hotplug
766 intel_hpd_init(dev_priv
);
767 /* Config may have changed between suspend and resume */
768 drm_helper_hpd_irq_event(dev
);
770 intel_opregion_init(dev
);
772 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
, false);
774 mutex_lock(&dev_priv
->modeset_restore_lock
);
775 dev_priv
->modeset_restore
= MODESET_DONE
;
776 mutex_unlock(&dev_priv
->modeset_restore_lock
);
778 intel_opregion_notify_adapter(dev
, PCI_D0
);
780 drm_kms_helper_poll_enable(dev
);
785 static int i915_drm_resume_early(struct drm_device
*dev
)
787 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
791 * We have a resume ordering issue with the snd-hda driver also
792 * requiring our device to be power up. Due to the lack of a
793 * parent/child relationship we currently solve this with an early
796 * FIXME: This should be solved with a special hdmi sink device or
797 * similar so that power domains can be employed.
799 if (pci_enable_device(dev
->pdev
))
802 pci_set_master(dev
->pdev
);
804 if (IS_VALLEYVIEW(dev_priv
))
805 ret
= vlv_resume_prepare(dev_priv
, false);
807 DRM_ERROR("Resume prepare failed: %d,Continuing resume\n", ret
);
809 intel_uncore_early_sanitize(dev
, true);
811 if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
812 hsw_disable_pc8(dev_priv
);
813 else if (IS_SKYLAKE(dev_priv
))
814 ret
= skl_resume_prepare(dev_priv
);
816 intel_uncore_sanitize(dev
);
817 intel_power_domains_init_hw(dev_priv
);
822 int i915_resume_legacy(struct drm_device
*dev
)
826 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
829 ret
= i915_drm_resume_early(dev
);
833 return i915_drm_resume(dev
);
837 * i915_reset - reset chip after a hang
838 * @dev: drm device to reset
840 * Reset the chip. Useful if a hang is detected. Returns zero on successful
841 * reset or otherwise an error code.
843 * Procedure is fairly simple:
844 * - reset the chip using the reset reg
845 * - re-init context state
846 * - re-init hardware status page
847 * - re-init ring buffer
848 * - re-init interrupt state
851 int i915_reset(struct drm_device
*dev
)
853 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
860 intel_reset_gt_powersave(dev
);
862 mutex_lock(&dev
->struct_mutex
);
866 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
868 ret
= intel_gpu_reset(dev
);
870 /* Also reset the gpu hangman. */
872 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
873 dev_priv
->gpu_error
.stop_rings
= 0;
874 if (ret
== -ENODEV
) {
875 DRM_INFO("Reset not implemented, but ignoring "
876 "error for simulated gpu hangs\n");
881 if (i915_stop_ring_allow_warn(dev_priv
))
882 pr_notice("drm/i915: Resetting chip after gpu hang\n");
885 DRM_ERROR("Failed to reset chip: %i\n", ret
);
886 mutex_unlock(&dev
->struct_mutex
);
890 intel_overlay_reset(dev_priv
);
892 /* Ok, now get things going again... */
895 * Everything depends on having the GTT running, so we need to start
896 * there. Fortunately we don't need to do this unless we reset the
897 * chip at a PCI level.
899 * Next we need to restore the context, but we don't use those
902 * Ring buffer needs to be re-initialized in the KMS case, or if X
903 * was running at the time of the reset (i.e. we weren't VT
907 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
908 dev_priv
->gpu_error
.reload_in_reset
= true;
910 ret
= i915_gem_init_hw(dev
);
912 dev_priv
->gpu_error
.reload_in_reset
= false;
914 mutex_unlock(&dev
->struct_mutex
);
916 DRM_ERROR("Failed hw init on reset %d\n", ret
);
921 * rps/rc6 re-init is necessary to restore state lost after the
922 * reset and the re-install of gt irqs. Skip for ironlake per
923 * previous concerns that it doesn't respond well to some forms
924 * of re-init after reset.
926 if (INTEL_INFO(dev
)->gen
> 5)
927 intel_enable_gt_powersave(dev
);
932 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
934 struct intel_device_info
*intel_info
=
935 (struct intel_device_info
*) ent
->driver_data
;
937 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
938 DRM_INFO("This hardware requires preliminary hardware support.\n"
939 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
943 /* Only bind to function 0 of the device. Early generations
944 * used function 1 as a placeholder for multi-head. This causes
945 * us confusion instead, especially on the systems where both
946 * functions have the same PCI-ID!
948 if (PCI_FUNC(pdev
->devfn
))
951 driver
.driver_features
&= ~(DRIVER_USE_AGP
);
953 return drm_get_pci_dev(pdev
, ent
, &driver
);
957 i915_pci_remove(struct pci_dev
*pdev
)
959 struct drm_device
*dev
= pci_get_drvdata(pdev
);
964 static int i915_pm_suspend(struct device
*dev
)
966 struct pci_dev
*pdev
= to_pci_dev(dev
);
967 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
969 if (!drm_dev
|| !drm_dev
->dev_private
) {
970 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
974 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
977 return i915_drm_suspend(drm_dev
);
980 static int i915_pm_suspend_late(struct device
*dev
)
982 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
985 * We have a suspedn ordering issue with the snd-hda driver also
986 * requiring our device to be power up. Due to the lack of a
987 * parent/child relationship we currently solve this with an late
990 * FIXME: This should be solved with a special hdmi sink device or
991 * similar so that power domains can be employed.
993 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
996 return i915_drm_suspend_late(drm_dev
, false);
999 static int i915_pm_poweroff_late(struct device
*dev
)
1001 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1003 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1006 return i915_drm_suspend_late(drm_dev
, true);
1009 static int i915_pm_resume_early(struct device
*dev
)
1011 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1013 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1016 return i915_drm_resume_early(drm_dev
);
1019 static int i915_pm_resume(struct device
*dev
)
1021 struct drm_device
*drm_dev
= dev_to_i915(dev
)->dev
;
1023 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
1026 return i915_drm_resume(drm_dev
);
1029 static int skl_suspend_complete(struct drm_i915_private
*dev_priv
)
1031 /* Enabling DC6 is not a hard requirement to enter runtime D3 */
1034 * This is to ensure that CSR isn't identified as loaded before
1035 * CSR-loading program is called during runtime-resume.
1037 intel_csr_load_status_set(dev_priv
, FW_UNINITIALIZED
);
1042 static int hsw_suspend_complete(struct drm_i915_private
*dev_priv
)
1044 hsw_enable_pc8(dev_priv
);
1049 static int bxt_suspend_complete(struct drm_i915_private
*dev_priv
)
1051 struct drm_device
*dev
= dev_priv
->dev
;
1053 /* TODO: when DC5 support is added disable DC5 here. */
1055 broxton_ddi_phy_uninit(dev
);
1056 broxton_uninit_cdclk(dev
);
1057 bxt_enable_dc9(dev_priv
);
1062 static int bxt_resume_prepare(struct drm_i915_private
*dev_priv
)
1064 struct drm_device
*dev
= dev_priv
->dev
;
1066 /* TODO: when CSR FW support is added make sure the FW is loaded */
1068 bxt_disable_dc9(dev_priv
);
1071 * TODO: when DC5 support is added enable DC5 here if the CSR FW
1074 broxton_init_cdclk(dev
);
1075 broxton_ddi_phy_init(dev
);
1076 intel_prepare_ddi(dev
);
1081 static int skl_resume_prepare(struct drm_i915_private
*dev_priv
)
1083 struct drm_device
*dev
= dev_priv
->dev
;
1085 intel_csr_load_program(dev
);
1091 * Save all Gunit registers that may be lost after a D3 and a subsequent
1092 * S0i[R123] transition. The list of registers needing a save/restore is
1093 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
1094 * registers in the following way:
1095 * - Driver: saved/restored by the driver
1096 * - Punit : saved/restored by the Punit firmware
1097 * - No, w/o marking: no need to save/restore, since the register is R/O or
1098 * used internally by the HW in a way that doesn't depend
1099 * keeping the content across a suspend/resume.
1100 * - Debug : used for debugging
1102 * We save/restore all registers marked with 'Driver', with the following
1104 * - Registers out of use, including also registers marked with 'Debug'.
1105 * These have no effect on the driver's operation, so we don't save/restore
1106 * them to reduce the overhead.
1107 * - Registers that are fully setup by an initialization function called from
1108 * the resume path. For example many clock gating and RPS/RC6 registers.
1109 * - Registers that provide the right functionality with their reset defaults.
1111 * TODO: Except for registers that based on the above 3 criteria can be safely
1112 * ignored, we save/restore all others, practically treating the HW context as
1113 * a black-box for the driver. Further investigation is needed to reduce the
1114 * saved/restored registers even further, by following the same 3 criteria.
1116 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1118 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1121 /* GAM 0x4000-0x4770 */
1122 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
1123 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
1124 s
->arb_mode
= I915_READ(ARB_MODE
);
1125 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
1126 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
1128 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1129 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS_BASE
+ i
* 4);
1131 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
1132 s
->gfx_max_req_count
= I915_READ(GEN7_GFX_MAX_REQ_COUNT
);
1134 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
1135 s
->ecochk
= I915_READ(GAM_ECOCHK
);
1136 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
1137 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
1139 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
1141 /* MBC 0x9024-0x91D0, 0x8500 */
1142 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
1143 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
1144 s
->mbctl
= I915_READ(GEN6_MBCTL
);
1146 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1147 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1148 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1149 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1150 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1151 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1152 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1154 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1155 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1156 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1157 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1158 s
->ecobus
= I915_READ(ECOBUS
);
1159 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1160 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1161 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1162 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1163 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1164 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1166 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1167 s
->gt_imr
= I915_READ(GTIMR
);
1168 s
->gt_ier
= I915_READ(GTIER
);
1169 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1170 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1172 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1173 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH_BASE
+ i
* 4);
1175 /* GT SA CZ domain, 0x100000-0x138124 */
1176 s
->tilectl
= I915_READ(TILECTL
);
1177 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1178 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1179 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1180 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1182 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1183 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1184 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1185 s
->pcbr
= I915_READ(VLV_PCBR
);
1186 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1189 * Not saving any of:
1190 * DFT, 0x9800-0x9EC0
1191 * SARB, 0xB000-0xB1FC
1192 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1197 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1199 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1203 /* GAM 0x4000-0x4770 */
1204 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1205 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1206 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1207 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1208 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1210 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1211 I915_WRITE(GEN7_LRA_LIMITS_BASE
+ i
* 4, s
->lra_limits
[i
]);
1213 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1214 I915_WRITE(GEN7_GFX_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1216 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1217 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1218 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1219 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1221 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1223 /* MBC 0x9024-0x91D0, 0x8500 */
1224 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1225 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1226 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1228 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1229 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1230 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1231 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1232 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1233 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1234 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1236 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1237 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1238 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1239 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1240 I915_WRITE(ECOBUS
, s
->ecobus
);
1241 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1242 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1243 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1244 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1245 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1246 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1248 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1249 I915_WRITE(GTIMR
, s
->gt_imr
);
1250 I915_WRITE(GTIER
, s
->gt_ier
);
1251 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1252 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1254 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1255 I915_WRITE(GEN7_GT_SCRATCH_BASE
+ i
* 4, s
->gt_scratch
[i
]);
1257 /* GT SA CZ domain, 0x100000-0x138124 */
1258 I915_WRITE(TILECTL
, s
->tilectl
);
1259 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1261 * Preserve the GT allow wake and GFX force clock bit, they are not
1262 * be restored, as they are used to control the s0ix suspend/resume
1263 * sequence by the caller.
1265 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1266 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1267 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1268 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1270 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1271 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1272 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1273 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1275 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1277 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1278 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1279 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1280 I915_WRITE(VLV_PCBR
, s
->pcbr
);
1281 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1284 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1289 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1291 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1292 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1294 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1295 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1300 err
= wait_for(COND
, 20);
1302 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1303 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1309 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1314 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1315 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1317 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1318 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1319 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1321 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1323 err
= wait_for(COND
, 1);
1325 DRM_ERROR("timeout disabling GT waking\n");
1330 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1337 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1338 val
= wait_for_on
? mask
: 0;
1339 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1343 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1344 wait_for_on
? "on" : "off",
1345 I915_READ(VLV_GTLC_PW_STATUS
));
1348 * RC6 transitioning can be delayed up to 2 msec (see
1349 * valleyview_enable_rps), use 3 msec for safety.
1351 err
= wait_for(COND
, 3);
1353 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1354 wait_for_on
? "on" : "off");
1360 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1362 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1365 DRM_ERROR("GT register access while GT waking disabled\n");
1366 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1369 static int vlv_suspend_complete(struct drm_i915_private
*dev_priv
)
1375 * Bspec defines the following GT well on flags as debug only, so
1376 * don't treat them as hard failures.
1378 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1380 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1381 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1383 vlv_check_no_gt_access(dev_priv
);
1385 err
= vlv_force_gfx_clock(dev_priv
, true);
1389 err
= vlv_allow_gt_wake(dev_priv
, false);
1393 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1394 vlv_save_gunit_s0ix_state(dev_priv
);
1396 err
= vlv_force_gfx_clock(dev_priv
, false);
1403 /* For safety always re-enable waking and disable gfx clock forcing */
1404 vlv_allow_gt_wake(dev_priv
, true);
1406 vlv_force_gfx_clock(dev_priv
, false);
1411 static int vlv_resume_prepare(struct drm_i915_private
*dev_priv
,
1414 struct drm_device
*dev
= dev_priv
->dev
;
1419 * If any of the steps fail just try to continue, that's the best we
1420 * can do at this point. Return the first error code (which will also
1421 * leave RPM permanently disabled).
1423 ret
= vlv_force_gfx_clock(dev_priv
, true);
1425 if (!IS_CHERRYVIEW(dev_priv
->dev
))
1426 vlv_restore_gunit_s0ix_state(dev_priv
);
1428 err
= vlv_allow_gt_wake(dev_priv
, true);
1432 err
= vlv_force_gfx_clock(dev_priv
, false);
1436 vlv_check_no_gt_access(dev_priv
);
1439 intel_init_clock_gating(dev
);
1440 i915_gem_restore_fences(dev
);
1446 static int intel_runtime_suspend(struct device
*device
)
1448 struct pci_dev
*pdev
= to_pci_dev(device
);
1449 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1450 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1453 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1456 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1459 DRM_DEBUG_KMS("Suspending device\n");
1462 * We could deadlock here in case another thread holding struct_mutex
1463 * calls RPM suspend concurrently, since the RPM suspend will wait
1464 * first for this RPM suspend to finish. In this case the concurrent
1465 * RPM resume will be followed by its RPM suspend counterpart. Still
1466 * for consistency return -EAGAIN, which will reschedule this suspend.
1468 if (!mutex_trylock(&dev
->struct_mutex
)) {
1469 DRM_DEBUG_KMS("device lock contention, deffering suspend\n");
1471 * Bump the expiration timestamp, otherwise the suspend won't
1474 pm_runtime_mark_last_busy(device
);
1479 * We are safe here against re-faults, since the fault handler takes
1482 i915_gem_release_all_mmaps(dev_priv
);
1483 mutex_unlock(&dev
->struct_mutex
);
1485 intel_suspend_gt_powersave(dev
);
1486 intel_runtime_pm_disable_interrupts(dev_priv
);
1488 ret
= intel_suspend_complete(dev_priv
);
1490 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1491 intel_runtime_pm_enable_interrupts(dev_priv
);
1496 cancel_delayed_work_sync(&dev_priv
->gpu_error
.hangcheck_work
);
1497 intel_uncore_forcewake_reset(dev
, false);
1498 dev_priv
->pm
.suspended
= true;
1501 * FIXME: We really should find a document that references the arguments
1504 if (IS_HASWELL(dev
)) {
1506 * current versions of firmware which depend on this opregion
1507 * notification have repurposed the D1 definition to mean
1508 * "runtime suspended" vs. what you would normally expect (D3)
1509 * to distinguish it from notifications that might be sent via
1512 intel_opregion_notify_adapter(dev
, PCI_D1
);
1515 * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1516 * being detected, and the call we do at intel_runtime_resume()
1517 * won't be able to restore them. Since PCI_D3hot matches the
1518 * actual specification and appears to be working, use it. Let's
1519 * assume the other non-Haswell platforms will stay the same as
1522 intel_opregion_notify_adapter(dev
, PCI_D3hot
);
1525 assert_forcewakes_inactive(dev_priv
);
1527 DRM_DEBUG_KMS("Device suspended\n");
1531 static int intel_runtime_resume(struct device
*device
)
1533 struct pci_dev
*pdev
= to_pci_dev(device
);
1534 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1535 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1538 if (WARN_ON_ONCE(!HAS_RUNTIME_PM(dev
)))
1541 DRM_DEBUG_KMS("Resuming device\n");
1543 intel_opregion_notify_adapter(dev
, PCI_D0
);
1544 dev_priv
->pm
.suspended
= false;
1546 if (IS_GEN6(dev_priv
))
1547 intel_init_pch_refclk(dev
);
1549 if (IS_BROXTON(dev
))
1550 ret
= bxt_resume_prepare(dev_priv
);
1551 else if (IS_SKYLAKE(dev
))
1552 ret
= skl_resume_prepare(dev_priv
);
1553 else if (IS_HASWELL(dev_priv
) || IS_BROADWELL(dev_priv
))
1554 hsw_disable_pc8(dev_priv
);
1555 else if (IS_VALLEYVIEW(dev_priv
))
1556 ret
= vlv_resume_prepare(dev_priv
, true);
1559 * No point of rolling back things in case of an error, as the best
1560 * we can do is to hope that things will still work (and disable RPM).
1562 i915_gem_init_swizzling(dev
);
1563 gen6_update_ring_freq(dev
);
1565 intel_runtime_pm_enable_interrupts(dev_priv
);
1566 intel_enable_gt_powersave(dev
);
1569 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1571 DRM_DEBUG_KMS("Device resumed\n");
1577 * This function implements common functionality of runtime and system
1580 static int intel_suspend_complete(struct drm_i915_private
*dev_priv
)
1582 struct drm_device
*dev
= dev_priv
->dev
;
1585 if (IS_BROXTON(dev
))
1586 ret
= bxt_suspend_complete(dev_priv
);
1587 else if (IS_SKYLAKE(dev
))
1588 ret
= skl_suspend_complete(dev_priv
);
1589 else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
))
1590 ret
= hsw_suspend_complete(dev_priv
);
1591 else if (IS_VALLEYVIEW(dev
))
1592 ret
= vlv_suspend_complete(dev_priv
);
1599 static const struct dev_pm_ops i915_pm_ops
= {
1601 * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1604 .suspend
= i915_pm_suspend
,
1605 .suspend_late
= i915_pm_suspend_late
,
1606 .resume_early
= i915_pm_resume_early
,
1607 .resume
= i915_pm_resume
,
1611 * @freeze, @freeze_late : called (1) before creating the
1612 * hibernation image [PMSG_FREEZE] and
1613 * (2) after rebooting, before restoring
1614 * the image [PMSG_QUIESCE]
1615 * @thaw, @thaw_early : called (1) after creating the hibernation
1616 * image, before writing it [PMSG_THAW]
1617 * and (2) after failing to create or
1618 * restore the image [PMSG_RECOVER]
1619 * @poweroff, @poweroff_late: called after writing the hibernation
1620 * image, before rebooting [PMSG_HIBERNATE]
1621 * @restore, @restore_early : called after rebooting and restoring the
1622 * hibernation image [PMSG_RESTORE]
1624 .freeze
= i915_pm_suspend
,
1625 .freeze_late
= i915_pm_suspend_late
,
1626 .thaw_early
= i915_pm_resume_early
,
1627 .thaw
= i915_pm_resume
,
1628 .poweroff
= i915_pm_suspend
,
1629 .poweroff_late
= i915_pm_poweroff_late
,
1630 .restore_early
= i915_pm_resume_early
,
1631 .restore
= i915_pm_resume
,
1633 /* S0ix (via runtime suspend) event handlers */
1634 .runtime_suspend
= intel_runtime_suspend
,
1635 .runtime_resume
= intel_runtime_resume
,
1638 static const struct vm_operations_struct i915_gem_vm_ops
= {
1639 .fault
= i915_gem_fault
,
1640 .open
= drm_gem_vm_open
,
1641 .close
= drm_gem_vm_close
,
1644 static const struct file_operations i915_driver_fops
= {
1645 .owner
= THIS_MODULE
,
1647 .release
= drm_release
,
1648 .unlocked_ioctl
= drm_ioctl
,
1649 .mmap
= drm_gem_mmap
,
1652 #ifdef CONFIG_COMPAT
1653 .compat_ioctl
= i915_compat_ioctl
,
1655 .llseek
= noop_llseek
,
1658 static struct drm_driver driver
= {
1659 /* Don't use MTRRs here; the Xserver or userspace app should
1660 * deal with them for Intel hardware.
1664 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1666 .load
= i915_driver_load
,
1667 .unload
= i915_driver_unload
,
1668 .open
= i915_driver_open
,
1669 .lastclose
= i915_driver_lastclose
,
1670 .preclose
= i915_driver_preclose
,
1671 .postclose
= i915_driver_postclose
,
1672 .set_busid
= drm_pci_set_busid
,
1674 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1675 .suspend
= i915_suspend_legacy
,
1676 .resume
= i915_resume_legacy
,
1678 .device_is_agp
= i915_driver_device_is_agp
,
1679 #if defined(CONFIG_DEBUG_FS)
1680 .debugfs_init
= i915_debugfs_init
,
1681 .debugfs_cleanup
= i915_debugfs_cleanup
,
1683 .gem_free_object
= i915_gem_free_object
,
1684 .gem_vm_ops
= &i915_gem_vm_ops
,
1686 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1687 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1688 .gem_prime_export
= i915_gem_prime_export
,
1689 .gem_prime_import
= i915_gem_prime_import
,
1691 .dumb_create
= i915_gem_dumb_create
,
1692 .dumb_map_offset
= i915_gem_mmap_gtt
,
1693 .dumb_destroy
= drm_gem_dumb_destroy
,
1694 .ioctls
= i915_ioctls
,
1695 .fops
= &i915_driver_fops
,
1696 .name
= DRIVER_NAME
,
1697 .desc
= DRIVER_DESC
,
1698 .date
= DRIVER_DATE
,
1699 .major
= DRIVER_MAJOR
,
1700 .minor
= DRIVER_MINOR
,
1701 .patchlevel
= DRIVER_PATCHLEVEL
,
1704 static struct pci_driver i915_pci_driver
= {
1705 .name
= DRIVER_NAME
,
1706 .id_table
= pciidlist
,
1707 .probe
= i915_pci_probe
,
1708 .remove
= i915_pci_remove
,
1709 .driver
.pm
= &i915_pm_ops
,
1712 static int __init
i915_init(void)
1714 driver
.num_ioctls
= i915_max_ioctl
;
1717 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1718 * explicitly disabled with the module pararmeter.
1720 * Otherwise, just follow the parameter (defaulting to off).
1722 * Allow optional vga_text_mode_force boot option to override
1723 * the default behavior.
1725 #if defined(CONFIG_DRM_I915_KMS)
1726 if (i915
.modeset
!= 0)
1727 driver
.driver_features
|= DRIVER_MODESET
;
1729 if (i915
.modeset
== 1)
1730 driver
.driver_features
|= DRIVER_MODESET
;
1732 #ifdef CONFIG_VGA_CONSOLE
1733 if (vgacon_text_force() && i915
.modeset
== -1)
1734 driver
.driver_features
&= ~DRIVER_MODESET
;
1737 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1738 driver
.get_vblank_timestamp
= NULL
;
1739 /* Silently fail loading to not upset userspace. */
1740 DRM_DEBUG_DRIVER("KMS and UMS disabled.\n");
1745 * FIXME: Note that we're lying to the DRM core here so that we can get access
1746 * to the atomic ioctl and the atomic properties. Only plane operations on
1747 * a single CRTC will actually work.
1749 if (i915
.nuclear_pageflip
)
1750 driver
.driver_features
|= DRIVER_ATOMIC
;
1752 return drm_pci_init(&driver
, &i915_pci_driver
);
1755 static void __exit
i915_exit(void)
1757 if (!(driver
.driver_features
& DRIVER_MODESET
))
1758 return; /* Never loaded a driver. */
1760 drm_pci_exit(&driver
, &i915_pci_driver
);
1763 module_init(i915_init
);
1764 module_exit(i915_exit
);
1766 MODULE_AUTHOR("Tungsten Graphics, Inc.");
1767 MODULE_AUTHOR("Intel Corporation");
1769 MODULE_DESCRIPTION(DRIVER_DESC
);
1770 MODULE_LICENSE("GPL and additional rights");