1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static struct drm_driver driver
;
43 #define GEN_DEFAULT_PIPEOFFSETS \
44 .pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
45 PIPE_C_OFFSET, PIPE_EDP_OFFSET }, \
46 .trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
47 TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET }, \
48 .dpll_offsets = { DPLL_A_OFFSET, DPLL_B_OFFSET }, \
49 .dpll_md_offsets = { DPLL_A_MD_OFFSET, DPLL_B_MD_OFFSET }, \
50 .palette_offsets = { PALETTE_A_OFFSET, PALETTE_B_OFFSET }
53 static const struct intel_device_info intel_i830_info
= {
54 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
55 .has_overlay
= 1, .overlay_needs_physical
= 1,
56 .ring_mask
= RENDER_RING
,
57 GEN_DEFAULT_PIPEOFFSETS
,
60 static const struct intel_device_info intel_845g_info
= {
61 .gen
= 2, .num_pipes
= 1,
62 .has_overlay
= 1, .overlay_needs_physical
= 1,
63 .ring_mask
= RENDER_RING
,
64 GEN_DEFAULT_PIPEOFFSETS
,
67 static const struct intel_device_info intel_i85x_info
= {
68 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
69 .cursor_needs_physical
= 1,
70 .has_overlay
= 1, .overlay_needs_physical
= 1,
72 .ring_mask
= RENDER_RING
,
73 GEN_DEFAULT_PIPEOFFSETS
,
76 static const struct intel_device_info intel_i865g_info
= {
77 .gen
= 2, .num_pipes
= 1,
78 .has_overlay
= 1, .overlay_needs_physical
= 1,
79 .ring_mask
= RENDER_RING
,
80 GEN_DEFAULT_PIPEOFFSETS
,
83 static const struct intel_device_info intel_i915g_info
= {
84 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
85 .has_overlay
= 1, .overlay_needs_physical
= 1,
86 .ring_mask
= RENDER_RING
,
87 GEN_DEFAULT_PIPEOFFSETS
,
89 static const struct intel_device_info intel_i915gm_info
= {
90 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
91 .cursor_needs_physical
= 1,
92 .has_overlay
= 1, .overlay_needs_physical
= 1,
95 .ring_mask
= RENDER_RING
,
96 GEN_DEFAULT_PIPEOFFSETS
,
98 static const struct intel_device_info intel_i945g_info
= {
99 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
100 .has_overlay
= 1, .overlay_needs_physical
= 1,
101 .ring_mask
= RENDER_RING
,
102 GEN_DEFAULT_PIPEOFFSETS
,
104 static const struct intel_device_info intel_i945gm_info
= {
105 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
106 .has_hotplug
= 1, .cursor_needs_physical
= 1,
107 .has_overlay
= 1, .overlay_needs_physical
= 1,
110 .ring_mask
= RENDER_RING
,
111 GEN_DEFAULT_PIPEOFFSETS
,
114 static const struct intel_device_info intel_i965g_info
= {
115 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
118 .ring_mask
= RENDER_RING
,
119 GEN_DEFAULT_PIPEOFFSETS
,
122 static const struct intel_device_info intel_i965gm_info
= {
123 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
124 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
127 .ring_mask
= RENDER_RING
,
128 GEN_DEFAULT_PIPEOFFSETS
,
131 static const struct intel_device_info intel_g33_info
= {
132 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
133 .need_gfx_hws
= 1, .has_hotplug
= 1,
135 .ring_mask
= RENDER_RING
,
136 GEN_DEFAULT_PIPEOFFSETS
,
139 static const struct intel_device_info intel_g45_info
= {
140 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
141 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
142 .ring_mask
= RENDER_RING
| BSD_RING
,
143 GEN_DEFAULT_PIPEOFFSETS
,
146 static const struct intel_device_info intel_gm45_info
= {
147 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
148 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
149 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
151 .ring_mask
= RENDER_RING
| BSD_RING
,
152 GEN_DEFAULT_PIPEOFFSETS
,
155 static const struct intel_device_info intel_pineview_info
= {
156 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
157 .need_gfx_hws
= 1, .has_hotplug
= 1,
159 GEN_DEFAULT_PIPEOFFSETS
,
162 static const struct intel_device_info intel_ironlake_d_info
= {
163 .gen
= 5, .num_pipes
= 2,
164 .need_gfx_hws
= 1, .has_hotplug
= 1,
165 .ring_mask
= RENDER_RING
| BSD_RING
,
166 GEN_DEFAULT_PIPEOFFSETS
,
169 static const struct intel_device_info intel_ironlake_m_info
= {
170 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
171 .need_gfx_hws
= 1, .has_hotplug
= 1,
173 .ring_mask
= RENDER_RING
| BSD_RING
,
174 GEN_DEFAULT_PIPEOFFSETS
,
177 static const struct intel_device_info intel_sandybridge_d_info
= {
178 .gen
= 6, .num_pipes
= 2,
179 .need_gfx_hws
= 1, .has_hotplug
= 1,
181 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
183 GEN_DEFAULT_PIPEOFFSETS
,
186 static const struct intel_device_info intel_sandybridge_m_info
= {
187 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
188 .need_gfx_hws
= 1, .has_hotplug
= 1,
190 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
,
192 GEN_DEFAULT_PIPEOFFSETS
,
195 #define GEN7_FEATURES \
196 .gen = 7, .num_pipes = 3, \
197 .need_gfx_hws = 1, .has_hotplug = 1, \
199 .ring_mask = RENDER_RING | BSD_RING | BLT_RING, \
202 static const struct intel_device_info intel_ivybridge_d_info
= {
205 GEN_DEFAULT_PIPEOFFSETS
,
208 static const struct intel_device_info intel_ivybridge_m_info
= {
212 GEN_DEFAULT_PIPEOFFSETS
,
215 static const struct intel_device_info intel_ivybridge_q_info
= {
218 .num_pipes
= 0, /* legal, last one wins */
219 GEN_DEFAULT_PIPEOFFSETS
,
222 static const struct intel_device_info intel_valleyview_m_info
= {
227 .display_mmio_offset
= VLV_DISPLAY_BASE
,
228 .has_fbc
= 0, /* legal, last one wins */
229 .has_llc
= 0, /* legal, last one wins */
230 GEN_DEFAULT_PIPEOFFSETS
,
233 static const struct intel_device_info intel_valleyview_d_info
= {
237 .display_mmio_offset
= VLV_DISPLAY_BASE
,
238 .has_fbc
= 0, /* legal, last one wins */
239 .has_llc
= 0, /* legal, last one wins */
240 GEN_DEFAULT_PIPEOFFSETS
,
243 static const struct intel_device_info intel_haswell_d_info
= {
248 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
249 GEN_DEFAULT_PIPEOFFSETS
,
252 static const struct intel_device_info intel_haswell_m_info
= {
258 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
259 GEN_DEFAULT_PIPEOFFSETS
,
262 static const struct intel_device_info intel_broadwell_d_info
= {
263 .gen
= 8, .num_pipes
= 3,
264 .need_gfx_hws
= 1, .has_hotplug
= 1,
265 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
269 GEN_DEFAULT_PIPEOFFSETS
,
272 static const struct intel_device_info intel_broadwell_m_info
= {
273 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
274 .need_gfx_hws
= 1, .has_hotplug
= 1,
275 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
,
279 GEN_DEFAULT_PIPEOFFSETS
,
282 static const struct intel_device_info intel_broadwell_gt3d_info
= {
283 .gen
= 8, .num_pipes
= 3,
284 .need_gfx_hws
= 1, .has_hotplug
= 1,
285 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
289 GEN_DEFAULT_PIPEOFFSETS
,
292 static const struct intel_device_info intel_broadwell_gt3m_info
= {
293 .gen
= 8, .is_mobile
= 1, .num_pipes
= 3,
294 .need_gfx_hws
= 1, .has_hotplug
= 1,
295 .ring_mask
= RENDER_RING
| BSD_RING
| BLT_RING
| VEBOX_RING
| BSD2_RING
,
299 GEN_DEFAULT_PIPEOFFSETS
,
303 * Make sure any device matches here are from most specific to most
304 * general. For example, since the Quanta match is based on the subsystem
305 * and subvendor IDs, we need it to come before the more general IVB
306 * PCI ID matches, otherwise we'll use the wrong info struct above.
308 #define INTEL_PCI_IDS \
309 INTEL_I830_IDS(&intel_i830_info), \
310 INTEL_I845G_IDS(&intel_845g_info), \
311 INTEL_I85X_IDS(&intel_i85x_info), \
312 INTEL_I865G_IDS(&intel_i865g_info), \
313 INTEL_I915G_IDS(&intel_i915g_info), \
314 INTEL_I915GM_IDS(&intel_i915gm_info), \
315 INTEL_I945G_IDS(&intel_i945g_info), \
316 INTEL_I945GM_IDS(&intel_i945gm_info), \
317 INTEL_I965G_IDS(&intel_i965g_info), \
318 INTEL_G33_IDS(&intel_g33_info), \
319 INTEL_I965GM_IDS(&intel_i965gm_info), \
320 INTEL_GM45_IDS(&intel_gm45_info), \
321 INTEL_G45_IDS(&intel_g45_info), \
322 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
323 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
324 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
325 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
326 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
327 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
328 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
329 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
330 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
331 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
332 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
333 INTEL_VLV_D_IDS(&intel_valleyview_d_info), \
334 INTEL_BDW_GT12M_IDS(&intel_broadwell_m_info), \
335 INTEL_BDW_GT12D_IDS(&intel_broadwell_d_info), \
336 INTEL_BDW_GT3M_IDS(&intel_broadwell_gt3m_info), \
337 INTEL_BDW_GT3D_IDS(&intel_broadwell_gt3d_info)
339 static const struct pci_device_id pciidlist
[] = { /* aka */
344 #if defined(CONFIG_DRM_I915_KMS)
345 MODULE_DEVICE_TABLE(pci
, pciidlist
);
348 void intel_detect_pch(struct drm_device
*dev
)
350 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
351 struct pci_dev
*pch
= NULL
;
353 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
354 * (which really amounts to a PCH but no South Display).
356 if (INTEL_INFO(dev
)->num_pipes
== 0) {
357 dev_priv
->pch_type
= PCH_NOP
;
362 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
363 * make graphics device passthrough work easy for VMM, that only
364 * need to expose ISA bridge to let driver know the real hardware
365 * underneath. This is a requirement from virtualization team.
367 * In some virtualized environments (e.g. XEN), there is irrelevant
368 * ISA bridge in the system. To work reliably, we should scan trhough
369 * all the ISA bridge devices and check for the first match, instead
370 * of only checking the first one.
372 while ((pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, pch
))) {
373 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
374 unsigned short id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
375 dev_priv
->pch_id
= id
;
377 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
378 dev_priv
->pch_type
= PCH_IBX
;
379 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
380 WARN_ON(!IS_GEN5(dev
));
381 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
382 dev_priv
->pch_type
= PCH_CPT
;
383 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
384 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
385 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
386 /* PantherPoint is CPT compatible */
387 dev_priv
->pch_type
= PCH_CPT
;
388 DRM_DEBUG_KMS("Found PantherPoint PCH\n");
389 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
390 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
391 dev_priv
->pch_type
= PCH_LPT
;
392 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
393 WARN_ON(!IS_HASWELL(dev
));
394 WARN_ON(IS_ULT(dev
));
395 } else if (IS_BROADWELL(dev
)) {
396 dev_priv
->pch_type
= PCH_LPT
;
398 INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
;
399 DRM_DEBUG_KMS("This is Broadwell, assuming "
400 "LynxPoint LP PCH\n");
401 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
402 dev_priv
->pch_type
= PCH_LPT
;
403 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
404 WARN_ON(!IS_HASWELL(dev
));
405 WARN_ON(!IS_ULT(dev
));
413 DRM_DEBUG_KMS("No PCH found.\n");
418 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
420 if (INTEL_INFO(dev
)->gen
< 6)
423 if (i915
.semaphores
>= 0)
424 return i915
.semaphores
;
426 /* Until we get further testing... */
430 #ifdef CONFIG_INTEL_IOMMU
431 /* Enable semaphores on SNB when IO remapping is off */
432 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
439 static int i915_drm_freeze(struct drm_device
*dev
)
441 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
442 struct drm_crtc
*crtc
;
444 intel_runtime_pm_get(dev_priv
);
446 /* ignore lid events during suspend */
447 mutex_lock(&dev_priv
->modeset_restore_lock
);
448 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
449 mutex_unlock(&dev_priv
->modeset_restore_lock
);
451 /* We do a lot of poking in a lot of registers, make sure they work
453 intel_display_set_init_power(dev_priv
, true);
455 drm_kms_helper_poll_disable(dev
);
457 pci_save_state(dev
->pdev
);
459 /* If KMS is active, we do the leavevt stuff here */
460 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
463 error
= i915_gem_suspend(dev
);
465 dev_err(&dev
->pdev
->dev
,
466 "GEM idle failed, resume might fail\n");
470 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
472 drm_irq_uninstall(dev
);
473 dev_priv
->enable_hotplug_processing
= false;
475 * Disable CRTCs directly since we want to preserve sw state
478 mutex_lock(&dev
->mode_config
.mutex
);
479 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
480 dev_priv
->display
.crtc_disable(crtc
);
481 mutex_unlock(&dev
->mode_config
.mutex
);
483 intel_modeset_suspend_hw(dev
);
486 i915_gem_suspend_gtt_mappings(dev
);
488 i915_save_state(dev
);
490 intel_opregion_fini(dev
);
491 intel_uncore_fini(dev
);
494 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
);
497 dev_priv
->suspend_count
++;
502 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
506 if (!dev
|| !dev
->dev_private
) {
507 DRM_ERROR("dev: %p\n", dev
);
508 DRM_ERROR("DRM not initialized, aborting suspend.\n");
512 if (state
.event
== PM_EVENT_PRETHAW
)
516 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
519 error
= i915_drm_freeze(dev
);
523 if (state
.event
== PM_EVENT_SUSPEND
) {
524 /* Shut down the device */
525 pci_disable_device(dev
->pdev
);
526 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
532 void intel_console_resume(struct work_struct
*work
)
534 struct drm_i915_private
*dev_priv
=
535 container_of(work
, struct drm_i915_private
,
536 console_resume_work
);
537 struct drm_device
*dev
= dev_priv
->dev
;
540 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
544 static void intel_resume_hotplug(struct drm_device
*dev
)
546 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
547 struct intel_encoder
*encoder
;
549 mutex_lock(&mode_config
->mutex
);
550 DRM_DEBUG_KMS("running encoder hotplug functions\n");
552 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
553 if (encoder
->hot_plug
)
554 encoder
->hot_plug(encoder
);
556 mutex_unlock(&mode_config
->mutex
);
558 /* Just fire off a uevent and let userspace tell us what to do */
559 drm_helper_hpd_irq_event(dev
);
562 static int i915_drm_thaw_early(struct drm_device
*dev
)
564 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
566 intel_uncore_early_sanitize(dev
);
567 intel_uncore_sanitize(dev
);
568 intel_power_domains_init_hw(dev_priv
);
573 static int __i915_drm_thaw(struct drm_device
*dev
, bool restore_gtt_mappings
)
575 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
577 if (drm_core_check_feature(dev
, DRIVER_MODESET
) &&
578 restore_gtt_mappings
) {
579 mutex_lock(&dev
->struct_mutex
);
580 i915_gem_restore_gtt_mappings(dev
);
581 mutex_unlock(&dev
->struct_mutex
);
584 i915_restore_state(dev
);
585 intel_opregion_setup(dev
);
587 /* KMS EnterVT equivalent */
588 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
589 intel_init_pch_refclk(dev
);
590 drm_mode_config_reset(dev
);
592 mutex_lock(&dev
->struct_mutex
);
593 if (i915_gem_init_hw(dev
)) {
594 DRM_ERROR("failed to re-initialize GPU, declaring wedged!\n");
595 atomic_set_mask(I915_WEDGED
, &dev_priv
->gpu_error
.reset_counter
);
597 mutex_unlock(&dev
->struct_mutex
);
599 /* We need working interrupts for modeset enabling ... */
600 drm_irq_install(dev
, dev
->pdev
->irq
);
602 intel_modeset_init_hw(dev
);
604 drm_modeset_lock_all(dev
);
605 intel_modeset_setup_hw_state(dev
, true);
606 drm_modeset_unlock_all(dev
);
609 * ... but also need to make sure that hotplug processing
610 * doesn't cause havoc. Like in the driver load code we don't
611 * bother with the tiny race here where we might loose hotplug
615 dev_priv
->enable_hotplug_processing
= true;
616 /* Config may have changed between suspend and resume */
617 intel_resume_hotplug(dev
);
620 intel_opregion_init(dev
);
623 * The console lock can be pretty contented on resume due
624 * to all the printk activity. Try to keep it out of the hot
625 * path of resume if possible.
627 if (console_trylock()) {
628 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
631 schedule_work(&dev_priv
->console_resume_work
);
634 mutex_lock(&dev_priv
->modeset_restore_lock
);
635 dev_priv
->modeset_restore
= MODESET_DONE
;
636 mutex_unlock(&dev_priv
->modeset_restore_lock
);
638 intel_runtime_pm_put(dev_priv
);
642 static int i915_drm_thaw(struct drm_device
*dev
)
644 if (drm_core_check_feature(dev
, DRIVER_MODESET
))
645 i915_check_and_clear_faults(dev
);
647 return __i915_drm_thaw(dev
, true);
650 static int i915_resume_early(struct drm_device
*dev
)
652 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
656 * We have a resume ordering issue with the snd-hda driver also
657 * requiring our device to be power up. Due to the lack of a
658 * parent/child relationship we currently solve this with an early
661 * FIXME: This should be solved with a special hdmi sink device or
662 * similar so that power domains can be employed.
664 if (pci_enable_device(dev
->pdev
))
667 pci_set_master(dev
->pdev
);
669 return i915_drm_thaw_early(dev
);
672 int i915_resume(struct drm_device
*dev
)
674 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
678 * Platforms with opregion should have sane BIOS, older ones (gen3 and
679 * earlier) need to restore the GTT mappings since the BIOS might clear
680 * all our scratch PTEs.
682 ret
= __i915_drm_thaw(dev
, !dev_priv
->opregion
.header
);
686 drm_kms_helper_poll_enable(dev
);
690 static int i915_resume_legacy(struct drm_device
*dev
)
692 i915_resume_early(dev
);
699 * i915_reset - reset chip after a hang
700 * @dev: drm device to reset
702 * Reset the chip. Useful if a hang is detected. Returns zero on successful
703 * reset or otherwise an error code.
705 * Procedure is fairly simple:
706 * - reset the chip using the reset reg
707 * - re-init context state
708 * - re-init hardware status page
709 * - re-init ring buffer
710 * - re-init interrupt state
713 int i915_reset(struct drm_device
*dev
)
715 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
722 mutex_lock(&dev
->struct_mutex
);
726 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
728 ret
= intel_gpu_reset(dev
);
730 /* Also reset the gpu hangman. */
732 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
733 dev_priv
->gpu_error
.stop_rings
= 0;
734 if (ret
== -ENODEV
) {
735 DRM_INFO("Reset not implemented, but ignoring "
736 "error for simulated gpu hangs\n");
742 DRM_ERROR("Failed to reset chip: %i\n", ret
);
743 mutex_unlock(&dev
->struct_mutex
);
747 /* Ok, now get things going again... */
750 * Everything depends on having the GTT running, so we need to start
751 * there. Fortunately we don't need to do this unless we reset the
752 * chip at a PCI level.
754 * Next we need to restore the context, but we don't use those
757 * Ring buffer needs to be re-initialized in the KMS case, or if X
758 * was running at the time of the reset (i.e. we weren't VT
761 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
762 !dev_priv
->ums
.mm_suspended
) {
763 dev_priv
->ums
.mm_suspended
= 0;
765 ret
= i915_gem_init_hw(dev
);
766 mutex_unlock(&dev
->struct_mutex
);
768 DRM_ERROR("Failed hw init on reset %d\n", ret
);
773 * FIXME: This is horribly race against concurrent pageflip and
774 * vblank wait ioctls since they can observe dev->irqs_disabled
775 * being false when they shouldn't be able to.
777 drm_irq_uninstall(dev
);
778 drm_irq_install(dev
, dev
->pdev
->irq
);
780 /* rps/rc6 re-init is necessary to restore state lost after the
781 * reset and the re-install of drm irq. Skip for ironlake per
782 * previous concerns that it doesn't respond well to some forms
783 * of re-init after reset. */
784 if (INTEL_INFO(dev
)->gen
> 5)
785 intel_reset_gt_powersave(dev
);
789 mutex_unlock(&dev
->struct_mutex
);
795 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
797 struct intel_device_info
*intel_info
=
798 (struct intel_device_info
*) ent
->driver_data
;
800 if (IS_PRELIMINARY_HW(intel_info
) && !i915
.preliminary_hw_support
) {
801 DRM_INFO("This hardware requires preliminary hardware support.\n"
802 "See CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT, and/or modparam preliminary_hw_support\n");
806 /* Only bind to function 0 of the device. Early generations
807 * used function 1 as a placeholder for multi-head. This causes
808 * us confusion instead, especially on the systems where both
809 * functions have the same PCI-ID!
811 if (PCI_FUNC(pdev
->devfn
))
814 driver
.driver_features
&= ~(DRIVER_USE_AGP
);
816 return drm_get_pci_dev(pdev
, ent
, &driver
);
820 i915_pci_remove(struct pci_dev
*pdev
)
822 struct drm_device
*dev
= pci_get_drvdata(pdev
);
827 static int i915_pm_suspend(struct device
*dev
)
829 struct pci_dev
*pdev
= to_pci_dev(dev
);
830 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
832 if (!drm_dev
|| !drm_dev
->dev_private
) {
833 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
837 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
840 return i915_drm_freeze(drm_dev
);
843 static int i915_pm_suspend_late(struct device
*dev
)
845 struct pci_dev
*pdev
= to_pci_dev(dev
);
846 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
849 * We have a suspedn ordering issue with the snd-hda driver also
850 * requiring our device to be power up. Due to the lack of a
851 * parent/child relationship we currently solve this with an late
854 * FIXME: This should be solved with a special hdmi sink device or
855 * similar so that power domains can be employed.
857 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
860 pci_disable_device(pdev
);
861 pci_set_power_state(pdev
, PCI_D3hot
);
866 static int i915_pm_resume_early(struct device
*dev
)
868 struct pci_dev
*pdev
= to_pci_dev(dev
);
869 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
871 return i915_resume_early(drm_dev
);
874 static int i915_pm_resume(struct device
*dev
)
876 struct pci_dev
*pdev
= to_pci_dev(dev
);
877 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
879 return i915_resume(drm_dev
);
882 static int i915_pm_freeze(struct device
*dev
)
884 struct pci_dev
*pdev
= to_pci_dev(dev
);
885 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
887 if (!drm_dev
|| !drm_dev
->dev_private
) {
888 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
892 return i915_drm_freeze(drm_dev
);
895 static int i915_pm_thaw_early(struct device
*dev
)
897 struct pci_dev
*pdev
= to_pci_dev(dev
);
898 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
900 return i915_drm_thaw_early(drm_dev
);
903 static int i915_pm_thaw(struct device
*dev
)
905 struct pci_dev
*pdev
= to_pci_dev(dev
);
906 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
908 return i915_drm_thaw(drm_dev
);
911 static int i915_pm_poweroff(struct device
*dev
)
913 struct pci_dev
*pdev
= to_pci_dev(dev
);
914 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
916 return i915_drm_freeze(drm_dev
);
919 static int hsw_runtime_suspend(struct drm_i915_private
*dev_priv
)
921 hsw_enable_pc8(dev_priv
);
926 static int snb_runtime_resume(struct drm_i915_private
*dev_priv
)
928 struct drm_device
*dev
= dev_priv
->dev
;
930 intel_init_pch_refclk(dev
);
935 static int hsw_runtime_resume(struct drm_i915_private
*dev_priv
)
937 hsw_disable_pc8(dev_priv
);
943 * Save all Gunit registers that may be lost after a D3 and a subsequent
944 * S0i[R123] transition. The list of registers needing a save/restore is
945 * defined in the VLV2_S0IXRegs document. This documents marks all Gunit
946 * registers in the following way:
947 * - Driver: saved/restored by the driver
948 * - Punit : saved/restored by the Punit firmware
949 * - No, w/o marking: no need to save/restore, since the register is R/O or
950 * used internally by the HW in a way that doesn't depend
951 * keeping the content across a suspend/resume.
952 * - Debug : used for debugging
954 * We save/restore all registers marked with 'Driver', with the following
956 * - Registers out of use, including also registers marked with 'Debug'.
957 * These have no effect on the driver's operation, so we don't save/restore
958 * them to reduce the overhead.
959 * - Registers that are fully setup by an initialization function called from
960 * the resume path. For example many clock gating and RPS/RC6 registers.
961 * - Registers that provide the right functionality with their reset defaults.
963 * TODO: Except for registers that based on the above 3 criteria can be safely
964 * ignored, we save/restore all others, practically treating the HW context as
965 * a black-box for the driver. Further investigation is needed to reduce the
966 * saved/restored registers even further, by following the same 3 criteria.
968 static void vlv_save_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
970 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
973 /* GAM 0x4000-0x4770 */
974 s
->wr_watermark
= I915_READ(GEN7_WR_WATERMARK
);
975 s
->gfx_prio_ctrl
= I915_READ(GEN7_GFX_PRIO_CTRL
);
976 s
->arb_mode
= I915_READ(ARB_MODE
);
977 s
->gfx_pend_tlb0
= I915_READ(GEN7_GFX_PEND_TLB0
);
978 s
->gfx_pend_tlb1
= I915_READ(GEN7_GFX_PEND_TLB1
);
980 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
981 s
->lra_limits
[i
] = I915_READ(GEN7_LRA_LIMITS_BASE
+ i
* 4);
983 s
->media_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
984 s
->gfx_max_req_count
= I915_READ(GEN7_MEDIA_MAX_REQ_COUNT
);
986 s
->render_hwsp
= I915_READ(RENDER_HWS_PGA_GEN7
);
987 s
->ecochk
= I915_READ(GAM_ECOCHK
);
988 s
->bsd_hwsp
= I915_READ(BSD_HWS_PGA_GEN7
);
989 s
->blt_hwsp
= I915_READ(BLT_HWS_PGA_GEN7
);
991 s
->tlb_rd_addr
= I915_READ(GEN7_TLB_RD_ADDR
);
993 /* MBC 0x9024-0x91D0, 0x8500 */
994 s
->g3dctl
= I915_READ(VLV_G3DCTL
);
995 s
->gsckgctl
= I915_READ(VLV_GSCKGCTL
);
996 s
->mbctl
= I915_READ(GEN6_MBCTL
);
998 /* GCP 0x9400-0x9424, 0x8100-0x810C */
999 s
->ucgctl1
= I915_READ(GEN6_UCGCTL1
);
1000 s
->ucgctl3
= I915_READ(GEN6_UCGCTL3
);
1001 s
->rcgctl1
= I915_READ(GEN6_RCGCTL1
);
1002 s
->rcgctl2
= I915_READ(GEN6_RCGCTL2
);
1003 s
->rstctl
= I915_READ(GEN6_RSTCTL
);
1004 s
->misccpctl
= I915_READ(GEN7_MISCCPCTL
);
1006 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1007 s
->gfxpause
= I915_READ(GEN6_GFXPAUSE
);
1008 s
->rpdeuhwtc
= I915_READ(GEN6_RPDEUHWTC
);
1009 s
->rpdeuc
= I915_READ(GEN6_RPDEUC
);
1010 s
->ecobus
= I915_READ(ECOBUS
);
1011 s
->pwrdwnupctl
= I915_READ(VLV_PWRDWNUPCTL
);
1012 s
->rp_down_timeout
= I915_READ(GEN6_RP_DOWN_TIMEOUT
);
1013 s
->rp_deucsw
= I915_READ(GEN6_RPDEUCSW
);
1014 s
->rcubmabdtmr
= I915_READ(GEN6_RCUBMABDTMR
);
1015 s
->rcedata
= I915_READ(VLV_RCEDATA
);
1016 s
->spare2gh
= I915_READ(VLV_SPAREG2H
);
1018 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1019 s
->gt_imr
= I915_READ(GTIMR
);
1020 s
->gt_ier
= I915_READ(GTIER
);
1021 s
->pm_imr
= I915_READ(GEN6_PMIMR
);
1022 s
->pm_ier
= I915_READ(GEN6_PMIER
);
1024 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1025 s
->gt_scratch
[i
] = I915_READ(GEN7_GT_SCRATCH_BASE
+ i
* 4);
1027 /* GT SA CZ domain, 0x100000-0x138124 */
1028 s
->tilectl
= I915_READ(TILECTL
);
1029 s
->gt_fifoctl
= I915_READ(GTFIFOCTL
);
1030 s
->gtlc_wake_ctrl
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1031 s
->gtlc_survive
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1032 s
->pmwgicz
= I915_READ(VLV_PMWGICZ
);
1034 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1035 s
->gu_ctl0
= I915_READ(VLV_GU_CTL0
);
1036 s
->gu_ctl1
= I915_READ(VLV_GU_CTL1
);
1037 s
->clock_gate_dis2
= I915_READ(VLV_GUNIT_CLOCK_GATE2
);
1040 * Not saving any of:
1041 * DFT, 0x9800-0x9EC0
1042 * SARB, 0xB000-0xB1FC
1043 * GAC, 0x5208-0x524C, 0x14000-0x14C000
1048 static void vlv_restore_gunit_s0ix_state(struct drm_i915_private
*dev_priv
)
1050 struct vlv_s0ix_state
*s
= &dev_priv
->vlv_s0ix_state
;
1054 /* GAM 0x4000-0x4770 */
1055 I915_WRITE(GEN7_WR_WATERMARK
, s
->wr_watermark
);
1056 I915_WRITE(GEN7_GFX_PRIO_CTRL
, s
->gfx_prio_ctrl
);
1057 I915_WRITE(ARB_MODE
, s
->arb_mode
| (0xffff << 16));
1058 I915_WRITE(GEN7_GFX_PEND_TLB0
, s
->gfx_pend_tlb0
);
1059 I915_WRITE(GEN7_GFX_PEND_TLB1
, s
->gfx_pend_tlb1
);
1061 for (i
= 0; i
< ARRAY_SIZE(s
->lra_limits
); i
++)
1062 I915_WRITE(GEN7_LRA_LIMITS_BASE
+ i
* 4, s
->lra_limits
[i
]);
1064 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->media_max_req_count
);
1065 I915_WRITE(GEN7_MEDIA_MAX_REQ_COUNT
, s
->gfx_max_req_count
);
1067 I915_WRITE(RENDER_HWS_PGA_GEN7
, s
->render_hwsp
);
1068 I915_WRITE(GAM_ECOCHK
, s
->ecochk
);
1069 I915_WRITE(BSD_HWS_PGA_GEN7
, s
->bsd_hwsp
);
1070 I915_WRITE(BLT_HWS_PGA_GEN7
, s
->blt_hwsp
);
1072 I915_WRITE(GEN7_TLB_RD_ADDR
, s
->tlb_rd_addr
);
1074 /* MBC 0x9024-0x91D0, 0x8500 */
1075 I915_WRITE(VLV_G3DCTL
, s
->g3dctl
);
1076 I915_WRITE(VLV_GSCKGCTL
, s
->gsckgctl
);
1077 I915_WRITE(GEN6_MBCTL
, s
->mbctl
);
1079 /* GCP 0x9400-0x9424, 0x8100-0x810C */
1080 I915_WRITE(GEN6_UCGCTL1
, s
->ucgctl1
);
1081 I915_WRITE(GEN6_UCGCTL3
, s
->ucgctl3
);
1082 I915_WRITE(GEN6_RCGCTL1
, s
->rcgctl1
);
1083 I915_WRITE(GEN6_RCGCTL2
, s
->rcgctl2
);
1084 I915_WRITE(GEN6_RSTCTL
, s
->rstctl
);
1085 I915_WRITE(GEN7_MISCCPCTL
, s
->misccpctl
);
1087 /* GPM 0xA000-0xAA84, 0x8000-0x80FC */
1088 I915_WRITE(GEN6_GFXPAUSE
, s
->gfxpause
);
1089 I915_WRITE(GEN6_RPDEUHWTC
, s
->rpdeuhwtc
);
1090 I915_WRITE(GEN6_RPDEUC
, s
->rpdeuc
);
1091 I915_WRITE(ECOBUS
, s
->ecobus
);
1092 I915_WRITE(VLV_PWRDWNUPCTL
, s
->pwrdwnupctl
);
1093 I915_WRITE(GEN6_RP_DOWN_TIMEOUT
,s
->rp_down_timeout
);
1094 I915_WRITE(GEN6_RPDEUCSW
, s
->rp_deucsw
);
1095 I915_WRITE(GEN6_RCUBMABDTMR
, s
->rcubmabdtmr
);
1096 I915_WRITE(VLV_RCEDATA
, s
->rcedata
);
1097 I915_WRITE(VLV_SPAREG2H
, s
->spare2gh
);
1099 /* Display CZ domain, 0x4400C-0x4402C, 0x4F000-0x4F11F */
1100 I915_WRITE(GTIMR
, s
->gt_imr
);
1101 I915_WRITE(GTIER
, s
->gt_ier
);
1102 I915_WRITE(GEN6_PMIMR
, s
->pm_imr
);
1103 I915_WRITE(GEN6_PMIER
, s
->pm_ier
);
1105 for (i
= 0; i
< ARRAY_SIZE(s
->gt_scratch
); i
++)
1106 I915_WRITE(GEN7_GT_SCRATCH_BASE
+ i
* 4, s
->gt_scratch
[i
]);
1108 /* GT SA CZ domain, 0x100000-0x138124 */
1109 I915_WRITE(TILECTL
, s
->tilectl
);
1110 I915_WRITE(GTFIFOCTL
, s
->gt_fifoctl
);
1112 * Preserve the GT allow wake and GFX force clock bit, they are not
1113 * be restored, as they are used to control the s0ix suspend/resume
1114 * sequence by the caller.
1116 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1117 val
&= VLV_GTLC_ALLOWWAKEREQ
;
1118 val
|= s
->gtlc_wake_ctrl
& ~VLV_GTLC_ALLOWWAKEREQ
;
1119 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1121 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1122 val
&= VLV_GFX_CLK_FORCE_ON_BIT
;
1123 val
|= s
->gtlc_survive
& ~VLV_GFX_CLK_FORCE_ON_BIT
;
1124 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1126 I915_WRITE(VLV_PMWGICZ
, s
->pmwgicz
);
1128 /* Gunit-Display CZ domain, 0x182028-0x1821CF */
1129 I915_WRITE(VLV_GU_CTL0
, s
->gu_ctl0
);
1130 I915_WRITE(VLV_GU_CTL1
, s
->gu_ctl1
);
1131 I915_WRITE(VLV_GUNIT_CLOCK_GATE2
, s
->clock_gate_dis2
);
1134 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool force_on
)
1139 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1140 WARN_ON(!!(val
& VLV_GFX_CLK_FORCE_ON_BIT
) == force_on
);
1142 #define COND (I915_READ(VLV_GTLC_SURVIVABILITY_REG) & VLV_GFX_CLK_STATUS_BIT)
1143 /* Wait for a previous force-off to settle */
1145 err
= wait_for(!COND
, 20);
1147 DRM_ERROR("timeout waiting for GFX clock force-off (%08x)\n",
1148 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1153 val
= I915_READ(VLV_GTLC_SURVIVABILITY_REG
);
1154 val
&= ~VLV_GFX_CLK_FORCE_ON_BIT
;
1156 val
|= VLV_GFX_CLK_FORCE_ON_BIT
;
1157 I915_WRITE(VLV_GTLC_SURVIVABILITY_REG
, val
);
1162 err
= wait_for(COND
, 20);
1164 DRM_ERROR("timeout waiting for GFX clock force-on (%08x)\n",
1165 I915_READ(VLV_GTLC_SURVIVABILITY_REG
));
1171 static int vlv_allow_gt_wake(struct drm_i915_private
*dev_priv
, bool allow
)
1176 val
= I915_READ(VLV_GTLC_WAKE_CTRL
);
1177 val
&= ~VLV_GTLC_ALLOWWAKEREQ
;
1179 val
|= VLV_GTLC_ALLOWWAKEREQ
;
1180 I915_WRITE(VLV_GTLC_WAKE_CTRL
, val
);
1181 POSTING_READ(VLV_GTLC_WAKE_CTRL
);
1183 #define COND (!!(I915_READ(VLV_GTLC_PW_STATUS) & VLV_GTLC_ALLOWWAKEACK) == \
1185 err
= wait_for(COND
, 1);
1187 DRM_ERROR("timeout disabling GT waking\n");
1192 static int vlv_wait_for_gt_wells(struct drm_i915_private
*dev_priv
,
1199 mask
= VLV_GTLC_PW_MEDIA_STATUS_MASK
| VLV_GTLC_PW_RENDER_STATUS_MASK
;
1200 val
= wait_for_on
? mask
: 0;
1201 #define COND ((I915_READ(VLV_GTLC_PW_STATUS) & mask) == val)
1205 DRM_DEBUG_KMS("waiting for GT wells to go %s (%08x)\n",
1206 wait_for_on
? "on" : "off",
1207 I915_READ(VLV_GTLC_PW_STATUS
));
1210 * RC6 transitioning can be delayed up to 2 msec (see
1211 * valleyview_enable_rps), use 3 msec for safety.
1213 err
= wait_for(COND
, 3);
1215 DRM_ERROR("timeout waiting for GT wells to go %s\n",
1216 wait_for_on
? "on" : "off");
1222 static void vlv_check_no_gt_access(struct drm_i915_private
*dev_priv
)
1224 if (!(I915_READ(VLV_GTLC_PW_STATUS
) & VLV_GTLC_ALLOWWAKEERR
))
1227 DRM_ERROR("GT register access while GT waking disabled\n");
1228 I915_WRITE(VLV_GTLC_PW_STATUS
, VLV_GTLC_ALLOWWAKEERR
);
1231 static int vlv_runtime_suspend(struct drm_i915_private
*dev_priv
)
1237 * Bspec defines the following GT well on flags as debug only, so
1238 * don't treat them as hard failures.
1240 (void)vlv_wait_for_gt_wells(dev_priv
, false);
1242 mask
= VLV_GTLC_RENDER_CTX_EXISTS
| VLV_GTLC_MEDIA_CTX_EXISTS
;
1243 WARN_ON((I915_READ(VLV_GTLC_WAKE_CTRL
) & mask
) != mask
);
1245 vlv_check_no_gt_access(dev_priv
);
1247 err
= vlv_force_gfx_clock(dev_priv
, true);
1251 err
= vlv_allow_gt_wake(dev_priv
, false);
1254 vlv_save_gunit_s0ix_state(dev_priv
);
1256 err
= vlv_force_gfx_clock(dev_priv
, false);
1263 /* For safety always re-enable waking and disable gfx clock forcing */
1264 vlv_allow_gt_wake(dev_priv
, true);
1266 vlv_force_gfx_clock(dev_priv
, false);
1271 static int vlv_runtime_resume(struct drm_i915_private
*dev_priv
)
1273 struct drm_device
*dev
= dev_priv
->dev
;
1278 * If any of the steps fail just try to continue, that's the best we
1279 * can do at this point. Return the first error code (which will also
1280 * leave RPM permanently disabled).
1282 ret
= vlv_force_gfx_clock(dev_priv
, true);
1284 vlv_restore_gunit_s0ix_state(dev_priv
);
1286 err
= vlv_allow_gt_wake(dev_priv
, true);
1290 err
= vlv_force_gfx_clock(dev_priv
, false);
1294 vlv_check_no_gt_access(dev_priv
);
1296 intel_init_clock_gating(dev
);
1297 i915_gem_restore_fences(dev
);
1302 static int intel_runtime_suspend(struct device
*device
)
1304 struct pci_dev
*pdev
= to_pci_dev(device
);
1305 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1306 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1309 if (WARN_ON_ONCE(!(dev_priv
->rps
.enabled
&& intel_enable_rc6(dev
))))
1312 WARN_ON(!HAS_RUNTIME_PM(dev
));
1313 assert_force_wake_inactive(dev_priv
);
1315 DRM_DEBUG_KMS("Suspending device\n");
1318 * rps.work can't be rearmed here, since we get here only after making
1319 * sure the GPU is idle and the RPS freq is set to the minimum. See
1320 * intel_mark_idle().
1322 cancel_work_sync(&dev_priv
->rps
.work
);
1323 intel_runtime_pm_disable_interrupts(dev
);
1327 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1328 ret
= hsw_runtime_suspend(dev_priv
);
1329 } else if (IS_VALLEYVIEW(dev
)) {
1330 ret
= vlv_runtime_suspend(dev_priv
);
1337 DRM_ERROR("Runtime suspend failed, disabling it (%d)\n", ret
);
1338 intel_runtime_pm_restore_interrupts(dev
);
1343 i915_gem_release_all_mmaps(dev_priv
);
1345 del_timer_sync(&dev_priv
->gpu_error
.hangcheck_timer
);
1346 dev_priv
->pm
.suspended
= true;
1349 * current versions of firmware which depend on this opregion
1350 * notification have repurposed the D1 definition to mean
1351 * "runtime suspended" vs. what you would normally expect (D3)
1352 * to distinguish it from notifications that might be sent
1353 * via the suspend path.
1355 intel_opregion_notify_adapter(dev
, PCI_D1
);
1357 DRM_DEBUG_KMS("Device suspended\n");
1361 static int intel_runtime_resume(struct device
*device
)
1363 struct pci_dev
*pdev
= to_pci_dev(device
);
1364 struct drm_device
*dev
= pci_get_drvdata(pdev
);
1365 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
1368 WARN_ON(!HAS_RUNTIME_PM(dev
));
1370 DRM_DEBUG_KMS("Resuming device\n");
1372 intel_opregion_notify_adapter(dev
, PCI_D0
);
1373 dev_priv
->pm
.suspended
= false;
1376 ret
= snb_runtime_resume(dev_priv
);
1377 } else if (IS_HASWELL(dev
) || IS_BROADWELL(dev
)) {
1378 ret
= hsw_runtime_resume(dev_priv
);
1379 } else if (IS_VALLEYVIEW(dev
)) {
1380 ret
= vlv_runtime_resume(dev_priv
);
1387 * No point of rolling back things in case of an error, as the best
1388 * we can do is to hope that things will still work (and disable RPM).
1390 i915_gem_init_swizzling(dev
);
1391 gen6_update_ring_freq(dev
);
1393 intel_runtime_pm_restore_interrupts(dev
);
1394 intel_reset_gt_powersave(dev
);
1397 DRM_ERROR("Runtime resume failed, disabling it (%d)\n", ret
);
1399 DRM_DEBUG_KMS("Device resumed\n");
1404 static const struct dev_pm_ops i915_pm_ops
= {
1405 .suspend
= i915_pm_suspend
,
1406 .suspend_late
= i915_pm_suspend_late
,
1407 .resume_early
= i915_pm_resume_early
,
1408 .resume
= i915_pm_resume
,
1409 .freeze
= i915_pm_freeze
,
1410 .thaw_early
= i915_pm_thaw_early
,
1411 .thaw
= i915_pm_thaw
,
1412 .poweroff
= i915_pm_poweroff
,
1413 .restore_early
= i915_pm_resume_early
,
1414 .restore
= i915_pm_resume
,
1415 .runtime_suspend
= intel_runtime_suspend
,
1416 .runtime_resume
= intel_runtime_resume
,
1419 static const struct vm_operations_struct i915_gem_vm_ops
= {
1420 .fault
= i915_gem_fault
,
1421 .open
= drm_gem_vm_open
,
1422 .close
= drm_gem_vm_close
,
1425 static const struct file_operations i915_driver_fops
= {
1426 .owner
= THIS_MODULE
,
1428 .release
= drm_release
,
1429 .unlocked_ioctl
= drm_ioctl
,
1430 .mmap
= drm_gem_mmap
,
1433 #ifdef CONFIG_COMPAT
1434 .compat_ioctl
= i915_compat_ioctl
,
1436 .llseek
= noop_llseek
,
1439 static struct drm_driver driver
= {
1440 /* Don't use MTRRs here; the Xserver or userspace app should
1441 * deal with them for Intel hardware.
1445 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
1447 .load
= i915_driver_load
,
1448 .unload
= i915_driver_unload
,
1449 .open
= i915_driver_open
,
1450 .lastclose
= i915_driver_lastclose
,
1451 .preclose
= i915_driver_preclose
,
1452 .postclose
= i915_driver_postclose
,
1454 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
1455 .suspend
= i915_suspend
,
1456 .resume
= i915_resume_legacy
,
1458 .device_is_agp
= i915_driver_device_is_agp
,
1459 .master_create
= i915_master_create
,
1460 .master_destroy
= i915_master_destroy
,
1461 #if defined(CONFIG_DEBUG_FS)
1462 .debugfs_init
= i915_debugfs_init
,
1463 .debugfs_cleanup
= i915_debugfs_cleanup
,
1465 .gem_free_object
= i915_gem_free_object
,
1466 .gem_vm_ops
= &i915_gem_vm_ops
,
1468 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
1469 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
1470 .gem_prime_export
= i915_gem_prime_export
,
1471 .gem_prime_import
= i915_gem_prime_import
,
1473 .dumb_create
= i915_gem_dumb_create
,
1474 .dumb_map_offset
= i915_gem_mmap_gtt
,
1475 .dumb_destroy
= drm_gem_dumb_destroy
,
1476 .ioctls
= i915_ioctls
,
1477 .fops
= &i915_driver_fops
,
1478 .name
= DRIVER_NAME
,
1479 .desc
= DRIVER_DESC
,
1480 .date
= DRIVER_DATE
,
1481 .major
= DRIVER_MAJOR
,
1482 .minor
= DRIVER_MINOR
,
1483 .patchlevel
= DRIVER_PATCHLEVEL
,
1486 static struct pci_driver i915_pci_driver
= {
1487 .name
= DRIVER_NAME
,
1488 .id_table
= pciidlist
,
1489 .probe
= i915_pci_probe
,
1490 .remove
= i915_pci_remove
,
1491 .driver
.pm
= &i915_pm_ops
,
1494 static int __init
i915_init(void)
1496 driver
.num_ioctls
= i915_max_ioctl
;
1499 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
1500 * explicitly disabled with the module pararmeter.
1502 * Otherwise, just follow the parameter (defaulting to off).
1504 * Allow optional vga_text_mode_force boot option to override
1505 * the default behavior.
1507 #if defined(CONFIG_DRM_I915_KMS)
1508 if (i915
.modeset
!= 0)
1509 driver
.driver_features
|= DRIVER_MODESET
;
1511 if (i915
.modeset
== 1)
1512 driver
.driver_features
|= DRIVER_MODESET
;
1514 #ifdef CONFIG_VGA_CONSOLE
1515 if (vgacon_text_force() && i915
.modeset
== -1)
1516 driver
.driver_features
&= ~DRIVER_MODESET
;
1519 if (!(driver
.driver_features
& DRIVER_MODESET
)) {
1520 driver
.get_vblank_timestamp
= NULL
;
1521 #ifndef CONFIG_DRM_I915_UMS
1522 /* Silently fail loading to not upset userspace. */
1527 return drm_pci_init(&driver
, &i915_pci_driver
);
1530 static void __exit
i915_exit(void)
1532 #ifndef CONFIG_DRM_I915_UMS
1533 if (!(driver
.driver_features
& DRIVER_MODESET
))
1534 return; /* Never loaded a driver. */
1537 drm_pci_exit(&driver
, &i915_pci_driver
);
1540 module_init(i915_init
);
1541 module_exit(i915_exit
);
1543 MODULE_AUTHOR(DRIVER_AUTHOR
);
1544 MODULE_DESCRIPTION(DRIVER_DESC
);
1545 MODULE_LICENSE("GPL and additional rights");