1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
35 #include "drm_pciids.h"
37 static struct pci_device_id pciidlist
[] = {
46 static bool i915_pipe_enabled(struct drm_device
*dev
, enum pipe pipe
)
48 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
51 return (I915_READ(DPLL_A
) & DPLL_VCO_ENABLE
);
53 return (I915_READ(DPLL_B
) & DPLL_VCO_ENABLE
);
56 static void i915_save_palette(struct drm_device
*dev
, enum pipe pipe
)
58 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
59 unsigned long reg
= (pipe
== PIPE_A
? PALETTE_A
: PALETTE_B
);
63 if (!i915_pipe_enabled(dev
, pipe
))
67 array
= dev_priv
->save_palette_a
;
69 array
= dev_priv
->save_palette_b
;
71 for(i
= 0; i
< 256; i
++)
72 array
[i
] = I915_READ(reg
+ (i
<< 2));
75 static void i915_restore_palette(struct drm_device
*dev
, enum pipe pipe
)
77 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
78 unsigned long reg
= (pipe
== PIPE_A
? PALETTE_A
: PALETTE_B
);
82 if (!i915_pipe_enabled(dev
, pipe
))
86 array
= dev_priv
->save_palette_a
;
88 array
= dev_priv
->save_palette_b
;
90 for(i
= 0; i
< 256; i
++)
91 I915_WRITE(reg
+ (i
<< 2), array
[i
]);
94 static u8
i915_read_indexed(u16 index_port
, u16 data_port
, u8 reg
)
96 outb(reg
, index_port
);
97 return inb(data_port
);
100 static u8
i915_read_ar(u16 st01
, u8 reg
, u16 palette_enable
)
103 outb(palette_enable
| reg
, VGA_AR_INDEX
);
104 return inb(VGA_AR_DATA_READ
);
107 static void i915_write_ar(u8 st01
, u8 reg
, u8 val
, u16 palette_enable
)
110 outb(palette_enable
| reg
, VGA_AR_INDEX
);
111 outb(val
, VGA_AR_DATA_WRITE
);
114 static void i915_write_indexed(u16 index_port
, u16 data_port
, u8 reg
, u8 val
)
116 outb(reg
, index_port
);
117 outb(val
, data_port
);
120 static void i915_save_vga(struct drm_device
*dev
)
122 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
124 u16 cr_index
, cr_data
, st01
;
126 /* VGA color palette registers */
127 dev_priv
->saveDACMASK
= inb(VGA_DACMASK
);
128 /* DACCRX automatically increments during read */
130 /* Read 3 bytes of color data from each index */
131 for (i
= 0; i
< 256 * 3; i
++)
132 dev_priv
->saveDACDATA
[i
] = inb(VGA_DACDATA
);
135 dev_priv
->saveMSR
= inb(VGA_MSR_READ
);
136 if (dev_priv
->saveMSR
& VGA_MSR_CGA_MODE
) {
137 cr_index
= VGA_CR_INDEX_CGA
;
138 cr_data
= VGA_CR_DATA_CGA
;
141 cr_index
= VGA_CR_INDEX_MDA
;
142 cr_data
= VGA_CR_DATA_MDA
;
146 /* CRT controller regs */
147 i915_write_indexed(cr_index
, cr_data
, 0x11,
148 i915_read_indexed(cr_index
, cr_data
, 0x11) &
150 for (i
= 0; i
<= 0x24; i
++)
151 dev_priv
->saveCR
[i
] =
152 i915_read_indexed(cr_index
, cr_data
, i
);
153 /* Make sure we don't turn off CR group 0 writes */
154 dev_priv
->saveCR
[0x11] &= ~0x80;
156 /* Attribute controller registers */
158 dev_priv
->saveAR_INDEX
= inb(VGA_AR_INDEX
);
159 for (i
= 0; i
<= 0x14; i
++)
160 dev_priv
->saveAR
[i
] = i915_read_ar(st01
, i
, 0);
162 outb(dev_priv
->saveAR_INDEX
, VGA_AR_INDEX
);
165 /* Graphics controller registers */
166 for (i
= 0; i
< 9; i
++)
167 dev_priv
->saveGR
[i
] =
168 i915_read_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, i
);
170 dev_priv
->saveGR
[0x10] =
171 i915_read_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, 0x10);
172 dev_priv
->saveGR
[0x11] =
173 i915_read_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, 0x11);
174 dev_priv
->saveGR
[0x18] =
175 i915_read_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, 0x18);
177 /* Sequencer registers */
178 for (i
= 0; i
< 8; i
++)
179 dev_priv
->saveSR
[i
] =
180 i915_read_indexed(VGA_SR_INDEX
, VGA_SR_DATA
, i
);
183 static void i915_restore_vga(struct drm_device
*dev
)
185 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
187 u16 cr_index
, cr_data
, st01
;
190 outb(dev_priv
->saveMSR
, VGA_MSR_WRITE
);
191 if (dev_priv
->saveMSR
& VGA_MSR_CGA_MODE
) {
192 cr_index
= VGA_CR_INDEX_CGA
;
193 cr_data
= VGA_CR_DATA_CGA
;
196 cr_index
= VGA_CR_INDEX_MDA
;
197 cr_data
= VGA_CR_DATA_MDA
;
201 /* Sequencer registers, don't write SR07 */
202 for (i
= 0; i
< 7; i
++)
203 i915_write_indexed(VGA_SR_INDEX
, VGA_SR_DATA
, i
,
204 dev_priv
->saveSR
[i
]);
206 /* CRT controller regs */
207 /* Enable CR group 0 writes */
208 i915_write_indexed(cr_index
, cr_data
, 0x11, dev_priv
->saveCR
[0x11]);
209 for (i
= 0; i
<= 0x24; i
++)
210 i915_write_indexed(cr_index
, cr_data
, i
, dev_priv
->saveCR
[i
]);
212 /* Graphics controller regs */
213 for (i
= 0; i
< 9; i
++)
214 i915_write_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, i
,
215 dev_priv
->saveGR
[i
]);
217 i915_write_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, 0x10,
218 dev_priv
->saveGR
[0x10]);
219 i915_write_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, 0x11,
220 dev_priv
->saveGR
[0x11]);
221 i915_write_indexed(VGA_GR_INDEX
, VGA_GR_DATA
, 0x18,
222 dev_priv
->saveGR
[0x18]);
224 /* Attribute controller registers */
226 for (i
= 0; i
<= 0x14; i
++)
227 i915_write_ar(st01
, i
, dev_priv
->saveAR
[i
], 0);
228 inb(st01
); /* switch back to index mode */
229 outb(dev_priv
->saveAR_INDEX
| 0x20, VGA_AR_INDEX
);
232 /* VGA color palette registers */
233 outb(dev_priv
->saveDACMASK
, VGA_DACMASK
);
234 /* DACCRX automatically increments during read */
236 /* Read 3 bytes of color data from each index */
237 for (i
= 0; i
< 256 * 3; i
++)
238 outb(dev_priv
->saveDACDATA
[i
], VGA_DACDATA
);
242 static int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
244 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
247 if (!dev
|| !dev_priv
) {
248 printk(KERN_ERR
"dev: %p, dev_priv: %p\n", dev
, dev_priv
);
249 printk(KERN_ERR
"DRM not initialized, aborting suspend.\n");
253 if (state
.event
== PM_EVENT_PRETHAW
)
256 pci_save_state(dev
->pdev
);
257 pci_read_config_byte(dev
->pdev
, LBB
, &dev_priv
->saveLBB
);
259 /* Display arbitration control */
260 dev_priv
->saveDSPARB
= I915_READ(DSPARB
);
262 /* Pipe & plane A info */
263 dev_priv
->savePIPEACONF
= I915_READ(PIPEACONF
);
264 dev_priv
->savePIPEASRC
= I915_READ(PIPEASRC
);
265 dev_priv
->saveFPA0
= I915_READ(FPA0
);
266 dev_priv
->saveFPA1
= I915_READ(FPA1
);
267 dev_priv
->saveDPLL_A
= I915_READ(DPLL_A
);
269 dev_priv
->saveDPLL_A_MD
= I915_READ(DPLL_A_MD
);
270 dev_priv
->saveHTOTAL_A
= I915_READ(HTOTAL_A
);
271 dev_priv
->saveHBLANK_A
= I915_READ(HBLANK_A
);
272 dev_priv
->saveHSYNC_A
= I915_READ(HSYNC_A
);
273 dev_priv
->saveVTOTAL_A
= I915_READ(VTOTAL_A
);
274 dev_priv
->saveVBLANK_A
= I915_READ(VBLANK_A
);
275 dev_priv
->saveVSYNC_A
= I915_READ(VSYNC_A
);
276 dev_priv
->saveBCLRPAT_A
= I915_READ(BCLRPAT_A
);
278 dev_priv
->saveDSPACNTR
= I915_READ(DSPACNTR
);
279 dev_priv
->saveDSPASTRIDE
= I915_READ(DSPASTRIDE
);
280 dev_priv
->saveDSPASIZE
= I915_READ(DSPASIZE
);
281 dev_priv
->saveDSPAPOS
= I915_READ(DSPAPOS
);
282 dev_priv
->saveDSPABASE
= I915_READ(DSPABASE
);
284 dev_priv
->saveDSPASURF
= I915_READ(DSPASURF
);
285 dev_priv
->saveDSPATILEOFF
= I915_READ(DSPATILEOFF
);
287 i915_save_palette(dev
, PIPE_A
);
288 dev_priv
->savePIPEASTAT
= I915_READ(I915REG_PIPEASTAT
);
290 /* Pipe & plane B info */
291 dev_priv
->savePIPEBCONF
= I915_READ(PIPEBCONF
);
292 dev_priv
->savePIPEBSRC
= I915_READ(PIPEBSRC
);
293 dev_priv
->saveFPB0
= I915_READ(FPB0
);
294 dev_priv
->saveFPB1
= I915_READ(FPB1
);
295 dev_priv
->saveDPLL_B
= I915_READ(DPLL_B
);
297 dev_priv
->saveDPLL_B_MD
= I915_READ(DPLL_B_MD
);
298 dev_priv
->saveHTOTAL_B
= I915_READ(HTOTAL_B
);
299 dev_priv
->saveHBLANK_B
= I915_READ(HBLANK_B
);
300 dev_priv
->saveHSYNC_B
= I915_READ(HSYNC_B
);
301 dev_priv
->saveVTOTAL_B
= I915_READ(VTOTAL_B
);
302 dev_priv
->saveVBLANK_B
= I915_READ(VBLANK_B
);
303 dev_priv
->saveVSYNC_B
= I915_READ(VSYNC_B
);
304 dev_priv
->saveBCLRPAT_A
= I915_READ(BCLRPAT_A
);
306 dev_priv
->saveDSPBCNTR
= I915_READ(DSPBCNTR
);
307 dev_priv
->saveDSPBSTRIDE
= I915_READ(DSPBSTRIDE
);
308 dev_priv
->saveDSPBSIZE
= I915_READ(DSPBSIZE
);
309 dev_priv
->saveDSPBPOS
= I915_READ(DSPBPOS
);
310 dev_priv
->saveDSPBBASE
= I915_READ(DSPBBASE
);
311 if (IS_I965GM(dev
) || IS_IGD_GM(dev
)) {
312 dev_priv
->saveDSPBSURF
= I915_READ(DSPBSURF
);
313 dev_priv
->saveDSPBTILEOFF
= I915_READ(DSPBTILEOFF
);
315 i915_save_palette(dev
, PIPE_B
);
316 dev_priv
->savePIPEBSTAT
= I915_READ(I915REG_PIPEBSTAT
);
319 dev_priv
->saveADPA
= I915_READ(ADPA
);
322 dev_priv
->savePP_CONTROL
= I915_READ(PP_CONTROL
);
323 dev_priv
->savePFIT_PGM_RATIOS
= I915_READ(PFIT_PGM_RATIOS
);
324 dev_priv
->saveBLC_PWM_CTL
= I915_READ(BLC_PWM_CTL
);
326 dev_priv
->saveBLC_PWM_CTL2
= I915_READ(BLC_PWM_CTL2
);
327 if (IS_MOBILE(dev
) && !IS_I830(dev
))
328 dev_priv
->saveLVDS
= I915_READ(LVDS
);
329 if (!IS_I830(dev
) && !IS_845G(dev
))
330 dev_priv
->savePFIT_CONTROL
= I915_READ(PFIT_CONTROL
);
331 dev_priv
->saveLVDSPP_ON
= I915_READ(LVDSPP_ON
);
332 dev_priv
->saveLVDSPP_OFF
= I915_READ(LVDSPP_OFF
);
333 dev_priv
->savePP_CYCLE
= I915_READ(PP_CYCLE
);
335 /* FIXME: save TV & SDVO state */
338 dev_priv
->saveFBC_CFB_BASE
= I915_READ(FBC_CFB_BASE
);
339 dev_priv
->saveFBC_LL_BASE
= I915_READ(FBC_LL_BASE
);
340 dev_priv
->saveFBC_CONTROL2
= I915_READ(FBC_CONTROL2
);
341 dev_priv
->saveFBC_CONTROL
= I915_READ(FBC_CONTROL
);
343 /* Interrupt state */
344 dev_priv
->saveIIR
= I915_READ(I915REG_INT_IDENTITY_R
);
345 dev_priv
->saveIER
= I915_READ(I915REG_INT_ENABLE_R
);
346 dev_priv
->saveIMR
= I915_READ(I915REG_INT_MASK_R
);
349 dev_priv
->saveVCLK_DIVISOR_VGA0
= I915_READ(VCLK_DIVISOR_VGA0
);
350 dev_priv
->saveVCLK_DIVISOR_VGA1
= I915_READ(VCLK_DIVISOR_VGA1
);
351 dev_priv
->saveVCLK_POST_DIV
= I915_READ(VCLK_POST_DIV
);
352 dev_priv
->saveVGACNTRL
= I915_READ(VGACNTRL
);
354 /* Clock gating state */
355 dev_priv
->saveD_STATE
= I915_READ(D_STATE
);
356 dev_priv
->saveDSPCLK_GATE_D
= I915_READ(DSPCLK_GATE_D
);
358 /* Cache mode state */
359 dev_priv
->saveCACHE_MODE_0
= I915_READ(CACHE_MODE_0
);
361 /* Memory Arbitration state */
362 dev_priv
->saveMI_ARB_STATE
= I915_READ(MI_ARB_STATE
);
365 for (i
= 0; i
< 16; i
++) {
366 dev_priv
->saveSWF0
[i
] = I915_READ(SWF0
+ (i
<< 2));
367 dev_priv
->saveSWF1
[i
] = I915_READ(SWF10
+ (i
<< 2));
369 for (i
= 0; i
< 3; i
++)
370 dev_priv
->saveSWF2
[i
] = I915_READ(SWF30
+ (i
<< 2));
374 if (state
.event
== PM_EVENT_SUSPEND
) {
375 /* Shut down the device */
376 pci_disable_device(dev
->pdev
);
377 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
383 static int i915_resume(struct drm_device
*dev
)
385 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
388 pci_set_power_state(dev
->pdev
, PCI_D0
);
389 pci_restore_state(dev
->pdev
);
390 if (pci_enable_device(dev
->pdev
))
392 pci_set_master(dev
->pdev
);
394 pci_write_config_byte(dev
->pdev
, LBB
, dev_priv
->saveLBB
);
396 I915_WRITE(DSPARB
, dev_priv
->saveDSPARB
);
398 /* Pipe & plane A info */
399 /* Prime the clock */
400 if (dev_priv
->saveDPLL_A
& DPLL_VCO_ENABLE
) {
401 I915_WRITE(DPLL_A
, dev_priv
->saveDPLL_A
&
405 I915_WRITE(FPA0
, dev_priv
->saveFPA0
);
406 I915_WRITE(FPA1
, dev_priv
->saveFPA1
);
407 /* Actually enable it */
408 I915_WRITE(DPLL_A
, dev_priv
->saveDPLL_A
);
411 I915_WRITE(DPLL_A_MD
, dev_priv
->saveDPLL_A_MD
);
415 I915_WRITE(HTOTAL_A
, dev_priv
->saveHTOTAL_A
);
416 I915_WRITE(HBLANK_A
, dev_priv
->saveHBLANK_A
);
417 I915_WRITE(HSYNC_A
, dev_priv
->saveHSYNC_A
);
418 I915_WRITE(VTOTAL_A
, dev_priv
->saveVTOTAL_A
);
419 I915_WRITE(VBLANK_A
, dev_priv
->saveVBLANK_A
);
420 I915_WRITE(VSYNC_A
, dev_priv
->saveVSYNC_A
);
421 I915_WRITE(BCLRPAT_A
, dev_priv
->saveBCLRPAT_A
);
423 /* Restore plane info */
424 I915_WRITE(DSPASIZE
, dev_priv
->saveDSPASIZE
);
425 I915_WRITE(DSPAPOS
, dev_priv
->saveDSPAPOS
);
426 I915_WRITE(PIPEASRC
, dev_priv
->savePIPEASRC
);
427 I915_WRITE(DSPABASE
, dev_priv
->saveDSPABASE
);
428 I915_WRITE(DSPASTRIDE
, dev_priv
->saveDSPASTRIDE
);
430 I915_WRITE(DSPASURF
, dev_priv
->saveDSPASURF
);
431 I915_WRITE(DSPATILEOFF
, dev_priv
->saveDSPATILEOFF
);
434 I915_WRITE(PIPEACONF
, dev_priv
->savePIPEACONF
);
436 i915_restore_palette(dev
, PIPE_A
);
437 /* Enable the plane */
438 I915_WRITE(DSPACNTR
, dev_priv
->saveDSPACNTR
);
439 I915_WRITE(DSPABASE
, I915_READ(DSPABASE
));
441 /* Pipe & plane B info */
442 if (dev_priv
->saveDPLL_B
& DPLL_VCO_ENABLE
) {
443 I915_WRITE(DPLL_B
, dev_priv
->saveDPLL_B
&
447 I915_WRITE(FPB0
, dev_priv
->saveFPB0
);
448 I915_WRITE(FPB1
, dev_priv
->saveFPB1
);
449 /* Actually enable it */
450 I915_WRITE(DPLL_B
, dev_priv
->saveDPLL_B
);
453 I915_WRITE(DPLL_B_MD
, dev_priv
->saveDPLL_B_MD
);
457 I915_WRITE(HTOTAL_B
, dev_priv
->saveHTOTAL_B
);
458 I915_WRITE(HBLANK_B
, dev_priv
->saveHBLANK_B
);
459 I915_WRITE(HSYNC_B
, dev_priv
->saveHSYNC_B
);
460 I915_WRITE(VTOTAL_B
, dev_priv
->saveVTOTAL_B
);
461 I915_WRITE(VBLANK_B
, dev_priv
->saveVBLANK_B
);
462 I915_WRITE(VSYNC_B
, dev_priv
->saveVSYNC_B
);
463 I915_WRITE(BCLRPAT_B
, dev_priv
->saveBCLRPAT_B
);
465 /* Restore plane info */
466 I915_WRITE(DSPBSIZE
, dev_priv
->saveDSPBSIZE
);
467 I915_WRITE(DSPBPOS
, dev_priv
->saveDSPBPOS
);
468 I915_WRITE(PIPEBSRC
, dev_priv
->savePIPEBSRC
);
469 I915_WRITE(DSPBBASE
, dev_priv
->saveDSPBBASE
);
470 I915_WRITE(DSPBSTRIDE
, dev_priv
->saveDSPBSTRIDE
);
472 I915_WRITE(DSPBSURF
, dev_priv
->saveDSPBSURF
);
473 I915_WRITE(DSPBTILEOFF
, dev_priv
->saveDSPBTILEOFF
);
476 I915_WRITE(PIPEBCONF
, dev_priv
->savePIPEBCONF
);
478 i915_restore_palette(dev
, PIPE_B
);
479 /* Enable the plane */
480 I915_WRITE(DSPBCNTR
, dev_priv
->saveDSPBCNTR
);
481 I915_WRITE(DSPBBASE
, I915_READ(DSPBBASE
));
484 I915_WRITE(ADPA
, dev_priv
->saveADPA
);
488 I915_WRITE(BLC_PWM_CTL2
, dev_priv
->saveBLC_PWM_CTL2
);
489 if (IS_MOBILE(dev
) && !IS_I830(dev
))
490 I915_WRITE(LVDS
, dev_priv
->saveLVDS
);
491 if (!IS_I830(dev
) && !IS_845G(dev
))
492 I915_WRITE(PFIT_CONTROL
, dev_priv
->savePFIT_CONTROL
);
494 I915_WRITE(PFIT_PGM_RATIOS
, dev_priv
->savePFIT_PGM_RATIOS
);
495 I915_WRITE(BLC_PWM_CTL
, dev_priv
->saveBLC_PWM_CTL
);
496 I915_WRITE(LVDSPP_ON
, dev_priv
->saveLVDSPP_ON
);
497 I915_WRITE(LVDSPP_OFF
, dev_priv
->saveLVDSPP_OFF
);
498 I915_WRITE(PP_CYCLE
, dev_priv
->savePP_CYCLE
);
499 I915_WRITE(PP_CONTROL
, dev_priv
->savePP_CONTROL
);
501 /* FIXME: restore TV & SDVO state */
504 I915_WRITE(FBC_CFB_BASE
, dev_priv
->saveFBC_CFB_BASE
);
505 I915_WRITE(FBC_LL_BASE
, dev_priv
->saveFBC_LL_BASE
);
506 I915_WRITE(FBC_CONTROL2
, dev_priv
->saveFBC_CONTROL2
);
507 I915_WRITE(FBC_CONTROL
, dev_priv
->saveFBC_CONTROL
);
510 I915_WRITE(VGACNTRL
, dev_priv
->saveVGACNTRL
);
511 I915_WRITE(VCLK_DIVISOR_VGA0
, dev_priv
->saveVCLK_DIVISOR_VGA0
);
512 I915_WRITE(VCLK_DIVISOR_VGA1
, dev_priv
->saveVCLK_DIVISOR_VGA1
);
513 I915_WRITE(VCLK_POST_DIV
, dev_priv
->saveVCLK_POST_DIV
);
516 /* Clock gating state */
517 I915_WRITE (D_STATE
, dev_priv
->saveD_STATE
);
518 I915_WRITE (DSPCLK_GATE_D
, dev_priv
->saveDSPCLK_GATE_D
);
520 /* Cache mode state */
521 I915_WRITE (CACHE_MODE_0
, dev_priv
->saveCACHE_MODE_0
| 0xffff0000);
523 /* Memory arbitration state */
524 I915_WRITE (MI_ARB_STATE
, dev_priv
->saveMI_ARB_STATE
| 0xffff0000);
526 for (i
= 0; i
< 16; i
++) {
527 I915_WRITE(SWF0
+ (i
<< 2), dev_priv
->saveSWF0
[i
]);
528 I915_WRITE(SWF10
+ (i
<< 2), dev_priv
->saveSWF1
[i
+7]);
530 for (i
= 0; i
< 3; i
++)
531 I915_WRITE(SWF30
+ (i
<< 2), dev_priv
->saveSWF2
[i
]);
533 i915_restore_vga(dev
);
538 static struct drm_driver driver
= {
539 /* don't use mtrr's here, the Xserver or user space app should
540 * deal with them for intel hardware.
543 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
| /* DRIVER_USE_MTRR |*/
544 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_IRQ_VBL
|
546 .load
= i915_driver_load
,
547 .unload
= i915_driver_unload
,
548 .lastclose
= i915_driver_lastclose
,
549 .preclose
= i915_driver_preclose
,
550 .suspend
= i915_suspend
,
551 .resume
= i915_resume
,
552 .device_is_agp
= i915_driver_device_is_agp
,
553 .vblank_wait
= i915_driver_vblank_wait
,
554 .vblank_wait2
= i915_driver_vblank_wait2
,
555 .irq_preinstall
= i915_driver_irq_preinstall
,
556 .irq_postinstall
= i915_driver_irq_postinstall
,
557 .irq_uninstall
= i915_driver_irq_uninstall
,
558 .irq_handler
= i915_driver_irq_handler
,
559 .reclaim_buffers
= drm_core_reclaim_buffers
,
560 .get_map_ofs
= drm_core_get_map_ofs
,
561 .get_reg_ofs
= drm_core_get_reg_ofs
,
562 .ioctls
= i915_ioctls
,
564 .owner
= THIS_MODULE
,
566 .release
= drm_release
,
570 .fasync
= drm_fasync
,
572 .compat_ioctl
= i915_compat_ioctl
,
578 .id_table
= pciidlist
,
584 .major
= DRIVER_MAJOR
,
585 .minor
= DRIVER_MINOR
,
586 .patchlevel
= DRIVER_PATCHLEVEL
,
589 static int __init
i915_init(void)
591 driver
.num_ioctls
= i915_max_ioctl
;
592 return drm_init(&driver
);
595 static void __exit
i915_exit(void)
600 module_init(i915_init
);
601 module_exit(i915_exit
);
603 MODULE_AUTHOR(DRIVER_AUTHOR
);
604 MODULE_DESCRIPTION(DRIVER_DESC
);
605 MODULE_LICENSE("GPL and additional rights");