1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
30 #include <linux/device.h>
32 #include <drm/i915_drm.h>
34 #include "i915_trace.h"
35 #include "intel_drv.h"
37 #include <linux/console.h>
38 #include <linux/module.h>
39 #include <drm/drm_crtc_helper.h>
41 static int i915_modeset __read_mostly
= -1;
42 module_param_named(modeset
, i915_modeset
, int, 0400);
43 MODULE_PARM_DESC(modeset
,
44 "Use kernel modesetting [KMS] (0=DRM_I915_KMS from .config, "
45 "1=on, -1=force vga console preference [default])");
47 unsigned int i915_fbpercrtc __always_unused
= 0;
48 module_param_named(fbpercrtc
, i915_fbpercrtc
, int, 0400);
50 int i915_panel_ignore_lid __read_mostly
= 1;
51 module_param_named(panel_ignore_lid
, i915_panel_ignore_lid
, int, 0600);
52 MODULE_PARM_DESC(panel_ignore_lid
,
53 "Override lid status (0=autodetect, 1=autodetect disabled [default], "
54 "-1=force lid closed, -2=force lid open)");
56 unsigned int i915_powersave __read_mostly
= 1;
57 module_param_named(powersave
, i915_powersave
, int, 0600);
58 MODULE_PARM_DESC(powersave
,
59 "Enable powersavings, fbc, downclocking, etc. (default: true)");
61 int i915_semaphores __read_mostly
= -1;
62 module_param_named(semaphores
, i915_semaphores
, int, 0600);
63 MODULE_PARM_DESC(semaphores
,
64 "Use semaphores for inter-ring sync (default: -1 (use per-chip defaults))");
66 int i915_enable_rc6 __read_mostly
= -1;
67 module_param_named(i915_enable_rc6
, i915_enable_rc6
, int, 0400);
68 MODULE_PARM_DESC(i915_enable_rc6
,
69 "Enable power-saving render C-state 6. "
70 "Different stages can be selected via bitmask values "
71 "(0 = disable; 1 = enable rc6; 2 = enable deep rc6; 4 = enable deepest rc6). "
72 "For example, 3 would enable rc6 and deep rc6, and 7 would enable everything. "
73 "default: -1 (use per-chip default)");
75 int i915_enable_fbc __read_mostly
= -1;
76 module_param_named(i915_enable_fbc
, i915_enable_fbc
, int, 0600);
77 MODULE_PARM_DESC(i915_enable_fbc
,
78 "Enable frame buffer compression for power savings "
79 "(default: -1 (use per-chip default))");
81 unsigned int i915_lvds_downclock __read_mostly
= 0;
82 module_param_named(lvds_downclock
, i915_lvds_downclock
, int, 0400);
83 MODULE_PARM_DESC(lvds_downclock
,
84 "Use panel (LVDS/eDP) downclocking for power savings "
87 int i915_lvds_channel_mode __read_mostly
;
88 module_param_named(lvds_channel_mode
, i915_lvds_channel_mode
, int, 0600);
89 MODULE_PARM_DESC(lvds_channel_mode
,
90 "Specify LVDS channel mode "
91 "(0=probe BIOS [default], 1=single-channel, 2=dual-channel)");
93 int i915_panel_use_ssc __read_mostly
= -1;
94 module_param_named(lvds_use_ssc
, i915_panel_use_ssc
, int, 0600);
95 MODULE_PARM_DESC(lvds_use_ssc
,
96 "Use Spread Spectrum Clock with panels [LVDS/eDP] "
97 "(default: auto from VBT)");
99 int i915_vbt_sdvo_panel_type __read_mostly
= -1;
100 module_param_named(vbt_sdvo_panel_type
, i915_vbt_sdvo_panel_type
, int, 0600);
101 MODULE_PARM_DESC(vbt_sdvo_panel_type
,
102 "Override/Ignore selection of SDVO panel mode in the VBT "
103 "(-2=ignore, -1=auto [default], index in VBT BIOS table)");
105 static bool i915_try_reset __read_mostly
= true;
106 module_param_named(reset
, i915_try_reset
, bool, 0600);
107 MODULE_PARM_DESC(reset
, "Attempt GPU resets (default: true)");
109 bool i915_enable_hangcheck __read_mostly
= true;
110 module_param_named(enable_hangcheck
, i915_enable_hangcheck
, bool, 0644);
111 MODULE_PARM_DESC(enable_hangcheck
,
112 "Periodically check GPU activity for detecting hangs. "
113 "WARNING: Disabling this can cause system wide hangs. "
116 int i915_enable_ppgtt __read_mostly
= -1;
117 module_param_named(i915_enable_ppgtt
, i915_enable_ppgtt
, int, 0600);
118 MODULE_PARM_DESC(i915_enable_ppgtt
,
119 "Enable PPGTT (default: true)");
121 int i915_enable_psr __read_mostly
= 0;
122 module_param_named(enable_psr
, i915_enable_psr
, int, 0600);
123 MODULE_PARM_DESC(enable_psr
, "Enable PSR (default: false)");
125 unsigned int i915_preliminary_hw_support __read_mostly
= IS_ENABLED(CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT
);
126 module_param_named(preliminary_hw_support
, i915_preliminary_hw_support
, int, 0600);
127 MODULE_PARM_DESC(preliminary_hw_support
,
128 "Enable preliminary hardware support.");
130 int i915_disable_power_well __read_mostly
= 1;
131 module_param_named(disable_power_well
, i915_disable_power_well
, int, 0600);
132 MODULE_PARM_DESC(disable_power_well
,
133 "Disable the power well when possible (default: true)");
135 int i915_enable_ips __read_mostly
= 1;
136 module_param_named(enable_ips
, i915_enable_ips
, int, 0600);
137 MODULE_PARM_DESC(enable_ips
, "Enable IPS (default: true)");
139 bool i915_fastboot __read_mostly
= 0;
140 module_param_named(fastboot
, i915_fastboot
, bool, 0600);
141 MODULE_PARM_DESC(fastboot
, "Try to skip unnecessary mode sets at boot time "
144 int i915_enable_pc8 __read_mostly
= 1;
145 module_param_named(enable_pc8
, i915_enable_pc8
, int, 0600);
146 MODULE_PARM_DESC(enable_pc8
, "Enable support for low power package C states (PC8+) (default: true)");
148 int i915_pc8_timeout __read_mostly
= 5000;
149 module_param_named(pc8_timeout
, i915_pc8_timeout
, int, 0600);
150 MODULE_PARM_DESC(pc8_timeout
, "Number of msecs of idleness required to enter PC8+ (default: 5000)");
152 bool i915_prefault_disable __read_mostly
;
153 module_param_named(prefault_disable
, i915_prefault_disable
, bool, 0600);
154 MODULE_PARM_DESC(prefault_disable
,
155 "Disable page prefaulting for pread/pwrite/reloc (default:false). For developers only.");
157 static struct drm_driver driver
;
158 extern int intel_agp_enabled
;
160 static const struct intel_device_info intel_i830_info
= {
161 .gen
= 2, .is_mobile
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
162 .has_overlay
= 1, .overlay_needs_physical
= 1,
165 static const struct intel_device_info intel_845g_info
= {
166 .gen
= 2, .num_pipes
= 1,
167 .has_overlay
= 1, .overlay_needs_physical
= 1,
170 static const struct intel_device_info intel_i85x_info
= {
171 .gen
= 2, .is_i85x
= 1, .is_mobile
= 1, .num_pipes
= 2,
172 .cursor_needs_physical
= 1,
173 .has_overlay
= 1, .overlay_needs_physical
= 1,
176 static const struct intel_device_info intel_i865g_info
= {
177 .gen
= 2, .num_pipes
= 1,
178 .has_overlay
= 1, .overlay_needs_physical
= 1,
181 static const struct intel_device_info intel_i915g_info
= {
182 .gen
= 3, .is_i915g
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
183 .has_overlay
= 1, .overlay_needs_physical
= 1,
185 static const struct intel_device_info intel_i915gm_info
= {
186 .gen
= 3, .is_mobile
= 1, .num_pipes
= 2,
187 .cursor_needs_physical
= 1,
188 .has_overlay
= 1, .overlay_needs_physical
= 1,
191 static const struct intel_device_info intel_i945g_info
= {
192 .gen
= 3, .has_hotplug
= 1, .cursor_needs_physical
= 1, .num_pipes
= 2,
193 .has_overlay
= 1, .overlay_needs_physical
= 1,
195 static const struct intel_device_info intel_i945gm_info
= {
196 .gen
= 3, .is_i945gm
= 1, .is_mobile
= 1, .num_pipes
= 2,
197 .has_hotplug
= 1, .cursor_needs_physical
= 1,
198 .has_overlay
= 1, .overlay_needs_physical
= 1,
202 static const struct intel_device_info intel_i965g_info
= {
203 .gen
= 4, .is_broadwater
= 1, .num_pipes
= 2,
208 static const struct intel_device_info intel_i965gm_info
= {
209 .gen
= 4, .is_crestline
= 1, .num_pipes
= 2,
210 .is_mobile
= 1, .has_fbc
= 1, .has_hotplug
= 1,
215 static const struct intel_device_info intel_g33_info
= {
216 .gen
= 3, .is_g33
= 1, .num_pipes
= 2,
217 .need_gfx_hws
= 1, .has_hotplug
= 1,
221 static const struct intel_device_info intel_g45_info
= {
222 .gen
= 4, .is_g4x
= 1, .need_gfx_hws
= 1, .num_pipes
= 2,
223 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
227 static const struct intel_device_info intel_gm45_info
= {
228 .gen
= 4, .is_g4x
= 1, .num_pipes
= 2,
229 .is_mobile
= 1, .need_gfx_hws
= 1, .has_fbc
= 1,
230 .has_pipe_cxsr
= 1, .has_hotplug
= 1,
235 static const struct intel_device_info intel_pineview_info
= {
236 .gen
= 3, .is_g33
= 1, .is_pineview
= 1, .is_mobile
= 1, .num_pipes
= 2,
237 .need_gfx_hws
= 1, .has_hotplug
= 1,
241 static const struct intel_device_info intel_ironlake_d_info
= {
242 .gen
= 5, .num_pipes
= 2,
243 .need_gfx_hws
= 1, .has_hotplug
= 1,
247 static const struct intel_device_info intel_ironlake_m_info
= {
248 .gen
= 5, .is_mobile
= 1, .num_pipes
= 2,
249 .need_gfx_hws
= 1, .has_hotplug
= 1,
254 static const struct intel_device_info intel_sandybridge_d_info
= {
255 .gen
= 6, .num_pipes
= 2,
256 .need_gfx_hws
= 1, .has_hotplug
= 1,
263 static const struct intel_device_info intel_sandybridge_m_info
= {
264 .gen
= 6, .is_mobile
= 1, .num_pipes
= 2,
265 .need_gfx_hws
= 1, .has_hotplug
= 1,
273 #define GEN7_FEATURES \
274 .gen = 7, .num_pipes = 3, \
275 .need_gfx_hws = 1, .has_hotplug = 1, \
281 static const struct intel_device_info intel_ivybridge_d_info
= {
286 static const struct intel_device_info intel_ivybridge_m_info
= {
293 static const struct intel_device_info intel_ivybridge_q_info
= {
296 .num_pipes
= 0, /* legal, last one wins */
299 static const struct intel_device_info intel_valleyview_m_info
= {
304 .display_mmio_offset
= VLV_DISPLAY_BASE
,
305 .has_llc
= 0, /* legal, last one wins */
308 static const struct intel_device_info intel_valleyview_d_info
= {
312 .display_mmio_offset
= VLV_DISPLAY_BASE
,
313 .has_llc
= 0, /* legal, last one wins */
316 static const struct intel_device_info intel_haswell_d_info
= {
324 static const struct intel_device_info intel_haswell_m_info
= {
335 * Make sure any device matches here are from most specific to most
336 * general. For example, since the Quanta match is based on the subsystem
337 * and subvendor IDs, we need it to come before the more general IVB
338 * PCI ID matches, otherwise we'll use the wrong info struct above.
340 #define INTEL_PCI_IDS \
341 INTEL_I830_IDS(&intel_i830_info), \
342 INTEL_I845G_IDS(&intel_845g_info), \
343 INTEL_I85X_IDS(&intel_i85x_info), \
344 INTEL_I865G_IDS(&intel_i865g_info), \
345 INTEL_I915G_IDS(&intel_i915g_info), \
346 INTEL_I915GM_IDS(&intel_i915gm_info), \
347 INTEL_I945G_IDS(&intel_i945g_info), \
348 INTEL_I945GM_IDS(&intel_i945gm_info), \
349 INTEL_I965G_IDS(&intel_i965g_info), \
350 INTEL_G33_IDS(&intel_g33_info), \
351 INTEL_I965GM_IDS(&intel_i965gm_info), \
352 INTEL_GM45_IDS(&intel_gm45_info), \
353 INTEL_G45_IDS(&intel_g45_info), \
354 INTEL_PINEVIEW_IDS(&intel_pineview_info), \
355 INTEL_IRONLAKE_D_IDS(&intel_ironlake_d_info), \
356 INTEL_IRONLAKE_M_IDS(&intel_ironlake_m_info), \
357 INTEL_SNB_D_IDS(&intel_sandybridge_d_info), \
358 INTEL_SNB_M_IDS(&intel_sandybridge_m_info), \
359 INTEL_IVB_Q_IDS(&intel_ivybridge_q_info), /* must be first IVB */ \
360 INTEL_IVB_M_IDS(&intel_ivybridge_m_info), \
361 INTEL_IVB_D_IDS(&intel_ivybridge_d_info), \
362 INTEL_HSW_D_IDS(&intel_haswell_d_info), \
363 INTEL_HSW_M_IDS(&intel_haswell_m_info), \
364 INTEL_VLV_M_IDS(&intel_valleyview_m_info), \
365 INTEL_VLV_D_IDS(&intel_valleyview_d_info)
367 static const struct pci_device_id pciidlist
[] = { /* aka */
372 #if defined(CONFIG_DRM_I915_KMS)
373 MODULE_DEVICE_TABLE(pci
, pciidlist
);
376 void intel_detect_pch(struct drm_device
*dev
)
378 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
381 /* In all current cases, num_pipes is equivalent to the PCH_NOP setting
382 * (which really amounts to a PCH but no South Display).
384 if (INTEL_INFO(dev
)->num_pipes
== 0) {
385 dev_priv
->pch_type
= PCH_NOP
;
390 * The reason to probe ISA bridge instead of Dev31:Fun0 is to
391 * make graphics device passthrough work easy for VMM, that only
392 * need to expose ISA bridge to let driver know the real hardware
393 * underneath. This is a requirement from virtualization team.
395 * In some virtualized environments (e.g. XEN), there is irrelevant
396 * ISA bridge in the system. To work reliably, we should scan trhough
397 * all the ISA bridge devices and check for the first match, instead
398 * of only checking the first one.
400 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, NULL
);
402 struct pci_dev
*curr
= pch
;
403 if (pch
->vendor
== PCI_VENDOR_ID_INTEL
) {
405 id
= pch
->device
& INTEL_PCH_DEVICE_ID_MASK
;
406 dev_priv
->pch_id
= id
;
408 if (id
== INTEL_PCH_IBX_DEVICE_ID_TYPE
) {
409 dev_priv
->pch_type
= PCH_IBX
;
410 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
411 WARN_ON(!IS_GEN5(dev
));
412 } else if (id
== INTEL_PCH_CPT_DEVICE_ID_TYPE
) {
413 dev_priv
->pch_type
= PCH_CPT
;
414 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
415 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
416 } else if (id
== INTEL_PCH_PPT_DEVICE_ID_TYPE
) {
417 /* PantherPoint is CPT compatible */
418 dev_priv
->pch_type
= PCH_CPT
;
419 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
420 WARN_ON(!(IS_GEN6(dev
) || IS_IVYBRIDGE(dev
)));
421 } else if (id
== INTEL_PCH_LPT_DEVICE_ID_TYPE
) {
422 dev_priv
->pch_type
= PCH_LPT
;
423 DRM_DEBUG_KMS("Found LynxPoint PCH\n");
424 WARN_ON(!IS_HASWELL(dev
));
425 WARN_ON(IS_ULT(dev
));
426 } else if (id
== INTEL_PCH_LPT_LP_DEVICE_ID_TYPE
) {
427 dev_priv
->pch_type
= PCH_LPT
;
428 DRM_DEBUG_KMS("Found LynxPoint LP PCH\n");
429 WARN_ON(!IS_HASWELL(dev
));
430 WARN_ON(!IS_ULT(dev
));
438 pch
= pci_get_class(PCI_CLASS_BRIDGE_ISA
<< 8, curr
);
442 DRM_DEBUG_KMS("No PCH found?\n");
445 bool i915_semaphore_is_enabled(struct drm_device
*dev
)
447 if (INTEL_INFO(dev
)->gen
< 6)
450 if (i915_semaphores
>= 0)
451 return i915_semaphores
;
453 #ifdef CONFIG_INTEL_IOMMU
454 /* Enable semaphores on SNB when IO remapping is off */
455 if (INTEL_INFO(dev
)->gen
== 6 && intel_iommu_gfx_mapped
)
462 static int i915_drm_freeze(struct drm_device
*dev
)
464 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
465 struct drm_crtc
*crtc
;
467 /* ignore lid events during suspend */
468 mutex_lock(&dev_priv
->modeset_restore_lock
);
469 dev_priv
->modeset_restore
= MODESET_SUSPENDED
;
470 mutex_unlock(&dev_priv
->modeset_restore_lock
);
472 /* We do a lot of poking in a lot of registers, make sure they work
474 hsw_disable_package_c8(dev_priv
);
475 intel_set_power_well(dev
, true);
477 drm_kms_helper_poll_disable(dev
);
479 pci_save_state(dev
->pdev
);
481 /* If KMS is active, we do the leavevt stuff here */
482 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
485 mutex_lock(&dev
->struct_mutex
);
486 error
= i915_gem_idle(dev
);
487 mutex_unlock(&dev
->struct_mutex
);
489 dev_err(&dev
->pdev
->dev
,
490 "GEM idle failed, resume might fail\n");
494 cancel_delayed_work_sync(&dev_priv
->rps
.delayed_resume_work
);
496 drm_irq_uninstall(dev
);
497 dev_priv
->enable_hotplug_processing
= false;
499 * Disable CRTCs directly since we want to preserve sw state
502 list_for_each_entry(crtc
, &dev
->mode_config
.crtc_list
, head
)
503 dev_priv
->display
.crtc_disable(crtc
);
505 intel_modeset_suspend_hw(dev
);
508 i915_save_state(dev
);
510 intel_opregion_fini(dev
);
513 intel_fbdev_set_suspend(dev
, FBINFO_STATE_SUSPENDED
);
519 int i915_suspend(struct drm_device
*dev
, pm_message_t state
)
523 if (!dev
|| !dev
->dev_private
) {
524 DRM_ERROR("dev: %p\n", dev
);
525 DRM_ERROR("DRM not initialized, aborting suspend.\n");
529 if (state
.event
== PM_EVENT_PRETHAW
)
533 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
536 error
= i915_drm_freeze(dev
);
540 if (state
.event
== PM_EVENT_SUSPEND
) {
541 /* Shut down the device */
542 pci_disable_device(dev
->pdev
);
543 pci_set_power_state(dev
->pdev
, PCI_D3hot
);
549 void intel_console_resume(struct work_struct
*work
)
551 struct drm_i915_private
*dev_priv
=
552 container_of(work
, struct drm_i915_private
,
553 console_resume_work
);
554 struct drm_device
*dev
= dev_priv
->dev
;
557 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
561 static void intel_resume_hotplug(struct drm_device
*dev
)
563 struct drm_mode_config
*mode_config
= &dev
->mode_config
;
564 struct intel_encoder
*encoder
;
566 mutex_lock(&mode_config
->mutex
);
567 DRM_DEBUG_KMS("running encoder hotplug functions\n");
569 list_for_each_entry(encoder
, &mode_config
->encoder_list
, base
.head
)
570 if (encoder
->hot_plug
)
571 encoder
->hot_plug(encoder
);
573 mutex_unlock(&mode_config
->mutex
);
575 /* Just fire off a uevent and let userspace tell us what to do */
576 drm_helper_hpd_irq_event(dev
);
579 static int __i915_drm_thaw(struct drm_device
*dev
)
581 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
584 i915_restore_state(dev
);
585 intel_opregion_setup(dev
);
587 /* KMS EnterVT equivalent */
588 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
589 intel_init_pch_refclk(dev
);
591 mutex_lock(&dev
->struct_mutex
);
593 error
= i915_gem_init_hw(dev
);
594 mutex_unlock(&dev
->struct_mutex
);
596 /* We need working interrupts for modeset enabling ... */
597 drm_irq_install(dev
);
599 intel_modeset_init_hw(dev
);
601 drm_modeset_lock_all(dev
);
602 intel_modeset_setup_hw_state(dev
, true);
603 drm_modeset_unlock_all(dev
);
606 * ... but also need to make sure that hotplug processing
607 * doesn't cause havoc. Like in the driver load code we don't
608 * bother with the tiny race here where we might loose hotplug
612 dev_priv
->enable_hotplug_processing
= true;
613 /* Config may have changed between suspend and resume */
614 intel_resume_hotplug(dev
);
617 intel_opregion_init(dev
);
620 * The console lock can be pretty contented on resume due
621 * to all the printk activity. Try to keep it out of the hot
622 * path of resume if possible.
624 if (console_trylock()) {
625 intel_fbdev_set_suspend(dev
, FBINFO_STATE_RUNNING
);
628 schedule_work(&dev_priv
->console_resume_work
);
631 /* Undo what we did at i915_drm_freeze so the refcount goes back to the
633 hsw_enable_package_c8(dev_priv
);
635 mutex_lock(&dev_priv
->modeset_restore_lock
);
636 dev_priv
->modeset_restore
= MODESET_DONE
;
637 mutex_unlock(&dev_priv
->modeset_restore_lock
);
641 static int i915_drm_thaw(struct drm_device
*dev
)
645 intel_uncore_sanitize(dev
);
647 if (drm_core_check_feature(dev
, DRIVER_MODESET
)) {
648 mutex_lock(&dev
->struct_mutex
);
649 i915_gem_restore_gtt_mappings(dev
);
650 mutex_unlock(&dev
->struct_mutex
);
653 __i915_drm_thaw(dev
);
658 int i915_resume(struct drm_device
*dev
)
660 struct drm_i915_private
*dev_priv
= dev
->dev_private
;
663 if (dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
666 if (pci_enable_device(dev
->pdev
))
669 pci_set_master(dev
->pdev
);
671 intel_uncore_sanitize(dev
);
674 * Platforms with opregion should have sane BIOS, older ones (gen3 and
675 * earlier) need this since the BIOS might clear all our scratch PTEs.
677 if (drm_core_check_feature(dev
, DRIVER_MODESET
) &&
678 !dev_priv
->opregion
.header
) {
679 mutex_lock(&dev
->struct_mutex
);
680 i915_gem_restore_gtt_mappings(dev
);
681 mutex_unlock(&dev
->struct_mutex
);
684 ret
= __i915_drm_thaw(dev
);
688 drm_kms_helper_poll_enable(dev
);
693 * i915_reset - reset chip after a hang
694 * @dev: drm device to reset
696 * Reset the chip. Useful if a hang is detected. Returns zero on successful
697 * reset or otherwise an error code.
699 * Procedure is fairly simple:
700 * - reset the chip using the reset reg
701 * - re-init context state
702 * - re-init hardware status page
703 * - re-init ring buffer
704 * - re-init interrupt state
707 int i915_reset(struct drm_device
*dev
)
709 drm_i915_private_t
*dev_priv
= dev
->dev_private
;
716 mutex_lock(&dev
->struct_mutex
);
720 simulated
= dev_priv
->gpu_error
.stop_rings
!= 0;
722 if (!simulated
&& get_seconds() - dev_priv
->gpu_error
.last_reset
< 5) {
723 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
726 ret
= intel_gpu_reset(dev
);
728 /* Also reset the gpu hangman. */
730 DRM_INFO("Simulated gpu hang, resetting stop_rings\n");
731 dev_priv
->gpu_error
.stop_rings
= 0;
732 if (ret
== -ENODEV
) {
733 DRM_ERROR("Reset not implemented, but ignoring "
734 "error for simulated gpu hangs\n");
738 dev_priv
->gpu_error
.last_reset
= get_seconds();
741 DRM_ERROR("Failed to reset chip.\n");
742 mutex_unlock(&dev
->struct_mutex
);
746 /* Ok, now get things going again... */
749 * Everything depends on having the GTT running, so we need to start
750 * there. Fortunately we don't need to do this unless we reset the
751 * chip at a PCI level.
753 * Next we need to restore the context, but we don't use those
756 * Ring buffer needs to be re-initialized in the KMS case, or if X
757 * was running at the time of the reset (i.e. we weren't VT
760 if (drm_core_check_feature(dev
, DRIVER_MODESET
) ||
761 !dev_priv
->ums
.mm_suspended
) {
762 struct intel_ring_buffer
*ring
;
765 dev_priv
->ums
.mm_suspended
= 0;
767 i915_gem_init_swizzling(dev
);
769 for_each_ring(ring
, dev_priv
, i
)
772 i915_gem_context_init(dev
);
773 if (dev_priv
->mm
.aliasing_ppgtt
) {
774 ret
= dev_priv
->mm
.aliasing_ppgtt
->enable(dev
);
776 i915_gem_cleanup_aliasing_ppgtt(dev
);
780 * It would make sense to re-init all the other hw state, at
781 * least the rps/rc6/emon init done within modeset_init_hw. For
782 * some unknown reason, this blows up my ilk, so don't.
785 mutex_unlock(&dev
->struct_mutex
);
787 drm_irq_uninstall(dev
);
788 drm_irq_install(dev
);
791 mutex_unlock(&dev
->struct_mutex
);
797 static int i915_pci_probe(struct pci_dev
*pdev
, const struct pci_device_id
*ent
)
799 struct intel_device_info
*intel_info
=
800 (struct intel_device_info
*) ent
->driver_data
;
802 /* Only bind to function 0 of the device. Early generations
803 * used function 1 as a placeholder for multi-head. This causes
804 * us confusion instead, especially on the systems where both
805 * functions have the same PCI-ID!
807 if (PCI_FUNC(pdev
->devfn
))
810 /* We've managed to ship a kms-enabled ddx that shipped with an XvMC
811 * implementation for gen3 (and only gen3) that used legacy drm maps
812 * (gasp!) to share buffers between X and the client. Hence we need to
813 * keep around the fake agp stuff for gen3, even when kms is enabled. */
814 if (intel_info
->gen
!= 3) {
815 driver
.driver_features
&=
816 ~(DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
);
817 } else if (!intel_agp_enabled
) {
818 DRM_ERROR("drm/i915 can't work without intel_agp module!\n");
822 return drm_get_pci_dev(pdev
, ent
, &driver
);
826 i915_pci_remove(struct pci_dev
*pdev
)
828 struct drm_device
*dev
= pci_get_drvdata(pdev
);
833 static int i915_pm_suspend(struct device
*dev
)
835 struct pci_dev
*pdev
= to_pci_dev(dev
);
836 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
839 if (!drm_dev
|| !drm_dev
->dev_private
) {
840 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
844 if (drm_dev
->switch_power_state
== DRM_SWITCH_POWER_OFF
)
847 error
= i915_drm_freeze(drm_dev
);
851 pci_disable_device(pdev
);
852 pci_set_power_state(pdev
, PCI_D3hot
);
857 static int i915_pm_resume(struct device
*dev
)
859 struct pci_dev
*pdev
= to_pci_dev(dev
);
860 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
862 return i915_resume(drm_dev
);
865 static int i915_pm_freeze(struct device
*dev
)
867 struct pci_dev
*pdev
= to_pci_dev(dev
);
868 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
870 if (!drm_dev
|| !drm_dev
->dev_private
) {
871 dev_err(dev
, "DRM not initialized, aborting suspend.\n");
875 return i915_drm_freeze(drm_dev
);
878 static int i915_pm_thaw(struct device
*dev
)
880 struct pci_dev
*pdev
= to_pci_dev(dev
);
881 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
883 return i915_drm_thaw(drm_dev
);
886 static int i915_pm_poweroff(struct device
*dev
)
888 struct pci_dev
*pdev
= to_pci_dev(dev
);
889 struct drm_device
*drm_dev
= pci_get_drvdata(pdev
);
891 return i915_drm_freeze(drm_dev
);
894 static const struct dev_pm_ops i915_pm_ops
= {
895 .suspend
= i915_pm_suspend
,
896 .resume
= i915_pm_resume
,
897 .freeze
= i915_pm_freeze
,
898 .thaw
= i915_pm_thaw
,
899 .poweroff
= i915_pm_poweroff
,
900 .restore
= i915_pm_resume
,
903 static const struct vm_operations_struct i915_gem_vm_ops
= {
904 .fault
= i915_gem_fault
,
905 .open
= drm_gem_vm_open
,
906 .close
= drm_gem_vm_close
,
909 static const struct file_operations i915_driver_fops
= {
910 .owner
= THIS_MODULE
,
912 .release
= drm_release
,
913 .unlocked_ioctl
= drm_ioctl
,
914 .mmap
= drm_gem_mmap
,
918 .compat_ioctl
= i915_compat_ioctl
,
920 .llseek
= noop_llseek
,
923 static struct drm_driver driver
= {
924 /* Don't use MTRRs here; the Xserver or userspace app should
925 * deal with them for Intel hardware.
928 DRIVER_USE_AGP
| DRIVER_REQUIRE_AGP
|
929 DRIVER_HAVE_IRQ
| DRIVER_IRQ_SHARED
| DRIVER_GEM
| DRIVER_PRIME
|
931 .load
= i915_driver_load
,
932 .unload
= i915_driver_unload
,
933 .open
= i915_driver_open
,
934 .lastclose
= i915_driver_lastclose
,
935 .preclose
= i915_driver_preclose
,
936 .postclose
= i915_driver_postclose
,
938 /* Used in place of i915_pm_ops for non-DRIVER_MODESET */
939 .suspend
= i915_suspend
,
940 .resume
= i915_resume
,
942 .device_is_agp
= i915_driver_device_is_agp
,
943 .master_create
= i915_master_create
,
944 .master_destroy
= i915_master_destroy
,
945 #if defined(CONFIG_DEBUG_FS)
946 .debugfs_init
= i915_debugfs_init
,
947 .debugfs_cleanup
= i915_debugfs_cleanup
,
949 .gem_init_object
= i915_gem_init_object
,
950 .gem_free_object
= i915_gem_free_object
,
951 .gem_vm_ops
= &i915_gem_vm_ops
,
953 .prime_handle_to_fd
= drm_gem_prime_handle_to_fd
,
954 .prime_fd_to_handle
= drm_gem_prime_fd_to_handle
,
955 .gem_prime_export
= i915_gem_prime_export
,
956 .gem_prime_import
= i915_gem_prime_import
,
958 .dumb_create
= i915_gem_dumb_create
,
959 .dumb_map_offset
= i915_gem_mmap_gtt
,
960 .dumb_destroy
= drm_gem_dumb_destroy
,
961 .ioctls
= i915_ioctls
,
962 .fops
= &i915_driver_fops
,
966 .major
= DRIVER_MAJOR
,
967 .minor
= DRIVER_MINOR
,
968 .patchlevel
= DRIVER_PATCHLEVEL
,
971 static struct pci_driver i915_pci_driver
= {
973 .id_table
= pciidlist
,
974 .probe
= i915_pci_probe
,
975 .remove
= i915_pci_remove
,
976 .driver
.pm
= &i915_pm_ops
,
979 static int __init
i915_init(void)
981 driver
.num_ioctls
= i915_max_ioctl
;
984 * If CONFIG_DRM_I915_KMS is set, default to KMS unless
985 * explicitly disabled with the module pararmeter.
987 * Otherwise, just follow the parameter (defaulting to off).
989 * Allow optional vga_text_mode_force boot option to override
990 * the default behavior.
992 #if defined(CONFIG_DRM_I915_KMS)
993 if (i915_modeset
!= 0)
994 driver
.driver_features
|= DRIVER_MODESET
;
996 if (i915_modeset
== 1)
997 driver
.driver_features
|= DRIVER_MODESET
;
999 #ifdef CONFIG_VGA_CONSOLE
1000 if (vgacon_text_force() && i915_modeset
== -1)
1001 driver
.driver_features
&= ~DRIVER_MODESET
;
1004 if (!(driver
.driver_features
& DRIVER_MODESET
))
1005 driver
.get_vblank_timestamp
= NULL
;
1007 return drm_pci_init(&driver
, &i915_pci_driver
);
1010 static void __exit
i915_exit(void)
1012 drm_pci_exit(&driver
, &i915_pci_driver
);
1015 module_init(i915_init
);
1016 module_exit(i915_exit
);
1018 MODULE_AUTHOR(DRIVER_AUTHOR
);
1019 MODULE_DESCRIPTION(DRIVER_DESC
);
1020 MODULE_LICENSE("GPL and additional rights");