03d6823077bdd20241e72f8bed47a575ed70e9fd
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
35
36 #include "i915_reg.h"
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
53 #include "intel_guc.h"
54
55 /* General customization:
56 */
57
58 #define DRIVER_NAME "i915"
59 #define DRIVER_DESC "Intel Graphics"
60 #define DRIVER_DATE "20151120"
61
62 #undef WARN_ON
63 /* Many gcc seem to no see through this and fall over :( */
64 #if 0
65 #define WARN_ON(x) ({ \
66 bool __i915_warn_cond = (x); \
67 if (__builtin_constant_p(__i915_warn_cond)) \
68 BUILD_BUG_ON(__i915_warn_cond); \
69 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #else
71 #define WARN_ON(x) WARN((x), "WARN_ON(%s)", #x )
72 #endif
73
74 #undef WARN_ON_ONCE
75 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(%s)", #x )
76
77 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
78 (long) (x), __func__);
79
80 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
81 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
82 * which may not necessarily be a user visible problem. This will either
83 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
84 * enable distros and users to tailor their preferred amount of i915 abrt
85 * spam.
86 */
87 #define I915_STATE_WARN(condition, format...) ({ \
88 int __ret_warn_on = !!(condition); \
89 if (unlikely(__ret_warn_on)) { \
90 if (i915.verbose_state_checks) \
91 WARN(1, format); \
92 else \
93 DRM_ERROR(format); \
94 } \
95 unlikely(__ret_warn_on); \
96 })
97
98 #define I915_STATE_WARN_ON(condition) ({ \
99 int __ret_warn_on = !!(condition); \
100 if (unlikely(__ret_warn_on)) { \
101 if (i915.verbose_state_checks) \
102 WARN(1, "WARN_ON(" #condition ")\n"); \
103 else \
104 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 } \
106 unlikely(__ret_warn_on); \
107 })
108
109 static inline const char *yesno(bool v)
110 {
111 return v ? "yes" : "no";
112 }
113
114 enum pipe {
115 INVALID_PIPE = -1,
116 PIPE_A = 0,
117 PIPE_B,
118 PIPE_C,
119 _PIPE_EDP,
120 I915_MAX_PIPES = _PIPE_EDP
121 };
122 #define pipe_name(p) ((p) + 'A')
123
124 enum transcoder {
125 TRANSCODER_A = 0,
126 TRANSCODER_B,
127 TRANSCODER_C,
128 TRANSCODER_EDP,
129 I915_MAX_TRANSCODERS
130 };
131 #define transcoder_name(t) ((t) + 'A')
132
133 /*
134 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
135 * number of planes per CRTC. Not all platforms really have this many planes,
136 * which means some arrays of size I915_MAX_PLANES may have unused entries
137 * between the topmost sprite plane and the cursor plane.
138 */
139 enum plane {
140 PLANE_A = 0,
141 PLANE_B,
142 PLANE_C,
143 PLANE_CURSOR,
144 I915_MAX_PLANES,
145 };
146 #define plane_name(p) ((p) + 'A')
147
148 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
149
150 enum port {
151 PORT_A = 0,
152 PORT_B,
153 PORT_C,
154 PORT_D,
155 PORT_E,
156 I915_MAX_PORTS
157 };
158 #define port_name(p) ((p) + 'A')
159
160 #define I915_NUM_PHYS_VLV 2
161
162 enum dpio_channel {
163 DPIO_CH0,
164 DPIO_CH1
165 };
166
167 enum dpio_phy {
168 DPIO_PHY0,
169 DPIO_PHY1
170 };
171
172 enum intel_display_power_domain {
173 POWER_DOMAIN_PIPE_A,
174 POWER_DOMAIN_PIPE_B,
175 POWER_DOMAIN_PIPE_C,
176 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
177 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
178 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
179 POWER_DOMAIN_TRANSCODER_A,
180 POWER_DOMAIN_TRANSCODER_B,
181 POWER_DOMAIN_TRANSCODER_C,
182 POWER_DOMAIN_TRANSCODER_EDP,
183 POWER_DOMAIN_PORT_DDI_A_LANES,
184 POWER_DOMAIN_PORT_DDI_B_LANES,
185 POWER_DOMAIN_PORT_DDI_C_LANES,
186 POWER_DOMAIN_PORT_DDI_D_LANES,
187 POWER_DOMAIN_PORT_DDI_E_LANES,
188 POWER_DOMAIN_PORT_DSI,
189 POWER_DOMAIN_PORT_CRT,
190 POWER_DOMAIN_PORT_OTHER,
191 POWER_DOMAIN_VGA,
192 POWER_DOMAIN_AUDIO,
193 POWER_DOMAIN_PLLS,
194 POWER_DOMAIN_AUX_A,
195 POWER_DOMAIN_AUX_B,
196 POWER_DOMAIN_AUX_C,
197 POWER_DOMAIN_AUX_D,
198 POWER_DOMAIN_GMBUS,
199 POWER_DOMAIN_MODESET,
200 POWER_DOMAIN_INIT,
201
202 POWER_DOMAIN_NUM,
203 };
204
205 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
206 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
207 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
208 #define POWER_DOMAIN_TRANSCODER(tran) \
209 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
210 (tran) + POWER_DOMAIN_TRANSCODER_A)
211
212 enum hpd_pin {
213 HPD_NONE = 0,
214 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
215 HPD_CRT,
216 HPD_SDVO_B,
217 HPD_SDVO_C,
218 HPD_PORT_A,
219 HPD_PORT_B,
220 HPD_PORT_C,
221 HPD_PORT_D,
222 HPD_PORT_E,
223 HPD_NUM_PINS
224 };
225
226 #define for_each_hpd_pin(__pin) \
227 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
228
229 struct i915_hotplug {
230 struct work_struct hotplug_work;
231
232 struct {
233 unsigned long last_jiffies;
234 int count;
235 enum {
236 HPD_ENABLED = 0,
237 HPD_DISABLED = 1,
238 HPD_MARK_DISABLED = 2
239 } state;
240 } stats[HPD_NUM_PINS];
241 u32 event_bits;
242 struct delayed_work reenable_work;
243
244 struct intel_digital_port *irq_port[I915_MAX_PORTS];
245 u32 long_port_mask;
246 u32 short_port_mask;
247 struct work_struct dig_port_work;
248
249 /*
250 * if we get a HPD irq from DP and a HPD irq from non-DP
251 * the non-DP HPD could block the workqueue on a mode config
252 * mutex getting, that userspace may have taken. However
253 * userspace is waiting on the DP workqueue to run which is
254 * blocked behind the non-DP one.
255 */
256 struct workqueue_struct *dp_wq;
257 };
258
259 #define I915_GEM_GPU_DOMAINS \
260 (I915_GEM_DOMAIN_RENDER | \
261 I915_GEM_DOMAIN_SAMPLER | \
262 I915_GEM_DOMAIN_COMMAND | \
263 I915_GEM_DOMAIN_INSTRUCTION | \
264 I915_GEM_DOMAIN_VERTEX)
265
266 #define for_each_pipe(__dev_priv, __p) \
267 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
268 #define for_each_plane(__dev_priv, __pipe, __p) \
269 for ((__p) = 0; \
270 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
271 (__p)++)
272 #define for_each_sprite(__dev_priv, __p, __s) \
273 for ((__s) = 0; \
274 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
275 (__s)++)
276
277 #define for_each_crtc(dev, crtc) \
278 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
279
280 #define for_each_intel_plane(dev, intel_plane) \
281 list_for_each_entry(intel_plane, \
282 &dev->mode_config.plane_list, \
283 base.head)
284
285 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
286 list_for_each_entry(intel_plane, \
287 &(dev)->mode_config.plane_list, \
288 base.head) \
289 if ((intel_plane)->pipe == (intel_crtc)->pipe)
290
291 #define for_each_intel_crtc(dev, intel_crtc) \
292 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
293
294 #define for_each_intel_encoder(dev, intel_encoder) \
295 list_for_each_entry(intel_encoder, \
296 &(dev)->mode_config.encoder_list, \
297 base.head)
298
299 #define for_each_intel_connector(dev, intel_connector) \
300 list_for_each_entry(intel_connector, \
301 &dev->mode_config.connector_list, \
302 base.head)
303
304 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
305 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
306 if ((intel_encoder)->base.crtc == (__crtc))
307
308 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
309 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
310 if ((intel_connector)->base.encoder == (__encoder))
311
312 #define for_each_power_domain(domain, mask) \
313 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
314 if ((1 << (domain)) & (mask))
315
316 struct drm_i915_private;
317 struct i915_mm_struct;
318 struct i915_mmu_object;
319
320 struct drm_i915_file_private {
321 struct drm_i915_private *dev_priv;
322 struct drm_file *file;
323
324 struct {
325 spinlock_t lock;
326 struct list_head request_list;
327 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
328 * chosen to prevent the CPU getting more than a frame ahead of the GPU
329 * (when using lax throttling for the frontbuffer). We also use it to
330 * offer free GPU waitboosts for severely congested workloads.
331 */
332 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
333 } mm;
334 struct idr context_idr;
335
336 struct intel_rps_client {
337 struct list_head link;
338 unsigned boosts;
339 } rps;
340
341 struct intel_engine_cs *bsd_ring;
342 };
343
344 enum intel_dpll_id {
345 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
346 /* real shared dpll ids must be >= 0 */
347 DPLL_ID_PCH_PLL_A = 0,
348 DPLL_ID_PCH_PLL_B = 1,
349 /* hsw/bdw */
350 DPLL_ID_WRPLL1 = 0,
351 DPLL_ID_WRPLL2 = 1,
352 DPLL_ID_SPLL = 2,
353
354 /* skl */
355 DPLL_ID_SKL_DPLL1 = 0,
356 DPLL_ID_SKL_DPLL2 = 1,
357 DPLL_ID_SKL_DPLL3 = 2,
358 };
359 #define I915_NUM_PLLS 3
360
361 struct intel_dpll_hw_state {
362 /* i9xx, pch plls */
363 uint32_t dpll;
364 uint32_t dpll_md;
365 uint32_t fp0;
366 uint32_t fp1;
367
368 /* hsw, bdw */
369 uint32_t wrpll;
370 uint32_t spll;
371
372 /* skl */
373 /*
374 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
375 * lower part of ctrl1 and they get shifted into position when writing
376 * the register. This allows us to easily compare the state to share
377 * the DPLL.
378 */
379 uint32_t ctrl1;
380 /* HDMI only, 0 when used for DP */
381 uint32_t cfgcr1, cfgcr2;
382
383 /* bxt */
384 uint32_t ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10,
385 pcsdw12;
386 };
387
388 struct intel_shared_dpll_config {
389 unsigned crtc_mask; /* mask of CRTCs sharing this PLL */
390 struct intel_dpll_hw_state hw_state;
391 };
392
393 struct intel_shared_dpll {
394 struct intel_shared_dpll_config config;
395
396 int active; /* count of number of active CRTCs (i.e. DPMS on) */
397 bool on; /* is the PLL actually active? Disabled during modeset */
398 const char *name;
399 /* should match the index in the dev_priv->shared_dplls array */
400 enum intel_dpll_id id;
401 /* The mode_set hook is optional and should be used together with the
402 * intel_prepare_shared_dpll function. */
403 void (*mode_set)(struct drm_i915_private *dev_priv,
404 struct intel_shared_dpll *pll);
405 void (*enable)(struct drm_i915_private *dev_priv,
406 struct intel_shared_dpll *pll);
407 void (*disable)(struct drm_i915_private *dev_priv,
408 struct intel_shared_dpll *pll);
409 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
410 struct intel_shared_dpll *pll,
411 struct intel_dpll_hw_state *hw_state);
412 };
413
414 #define SKL_DPLL0 0
415 #define SKL_DPLL1 1
416 #define SKL_DPLL2 2
417 #define SKL_DPLL3 3
418
419 /* Used by dp and fdi links */
420 struct intel_link_m_n {
421 uint32_t tu;
422 uint32_t gmch_m;
423 uint32_t gmch_n;
424 uint32_t link_m;
425 uint32_t link_n;
426 };
427
428 void intel_link_compute_m_n(int bpp, int nlanes,
429 int pixel_clock, int link_clock,
430 struct intel_link_m_n *m_n);
431
432 /* Interface history:
433 *
434 * 1.1: Original.
435 * 1.2: Add Power Management
436 * 1.3: Add vblank support
437 * 1.4: Fix cmdbuffer path, add heap destroy
438 * 1.5: Add vblank pipe configuration
439 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
440 * - Support vertical blank on secondary display pipe
441 */
442 #define DRIVER_MAJOR 1
443 #define DRIVER_MINOR 6
444 #define DRIVER_PATCHLEVEL 0
445
446 #define WATCH_LISTS 0
447
448 struct opregion_header;
449 struct opregion_acpi;
450 struct opregion_swsci;
451 struct opregion_asle;
452
453 struct intel_opregion {
454 struct opregion_header *header;
455 struct opregion_acpi *acpi;
456 struct opregion_swsci *swsci;
457 u32 swsci_gbda_sub_functions;
458 u32 swsci_sbcb_sub_functions;
459 struct opregion_asle *asle;
460 void *vbt;
461 u32 *lid_state;
462 struct work_struct asle_work;
463 };
464 #define OPREGION_SIZE (8*1024)
465
466 struct intel_overlay;
467 struct intel_overlay_error_state;
468
469 #define I915_FENCE_REG_NONE -1
470 #define I915_MAX_NUM_FENCES 32
471 /* 32 fences + sign bit for FENCE_REG_NONE */
472 #define I915_MAX_NUM_FENCE_BITS 6
473
474 struct drm_i915_fence_reg {
475 struct list_head lru_list;
476 struct drm_i915_gem_object *obj;
477 int pin_count;
478 };
479
480 struct sdvo_device_mapping {
481 u8 initialized;
482 u8 dvo_port;
483 u8 slave_addr;
484 u8 dvo_wiring;
485 u8 i2c_pin;
486 u8 ddc_pin;
487 };
488
489 struct intel_display_error_state;
490
491 struct drm_i915_error_state {
492 struct kref ref;
493 struct timeval time;
494
495 char error_msg[128];
496 int iommu;
497 u32 reset_count;
498 u32 suspend_count;
499
500 /* Generic register state */
501 u32 eir;
502 u32 pgtbl_er;
503 u32 ier;
504 u32 gtier[4];
505 u32 ccid;
506 u32 derrmr;
507 u32 forcewake;
508 u32 error; /* gen6+ */
509 u32 err_int; /* gen7 */
510 u32 fault_data0; /* gen8, gen9 */
511 u32 fault_data1; /* gen8, gen9 */
512 u32 done_reg;
513 u32 gac_eco;
514 u32 gam_ecochk;
515 u32 gab_ctl;
516 u32 gfx_mode;
517 u32 extra_instdone[I915_NUM_INSTDONE_REG];
518 u64 fence[I915_MAX_NUM_FENCES];
519 struct intel_overlay_error_state *overlay;
520 struct intel_display_error_state *display;
521 struct drm_i915_error_object *semaphore_obj;
522
523 struct drm_i915_error_ring {
524 bool valid;
525 /* Software tracked state */
526 bool waiting;
527 int hangcheck_score;
528 enum intel_ring_hangcheck_action hangcheck_action;
529 int num_requests;
530
531 /* our own tracking of ring head and tail */
532 u32 cpu_ring_head;
533 u32 cpu_ring_tail;
534
535 u32 semaphore_seqno[I915_NUM_RINGS - 1];
536
537 /* Register state */
538 u32 start;
539 u32 tail;
540 u32 head;
541 u32 ctl;
542 u32 hws;
543 u32 ipeir;
544 u32 ipehr;
545 u32 instdone;
546 u32 bbstate;
547 u32 instpm;
548 u32 instps;
549 u32 seqno;
550 u64 bbaddr;
551 u64 acthd;
552 u32 fault_reg;
553 u64 faddr;
554 u32 rc_psmi; /* sleep state */
555 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
556
557 struct drm_i915_error_object {
558 int page_count;
559 u64 gtt_offset;
560 u32 *pages[0];
561 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
562
563 struct drm_i915_error_request {
564 long jiffies;
565 u32 seqno;
566 u32 tail;
567 } *requests;
568
569 struct {
570 u32 gfx_mode;
571 union {
572 u64 pdp[4];
573 u32 pp_dir_base;
574 };
575 } vm_info;
576
577 pid_t pid;
578 char comm[TASK_COMM_LEN];
579 } ring[I915_NUM_RINGS];
580
581 struct drm_i915_error_buffer {
582 u32 size;
583 u32 name;
584 u32 rseqno[I915_NUM_RINGS], wseqno;
585 u64 gtt_offset;
586 u32 read_domains;
587 u32 write_domain;
588 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
589 s32 pinned:2;
590 u32 tiling:2;
591 u32 dirty:1;
592 u32 purgeable:1;
593 u32 userptr:1;
594 s32 ring:4;
595 u32 cache_level:3;
596 } **active_bo, **pinned_bo;
597
598 u32 *active_bo_count, *pinned_bo_count;
599 u32 vm_count;
600 };
601
602 struct intel_connector;
603 struct intel_encoder;
604 struct intel_crtc_state;
605 struct intel_initial_plane_config;
606 struct intel_crtc;
607 struct intel_limit;
608 struct dpll;
609
610 struct drm_i915_display_funcs {
611 int (*get_display_clock_speed)(struct drm_device *dev);
612 int (*get_fifo_size)(struct drm_device *dev, int plane);
613 /**
614 * find_dpll() - Find the best values for the PLL
615 * @limit: limits for the PLL
616 * @crtc: current CRTC
617 * @target: target frequency in kHz
618 * @refclk: reference clock frequency in kHz
619 * @match_clock: if provided, @best_clock P divider must
620 * match the P divider from @match_clock
621 * used for LVDS downclocking
622 * @best_clock: best PLL values found
623 *
624 * Returns true on success, false on failure.
625 */
626 bool (*find_dpll)(const struct intel_limit *limit,
627 struct intel_crtc_state *crtc_state,
628 int target, int refclk,
629 struct dpll *match_clock,
630 struct dpll *best_clock);
631 int (*compute_pipe_wm)(struct intel_crtc *crtc,
632 struct drm_atomic_state *state);
633 void (*update_wm)(struct drm_crtc *crtc);
634 int (*modeset_calc_cdclk)(struct drm_atomic_state *state);
635 void (*modeset_commit_cdclk)(struct drm_atomic_state *state);
636 /* Returns the active state of the crtc, and if the crtc is active,
637 * fills out the pipe-config with the hw state. */
638 bool (*get_pipe_config)(struct intel_crtc *,
639 struct intel_crtc_state *);
640 void (*get_initial_plane_config)(struct intel_crtc *,
641 struct intel_initial_plane_config *);
642 int (*crtc_compute_clock)(struct intel_crtc *crtc,
643 struct intel_crtc_state *crtc_state);
644 void (*crtc_enable)(struct drm_crtc *crtc);
645 void (*crtc_disable)(struct drm_crtc *crtc);
646 void (*audio_codec_enable)(struct drm_connector *connector,
647 struct intel_encoder *encoder,
648 const struct drm_display_mode *adjusted_mode);
649 void (*audio_codec_disable)(struct intel_encoder *encoder);
650 void (*fdi_link_train)(struct drm_crtc *crtc);
651 void (*init_clock_gating)(struct drm_device *dev);
652 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
653 struct drm_framebuffer *fb,
654 struct drm_i915_gem_object *obj,
655 struct drm_i915_gem_request *req,
656 uint32_t flags);
657 void (*update_primary_plane)(struct drm_crtc *crtc,
658 struct drm_framebuffer *fb,
659 int x, int y);
660 void (*hpd_irq_setup)(struct drm_device *dev);
661 /* clock updates for mode set */
662 /* cursor updates */
663 /* render clock increase/decrease */
664 /* display clock increase/decrease */
665 /* pll clock increase/decrease */
666 };
667
668 enum forcewake_domain_id {
669 FW_DOMAIN_ID_RENDER = 0,
670 FW_DOMAIN_ID_BLITTER,
671 FW_DOMAIN_ID_MEDIA,
672
673 FW_DOMAIN_ID_COUNT
674 };
675
676 enum forcewake_domains {
677 FORCEWAKE_RENDER = (1 << FW_DOMAIN_ID_RENDER),
678 FORCEWAKE_BLITTER = (1 << FW_DOMAIN_ID_BLITTER),
679 FORCEWAKE_MEDIA = (1 << FW_DOMAIN_ID_MEDIA),
680 FORCEWAKE_ALL = (FORCEWAKE_RENDER |
681 FORCEWAKE_BLITTER |
682 FORCEWAKE_MEDIA)
683 };
684
685 struct intel_uncore_funcs {
686 void (*force_wake_get)(struct drm_i915_private *dev_priv,
687 enum forcewake_domains domains);
688 void (*force_wake_put)(struct drm_i915_private *dev_priv,
689 enum forcewake_domains domains);
690
691 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
692 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
693 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
694 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, i915_reg_t r, bool trace);
695
696 void (*mmio_writeb)(struct drm_i915_private *dev_priv, i915_reg_t r,
697 uint8_t val, bool trace);
698 void (*mmio_writew)(struct drm_i915_private *dev_priv, i915_reg_t r,
699 uint16_t val, bool trace);
700 void (*mmio_writel)(struct drm_i915_private *dev_priv, i915_reg_t r,
701 uint32_t val, bool trace);
702 void (*mmio_writeq)(struct drm_i915_private *dev_priv, i915_reg_t r,
703 uint64_t val, bool trace);
704 };
705
706 struct intel_uncore {
707 spinlock_t lock; /** lock is also taken in irq contexts. */
708
709 struct intel_uncore_funcs funcs;
710
711 unsigned fifo_count;
712 enum forcewake_domains fw_domains;
713
714 struct intel_uncore_forcewake_domain {
715 struct drm_i915_private *i915;
716 enum forcewake_domain_id id;
717 unsigned wake_count;
718 struct timer_list timer;
719 i915_reg_t reg_set;
720 u32 val_set;
721 u32 val_clear;
722 i915_reg_t reg_ack;
723 i915_reg_t reg_post;
724 u32 val_reset;
725 } fw_domain[FW_DOMAIN_ID_COUNT];
726 };
727
728 /* Iterate over initialised fw domains */
729 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
730 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
731 (i__) < FW_DOMAIN_ID_COUNT; \
732 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
733 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
734
735 #define for_each_fw_domain(domain__, dev_priv__, i__) \
736 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
737
738 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
739 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
740 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
741
742 struct intel_csr {
743 struct work_struct work;
744 const char *fw_path;
745 uint32_t *dmc_payload;
746 uint32_t dmc_fw_size;
747 uint32_t version;
748 uint32_t mmio_count;
749 i915_reg_t mmioaddr[8];
750 uint32_t mmiodata[8];
751 };
752
753 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
754 func(is_mobile) sep \
755 func(is_i85x) sep \
756 func(is_i915g) sep \
757 func(is_i945gm) sep \
758 func(is_g33) sep \
759 func(need_gfx_hws) sep \
760 func(is_g4x) sep \
761 func(is_pineview) sep \
762 func(is_broadwater) sep \
763 func(is_crestline) sep \
764 func(is_ivybridge) sep \
765 func(is_valleyview) sep \
766 func(is_haswell) sep \
767 func(is_skylake) sep \
768 func(is_broxton) sep \
769 func(is_kabylake) sep \
770 func(is_preliminary) sep \
771 func(has_fbc) sep \
772 func(has_pipe_cxsr) sep \
773 func(has_hotplug) sep \
774 func(cursor_needs_physical) sep \
775 func(has_overlay) sep \
776 func(overlay_needs_physical) sep \
777 func(supports_tv) sep \
778 func(has_llc) sep \
779 func(has_ddi) sep \
780 func(has_fpga_dbg)
781
782 #define DEFINE_FLAG(name) u8 name:1
783 #define SEP_SEMICOLON ;
784
785 struct intel_device_info {
786 u32 display_mmio_offset;
787 u16 device_id;
788 u8 num_pipes:3;
789 u8 num_sprites[I915_MAX_PIPES];
790 u8 gen;
791 u8 ring_mask; /* Rings supported by the HW */
792 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
793 /* Register offsets for the various display pipes and transcoders */
794 int pipe_offsets[I915_MAX_TRANSCODERS];
795 int trans_offsets[I915_MAX_TRANSCODERS];
796 int palette_offsets[I915_MAX_PIPES];
797 int cursor_offsets[I915_MAX_PIPES];
798
799 /* Slice/subslice/EU info */
800 u8 slice_total;
801 u8 subslice_total;
802 u8 subslice_per_slice;
803 u8 eu_total;
804 u8 eu_per_subslice;
805 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
806 u8 subslice_7eu[3];
807 u8 has_slice_pg:1;
808 u8 has_subslice_pg:1;
809 u8 has_eu_pg:1;
810 };
811
812 #undef DEFINE_FLAG
813 #undef SEP_SEMICOLON
814
815 enum i915_cache_level {
816 I915_CACHE_NONE = 0,
817 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
818 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
819 caches, eg sampler/render caches, and the
820 large Last-Level-Cache. LLC is coherent with
821 the CPU, but L3 is only visible to the GPU. */
822 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
823 };
824
825 struct i915_ctx_hang_stats {
826 /* This context had batch pending when hang was declared */
827 unsigned batch_pending;
828
829 /* This context had batch active when hang was declared */
830 unsigned batch_active;
831
832 /* Time when this context was last blamed for a GPU reset */
833 unsigned long guilty_ts;
834
835 /* If the contexts causes a second GPU hang within this time,
836 * it is permanently banned from submitting any more work.
837 */
838 unsigned long ban_period_seconds;
839
840 /* This context is banned to submit more work */
841 bool banned;
842 };
843
844 /* This must match up with the value previously used for execbuf2.rsvd1. */
845 #define DEFAULT_CONTEXT_HANDLE 0
846
847 #define CONTEXT_NO_ZEROMAP (1<<0)
848 /**
849 * struct intel_context - as the name implies, represents a context.
850 * @ref: reference count.
851 * @user_handle: userspace tracking identity for this context.
852 * @remap_slice: l3 row remapping information.
853 * @flags: context specific flags:
854 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
855 * @file_priv: filp associated with this context (NULL for global default
856 * context).
857 * @hang_stats: information about the role of this context in possible GPU
858 * hangs.
859 * @ppgtt: virtual memory space used by this context.
860 * @legacy_hw_ctx: render context backing object and whether it is correctly
861 * initialized (legacy ring submission mechanism only).
862 * @link: link in the global list of contexts.
863 *
864 * Contexts are memory images used by the hardware to store copies of their
865 * internal state.
866 */
867 struct intel_context {
868 struct kref ref;
869 int user_handle;
870 uint8_t remap_slice;
871 struct drm_i915_private *i915;
872 int flags;
873 struct drm_i915_file_private *file_priv;
874 struct i915_ctx_hang_stats hang_stats;
875 struct i915_hw_ppgtt *ppgtt;
876
877 /* Legacy ring buffer submission */
878 struct {
879 struct drm_i915_gem_object *rcs_state;
880 bool initialized;
881 } legacy_hw_ctx;
882
883 /* Execlists */
884 struct {
885 struct drm_i915_gem_object *state;
886 struct intel_ringbuffer *ringbuf;
887 int pin_count;
888 } engine[I915_NUM_RINGS];
889
890 struct list_head link;
891 };
892
893 enum fb_op_origin {
894 ORIGIN_GTT,
895 ORIGIN_CPU,
896 ORIGIN_CS,
897 ORIGIN_FLIP,
898 ORIGIN_DIRTYFB,
899 };
900
901 struct i915_fbc {
902 /* This is always the inner lock when overlapping with struct_mutex and
903 * it's the outer lock when overlapping with stolen_lock. */
904 struct mutex lock;
905 unsigned long uncompressed_size;
906 unsigned threshold;
907 unsigned int fb_id;
908 unsigned int possible_framebuffer_bits;
909 unsigned int busy_bits;
910 struct intel_crtc *crtc;
911 int y;
912
913 struct drm_mm_node compressed_fb;
914 struct drm_mm_node *compressed_llb;
915
916 bool false_color;
917
918 bool active;
919
920 struct intel_fbc_work {
921 struct delayed_work work;
922 struct drm_framebuffer *fb;
923 } *fbc_work;
924
925 const char *no_fbc_reason;
926
927 bool (*is_active)(struct drm_i915_private *dev_priv);
928 void (*activate)(struct intel_crtc *crtc);
929 void (*deactivate)(struct drm_i915_private *dev_priv);
930 };
931
932 /**
933 * HIGH_RR is the highest eDP panel refresh rate read from EDID
934 * LOW_RR is the lowest eDP panel refresh rate found from EDID
935 * parsing for same resolution.
936 */
937 enum drrs_refresh_rate_type {
938 DRRS_HIGH_RR,
939 DRRS_LOW_RR,
940 DRRS_MAX_RR, /* RR count */
941 };
942
943 enum drrs_support_type {
944 DRRS_NOT_SUPPORTED = 0,
945 STATIC_DRRS_SUPPORT = 1,
946 SEAMLESS_DRRS_SUPPORT = 2
947 };
948
949 struct intel_dp;
950 struct i915_drrs {
951 struct mutex mutex;
952 struct delayed_work work;
953 struct intel_dp *dp;
954 unsigned busy_frontbuffer_bits;
955 enum drrs_refresh_rate_type refresh_rate_type;
956 enum drrs_support_type type;
957 };
958
959 struct i915_psr {
960 struct mutex lock;
961 bool sink_support;
962 bool source_ok;
963 struct intel_dp *enabled;
964 bool active;
965 struct delayed_work work;
966 unsigned busy_frontbuffer_bits;
967 bool psr2_support;
968 bool aux_frame_sync;
969 };
970
971 enum intel_pch {
972 PCH_NONE = 0, /* No PCH present */
973 PCH_IBX, /* Ibexpeak PCH */
974 PCH_CPT, /* Cougarpoint PCH */
975 PCH_LPT, /* Lynxpoint PCH */
976 PCH_SPT, /* Sunrisepoint PCH */
977 PCH_NOP,
978 };
979
980 enum intel_sbi_destination {
981 SBI_ICLK,
982 SBI_MPHY,
983 };
984
985 #define QUIRK_PIPEA_FORCE (1<<0)
986 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
987 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
988 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
989 #define QUIRK_PIPEB_FORCE (1<<4)
990 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
991
992 struct intel_fbdev;
993 struct intel_fbc_work;
994
995 struct intel_gmbus {
996 struct i2c_adapter adapter;
997 u32 force_bit;
998 u32 reg0;
999 i915_reg_t gpio_reg;
1000 struct i2c_algo_bit_data bit_algo;
1001 struct drm_i915_private *dev_priv;
1002 };
1003
1004 struct i915_suspend_saved_registers {
1005 u32 saveDSPARB;
1006 u32 saveLVDS;
1007 u32 savePP_ON_DELAYS;
1008 u32 savePP_OFF_DELAYS;
1009 u32 savePP_ON;
1010 u32 savePP_OFF;
1011 u32 savePP_CONTROL;
1012 u32 savePP_DIVISOR;
1013 u32 saveFBC_CONTROL;
1014 u32 saveCACHE_MODE_0;
1015 u32 saveMI_ARB_STATE;
1016 u32 saveSWF0[16];
1017 u32 saveSWF1[16];
1018 u32 saveSWF3[3];
1019 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
1020 u32 savePCH_PORT_HOTPLUG;
1021 u16 saveGCDGMBUS;
1022 };
1023
1024 struct vlv_s0ix_state {
1025 /* GAM */
1026 u32 wr_watermark;
1027 u32 gfx_prio_ctrl;
1028 u32 arb_mode;
1029 u32 gfx_pend_tlb0;
1030 u32 gfx_pend_tlb1;
1031 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
1032 u32 media_max_req_count;
1033 u32 gfx_max_req_count;
1034 u32 render_hwsp;
1035 u32 ecochk;
1036 u32 bsd_hwsp;
1037 u32 blt_hwsp;
1038 u32 tlb_rd_addr;
1039
1040 /* MBC */
1041 u32 g3dctl;
1042 u32 gsckgctl;
1043 u32 mbctl;
1044
1045 /* GCP */
1046 u32 ucgctl1;
1047 u32 ucgctl3;
1048 u32 rcgctl1;
1049 u32 rcgctl2;
1050 u32 rstctl;
1051 u32 misccpctl;
1052
1053 /* GPM */
1054 u32 gfxpause;
1055 u32 rpdeuhwtc;
1056 u32 rpdeuc;
1057 u32 ecobus;
1058 u32 pwrdwnupctl;
1059 u32 rp_down_timeout;
1060 u32 rp_deucsw;
1061 u32 rcubmabdtmr;
1062 u32 rcedata;
1063 u32 spare2gh;
1064
1065 /* Display 1 CZ domain */
1066 u32 gt_imr;
1067 u32 gt_ier;
1068 u32 pm_imr;
1069 u32 pm_ier;
1070 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
1071
1072 /* GT SA CZ domain */
1073 u32 tilectl;
1074 u32 gt_fifoctl;
1075 u32 gtlc_wake_ctrl;
1076 u32 gtlc_survive;
1077 u32 pmwgicz;
1078
1079 /* Display 2 CZ domain */
1080 u32 gu_ctl0;
1081 u32 gu_ctl1;
1082 u32 pcbr;
1083 u32 clock_gate_dis2;
1084 };
1085
1086 struct intel_rps_ei {
1087 u32 cz_clock;
1088 u32 render_c0;
1089 u32 media_c0;
1090 };
1091
1092 struct intel_gen6_power_mgmt {
1093 /*
1094 * work, interrupts_enabled and pm_iir are protected by
1095 * dev_priv->irq_lock
1096 */
1097 struct work_struct work;
1098 bool interrupts_enabled;
1099 u32 pm_iir;
1100
1101 /* Frequencies are stored in potentially platform dependent multiples.
1102 * In other words, *_freq needs to be multiplied by X to be interesting.
1103 * Soft limits are those which are used for the dynamic reclocking done
1104 * by the driver (raise frequencies under heavy loads, and lower for
1105 * lighter loads). Hard limits are those imposed by the hardware.
1106 *
1107 * A distinction is made for overclocking, which is never enabled by
1108 * default, and is considered to be above the hard limit if it's
1109 * possible at all.
1110 */
1111 u8 cur_freq; /* Current frequency (cached, may not == HW) */
1112 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
1113 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
1114 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
1115 u8 min_freq; /* AKA RPn. Minimum frequency */
1116 u8 idle_freq; /* Frequency to request when we are idle */
1117 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
1118 u8 rp1_freq; /* "less than" RP0 power/freqency */
1119 u8 rp0_freq; /* Non-overclocked max frequency. */
1120
1121 u8 up_threshold; /* Current %busy required to uplock */
1122 u8 down_threshold; /* Current %busy required to downclock */
1123
1124 int last_adj;
1125 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1126
1127 spinlock_t client_lock;
1128 struct list_head clients;
1129 bool client_boost;
1130
1131 bool enabled;
1132 struct delayed_work delayed_resume_work;
1133 unsigned boosts;
1134
1135 struct intel_rps_client semaphores, mmioflips;
1136
1137 /* manual wa residency calculations */
1138 struct intel_rps_ei up_ei, down_ei;
1139
1140 /*
1141 * Protects RPS/RC6 register access and PCU communication.
1142 * Must be taken after struct_mutex if nested. Note that
1143 * this lock may be held for long periods of time when
1144 * talking to hw - so only take it when talking to hw!
1145 */
1146 struct mutex hw_lock;
1147 };
1148
1149 /* defined intel_pm.c */
1150 extern spinlock_t mchdev_lock;
1151
1152 struct intel_ilk_power_mgmt {
1153 u8 cur_delay;
1154 u8 min_delay;
1155 u8 max_delay;
1156 u8 fmax;
1157 u8 fstart;
1158
1159 u64 last_count1;
1160 unsigned long last_time1;
1161 unsigned long chipset_power;
1162 u64 last_count2;
1163 u64 last_time2;
1164 unsigned long gfx_power;
1165 u8 corr;
1166
1167 int c_m;
1168 int r_t;
1169 };
1170
1171 struct drm_i915_private;
1172 struct i915_power_well;
1173
1174 struct i915_power_well_ops {
1175 /*
1176 * Synchronize the well's hw state to match the current sw state, for
1177 * example enable/disable it based on the current refcount. Called
1178 * during driver init and resume time, possibly after first calling
1179 * the enable/disable handlers.
1180 */
1181 void (*sync_hw)(struct drm_i915_private *dev_priv,
1182 struct i915_power_well *power_well);
1183 /*
1184 * Enable the well and resources that depend on it (for example
1185 * interrupts located on the well). Called after the 0->1 refcount
1186 * transition.
1187 */
1188 void (*enable)(struct drm_i915_private *dev_priv,
1189 struct i915_power_well *power_well);
1190 /*
1191 * Disable the well and resources that depend on it. Called after
1192 * the 1->0 refcount transition.
1193 */
1194 void (*disable)(struct drm_i915_private *dev_priv,
1195 struct i915_power_well *power_well);
1196 /* Returns the hw enabled state. */
1197 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1198 struct i915_power_well *power_well);
1199 };
1200
1201 /* Power well structure for haswell */
1202 struct i915_power_well {
1203 const char *name;
1204 bool always_on;
1205 /* power well enable/disable usage count */
1206 int count;
1207 /* cached hw enabled state */
1208 bool hw_enabled;
1209 unsigned long domains;
1210 unsigned long data;
1211 const struct i915_power_well_ops *ops;
1212 };
1213
1214 struct i915_power_domains {
1215 /*
1216 * Power wells needed for initialization at driver init and suspend
1217 * time are on. They are kept on until after the first modeset.
1218 */
1219 bool init_power_on;
1220 bool initializing;
1221 int power_well_count;
1222
1223 struct mutex lock;
1224 int domain_use_count[POWER_DOMAIN_NUM];
1225 struct i915_power_well *power_wells;
1226 };
1227
1228 #define MAX_L3_SLICES 2
1229 struct intel_l3_parity {
1230 u32 *remap_info[MAX_L3_SLICES];
1231 struct work_struct error_work;
1232 int which_slice;
1233 };
1234
1235 struct i915_gem_mm {
1236 /** Memory allocator for GTT stolen memory */
1237 struct drm_mm stolen;
1238 /** Protects the usage of the GTT stolen memory allocator. This is
1239 * always the inner lock when overlapping with struct_mutex. */
1240 struct mutex stolen_lock;
1241
1242 /** List of all objects in gtt_space. Used to restore gtt
1243 * mappings on resume */
1244 struct list_head bound_list;
1245 /**
1246 * List of objects which are not bound to the GTT (thus
1247 * are idle and not used by the GPU) but still have
1248 * (presumably uncached) pages still attached.
1249 */
1250 struct list_head unbound_list;
1251
1252 /** Usable portion of the GTT for GEM */
1253 unsigned long stolen_base; /* limited to low memory (32-bit) */
1254
1255 /** PPGTT used for aliasing the PPGTT with the GTT */
1256 struct i915_hw_ppgtt *aliasing_ppgtt;
1257
1258 struct notifier_block oom_notifier;
1259 struct shrinker shrinker;
1260 bool shrinker_no_lock_stealing;
1261
1262 /** LRU list of objects with fence regs on them. */
1263 struct list_head fence_list;
1264
1265 /**
1266 * We leave the user IRQ off as much as possible,
1267 * but this means that requests will finish and never
1268 * be retired once the system goes idle. Set a timer to
1269 * fire periodically while the ring is running. When it
1270 * fires, go retire requests.
1271 */
1272 struct delayed_work retire_work;
1273
1274 /**
1275 * When we detect an idle GPU, we want to turn on
1276 * powersaving features. So once we see that there
1277 * are no more requests outstanding and no more
1278 * arrive within a small period of time, we fire
1279 * off the idle_work.
1280 */
1281 struct delayed_work idle_work;
1282
1283 /**
1284 * Are we in a non-interruptible section of code like
1285 * modesetting?
1286 */
1287 bool interruptible;
1288
1289 /**
1290 * Is the GPU currently considered idle, or busy executing userspace
1291 * requests? Whilst idle, we attempt to power down the hardware and
1292 * display clocks. In order to reduce the effect on performance, there
1293 * is a slight delay before we do so.
1294 */
1295 bool busy;
1296
1297 /* the indicator for dispatch video commands on two BSD rings */
1298 int bsd_ring_dispatch_index;
1299
1300 /** Bit 6 swizzling required for X tiling */
1301 uint32_t bit_6_swizzle_x;
1302 /** Bit 6 swizzling required for Y tiling */
1303 uint32_t bit_6_swizzle_y;
1304
1305 /* accounting, useful for userland debugging */
1306 spinlock_t object_stat_lock;
1307 size_t object_memory;
1308 u32 object_count;
1309 };
1310
1311 struct drm_i915_error_state_buf {
1312 struct drm_i915_private *i915;
1313 unsigned bytes;
1314 unsigned size;
1315 int err;
1316 u8 *buf;
1317 loff_t start;
1318 loff_t pos;
1319 };
1320
1321 struct i915_error_state_file_priv {
1322 struct drm_device *dev;
1323 struct drm_i915_error_state *error;
1324 };
1325
1326 struct i915_gpu_error {
1327 /* For hangcheck timer */
1328 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1329 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1330 /* Hang gpu twice in this window and your context gets banned */
1331 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1332
1333 struct workqueue_struct *hangcheck_wq;
1334 struct delayed_work hangcheck_work;
1335
1336 /* For reset and error_state handling. */
1337 spinlock_t lock;
1338 /* Protected by the above dev->gpu_error.lock. */
1339 struct drm_i915_error_state *first_error;
1340
1341 unsigned long missed_irq_rings;
1342
1343 /**
1344 * State variable controlling the reset flow and count
1345 *
1346 * This is a counter which gets incremented when reset is triggered,
1347 * and again when reset has been handled. So odd values (lowest bit set)
1348 * means that reset is in progress and even values that
1349 * (reset_counter >> 1):th reset was successfully completed.
1350 *
1351 * If reset is not completed succesfully, the I915_WEDGE bit is
1352 * set meaning that hardware is terminally sour and there is no
1353 * recovery. All waiters on the reset_queue will be woken when
1354 * that happens.
1355 *
1356 * This counter is used by the wait_seqno code to notice that reset
1357 * event happened and it needs to restart the entire ioctl (since most
1358 * likely the seqno it waited for won't ever signal anytime soon).
1359 *
1360 * This is important for lock-free wait paths, where no contended lock
1361 * naturally enforces the correct ordering between the bail-out of the
1362 * waiter and the gpu reset work code.
1363 */
1364 atomic_t reset_counter;
1365
1366 #define I915_RESET_IN_PROGRESS_FLAG 1
1367 #define I915_WEDGED (1 << 31)
1368
1369 /**
1370 * Waitqueue to signal when the reset has completed. Used by clients
1371 * that wait for dev_priv->mm.wedged to settle.
1372 */
1373 wait_queue_head_t reset_queue;
1374
1375 /* Userspace knobs for gpu hang simulation;
1376 * combines both a ring mask, and extra flags
1377 */
1378 u32 stop_rings;
1379 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1380 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1381
1382 /* For missed irq/seqno simulation. */
1383 unsigned int test_irq_rings;
1384
1385 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1386 bool reload_in_reset;
1387 };
1388
1389 enum modeset_restore {
1390 MODESET_ON_LID_OPEN,
1391 MODESET_DONE,
1392 MODESET_SUSPENDED,
1393 };
1394
1395 #define DP_AUX_A 0x40
1396 #define DP_AUX_B 0x10
1397 #define DP_AUX_C 0x20
1398 #define DP_AUX_D 0x30
1399
1400 #define DDC_PIN_B 0x05
1401 #define DDC_PIN_C 0x04
1402 #define DDC_PIN_D 0x06
1403
1404 struct ddi_vbt_port_info {
1405 /*
1406 * This is an index in the HDMI/DVI DDI buffer translation table.
1407 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1408 * populate this field.
1409 */
1410 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1411 uint8_t hdmi_level_shift;
1412
1413 uint8_t supports_dvi:1;
1414 uint8_t supports_hdmi:1;
1415 uint8_t supports_dp:1;
1416
1417 uint8_t alternate_aux_channel;
1418 uint8_t alternate_ddc_pin;
1419
1420 uint8_t dp_boost_level;
1421 uint8_t hdmi_boost_level;
1422 };
1423
1424 enum psr_lines_to_wait {
1425 PSR_0_LINES_TO_WAIT = 0,
1426 PSR_1_LINE_TO_WAIT,
1427 PSR_4_LINES_TO_WAIT,
1428 PSR_8_LINES_TO_WAIT
1429 };
1430
1431 struct intel_vbt_data {
1432 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1433 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1434
1435 /* Feature bits */
1436 unsigned int int_tv_support:1;
1437 unsigned int lvds_dither:1;
1438 unsigned int lvds_vbt:1;
1439 unsigned int int_crt_support:1;
1440 unsigned int lvds_use_ssc:1;
1441 unsigned int display_clock_mode:1;
1442 unsigned int fdi_rx_polarity_inverted:1;
1443 unsigned int has_mipi:1;
1444 int lvds_ssc_freq;
1445 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1446
1447 enum drrs_support_type drrs_type;
1448
1449 /* eDP */
1450 int edp_rate;
1451 int edp_lanes;
1452 int edp_preemphasis;
1453 int edp_vswing;
1454 bool edp_initialized;
1455 bool edp_support;
1456 int edp_bpp;
1457 struct edp_power_seq edp_pps;
1458
1459 struct {
1460 bool full_link;
1461 bool require_aux_wakeup;
1462 int idle_frames;
1463 enum psr_lines_to_wait lines_to_wait;
1464 int tp1_wakeup_time;
1465 int tp2_tp3_wakeup_time;
1466 } psr;
1467
1468 struct {
1469 u16 pwm_freq_hz;
1470 bool present;
1471 bool active_low_pwm;
1472 u8 min_brightness; /* min_brightness/255 of max */
1473 } backlight;
1474
1475 /* MIPI DSI */
1476 struct {
1477 u16 port;
1478 u16 panel_id;
1479 struct mipi_config *config;
1480 struct mipi_pps_data *pps;
1481 u8 seq_version;
1482 u32 size;
1483 u8 *data;
1484 u8 *sequence[MIPI_SEQ_MAX];
1485 } dsi;
1486
1487 int crt_ddc_pin;
1488
1489 int child_dev_num;
1490 union child_device_config *child_dev;
1491
1492 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1493 };
1494
1495 enum intel_ddb_partitioning {
1496 INTEL_DDB_PART_1_2,
1497 INTEL_DDB_PART_5_6, /* IVB+ */
1498 };
1499
1500 struct intel_wm_level {
1501 bool enable;
1502 uint32_t pri_val;
1503 uint32_t spr_val;
1504 uint32_t cur_val;
1505 uint32_t fbc_val;
1506 };
1507
1508 struct ilk_wm_values {
1509 uint32_t wm_pipe[3];
1510 uint32_t wm_lp[3];
1511 uint32_t wm_lp_spr[3];
1512 uint32_t wm_linetime[3];
1513 bool enable_fbc_wm;
1514 enum intel_ddb_partitioning partitioning;
1515 };
1516
1517 struct vlv_pipe_wm {
1518 uint16_t primary;
1519 uint16_t sprite[2];
1520 uint8_t cursor;
1521 };
1522
1523 struct vlv_sr_wm {
1524 uint16_t plane;
1525 uint8_t cursor;
1526 };
1527
1528 struct vlv_wm_values {
1529 struct vlv_pipe_wm pipe[3];
1530 struct vlv_sr_wm sr;
1531 struct {
1532 uint8_t cursor;
1533 uint8_t sprite[2];
1534 uint8_t primary;
1535 } ddl[3];
1536 uint8_t level;
1537 bool cxsr;
1538 };
1539
1540 struct skl_ddb_entry {
1541 uint16_t start, end; /* in number of blocks, 'end' is exclusive */
1542 };
1543
1544 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry *entry)
1545 {
1546 return entry->end - entry->start;
1547 }
1548
1549 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
1550 const struct skl_ddb_entry *e2)
1551 {
1552 if (e1->start == e2->start && e1->end == e2->end)
1553 return true;
1554
1555 return false;
1556 }
1557
1558 struct skl_ddb_allocation {
1559 struct skl_ddb_entry pipe[I915_MAX_PIPES];
1560 struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
1561 struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
1562 };
1563
1564 struct skl_wm_values {
1565 bool dirty[I915_MAX_PIPES];
1566 struct skl_ddb_allocation ddb;
1567 uint32_t wm_linetime[I915_MAX_PIPES];
1568 uint32_t plane[I915_MAX_PIPES][I915_MAX_PLANES][8];
1569 uint32_t plane_trans[I915_MAX_PIPES][I915_MAX_PLANES];
1570 };
1571
1572 struct skl_wm_level {
1573 bool plane_en[I915_MAX_PLANES];
1574 uint16_t plane_res_b[I915_MAX_PLANES];
1575 uint8_t plane_res_l[I915_MAX_PLANES];
1576 };
1577
1578 /*
1579 * This struct helps tracking the state needed for runtime PM, which puts the
1580 * device in PCI D3 state. Notice that when this happens, nothing on the
1581 * graphics device works, even register access, so we don't get interrupts nor
1582 * anything else.
1583 *
1584 * Every piece of our code that needs to actually touch the hardware needs to
1585 * either call intel_runtime_pm_get or call intel_display_power_get with the
1586 * appropriate power domain.
1587 *
1588 * Our driver uses the autosuspend delay feature, which means we'll only really
1589 * suspend if we stay with zero refcount for a certain amount of time. The
1590 * default value is currently very conservative (see intel_runtime_pm_enable), but
1591 * it can be changed with the standard runtime PM files from sysfs.
1592 *
1593 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1594 * goes back to false exactly before we reenable the IRQs. We use this variable
1595 * to check if someone is trying to enable/disable IRQs while they're supposed
1596 * to be disabled. This shouldn't happen and we'll print some error messages in
1597 * case it happens.
1598 *
1599 * For more, read the Documentation/power/runtime_pm.txt.
1600 */
1601 struct i915_runtime_pm {
1602 bool suspended;
1603 bool irqs_enabled;
1604 };
1605
1606 enum intel_pipe_crc_source {
1607 INTEL_PIPE_CRC_SOURCE_NONE,
1608 INTEL_PIPE_CRC_SOURCE_PLANE1,
1609 INTEL_PIPE_CRC_SOURCE_PLANE2,
1610 INTEL_PIPE_CRC_SOURCE_PF,
1611 INTEL_PIPE_CRC_SOURCE_PIPE,
1612 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1613 INTEL_PIPE_CRC_SOURCE_TV,
1614 INTEL_PIPE_CRC_SOURCE_DP_B,
1615 INTEL_PIPE_CRC_SOURCE_DP_C,
1616 INTEL_PIPE_CRC_SOURCE_DP_D,
1617 INTEL_PIPE_CRC_SOURCE_AUTO,
1618 INTEL_PIPE_CRC_SOURCE_MAX,
1619 };
1620
1621 struct intel_pipe_crc_entry {
1622 uint32_t frame;
1623 uint32_t crc[5];
1624 };
1625
1626 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1627 struct intel_pipe_crc {
1628 spinlock_t lock;
1629 bool opened; /* exclusive access to the result file */
1630 struct intel_pipe_crc_entry *entries;
1631 enum intel_pipe_crc_source source;
1632 int head, tail;
1633 wait_queue_head_t wq;
1634 };
1635
1636 struct i915_frontbuffer_tracking {
1637 struct mutex lock;
1638
1639 /*
1640 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1641 * scheduled flips.
1642 */
1643 unsigned busy_bits;
1644 unsigned flip_bits;
1645 };
1646
1647 struct i915_wa_reg {
1648 i915_reg_t addr;
1649 u32 value;
1650 /* bitmask representing WA bits */
1651 u32 mask;
1652 };
1653
1654 #define I915_MAX_WA_REGS 16
1655
1656 struct i915_workarounds {
1657 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1658 u32 count;
1659 };
1660
1661 struct i915_virtual_gpu {
1662 bool active;
1663 };
1664
1665 struct i915_execbuffer_params {
1666 struct drm_device *dev;
1667 struct drm_file *file;
1668 uint32_t dispatch_flags;
1669 uint32_t args_batch_start_offset;
1670 uint64_t batch_obj_vm_offset;
1671 struct intel_engine_cs *ring;
1672 struct drm_i915_gem_object *batch_obj;
1673 struct intel_context *ctx;
1674 struct drm_i915_gem_request *request;
1675 };
1676
1677 /* used in computing the new watermarks state */
1678 struct intel_wm_config {
1679 unsigned int num_pipes_active;
1680 bool sprites_enabled;
1681 bool sprites_scaled;
1682 };
1683
1684 struct drm_i915_private {
1685 struct drm_device *dev;
1686 struct kmem_cache *objects;
1687 struct kmem_cache *vmas;
1688 struct kmem_cache *requests;
1689
1690 const struct intel_device_info info;
1691
1692 int relative_constants_mode;
1693
1694 void __iomem *regs;
1695
1696 struct intel_uncore uncore;
1697
1698 struct i915_virtual_gpu vgpu;
1699
1700 struct intel_guc guc;
1701
1702 struct intel_csr csr;
1703
1704 struct intel_gmbus gmbus[GMBUS_NUM_PINS];
1705
1706 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1707 * controller on different i2c buses. */
1708 struct mutex gmbus_mutex;
1709
1710 /**
1711 * Base address of the gmbus and gpio block.
1712 */
1713 uint32_t gpio_mmio_base;
1714
1715 /* MMIO base address for MIPI regs */
1716 uint32_t mipi_mmio_base;
1717
1718 uint32_t psr_mmio_base;
1719
1720 wait_queue_head_t gmbus_wait_queue;
1721
1722 struct pci_dev *bridge_dev;
1723 struct intel_engine_cs ring[I915_NUM_RINGS];
1724 struct drm_i915_gem_object *semaphore_obj;
1725 uint32_t last_seqno, next_seqno;
1726
1727 struct drm_dma_handle *status_page_dmah;
1728 struct resource mch_res;
1729
1730 /* protects the irq masks */
1731 spinlock_t irq_lock;
1732
1733 /* protects the mmio flip data */
1734 spinlock_t mmio_flip_lock;
1735
1736 bool display_irqs_enabled;
1737
1738 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1739 struct pm_qos_request pm_qos;
1740
1741 /* Sideband mailbox protection */
1742 struct mutex sb_lock;
1743
1744 /** Cached value of IMR to avoid reads in updating the bitfield */
1745 union {
1746 u32 irq_mask;
1747 u32 de_irq_mask[I915_MAX_PIPES];
1748 };
1749 u32 gt_irq_mask;
1750 u32 pm_irq_mask;
1751 u32 pm_rps_events;
1752 u32 pipestat_irq_mask[I915_MAX_PIPES];
1753
1754 struct i915_hotplug hotplug;
1755 struct i915_fbc fbc;
1756 struct i915_drrs drrs;
1757 struct intel_opregion opregion;
1758 struct intel_vbt_data vbt;
1759
1760 bool preserve_bios_swizzle;
1761
1762 /* overlay */
1763 struct intel_overlay *overlay;
1764
1765 /* backlight registers and fields in struct intel_panel */
1766 struct mutex backlight_lock;
1767
1768 /* LVDS info */
1769 bool no_aux_handshake;
1770
1771 /* protects panel power sequencer state */
1772 struct mutex pps_mutex;
1773
1774 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1775 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1776
1777 unsigned int fsb_freq, mem_freq, is_ddr3;
1778 unsigned int skl_boot_cdclk;
1779 unsigned int cdclk_freq, max_cdclk_freq;
1780 unsigned int max_dotclk_freq;
1781 unsigned int hpll_freq;
1782 unsigned int czclk_freq;
1783
1784 /**
1785 * wq - Driver workqueue for GEM.
1786 *
1787 * NOTE: Work items scheduled here are not allowed to grab any modeset
1788 * locks, for otherwise the flushing done in the pageflip code will
1789 * result in deadlocks.
1790 */
1791 struct workqueue_struct *wq;
1792
1793 /* Display functions */
1794 struct drm_i915_display_funcs display;
1795
1796 /* PCH chipset type */
1797 enum intel_pch pch_type;
1798 unsigned short pch_id;
1799
1800 unsigned long quirks;
1801
1802 enum modeset_restore modeset_restore;
1803 struct mutex modeset_restore_lock;
1804
1805 struct list_head vm_list; /* Global list of all address spaces */
1806 struct i915_gtt gtt; /* VM representing the global address space */
1807
1808 struct i915_gem_mm mm;
1809 DECLARE_HASHTABLE(mm_structs, 7);
1810 struct mutex mm_lock;
1811
1812 /* Kernel Modesetting */
1813
1814 struct sdvo_device_mapping sdvo_mappings[2];
1815
1816 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1817 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1818 wait_queue_head_t pending_flip_queue;
1819
1820 #ifdef CONFIG_DEBUG_FS
1821 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1822 #endif
1823
1824 int num_shared_dpll;
1825 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1826 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1827
1828 struct i915_workarounds workarounds;
1829
1830 /* Reclocking support */
1831 bool render_reclock_avail;
1832
1833 struct i915_frontbuffer_tracking fb_tracking;
1834
1835 u16 orig_clock;
1836
1837 bool mchbar_need_disable;
1838
1839 struct intel_l3_parity l3_parity;
1840
1841 /* Cannot be determined by PCIID. You must always read a register. */
1842 size_t ellc_size;
1843
1844 /* gen6+ rps state */
1845 struct intel_gen6_power_mgmt rps;
1846
1847 /* ilk-only ips/rps state. Everything in here is protected by the global
1848 * mchdev_lock in intel_pm.c */
1849 struct intel_ilk_power_mgmt ips;
1850
1851 struct i915_power_domains power_domains;
1852
1853 struct i915_psr psr;
1854
1855 struct i915_gpu_error gpu_error;
1856
1857 struct drm_i915_gem_object *vlv_pctx;
1858
1859 #ifdef CONFIG_DRM_FBDEV_EMULATION
1860 /* list of fbdev register on this device */
1861 struct intel_fbdev *fbdev;
1862 struct work_struct fbdev_suspend_work;
1863 #endif
1864
1865 struct drm_property *broadcast_rgb_property;
1866 struct drm_property *force_audio_property;
1867
1868 /* hda/i915 audio component */
1869 struct i915_audio_component *audio_component;
1870 bool audio_component_registered;
1871 /**
1872 * av_mutex - mutex for audio/video sync
1873 *
1874 */
1875 struct mutex av_mutex;
1876
1877 uint32_t hw_context_size;
1878 struct list_head context_list;
1879
1880 u32 fdi_rx_config;
1881
1882 u32 chv_phy_control;
1883
1884 u32 suspend_count;
1885 bool suspended_to_idle;
1886 struct i915_suspend_saved_registers regfile;
1887 struct vlv_s0ix_state vlv_s0ix_state;
1888
1889 struct {
1890 /*
1891 * Raw watermark latency values:
1892 * in 0.1us units for WM0,
1893 * in 0.5us units for WM1+.
1894 */
1895 /* primary */
1896 uint16_t pri_latency[5];
1897 /* sprite */
1898 uint16_t spr_latency[5];
1899 /* cursor */
1900 uint16_t cur_latency[5];
1901 /*
1902 * Raw watermark memory latency values
1903 * for SKL for all 8 levels
1904 * in 1us units.
1905 */
1906 uint16_t skl_latency[8];
1907
1908 /* Committed wm config */
1909 struct intel_wm_config config;
1910
1911 /*
1912 * The skl_wm_values structure is a bit too big for stack
1913 * allocation, so we keep the staging struct where we store
1914 * intermediate results here instead.
1915 */
1916 struct skl_wm_values skl_results;
1917
1918 /* current hardware state */
1919 union {
1920 struct ilk_wm_values hw;
1921 struct skl_wm_values skl_hw;
1922 struct vlv_wm_values vlv;
1923 };
1924
1925 uint8_t max_level;
1926 } wm;
1927
1928 struct i915_runtime_pm pm;
1929
1930 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1931 struct {
1932 int (*execbuf_submit)(struct i915_execbuffer_params *params,
1933 struct drm_i915_gem_execbuffer2 *args,
1934 struct list_head *vmas);
1935 int (*init_rings)(struct drm_device *dev);
1936 void (*cleanup_ring)(struct intel_engine_cs *ring);
1937 void (*stop_ring)(struct intel_engine_cs *ring);
1938 } gt;
1939
1940 bool edp_low_vswing;
1941
1942 /* perform PHY state sanity checks? */
1943 bool chv_phy_assert[2];
1944
1945 /*
1946 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1947 * will be rejected. Instead look for a better place.
1948 */
1949 };
1950
1951 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1952 {
1953 return dev->dev_private;
1954 }
1955
1956 static inline struct drm_i915_private *dev_to_i915(struct device *dev)
1957 {
1958 return to_i915(dev_get_drvdata(dev));
1959 }
1960
1961 static inline struct drm_i915_private *guc_to_i915(struct intel_guc *guc)
1962 {
1963 return container_of(guc, struct drm_i915_private, guc);
1964 }
1965
1966 /* Iterate over initialised rings */
1967 #define for_each_ring(ring__, dev_priv__, i__) \
1968 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1969 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1970
1971 enum hdmi_force_audio {
1972 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1973 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1974 HDMI_AUDIO_AUTO, /* trust EDID */
1975 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1976 };
1977
1978 #define I915_GTT_OFFSET_NONE ((u32)-1)
1979
1980 struct drm_i915_gem_object_ops {
1981 /* Interface between the GEM object and its backing storage.
1982 * get_pages() is called once prior to the use of the associated set
1983 * of pages before to binding them into the GTT, and put_pages() is
1984 * called after we no longer need them. As we expect there to be
1985 * associated cost with migrating pages between the backing storage
1986 * and making them available for the GPU (e.g. clflush), we may hold
1987 * onto the pages after they are no longer referenced by the GPU
1988 * in case they may be used again shortly (for example migrating the
1989 * pages to a different memory domain within the GTT). put_pages()
1990 * will therefore most likely be called when the object itself is
1991 * being released or under memory pressure (where we attempt to
1992 * reap pages for the shrinker).
1993 */
1994 int (*get_pages)(struct drm_i915_gem_object *);
1995 void (*put_pages)(struct drm_i915_gem_object *);
1996 int (*dmabuf_export)(struct drm_i915_gem_object *);
1997 void (*release)(struct drm_i915_gem_object *);
1998 };
1999
2000 /*
2001 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2002 * considered to be the frontbuffer for the given plane interface-wise. This
2003 * doesn't mean that the hw necessarily already scans it out, but that any
2004 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2005 *
2006 * We have one bit per pipe and per scanout plane type.
2007 */
2008 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2009 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2010 #define INTEL_FRONTBUFFER_BITS \
2011 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2012 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2013 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2014 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2015 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2016 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2017 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2018 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2019 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2020 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2021 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2022
2023 struct drm_i915_gem_object {
2024 struct drm_gem_object base;
2025
2026 const struct drm_i915_gem_object_ops *ops;
2027
2028 /** List of VMAs backed by this object */
2029 struct list_head vma_list;
2030
2031 /** Stolen memory for this object, instead of being backed by shmem. */
2032 struct drm_mm_node *stolen;
2033 struct list_head global_list;
2034
2035 struct list_head ring_list[I915_NUM_RINGS];
2036 /** Used in execbuf to temporarily hold a ref */
2037 struct list_head obj_exec_link;
2038
2039 struct list_head batch_pool_link;
2040
2041 /**
2042 * This is set if the object is on the active lists (has pending
2043 * rendering and so a non-zero seqno), and is not set if it i s on
2044 * inactive (ready to be unbound) list.
2045 */
2046 unsigned int active:I915_NUM_RINGS;
2047
2048 /**
2049 * This is set if the object has been written to since last bound
2050 * to the GTT
2051 */
2052 unsigned int dirty:1;
2053
2054 /**
2055 * Fence register bits (if any) for this object. Will be set
2056 * as needed when mapped into the GTT.
2057 * Protected by dev->struct_mutex.
2058 */
2059 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
2060
2061 /**
2062 * Advice: are the backing pages purgeable?
2063 */
2064 unsigned int madv:2;
2065
2066 /**
2067 * Current tiling mode for the object.
2068 */
2069 unsigned int tiling_mode:2;
2070 /**
2071 * Whether the tiling parameters for the currently associated fence
2072 * register have changed. Note that for the purposes of tracking
2073 * tiling changes we also treat the unfenced register, the register
2074 * slot that the object occupies whilst it executes a fenced
2075 * command (such as BLT on gen2/3), as a "fence".
2076 */
2077 unsigned int fence_dirty:1;
2078
2079 /**
2080 * Is the object at the current location in the gtt mappable and
2081 * fenceable? Used to avoid costly recalculations.
2082 */
2083 unsigned int map_and_fenceable:1;
2084
2085 /**
2086 * Whether the current gtt mapping needs to be mappable (and isn't just
2087 * mappable by accident). Track pin and fault separate for a more
2088 * accurate mappable working set.
2089 */
2090 unsigned int fault_mappable:1;
2091
2092 /*
2093 * Is the object to be mapped as read-only to the GPU
2094 * Only honoured if hardware has relevant pte bit
2095 */
2096 unsigned long gt_ro:1;
2097 unsigned int cache_level:3;
2098 unsigned int cache_dirty:1;
2099
2100 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
2101
2102 unsigned int pin_display;
2103
2104 struct sg_table *pages;
2105 int pages_pin_count;
2106 struct get_page {
2107 struct scatterlist *sg;
2108 int last;
2109 } get_page;
2110
2111 /* prime dma-buf support */
2112 void *dma_buf_vmapping;
2113 int vmapping_count;
2114
2115 /** Breadcrumb of last rendering to the buffer.
2116 * There can only be one writer, but we allow for multiple readers.
2117 * If there is a writer that necessarily implies that all other
2118 * read requests are complete - but we may only be lazily clearing
2119 * the read requests. A read request is naturally the most recent
2120 * request on a ring, so we may have two different write and read
2121 * requests on one ring where the write request is older than the
2122 * read request. This allows for the CPU to read from an active
2123 * buffer by only waiting for the write to complete.
2124 * */
2125 struct drm_i915_gem_request *last_read_req[I915_NUM_RINGS];
2126 struct drm_i915_gem_request *last_write_req;
2127 /** Breadcrumb of last fenced GPU access to the buffer. */
2128 struct drm_i915_gem_request *last_fenced_req;
2129
2130 /** Current tiling stride for the object, if it's tiled. */
2131 uint32_t stride;
2132
2133 /** References from framebuffers, locks out tiling changes. */
2134 unsigned long framebuffer_references;
2135
2136 /** Record of address bit 17 of each page at last unbind. */
2137 unsigned long *bit_17;
2138
2139 union {
2140 /** for phy allocated objects */
2141 struct drm_dma_handle *phys_handle;
2142
2143 struct i915_gem_userptr {
2144 uintptr_t ptr;
2145 unsigned read_only :1;
2146 unsigned workers :4;
2147 #define I915_GEM_USERPTR_MAX_WORKERS 15
2148
2149 struct i915_mm_struct *mm;
2150 struct i915_mmu_object *mmu_object;
2151 struct work_struct *work;
2152 } userptr;
2153 };
2154 };
2155 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2156
2157 void i915_gem_track_fb(struct drm_i915_gem_object *old,
2158 struct drm_i915_gem_object *new,
2159 unsigned frontbuffer_bits);
2160
2161 /**
2162 * Request queue structure.
2163 *
2164 * The request queue allows us to note sequence numbers that have been emitted
2165 * and may be associated with active buffers to be retired.
2166 *
2167 * By keeping this list, we can avoid having to do questionable sequence
2168 * number comparisons on buffer last_read|write_seqno. It also allows an
2169 * emission time to be associated with the request for tracking how far ahead
2170 * of the GPU the submission is.
2171 *
2172 * The requests are reference counted, so upon creation they should have an
2173 * initial reference taken using kref_init
2174 */
2175 struct drm_i915_gem_request {
2176 struct kref ref;
2177
2178 /** On Which ring this request was generated */
2179 struct drm_i915_private *i915;
2180 struct intel_engine_cs *ring;
2181
2182 /** GEM sequence number associated with this request. */
2183 uint32_t seqno;
2184
2185 /** Position in the ringbuffer of the start of the request */
2186 u32 head;
2187
2188 /**
2189 * Position in the ringbuffer of the start of the postfix.
2190 * This is required to calculate the maximum available ringbuffer
2191 * space without overwriting the postfix.
2192 */
2193 u32 postfix;
2194
2195 /** Position in the ringbuffer of the end of the whole request */
2196 u32 tail;
2197
2198 /**
2199 * Context and ring buffer related to this request
2200 * Contexts are refcounted, so when this request is associated with a
2201 * context, we must increment the context's refcount, to guarantee that
2202 * it persists while any request is linked to it. Requests themselves
2203 * are also refcounted, so the request will only be freed when the last
2204 * reference to it is dismissed, and the code in
2205 * i915_gem_request_free() will then decrement the refcount on the
2206 * context.
2207 */
2208 struct intel_context *ctx;
2209 struct intel_ringbuffer *ringbuf;
2210
2211 /** Batch buffer related to this request if any (used for
2212 error state dump only) */
2213 struct drm_i915_gem_object *batch_obj;
2214
2215 /** Time at which this request was emitted, in jiffies. */
2216 unsigned long emitted_jiffies;
2217
2218 /** global list entry for this request */
2219 struct list_head list;
2220
2221 struct drm_i915_file_private *file_priv;
2222 /** file_priv list entry for this request */
2223 struct list_head client_list;
2224
2225 /** process identifier submitting this request */
2226 struct pid *pid;
2227
2228 /**
2229 * The ELSP only accepts two elements at a time, so we queue
2230 * context/tail pairs on a given queue (ring->execlist_queue) until the
2231 * hardware is available. The queue serves a double purpose: we also use
2232 * it to keep track of the up to 2 contexts currently in the hardware
2233 * (usually one in execution and the other queued up by the GPU): We
2234 * only remove elements from the head of the queue when the hardware
2235 * informs us that an element has been completed.
2236 *
2237 * All accesses to the queue are mediated by a spinlock
2238 * (ring->execlist_lock).
2239 */
2240
2241 /** Execlist link in the submission queue.*/
2242 struct list_head execlist_link;
2243
2244 /** Execlists no. of times this request has been sent to the ELSP */
2245 int elsp_submitted;
2246
2247 };
2248
2249 int i915_gem_request_alloc(struct intel_engine_cs *ring,
2250 struct intel_context *ctx,
2251 struct drm_i915_gem_request **req_out);
2252 void i915_gem_request_cancel(struct drm_i915_gem_request *req);
2253 void i915_gem_request_free(struct kref *req_ref);
2254 int i915_gem_request_add_to_client(struct drm_i915_gem_request *req,
2255 struct drm_file *file);
2256
2257 static inline uint32_t
2258 i915_gem_request_get_seqno(struct drm_i915_gem_request *req)
2259 {
2260 return req ? req->seqno : 0;
2261 }
2262
2263 static inline struct intel_engine_cs *
2264 i915_gem_request_get_ring(struct drm_i915_gem_request *req)
2265 {
2266 return req ? req->ring : NULL;
2267 }
2268
2269 static inline struct drm_i915_gem_request *
2270 i915_gem_request_reference(struct drm_i915_gem_request *req)
2271 {
2272 if (req)
2273 kref_get(&req->ref);
2274 return req;
2275 }
2276
2277 static inline void
2278 i915_gem_request_unreference(struct drm_i915_gem_request *req)
2279 {
2280 WARN_ON(!mutex_is_locked(&req->ring->dev->struct_mutex));
2281 kref_put(&req->ref, i915_gem_request_free);
2282 }
2283
2284 static inline void
2285 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request *req)
2286 {
2287 struct drm_device *dev;
2288
2289 if (!req)
2290 return;
2291
2292 dev = req->ring->dev;
2293 if (kref_put_mutex(&req->ref, i915_gem_request_free, &dev->struct_mutex))
2294 mutex_unlock(&dev->struct_mutex);
2295 }
2296
2297 static inline void i915_gem_request_assign(struct drm_i915_gem_request **pdst,
2298 struct drm_i915_gem_request *src)
2299 {
2300 if (src)
2301 i915_gem_request_reference(src);
2302
2303 if (*pdst)
2304 i915_gem_request_unreference(*pdst);
2305
2306 *pdst = src;
2307 }
2308
2309 /*
2310 * XXX: i915_gem_request_completed should be here but currently needs the
2311 * definition of i915_seqno_passed() which is below. It will be moved in
2312 * a later patch when the call to i915_seqno_passed() is obsoleted...
2313 */
2314
2315 /*
2316 * A command that requires special handling by the command parser.
2317 */
2318 struct drm_i915_cmd_descriptor {
2319 /*
2320 * Flags describing how the command parser processes the command.
2321 *
2322 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2323 * a length mask if not set
2324 * CMD_DESC_SKIP: The command is allowed but does not follow the
2325 * standard length encoding for the opcode range in
2326 * which it falls
2327 * CMD_DESC_REJECT: The command is never allowed
2328 * CMD_DESC_REGISTER: The command should be checked against the
2329 * register whitelist for the appropriate ring
2330 * CMD_DESC_MASTER: The command is allowed if the submitting process
2331 * is the DRM master
2332 */
2333 u32 flags;
2334 #define CMD_DESC_FIXED (1<<0)
2335 #define CMD_DESC_SKIP (1<<1)
2336 #define CMD_DESC_REJECT (1<<2)
2337 #define CMD_DESC_REGISTER (1<<3)
2338 #define CMD_DESC_BITMASK (1<<4)
2339 #define CMD_DESC_MASTER (1<<5)
2340
2341 /*
2342 * The command's unique identification bits and the bitmask to get them.
2343 * This isn't strictly the opcode field as defined in the spec and may
2344 * also include type, subtype, and/or subop fields.
2345 */
2346 struct {
2347 u32 value;
2348 u32 mask;
2349 } cmd;
2350
2351 /*
2352 * The command's length. The command is either fixed length (i.e. does
2353 * not include a length field) or has a length field mask. The flag
2354 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2355 * a length mask. All command entries in a command table must include
2356 * length information.
2357 */
2358 union {
2359 u32 fixed;
2360 u32 mask;
2361 } length;
2362
2363 /*
2364 * Describes where to find a register address in the command to check
2365 * against the ring's register whitelist. Only valid if flags has the
2366 * CMD_DESC_REGISTER bit set.
2367 *
2368 * A non-zero step value implies that the command may access multiple
2369 * registers in sequence (e.g. LRI), in that case step gives the
2370 * distance in dwords between individual offset fields.
2371 */
2372 struct {
2373 u32 offset;
2374 u32 mask;
2375 u32 step;
2376 } reg;
2377
2378 #define MAX_CMD_DESC_BITMASKS 3
2379 /*
2380 * Describes command checks where a particular dword is masked and
2381 * compared against an expected value. If the command does not match
2382 * the expected value, the parser rejects it. Only valid if flags has
2383 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2384 * are valid.
2385 *
2386 * If the check specifies a non-zero condition_mask then the parser
2387 * only performs the check when the bits specified by condition_mask
2388 * are non-zero.
2389 */
2390 struct {
2391 u32 offset;
2392 u32 mask;
2393 u32 expected;
2394 u32 condition_offset;
2395 u32 condition_mask;
2396 } bits[MAX_CMD_DESC_BITMASKS];
2397 };
2398
2399 /*
2400 * A table of commands requiring special handling by the command parser.
2401 *
2402 * Each ring has an array of tables. Each table consists of an array of command
2403 * descriptors, which must be sorted with command opcodes in ascending order.
2404 */
2405 struct drm_i915_cmd_table {
2406 const struct drm_i915_cmd_descriptor *table;
2407 int count;
2408 };
2409
2410 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2411 #define __I915__(p) ({ \
2412 struct drm_i915_private *__p; \
2413 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2414 __p = (struct drm_i915_private *)p; \
2415 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2416 __p = to_i915((struct drm_device *)p); \
2417 else \
2418 BUILD_BUG(); \
2419 __p; \
2420 })
2421 #define INTEL_INFO(p) (&__I915__(p)->info)
2422 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2423 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2424
2425 #define REVID_FOREVER 0xff
2426 /*
2427 * Return true if revision is in range [since,until] inclusive.
2428 *
2429 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2430 */
2431 #define IS_REVID(p, since, until) \
2432 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2433
2434 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2435 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2436 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2437 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2438 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2439 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2440 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2441 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2442 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2443 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2444 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2445 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2446 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2447 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2448 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2449 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2450 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2451 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2452 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2453 INTEL_DEVID(dev) == 0x0152 || \
2454 INTEL_DEVID(dev) == 0x015a)
2455 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2456 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2457 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2458 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2459 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2460 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2461 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2462 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2463 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2464 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2465 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2466 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2467 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2468 (INTEL_DEVID(dev) & 0xf) == 0xe))
2469 /* ULX machines are also considered ULT. */
2470 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2471 (INTEL_DEVID(dev) & 0xf) == 0xe)
2472 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2473 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2474 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2475 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2476 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2477 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2478 /* ULX machines are also considered ULT. */
2479 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2480 INTEL_DEVID(dev) == 0x0A1E)
2481 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2482 INTEL_DEVID(dev) == 0x1913 || \
2483 INTEL_DEVID(dev) == 0x1916 || \
2484 INTEL_DEVID(dev) == 0x1921 || \
2485 INTEL_DEVID(dev) == 0x1926)
2486 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2487 INTEL_DEVID(dev) == 0x1915 || \
2488 INTEL_DEVID(dev) == 0x191E)
2489 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2490 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2491 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2492 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2493
2494 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2495
2496 #define SKL_REVID_A0 0x0
2497 #define SKL_REVID_B0 0x1
2498 #define SKL_REVID_C0 0x2
2499 #define SKL_REVID_D0 0x3
2500 #define SKL_REVID_E0 0x4
2501 #define SKL_REVID_F0 0x5
2502
2503 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2504
2505 #define BXT_REVID_A0 0x0
2506 #define BXT_REVID_A1 0x1
2507 #define BXT_REVID_B0 0x3
2508 #define BXT_REVID_C0 0x9
2509
2510 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2511
2512 /*
2513 * The genX designation typically refers to the render engine, so render
2514 * capability related checks should use IS_GEN, while display and other checks
2515 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2516 * chips, etc.).
2517 */
2518 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2519 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2520 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2521 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2522 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2523 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2524 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2525 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2526
2527 #define RENDER_RING (1<<RCS)
2528 #define BSD_RING (1<<VCS)
2529 #define BLT_RING (1<<BCS)
2530 #define VEBOX_RING (1<<VECS)
2531 #define BSD2_RING (1<<VCS2)
2532 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2533 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2534 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2535 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2536 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2537 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2538 __I915__(dev)->ellc_size)
2539 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2540
2541 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2542 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2543 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2544 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2545 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2546
2547 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2548 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2549
2550 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2551 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2552 /*
2553 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2554 * even when in MSI mode. This results in spurious interrupt warnings if the
2555 * legacy irq no. is shared with another device. The kernel then disables that
2556 * interrupt source and so prevents the other device from working properly.
2557 */
2558 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2559 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2560
2561 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2562 * rows, which changed the alignment requirements and fence programming.
2563 */
2564 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2565 IS_I915GM(dev)))
2566 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2567 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2568
2569 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2570 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2571 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2572
2573 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2574
2575 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2576 INTEL_INFO(dev)->gen >= 9)
2577
2578 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2579 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2580 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2581 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2582 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2583 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2584 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2585 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2586 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2587 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2588
2589 #define HAS_CSR(dev) (IS_GEN9(dev))
2590
2591 #define HAS_GUC_UCODE(dev) (IS_GEN9(dev))
2592 #define HAS_GUC_SCHED(dev) (IS_GEN9(dev))
2593
2594 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2595 INTEL_INFO(dev)->gen >= 8)
2596
2597 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2598 !IS_VALLEYVIEW(dev) && !IS_BROXTON(dev))
2599
2600 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2601 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2602 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2603 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2604 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2605 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2606 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2607 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2608 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2609 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2610
2611 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2612 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2613 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2614 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2615 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2616 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2617 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2618 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2619 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2620
2621 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2622
2623 /* DPF == dynamic parity feature */
2624 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2625 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2626
2627 #define GT_FREQUENCY_MULTIPLIER 50
2628 #define GEN9_FREQ_SCALER 3
2629
2630 #include "i915_trace.h"
2631
2632 extern const struct drm_ioctl_desc i915_ioctls[];
2633 extern int i915_max_ioctl;
2634
2635 extern int i915_suspend_switcheroo(struct drm_device *dev, pm_message_t state);
2636 extern int i915_resume_switcheroo(struct drm_device *dev);
2637
2638 /* i915_params.c */
2639 struct i915_params {
2640 int modeset;
2641 int panel_ignore_lid;
2642 int semaphores;
2643 int lvds_channel_mode;
2644 int panel_use_ssc;
2645 int vbt_sdvo_panel_type;
2646 int enable_rc6;
2647 int enable_dc;
2648 int enable_fbc;
2649 int enable_ppgtt;
2650 int enable_execlists;
2651 int enable_psr;
2652 unsigned int preliminary_hw_support;
2653 int disable_power_well;
2654 int enable_ips;
2655 int invert_brightness;
2656 int enable_cmd_parser;
2657 /* leave bools at the end to not create holes */
2658 bool enable_hangcheck;
2659 bool fastboot;
2660 bool prefault_disable;
2661 bool load_detect_test;
2662 bool reset;
2663 bool disable_display;
2664 bool disable_vtd_wa;
2665 bool enable_guc_submission;
2666 int guc_log_level;
2667 int use_mmio_flip;
2668 int mmio_debug;
2669 bool verbose_state_checks;
2670 bool nuclear_pageflip;
2671 int edp_vswing;
2672 };
2673 extern struct i915_params i915 __read_mostly;
2674
2675 /* i915_dma.c */
2676 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2677 extern int i915_driver_unload(struct drm_device *);
2678 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2679 extern void i915_driver_lastclose(struct drm_device * dev);
2680 extern void i915_driver_preclose(struct drm_device *dev,
2681 struct drm_file *file);
2682 extern void i915_driver_postclose(struct drm_device *dev,
2683 struct drm_file *file);
2684 #ifdef CONFIG_COMPAT
2685 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2686 unsigned long arg);
2687 #endif
2688 extern int intel_gpu_reset(struct drm_device *dev);
2689 extern bool intel_has_gpu_reset(struct drm_device *dev);
2690 extern int i915_reset(struct drm_device *dev);
2691 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2692 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2693 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2694 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2695 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2696
2697 /* intel_hotplug.c */
2698 void intel_hpd_irq_handler(struct drm_device *dev, u32 pin_mask, u32 long_mask);
2699 void intel_hpd_init(struct drm_i915_private *dev_priv);
2700 void intel_hpd_init_work(struct drm_i915_private *dev_priv);
2701 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2702 bool intel_hpd_pin_to_port(enum hpd_pin pin, enum port *port);
2703
2704 /* i915_irq.c */
2705 void i915_queue_hangcheck(struct drm_device *dev);
2706 __printf(3, 4)
2707 void i915_handle_error(struct drm_device *dev, bool wedged,
2708 const char *fmt, ...);
2709
2710 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2711 int intel_irq_install(struct drm_i915_private *dev_priv);
2712 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2713
2714 extern void intel_uncore_sanitize(struct drm_device *dev);
2715 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2716 bool restore_forcewake);
2717 extern void intel_uncore_init(struct drm_device *dev);
2718 extern void intel_uncore_check_errors(struct drm_device *dev);
2719 extern void intel_uncore_fini(struct drm_device *dev);
2720 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2721 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id);
2722 void intel_uncore_forcewake_get(struct drm_i915_private *dev_priv,
2723 enum forcewake_domains domains);
2724 void intel_uncore_forcewake_put(struct drm_i915_private *dev_priv,
2725 enum forcewake_domains domains);
2726 /* Like above but the caller must manage the uncore.lock itself.
2727 * Must be used with I915_READ_FW and friends.
2728 */
2729 void intel_uncore_forcewake_get__locked(struct drm_i915_private *dev_priv,
2730 enum forcewake_domains domains);
2731 void intel_uncore_forcewake_put__locked(struct drm_i915_private *dev_priv,
2732 enum forcewake_domains domains);
2733 void assert_forcewakes_inactive(struct drm_i915_private *dev_priv);
2734 static inline bool intel_vgpu_active(struct drm_device *dev)
2735 {
2736 return to_i915(dev)->vgpu.active;
2737 }
2738
2739 void
2740 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2741 u32 status_mask);
2742
2743 void
2744 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2745 u32 status_mask);
2746
2747 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2748 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2749 void i915_hotplug_interrupt_update(struct drm_i915_private *dev_priv,
2750 uint32_t mask,
2751 uint32_t bits);
2752 void ilk_update_display_irq(struct drm_i915_private *dev_priv,
2753 uint32_t interrupt_mask,
2754 uint32_t enabled_irq_mask);
2755 static inline void
2756 ilk_enable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2757 {
2758 ilk_update_display_irq(dev_priv, bits, bits);
2759 }
2760 static inline void
2761 ilk_disable_display_irq(struct drm_i915_private *dev_priv, uint32_t bits)
2762 {
2763 ilk_update_display_irq(dev_priv, bits, 0);
2764 }
2765 void bdw_update_pipe_irq(struct drm_i915_private *dev_priv,
2766 enum pipe pipe,
2767 uint32_t interrupt_mask,
2768 uint32_t enabled_irq_mask);
2769 static inline void bdw_enable_pipe_irq(struct drm_i915_private *dev_priv,
2770 enum pipe pipe, uint32_t bits)
2771 {
2772 bdw_update_pipe_irq(dev_priv, pipe, bits, bits);
2773 }
2774 static inline void bdw_disable_pipe_irq(struct drm_i915_private *dev_priv,
2775 enum pipe pipe, uint32_t bits)
2776 {
2777 bdw_update_pipe_irq(dev_priv, pipe, bits, 0);
2778 }
2779 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2780 uint32_t interrupt_mask,
2781 uint32_t enabled_irq_mask);
2782 static inline void
2783 ibx_enable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2784 {
2785 ibx_display_interrupt_update(dev_priv, bits, bits);
2786 }
2787 static inline void
2788 ibx_disable_display_interrupt(struct drm_i915_private *dev_priv, uint32_t bits)
2789 {
2790 ibx_display_interrupt_update(dev_priv, bits, 0);
2791 }
2792
2793
2794 /* i915_gem.c */
2795 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2796 struct drm_file *file_priv);
2797 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2798 struct drm_file *file_priv);
2799 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2800 struct drm_file *file_priv);
2801 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2802 struct drm_file *file_priv);
2803 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2804 struct drm_file *file_priv);
2805 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2806 struct drm_file *file_priv);
2807 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2808 struct drm_file *file_priv);
2809 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2810 struct drm_i915_gem_request *req);
2811 void i915_gem_execbuffer_retire_commands(struct i915_execbuffer_params *params);
2812 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params *params,
2813 struct drm_i915_gem_execbuffer2 *args,
2814 struct list_head *vmas);
2815 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2816 struct drm_file *file_priv);
2817 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2818 struct drm_file *file_priv);
2819 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2820 struct drm_file *file_priv);
2821 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2822 struct drm_file *file);
2823 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2824 struct drm_file *file);
2825 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2826 struct drm_file *file_priv);
2827 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2828 struct drm_file *file_priv);
2829 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2830 struct drm_file *file_priv);
2831 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2832 struct drm_file *file_priv);
2833 int i915_gem_init_userptr(struct drm_device *dev);
2834 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2835 struct drm_file *file);
2836 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2837 struct drm_file *file_priv);
2838 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2839 struct drm_file *file_priv);
2840 void i915_gem_load(struct drm_device *dev);
2841 void *i915_gem_object_alloc(struct drm_device *dev);
2842 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2843 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2844 const struct drm_i915_gem_object_ops *ops);
2845 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2846 size_t size);
2847 struct drm_i915_gem_object *i915_gem_object_create_from_data(
2848 struct drm_device *dev, const void *data, size_t size);
2849 void i915_gem_free_object(struct drm_gem_object *obj);
2850 void i915_gem_vma_destroy(struct i915_vma *vma);
2851
2852 /* Flags used by pin/bind&friends. */
2853 #define PIN_MAPPABLE (1<<0)
2854 #define PIN_NONBLOCK (1<<1)
2855 #define PIN_GLOBAL (1<<2)
2856 #define PIN_OFFSET_BIAS (1<<3)
2857 #define PIN_USER (1<<4)
2858 #define PIN_UPDATE (1<<5)
2859 #define PIN_ZONE_4G (1<<6)
2860 #define PIN_HIGH (1<<7)
2861 #define PIN_OFFSET_MASK (~4095)
2862 int __must_check
2863 i915_gem_object_pin(struct drm_i915_gem_object *obj,
2864 struct i915_address_space *vm,
2865 uint32_t alignment,
2866 uint64_t flags);
2867 int __must_check
2868 i915_gem_object_ggtt_pin(struct drm_i915_gem_object *obj,
2869 const struct i915_ggtt_view *view,
2870 uint32_t alignment,
2871 uint64_t flags);
2872
2873 int i915_vma_bind(struct i915_vma *vma, enum i915_cache_level cache_level,
2874 u32 flags);
2875 int __must_check i915_vma_unbind(struct i915_vma *vma);
2876 /*
2877 * BEWARE: Do not use the function below unless you can _absolutely_
2878 * _guarantee_ VMA in question is _not in use_ anywhere.
2879 */
2880 int __must_check __i915_vma_unbind_no_wait(struct i915_vma *vma);
2881 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2882 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2883 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2884
2885 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2886 int *needs_clflush);
2887
2888 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2889
2890 static inline int __sg_page_count(struct scatterlist *sg)
2891 {
2892 return sg->length >> PAGE_SHIFT;
2893 }
2894
2895 static inline struct page *
2896 i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2897 {
2898 if (WARN_ON(n >= obj->base.size >> PAGE_SHIFT))
2899 return NULL;
2900
2901 if (n < obj->get_page.last) {
2902 obj->get_page.sg = obj->pages->sgl;
2903 obj->get_page.last = 0;
2904 }
2905
2906 while (obj->get_page.last + __sg_page_count(obj->get_page.sg) <= n) {
2907 obj->get_page.last += __sg_page_count(obj->get_page.sg++);
2908 if (unlikely(sg_is_chain(obj->get_page.sg)))
2909 obj->get_page.sg = sg_chain_ptr(obj->get_page.sg);
2910 }
2911
2912 return nth_page(sg_page(obj->get_page.sg), n - obj->get_page.last);
2913 }
2914
2915 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2916 {
2917 BUG_ON(obj->pages == NULL);
2918 obj->pages_pin_count++;
2919 }
2920 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2921 {
2922 BUG_ON(obj->pages_pin_count == 0);
2923 obj->pages_pin_count--;
2924 }
2925
2926 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2927 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2928 struct intel_engine_cs *to,
2929 struct drm_i915_gem_request **to_req);
2930 void i915_vma_move_to_active(struct i915_vma *vma,
2931 struct drm_i915_gem_request *req);
2932 int i915_gem_dumb_create(struct drm_file *file_priv,
2933 struct drm_device *dev,
2934 struct drm_mode_create_dumb *args);
2935 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2936 uint32_t handle, uint64_t *offset);
2937 /**
2938 * Returns true if seq1 is later than seq2.
2939 */
2940 static inline bool
2941 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2942 {
2943 return (int32_t)(seq1 - seq2) >= 0;
2944 }
2945
2946 static inline bool i915_gem_request_completed(struct drm_i915_gem_request *req,
2947 bool lazy_coherency)
2948 {
2949 u32 seqno;
2950
2951 BUG_ON(req == NULL);
2952
2953 seqno = req->ring->get_seqno(req->ring, lazy_coherency);
2954
2955 return i915_seqno_passed(seqno, req->seqno);
2956 }
2957
2958 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2959 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2960
2961 struct drm_i915_gem_request *
2962 i915_gem_find_active_request(struct intel_engine_cs *ring);
2963
2964 bool i915_gem_retire_requests(struct drm_device *dev);
2965 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2966 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2967 bool interruptible);
2968
2969 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2970 {
2971 return unlikely(atomic_read(&error->reset_counter)
2972 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2973 }
2974
2975 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2976 {
2977 return atomic_read(&error->reset_counter) & I915_WEDGED;
2978 }
2979
2980 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2981 {
2982 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2983 }
2984
2985 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2986 {
2987 return dev_priv->gpu_error.stop_rings == 0 ||
2988 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2989 }
2990
2991 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2992 {
2993 return dev_priv->gpu_error.stop_rings == 0 ||
2994 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2995 }
2996
2997 void i915_gem_reset(struct drm_device *dev);
2998 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2999 int __must_check i915_gem_init(struct drm_device *dev);
3000 int i915_gem_init_rings(struct drm_device *dev);
3001 int __must_check i915_gem_init_hw(struct drm_device *dev);
3002 int i915_gem_l3_remap(struct drm_i915_gem_request *req, int slice);
3003 void i915_gem_init_swizzling(struct drm_device *dev);
3004 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
3005 int __must_check i915_gpu_idle(struct drm_device *dev);
3006 int __must_check i915_gem_suspend(struct drm_device *dev);
3007 void __i915_add_request(struct drm_i915_gem_request *req,
3008 struct drm_i915_gem_object *batch_obj,
3009 bool flush_caches);
3010 #define i915_add_request(req) \
3011 __i915_add_request(req, NULL, true)
3012 #define i915_add_request_no_flush(req) \
3013 __i915_add_request(req, NULL, false)
3014 int __i915_wait_request(struct drm_i915_gem_request *req,
3015 unsigned reset_counter,
3016 bool interruptible,
3017 s64 *timeout,
3018 struct intel_rps_client *rps);
3019 int __must_check i915_wait_request(struct drm_i915_gem_request *req);
3020 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
3021 int __must_check
3022 i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj,
3023 bool readonly);
3024 int __must_check
3025 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
3026 bool write);
3027 int __must_check
3028 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
3029 int __must_check
3030 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
3031 u32 alignment,
3032 const struct i915_ggtt_view *view);
3033 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj,
3034 const struct i915_ggtt_view *view);
3035 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
3036 int align);
3037 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
3038 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
3039
3040 uint32_t
3041 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
3042 uint32_t
3043 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
3044 int tiling_mode, bool fenced);
3045
3046 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
3047 enum i915_cache_level cache_level);
3048
3049 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
3050 struct dma_buf *dma_buf);
3051
3052 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
3053 struct drm_gem_object *gem_obj, int flags);
3054
3055 u64 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object *o,
3056 const struct i915_ggtt_view *view);
3057 u64 i915_gem_obj_offset(struct drm_i915_gem_object *o,
3058 struct i915_address_space *vm);
3059 static inline u64
3060 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *o)
3061 {
3062 return i915_gem_obj_ggtt_offset_view(o, &i915_ggtt_view_normal);
3063 }
3064
3065 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
3066 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object *o,
3067 const struct i915_ggtt_view *view);
3068 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
3069 struct i915_address_space *vm);
3070
3071 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
3072 struct i915_address_space *vm);
3073 struct i915_vma *
3074 i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
3075 struct i915_address_space *vm);
3076 struct i915_vma *
3077 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object *obj,
3078 const struct i915_ggtt_view *view);
3079
3080 struct i915_vma *
3081 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
3082 struct i915_address_space *vm);
3083 struct i915_vma *
3084 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object *obj,
3085 const struct i915_ggtt_view *view);
3086
3087 static inline struct i915_vma *
3088 i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj)
3089 {
3090 return i915_gem_obj_to_ggtt_view(obj, &i915_ggtt_view_normal);
3091 }
3092 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj);
3093
3094 /* Some GGTT VM helpers */
3095 #define i915_obj_to_ggtt(obj) \
3096 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
3097 static inline bool i915_is_ggtt(struct i915_address_space *vm)
3098 {
3099 struct i915_address_space *ggtt =
3100 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
3101 return vm == ggtt;
3102 }
3103
3104 static inline struct i915_hw_ppgtt *
3105 i915_vm_to_ppgtt(struct i915_address_space *vm)
3106 {
3107 WARN_ON(i915_is_ggtt(vm));
3108
3109 return container_of(vm, struct i915_hw_ppgtt, base);
3110 }
3111
3112
3113 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
3114 {
3115 return i915_gem_obj_ggtt_bound_view(obj, &i915_ggtt_view_normal);
3116 }
3117
3118 static inline unsigned long
3119 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
3120 {
3121 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
3122 }
3123
3124 static inline int __must_check
3125 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
3126 uint32_t alignment,
3127 unsigned flags)
3128 {
3129 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
3130 alignment, flags | PIN_GLOBAL);
3131 }
3132
3133 static inline int
3134 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
3135 {
3136 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
3137 }
3138
3139 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object *obj,
3140 const struct i915_ggtt_view *view);
3141 static inline void
3142 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj)
3143 {
3144 i915_gem_object_ggtt_unpin_view(obj, &i915_ggtt_view_normal);
3145 }
3146
3147 /* i915_gem_fence.c */
3148 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
3149 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
3150
3151 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
3152 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
3153
3154 void i915_gem_restore_fences(struct drm_device *dev);
3155
3156 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
3157 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
3158 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
3159
3160 /* i915_gem_context.c */
3161 int __must_check i915_gem_context_init(struct drm_device *dev);
3162 void i915_gem_context_fini(struct drm_device *dev);
3163 void i915_gem_context_reset(struct drm_device *dev);
3164 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
3165 int i915_gem_context_enable(struct drm_i915_gem_request *req);
3166 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
3167 int i915_switch_context(struct drm_i915_gem_request *req);
3168 struct intel_context *
3169 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
3170 void i915_gem_context_free(struct kref *ctx_ref);
3171 struct drm_i915_gem_object *
3172 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
3173 static inline void i915_gem_context_reference(struct intel_context *ctx)
3174 {
3175 kref_get(&ctx->ref);
3176 }
3177
3178 static inline void i915_gem_context_unreference(struct intel_context *ctx)
3179 {
3180 kref_put(&ctx->ref, i915_gem_context_free);
3181 }
3182
3183 static inline bool i915_gem_context_is_default(const struct intel_context *c)
3184 {
3185 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
3186 }
3187
3188 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
3189 struct drm_file *file);
3190 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
3191 struct drm_file *file);
3192 int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data,
3193 struct drm_file *file_priv);
3194 int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
3195 struct drm_file *file_priv);
3196
3197 /* i915_gem_evict.c */
3198 int __must_check i915_gem_evict_something(struct drm_device *dev,
3199 struct i915_address_space *vm,
3200 int min_size,
3201 unsigned alignment,
3202 unsigned cache_level,
3203 unsigned long start,
3204 unsigned long end,
3205 unsigned flags);
3206 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
3207
3208 /* belongs in i915_gem_gtt.h */
3209 static inline void i915_gem_chipset_flush(struct drm_device *dev)
3210 {
3211 if (INTEL_INFO(dev)->gen < 6)
3212 intel_gtt_chipset_flush();
3213 }
3214
3215 /* i915_gem_stolen.c */
3216 int i915_gem_stolen_insert_node(struct drm_i915_private *dev_priv,
3217 struct drm_mm_node *node, u64 size,
3218 unsigned alignment);
3219 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private *dev_priv,
3220 struct drm_mm_node *node, u64 size,
3221 unsigned alignment, u64 start,
3222 u64 end);
3223 void i915_gem_stolen_remove_node(struct drm_i915_private *dev_priv,
3224 struct drm_mm_node *node);
3225 int i915_gem_init_stolen(struct drm_device *dev);
3226 void i915_gem_cleanup_stolen(struct drm_device *dev);
3227 struct drm_i915_gem_object *
3228 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
3229 struct drm_i915_gem_object *
3230 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
3231 u32 stolen_offset,
3232 u32 gtt_offset,
3233 u32 size);
3234
3235 /* i915_gem_shrinker.c */
3236 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
3237 unsigned long target,
3238 unsigned flags);
3239 #define I915_SHRINK_PURGEABLE 0x1
3240 #define I915_SHRINK_UNBOUND 0x2
3241 #define I915_SHRINK_BOUND 0x4
3242 #define I915_SHRINK_ACTIVE 0x8
3243 unsigned long i915_gem_shrink_all(struct drm_i915_private *dev_priv);
3244 void i915_gem_shrinker_init(struct drm_i915_private *dev_priv);
3245
3246
3247 /* i915_gem_tiling.c */
3248 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
3249 {
3250 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
3251
3252 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
3253 obj->tiling_mode != I915_TILING_NONE;
3254 }
3255
3256 /* i915_gem_debug.c */
3257 #if WATCH_LISTS
3258 int i915_verify_lists(struct drm_device *dev);
3259 #else
3260 #define i915_verify_lists(dev) 0
3261 #endif
3262
3263 /* i915_debugfs.c */
3264 int i915_debugfs_init(struct drm_minor *minor);
3265 void i915_debugfs_cleanup(struct drm_minor *minor);
3266 #ifdef CONFIG_DEBUG_FS
3267 int i915_debugfs_connector_add(struct drm_connector *connector);
3268 void intel_display_crc_init(struct drm_device *dev);
3269 #else
3270 static inline int i915_debugfs_connector_add(struct drm_connector *connector)
3271 { return 0; }
3272 static inline void intel_display_crc_init(struct drm_device *dev) {}
3273 #endif
3274
3275 /* i915_gpu_error.c */
3276 __printf(2, 3)
3277 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
3278 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
3279 const struct i915_error_state_file_priv *error);
3280 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
3281 struct drm_i915_private *i915,
3282 size_t count, loff_t pos);
3283 static inline void i915_error_state_buf_release(
3284 struct drm_i915_error_state_buf *eb)
3285 {
3286 kfree(eb->buf);
3287 }
3288 void i915_capture_error_state(struct drm_device *dev, bool wedge,
3289 const char *error_msg);
3290 void i915_error_state_get(struct drm_device *dev,
3291 struct i915_error_state_file_priv *error_priv);
3292 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
3293 void i915_destroy_error_state(struct drm_device *dev);
3294
3295 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
3296 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
3297
3298 /* i915_cmd_parser.c */
3299 int i915_cmd_parser_get_version(void);
3300 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
3301 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
3302 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
3303 int i915_parse_cmds(struct intel_engine_cs *ring,
3304 struct drm_i915_gem_object *batch_obj,
3305 struct drm_i915_gem_object *shadow_batch_obj,
3306 u32 batch_start_offset,
3307 u32 batch_len,
3308 bool is_master);
3309
3310 /* i915_suspend.c */
3311 extern int i915_save_state(struct drm_device *dev);
3312 extern int i915_restore_state(struct drm_device *dev);
3313
3314 /* i915_sysfs.c */
3315 void i915_setup_sysfs(struct drm_device *dev_priv);
3316 void i915_teardown_sysfs(struct drm_device *dev_priv);
3317
3318 /* intel_i2c.c */
3319 extern int intel_setup_gmbus(struct drm_device *dev);
3320 extern void intel_teardown_gmbus(struct drm_device *dev);
3321 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
3322 unsigned int pin);
3323
3324 extern struct i2c_adapter *
3325 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
3326 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
3327 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
3328 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
3329 {
3330 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
3331 }
3332 extern void intel_i2c_reset(struct drm_device *dev);
3333
3334 /* intel_opregion.c */
3335 #ifdef CONFIG_ACPI
3336 extern int intel_opregion_setup(struct drm_device *dev);
3337 extern void intel_opregion_init(struct drm_device *dev);
3338 extern void intel_opregion_fini(struct drm_device *dev);
3339 extern void intel_opregion_asle_intr(struct drm_device *dev);
3340 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
3341 bool enable);
3342 extern int intel_opregion_notify_adapter(struct drm_device *dev,
3343 pci_power_t state);
3344 #else
3345 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
3346 static inline void intel_opregion_init(struct drm_device *dev) { return; }
3347 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
3348 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
3349 static inline int
3350 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
3351 {
3352 return 0;
3353 }
3354 static inline int
3355 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
3356 {
3357 return 0;
3358 }
3359 #endif
3360
3361 /* intel_acpi.c */
3362 #ifdef CONFIG_ACPI
3363 extern void intel_register_dsm_handler(void);
3364 extern void intel_unregister_dsm_handler(void);
3365 #else
3366 static inline void intel_register_dsm_handler(void) { return; }
3367 static inline void intel_unregister_dsm_handler(void) { return; }
3368 #endif /* CONFIG_ACPI */
3369
3370 /* modesetting */
3371 extern void intel_modeset_init_hw(struct drm_device *dev);
3372 extern void intel_modeset_init(struct drm_device *dev);
3373 extern void intel_modeset_gem_init(struct drm_device *dev);
3374 extern void intel_modeset_cleanup(struct drm_device *dev);
3375 extern void intel_connector_unregister(struct intel_connector *);
3376 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
3377 extern void intel_display_resume(struct drm_device *dev);
3378 extern void i915_redisable_vga(struct drm_device *dev);
3379 extern void i915_redisable_vga_power_on(struct drm_device *dev);
3380 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
3381 extern void intel_init_pch_refclk(struct drm_device *dev);
3382 extern void intel_set_rps(struct drm_device *dev, u8 val);
3383 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
3384 bool enable);
3385 extern void intel_detect_pch(struct drm_device *dev);
3386 extern int intel_enable_rc6(const struct drm_device *dev);
3387
3388 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
3389 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
3390 struct drm_file *file);
3391 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
3392 struct drm_file *file);
3393
3394 /* overlay */
3395 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
3396 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
3397 struct intel_overlay_error_state *error);
3398
3399 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
3400 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
3401 struct drm_device *dev,
3402 struct intel_display_error_state *error);
3403
3404 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
3405 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
3406
3407 /* intel_sideband.c */
3408 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
3409 void vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
3410 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
3411 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
3412 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3413 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
3414 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3415 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
3416 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3417 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
3418 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3419 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
3420 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3421 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
3422 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
3423 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
3424 enum intel_sbi_destination destination);
3425 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
3426 enum intel_sbi_destination destination);
3427 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
3428 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
3429
3430 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val);
3431 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val);
3432
3433 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3434 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3435
3436 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3437 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3438 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3439 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3440
3441 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3442 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3443 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3444 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3445
3446 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3447 * will be implemented using 2 32-bit writes in an arbitrary order with
3448 * an arbitrary delay between them. This can cause the hardware to
3449 * act upon the intermediate value, possibly leading to corruption and
3450 * machine death. You have been warned.
3451 */
3452 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3453 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3454
3455 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3456 u32 upper, lower, old_upper, loop = 0; \
3457 upper = I915_READ(upper_reg); \
3458 do { \
3459 old_upper = upper; \
3460 lower = I915_READ(lower_reg); \
3461 upper = I915_READ(upper_reg); \
3462 } while (upper != old_upper && loop++ < 2); \
3463 (u64)upper << 32 | lower; })
3464
3465 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3466 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3467
3468 #define __raw_read(x, s) \
3469 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3470 i915_reg_t reg) \
3471 { \
3472 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3473 }
3474
3475 #define __raw_write(x, s) \
3476 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3477 i915_reg_t reg, uint##x##_t val) \
3478 { \
3479 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3480 }
3481 __raw_read(8, b)
3482 __raw_read(16, w)
3483 __raw_read(32, l)
3484 __raw_read(64, q)
3485
3486 __raw_write(8, b)
3487 __raw_write(16, w)
3488 __raw_write(32, l)
3489 __raw_write(64, q)
3490
3491 #undef __raw_read
3492 #undef __raw_write
3493
3494 /* These are untraced mmio-accessors that are only valid to be used inside
3495 * criticial sections inside IRQ handlers where forcewake is explicitly
3496 * controlled.
3497 * Think twice, and think again, before using these.
3498 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3499 * intel_uncore_forcewake_irqunlock().
3500 */
3501 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3502 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3503 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3504
3505 /* "Broadcast RGB" property */
3506 #define INTEL_BROADCAST_RGB_AUTO 0
3507 #define INTEL_BROADCAST_RGB_FULL 1
3508 #define INTEL_BROADCAST_RGB_LIMITED 2
3509
3510 static inline i915_reg_t i915_vgacntrl_reg(struct drm_device *dev)
3511 {
3512 if (IS_VALLEYVIEW(dev))
3513 return VLV_VGACNTRL;
3514 else if (INTEL_INFO(dev)->gen >= 5)
3515 return CPU_VGACNTRL;
3516 else
3517 return VGACNTRL;
3518 }
3519
3520 static inline void __user *to_user_ptr(u64 address)
3521 {
3522 return (void __user *)(uintptr_t)address;
3523 }
3524
3525 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
3526 {
3527 unsigned long j = msecs_to_jiffies(m);
3528
3529 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3530 }
3531
3532 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
3533 {
3534 return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
3535 }
3536
3537 static inline unsigned long
3538 timespec_to_jiffies_timeout(const struct timespec *value)
3539 {
3540 unsigned long j = timespec_to_jiffies(value);
3541
3542 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
3543 }
3544
3545 /*
3546 * If you need to wait X milliseconds between events A and B, but event B
3547 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3548 * when event A happened, then just before event B you call this function and
3549 * pass the timestamp as the first argument, and X as the second argument.
3550 */
3551 static inline void
3552 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3553 {
3554 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3555
3556 /*
3557 * Don't re-read the value of "jiffies" every time since it may change
3558 * behind our back and break the math.
3559 */
3560 tmp_jiffies = jiffies;
3561 target_jiffies = timestamp_jiffies +
3562 msecs_to_jiffies_timeout(to_wait_ms);
3563
3564 if (time_after(target_jiffies, tmp_jiffies)) {
3565 remaining_jiffies = target_jiffies - tmp_jiffies;
3566 while (remaining_jiffies)
3567 remaining_jiffies =
3568 schedule_timeout_uninterruptible(remaining_jiffies);
3569 }
3570 }
3571
3572 static inline void i915_trace_irq_get(struct intel_engine_cs *ring,
3573 struct drm_i915_gem_request *req)
3574 {
3575 if (ring->trace_irq_req == NULL && ring->irq_get(ring))
3576 i915_gem_request_assign(&ring->trace_irq_req, req);
3577 }
3578
3579 #endif
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