1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include <linux/io-mapping.h>
41 #include <linux/i2c.h>
42 #include <linux/i2c-algo-bit.h>
43 #include <drm/intel-gtt.h>
44 #include <linux/backlight.h>
45 #include <linux/hashtable.h>
46 #include <linux/intel-iommu.h>
47 #include <linux/kref.h>
48 #include <linux/pm_qos.h>
50 /* General customization:
53 #define DRIVER_NAME "i915"
54 #define DRIVER_DESC "Intel Graphics"
55 #define DRIVER_DATE "20140822"
63 I915_MAX_PIPES
= _PIPE_EDP
65 #define pipe_name(p) ((p) + 'A')
74 #define transcoder_name(t) ((t) + 'A')
81 #define plane_name(p) ((p) + 'A')
83 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
93 #define port_name(p) ((p) + 'A')
95 #define I915_NUM_PHYS_VLV 2
107 enum intel_display_power_domain
{
111 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
112 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
113 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
114 POWER_DOMAIN_TRANSCODER_A
,
115 POWER_DOMAIN_TRANSCODER_B
,
116 POWER_DOMAIN_TRANSCODER_C
,
117 POWER_DOMAIN_TRANSCODER_EDP
,
118 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
119 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
120 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
121 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
122 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
123 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
124 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
125 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
126 POWER_DOMAIN_PORT_DSI
,
127 POWER_DOMAIN_PORT_CRT
,
128 POWER_DOMAIN_PORT_OTHER
,
137 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
138 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
139 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
140 #define POWER_DOMAIN_TRANSCODER(tran) \
141 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
142 (tran) + POWER_DOMAIN_TRANSCODER_A)
146 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
147 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
157 #define I915_GEM_GPU_DOMAINS \
158 (I915_GEM_DOMAIN_RENDER | \
159 I915_GEM_DOMAIN_SAMPLER | \
160 I915_GEM_DOMAIN_COMMAND | \
161 I915_GEM_DOMAIN_INSTRUCTION | \
162 I915_GEM_DOMAIN_VERTEX)
164 #define for_each_pipe(__dev_priv, __p) \
165 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
166 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
168 #define for_each_crtc(dev, crtc) \
169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
171 #define for_each_intel_crtc(dev, intel_crtc) \
172 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
174 #define for_each_intel_encoder(dev, intel_encoder) \
175 list_for_each_entry(intel_encoder, \
176 &(dev)->mode_config.encoder_list, \
179 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
180 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
181 if ((intel_encoder)->base.crtc == (__crtc))
183 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
184 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
185 if ((intel_connector)->base.encoder == (__encoder))
187 #define for_each_power_domain(domain, mask) \
188 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
189 if ((1 << (domain)) & (mask))
191 struct drm_i915_private
;
192 struct i915_mmu_object
;
195 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
196 /* real shared dpll ids must be >= 0 */
197 DPLL_ID_PCH_PLL_A
= 0,
198 DPLL_ID_PCH_PLL_B
= 1,
202 #define I915_NUM_PLLS 2
204 struct intel_dpll_hw_state
{
215 struct intel_shared_dpll
{
216 int refcount
; /* count of number of CRTCs sharing this PLL */
217 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
218 bool on
; /* is the PLL actually active? Disabled during modeset */
220 /* should match the index in the dev_priv->shared_dplls array */
221 enum intel_dpll_id id
;
222 struct intel_dpll_hw_state hw_state
;
223 /* The mode_set hook is optional and should be used together with the
224 * intel_prepare_shared_dpll function. */
225 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
226 struct intel_shared_dpll
*pll
);
227 void (*enable
)(struct drm_i915_private
*dev_priv
,
228 struct intel_shared_dpll
*pll
);
229 void (*disable
)(struct drm_i915_private
*dev_priv
,
230 struct intel_shared_dpll
*pll
);
231 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
232 struct intel_shared_dpll
*pll
,
233 struct intel_dpll_hw_state
*hw_state
);
236 /* Used by dp and fdi links */
237 struct intel_link_m_n
{
245 void intel_link_compute_m_n(int bpp
, int nlanes
,
246 int pixel_clock
, int link_clock
,
247 struct intel_link_m_n
*m_n
);
249 /* Interface history:
252 * 1.2: Add Power Management
253 * 1.3: Add vblank support
254 * 1.4: Fix cmdbuffer path, add heap destroy
255 * 1.5: Add vblank pipe configuration
256 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
257 * - Support vertical blank on secondary display pipe
259 #define DRIVER_MAJOR 1
260 #define DRIVER_MINOR 6
261 #define DRIVER_PATCHLEVEL 0
263 #define WATCH_LISTS 0
266 struct opregion_header
;
267 struct opregion_acpi
;
268 struct opregion_swsci
;
269 struct opregion_asle
;
271 struct intel_opregion
{
272 struct opregion_header __iomem
*header
;
273 struct opregion_acpi __iomem
*acpi
;
274 struct opregion_swsci __iomem
*swsci
;
275 u32 swsci_gbda_sub_functions
;
276 u32 swsci_sbcb_sub_functions
;
277 struct opregion_asle __iomem
*asle
;
279 u32 __iomem
*lid_state
;
280 struct work_struct asle_work
;
282 #define OPREGION_SIZE (8*1024)
284 struct intel_overlay
;
285 struct intel_overlay_error_state
;
287 struct drm_i915_master_private
{
288 drm_local_map_t
*sarea
;
289 struct _drm_i915_sarea
*sarea_priv
;
291 #define I915_FENCE_REG_NONE -1
292 #define I915_MAX_NUM_FENCES 32
293 /* 32 fences + sign bit for FENCE_REG_NONE */
294 #define I915_MAX_NUM_FENCE_BITS 6
296 struct drm_i915_fence_reg
{
297 struct list_head lru_list
;
298 struct drm_i915_gem_object
*obj
;
302 struct sdvo_device_mapping
{
311 struct intel_display_error_state
;
313 struct drm_i915_error_state
{
321 /* Generic register state */
329 u32 error
; /* gen6+ */
330 u32 err_int
; /* gen7 */
336 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
337 u64 fence
[I915_MAX_NUM_FENCES
];
338 struct intel_overlay_error_state
*overlay
;
339 struct intel_display_error_state
*display
;
340 struct drm_i915_error_object
*semaphore_obj
;
342 struct drm_i915_error_ring
{
344 /* Software tracked state */
347 enum intel_ring_hangcheck_action hangcheck_action
;
350 /* our own tracking of ring head and tail */
354 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
372 u32 rc_psmi
; /* sleep state */
373 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
375 struct drm_i915_error_object
{
379 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
381 struct drm_i915_error_request
{
396 char comm
[TASK_COMM_LEN
];
397 } ring
[I915_NUM_RINGS
];
399 struct drm_i915_error_buffer
{
406 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
414 } **active_bo
, **pinned_bo
;
416 u32
*active_bo_count
, *pinned_bo_count
;
420 struct intel_connector
;
421 struct intel_crtc_config
;
422 struct intel_plane_config
;
427 struct drm_i915_display_funcs
{
428 bool (*fbc_enabled
)(struct drm_device
*dev
);
429 void (*enable_fbc
)(struct drm_crtc
*crtc
);
430 void (*disable_fbc
)(struct drm_device
*dev
);
431 int (*get_display_clock_speed
)(struct drm_device
*dev
);
432 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
434 * find_dpll() - Find the best values for the PLL
435 * @limit: limits for the PLL
436 * @crtc: current CRTC
437 * @target: target frequency in kHz
438 * @refclk: reference clock frequency in kHz
439 * @match_clock: if provided, @best_clock P divider must
440 * match the P divider from @match_clock
441 * used for LVDS downclocking
442 * @best_clock: best PLL values found
444 * Returns true on success, false on failure.
446 bool (*find_dpll
)(const struct intel_limit
*limit
,
447 struct drm_crtc
*crtc
,
448 int target
, int refclk
,
449 struct dpll
*match_clock
,
450 struct dpll
*best_clock
);
451 void (*update_wm
)(struct drm_crtc
*crtc
);
452 void (*update_sprite_wm
)(struct drm_plane
*plane
,
453 struct drm_crtc
*crtc
,
454 uint32_t sprite_width
, uint32_t sprite_height
,
455 int pixel_size
, bool enable
, bool scaled
);
456 void (*modeset_global_resources
)(struct drm_device
*dev
);
457 /* Returns the active state of the crtc, and if the crtc is active,
458 * fills out the pipe-config with the hw state. */
459 bool (*get_pipe_config
)(struct intel_crtc
*,
460 struct intel_crtc_config
*);
461 void (*get_plane_config
)(struct intel_crtc
*,
462 struct intel_plane_config
*);
463 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
465 struct drm_framebuffer
*old_fb
);
466 void (*crtc_enable
)(struct drm_crtc
*crtc
);
467 void (*crtc_disable
)(struct drm_crtc
*crtc
);
468 void (*off
)(struct drm_crtc
*crtc
);
469 void (*write_eld
)(struct drm_connector
*connector
,
470 struct drm_crtc
*crtc
,
471 struct drm_display_mode
*mode
);
472 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
473 void (*init_clock_gating
)(struct drm_device
*dev
);
474 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
475 struct drm_framebuffer
*fb
,
476 struct drm_i915_gem_object
*obj
,
477 struct intel_engine_cs
*ring
,
479 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
480 struct drm_framebuffer
*fb
,
482 void (*hpd_irq_setup
)(struct drm_device
*dev
);
483 /* clock updates for mode set */
485 /* render clock increase/decrease */
486 /* display clock increase/decrease */
487 /* pll clock increase/decrease */
489 int (*setup_backlight
)(struct intel_connector
*connector
);
490 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
491 void (*set_backlight
)(struct intel_connector
*connector
,
493 void (*disable_backlight
)(struct intel_connector
*connector
);
494 void (*enable_backlight
)(struct intel_connector
*connector
);
497 struct intel_uncore_funcs
{
498 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
500 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
503 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
504 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
505 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
506 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
508 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
509 uint8_t val
, bool trace
);
510 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
511 uint16_t val
, bool trace
);
512 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
513 uint32_t val
, bool trace
);
514 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
515 uint64_t val
, bool trace
);
518 struct intel_uncore
{
519 spinlock_t lock
; /** lock is also taken in irq contexts. */
521 struct intel_uncore_funcs funcs
;
524 unsigned forcewake_count
;
526 unsigned fw_rendercount
;
527 unsigned fw_mediacount
;
529 struct timer_list force_wake_timer
;
532 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
533 func(is_mobile) sep \
536 func(is_i945gm) sep \
538 func(need_gfx_hws) sep \
540 func(is_pineview) sep \
541 func(is_broadwater) sep \
542 func(is_crestline) sep \
543 func(is_ivybridge) sep \
544 func(is_valleyview) sep \
545 func(is_haswell) sep \
546 func(is_preliminary) sep \
548 func(has_pipe_cxsr) sep \
549 func(has_hotplug) sep \
550 func(cursor_needs_physical) sep \
551 func(has_overlay) sep \
552 func(overlay_needs_physical) sep \
553 func(supports_tv) sep \
558 #define DEFINE_FLAG(name) u8 name:1
559 #define SEP_SEMICOLON ;
561 struct intel_device_info
{
562 u32 display_mmio_offset
;
565 u8 num_sprites
[I915_MAX_PIPES
];
567 u8 ring_mask
; /* Rings supported by the HW */
568 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
569 /* Register offsets for the various display pipes and transcoders */
570 int pipe_offsets
[I915_MAX_TRANSCODERS
];
571 int trans_offsets
[I915_MAX_TRANSCODERS
];
572 int palette_offsets
[I915_MAX_PIPES
];
573 int cursor_offsets
[I915_MAX_PIPES
];
579 enum i915_cache_level
{
581 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
582 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
583 caches, eg sampler/render caches, and the
584 large Last-Level-Cache. LLC is coherent with
585 the CPU, but L3 is only visible to the GPU. */
586 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
589 struct i915_ctx_hang_stats
{
590 /* This context had batch pending when hang was declared */
591 unsigned batch_pending
;
593 /* This context had batch active when hang was declared */
594 unsigned batch_active
;
596 /* Time when this context was last blamed for a GPU reset */
597 unsigned long guilty_ts
;
599 /* This context is banned to submit more work */
603 /* This must match up with the value previously used for execbuf2.rsvd1. */
604 #define DEFAULT_CONTEXT_HANDLE 0
606 * struct intel_context - as the name implies, represents a context.
607 * @ref: reference count.
608 * @user_handle: userspace tracking identity for this context.
609 * @remap_slice: l3 row remapping information.
610 * @file_priv: filp associated with this context (NULL for global default
612 * @hang_stats: information about the role of this context in possible GPU
614 * @vm: virtual memory space used by this context.
615 * @legacy_hw_ctx: render context backing object and whether it is correctly
616 * initialized (legacy ring submission mechanism only).
617 * @link: link in the global list of contexts.
619 * Contexts are memory images used by the hardware to store copies of their
622 struct intel_context
{
626 struct drm_i915_file_private
*file_priv
;
627 struct i915_ctx_hang_stats hang_stats
;
628 struct i915_hw_ppgtt
*ppgtt
;
630 /* Legacy ring buffer submission */
632 struct drm_i915_gem_object
*rcs_state
;
638 struct drm_i915_gem_object
*state
;
639 struct intel_ringbuffer
*ringbuf
;
640 } engine
[I915_NUM_RINGS
];
642 struct list_head link
;
652 struct drm_mm_node compressed_fb
;
653 struct drm_mm_node
*compressed_llb
;
657 struct intel_fbc_work
{
658 struct delayed_work work
;
659 struct drm_crtc
*crtc
;
660 struct drm_framebuffer
*fb
;
664 FBC_OK
, /* FBC is enabled */
665 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
666 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
667 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
668 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
669 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
670 FBC_BAD_PLANE
, /* fbc not supported on plane */
671 FBC_NOT_TILED
, /* buffer not tiled */
672 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
674 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
679 struct intel_connector
*connector
;
687 struct intel_dp
*enabled
;
689 struct delayed_work work
;
690 unsigned busy_frontbuffer_bits
;
694 PCH_NONE
= 0, /* No PCH present */
695 PCH_IBX
, /* Ibexpeak PCH */
696 PCH_CPT
, /* Cougarpoint PCH */
697 PCH_LPT
, /* Lynxpoint PCH */
701 enum intel_sbi_destination
{
706 #define QUIRK_PIPEA_FORCE (1<<0)
707 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
708 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
709 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
712 struct intel_fbc_work
;
715 struct i2c_adapter adapter
;
719 struct i2c_algo_bit_data bit_algo
;
720 struct drm_i915_private
*dev_priv
;
723 struct i915_suspend_saved_registers
{
744 u32 saveTRANS_HTOTAL_A
;
745 u32 saveTRANS_HBLANK_A
;
746 u32 saveTRANS_HSYNC_A
;
747 u32 saveTRANS_VTOTAL_A
;
748 u32 saveTRANS_VBLANK_A
;
749 u32 saveTRANS_VSYNC_A
;
757 u32 savePFIT_PGM_RATIOS
;
758 u32 saveBLC_HIST_CTL
;
760 u32 saveBLC_PWM_CTL2
;
761 u32 saveBLC_HIST_CTL_B
;
762 u32 saveBLC_CPU_PWM_CTL
;
763 u32 saveBLC_CPU_PWM_CTL2
;
776 u32 saveTRANS_HTOTAL_B
;
777 u32 saveTRANS_HBLANK_B
;
778 u32 saveTRANS_HSYNC_B
;
779 u32 saveTRANS_VTOTAL_B
;
780 u32 saveTRANS_VBLANK_B
;
781 u32 saveTRANS_VSYNC_B
;
795 u32 savePP_ON_DELAYS
;
796 u32 savePP_OFF_DELAYS
;
804 u32 savePFIT_CONTROL
;
805 u32 save_palette_a
[256];
806 u32 save_palette_b
[256];
817 u32 saveCACHE_MODE_0
;
818 u32 saveMI_ARB_STATE
;
829 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
840 u32 savePIPEA_GMCH_DATA_M
;
841 u32 savePIPEB_GMCH_DATA_M
;
842 u32 savePIPEA_GMCH_DATA_N
;
843 u32 savePIPEB_GMCH_DATA_N
;
844 u32 savePIPEA_DP_LINK_M
;
845 u32 savePIPEB_DP_LINK_M
;
846 u32 savePIPEA_DP_LINK_N
;
847 u32 savePIPEB_DP_LINK_N
;
858 u32 savePCH_DREF_CONTROL
;
859 u32 saveDISP_ARB_CTL
;
860 u32 savePIPEA_DATA_M1
;
861 u32 savePIPEA_DATA_N1
;
862 u32 savePIPEA_LINK_M1
;
863 u32 savePIPEA_LINK_N1
;
864 u32 savePIPEB_DATA_M1
;
865 u32 savePIPEB_DATA_N1
;
866 u32 savePIPEB_LINK_M1
;
867 u32 savePIPEB_LINK_N1
;
868 u32 saveMCHBAR_RENDER_STANDBY
;
869 u32 savePCH_PORT_HOTPLUG
;
872 struct vlv_s0ix_state
{
879 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
880 u32 media_max_req_count
;
881 u32 gfx_max_req_count
;
913 /* Display 1 CZ domain */
918 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
920 /* GT SA CZ domain */
927 /* Display 2 CZ domain */
933 struct intel_rps_ei
{
939 struct intel_rps_bdw_cal
{
940 u32 it_threshold_pct
; /* interrupt, in percentage */
941 u32 eval_interval
; /* evaluation interval, in us */
947 struct intel_rps_bdw_turbo
{
948 struct intel_rps_bdw_cal up
;
949 struct intel_rps_bdw_cal down
;
950 struct timer_list flip_timer
;
952 atomic_t flip_received
;
953 struct work_struct work_max_freq
;
956 struct intel_gen6_power_mgmt
{
957 /* work and pm_iir are protected by dev_priv->irq_lock */
958 struct work_struct work
;
961 /* Frequencies are stored in potentially platform dependent multiples.
962 * In other words, *_freq needs to be multiplied by X to be interesting.
963 * Soft limits are those which are used for the dynamic reclocking done
964 * by the driver (raise frequencies under heavy loads, and lower for
965 * lighter loads). Hard limits are those imposed by the hardware.
967 * A distinction is made for overclocking, which is never enabled by
968 * default, and is considered to be above the hard limit if it's
971 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
972 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
973 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
974 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
975 u8 min_freq
; /* AKA RPn. Minimum frequency */
976 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
977 u8 rp1_freq
; /* "less than" RP0 power/freqency */
978 u8 rp0_freq
; /* Non-overclocked max frequency. */
981 u32 ei_interrupt_count
;
984 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
987 struct delayed_work delayed_resume_work
;
989 bool is_bdw_sw_turbo
; /* Switch of BDW software turbo */
990 struct intel_rps_bdw_turbo sw_turbo
; /* Calculate RP interrupt timing */
992 /* manual wa residency calculations */
993 struct intel_rps_ei up_ei
, down_ei
;
996 * Protects RPS/RC6 register access and PCU communication.
997 * Must be taken after struct_mutex if nested.
999 struct mutex hw_lock
;
1002 /* defined intel_pm.c */
1003 extern spinlock_t mchdev_lock
;
1005 struct intel_ilk_power_mgmt
{
1013 unsigned long last_time1
;
1014 unsigned long chipset_power
;
1017 unsigned long gfx_power
;
1023 struct drm_i915_gem_object
*pwrctx
;
1024 struct drm_i915_gem_object
*renderctx
;
1027 struct drm_i915_private
;
1028 struct i915_power_well
;
1030 struct i915_power_well_ops
{
1032 * Synchronize the well's hw state to match the current sw state, for
1033 * example enable/disable it based on the current refcount. Called
1034 * during driver init and resume time, possibly after first calling
1035 * the enable/disable handlers.
1037 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1038 struct i915_power_well
*power_well
);
1040 * Enable the well and resources that depend on it (for example
1041 * interrupts located on the well). Called after the 0->1 refcount
1044 void (*enable
)(struct drm_i915_private
*dev_priv
,
1045 struct i915_power_well
*power_well
);
1047 * Disable the well and resources that depend on it. Called after
1048 * the 1->0 refcount transition.
1050 void (*disable
)(struct drm_i915_private
*dev_priv
,
1051 struct i915_power_well
*power_well
);
1052 /* Returns the hw enabled state. */
1053 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1054 struct i915_power_well
*power_well
);
1057 /* Power well structure for haswell */
1058 struct i915_power_well
{
1061 /* power well enable/disable usage count */
1063 /* cached hw enabled state */
1065 unsigned long domains
;
1067 const struct i915_power_well_ops
*ops
;
1070 struct i915_power_domains
{
1072 * Power wells needed for initialization at driver init and suspend
1073 * time are on. They are kept on until after the first modeset.
1077 int power_well_count
;
1080 int domain_use_count
[POWER_DOMAIN_NUM
];
1081 struct i915_power_well
*power_wells
;
1084 struct i915_dri1_state
{
1085 unsigned allow_batchbuffer
: 1;
1086 u32 __iomem
*gfx_hws_cpu_addr
;
1097 struct i915_ums_state
{
1099 * Flag if the X Server, and thus DRM, is not currently in
1100 * control of the device.
1102 * This is set between LeaveVT and EnterVT. It needs to be
1103 * replaced with a semaphore. It also needs to be
1104 * transitioned away from for kernel modesetting.
1109 #define MAX_L3_SLICES 2
1110 struct intel_l3_parity
{
1111 u32
*remap_info
[MAX_L3_SLICES
];
1112 struct work_struct error_work
;
1116 struct i915_gem_mm
{
1117 /** Memory allocator for GTT stolen memory */
1118 struct drm_mm stolen
;
1119 /** List of all objects in gtt_space. Used to restore gtt
1120 * mappings on resume */
1121 struct list_head bound_list
;
1123 * List of objects which are not bound to the GTT (thus
1124 * are idle and not used by the GPU) but still have
1125 * (presumably uncached) pages still attached.
1127 struct list_head unbound_list
;
1129 /** Usable portion of the GTT for GEM */
1130 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1132 /** PPGTT used for aliasing the PPGTT with the GTT */
1133 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1135 struct notifier_block oom_notifier
;
1136 struct shrinker shrinker
;
1137 bool shrinker_no_lock_stealing
;
1139 /** LRU list of objects with fence regs on them. */
1140 struct list_head fence_list
;
1143 * We leave the user IRQ off as much as possible,
1144 * but this means that requests will finish and never
1145 * be retired once the system goes idle. Set a timer to
1146 * fire periodically while the ring is running. When it
1147 * fires, go retire requests.
1149 struct delayed_work retire_work
;
1152 * When we detect an idle GPU, we want to turn on
1153 * powersaving features. So once we see that there
1154 * are no more requests outstanding and no more
1155 * arrive within a small period of time, we fire
1156 * off the idle_work.
1158 struct delayed_work idle_work
;
1161 * Are we in a non-interruptible section of code like
1167 * Is the GPU currently considered idle, or busy executing userspace
1168 * requests? Whilst idle, we attempt to power down the hardware and
1169 * display clocks. In order to reduce the effect on performance, there
1170 * is a slight delay before we do so.
1174 /* the indicator for dispatch video commands on two BSD rings */
1175 int bsd_ring_dispatch_index
;
1177 /** Bit 6 swizzling required for X tiling */
1178 uint32_t bit_6_swizzle_x
;
1179 /** Bit 6 swizzling required for Y tiling */
1180 uint32_t bit_6_swizzle_y
;
1182 /* accounting, useful for userland debugging */
1183 spinlock_t object_stat_lock
;
1184 size_t object_memory
;
1188 struct drm_i915_error_state_buf
{
1189 struct drm_i915_private
*i915
;
1198 struct i915_error_state_file_priv
{
1199 struct drm_device
*dev
;
1200 struct drm_i915_error_state
*error
;
1203 struct i915_gpu_error
{
1204 /* For hangcheck timer */
1205 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1206 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1207 /* Hang gpu twice in this window and your context gets banned */
1208 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1210 struct timer_list hangcheck_timer
;
1212 /* For reset and error_state handling. */
1214 /* Protected by the above dev->gpu_error.lock. */
1215 struct drm_i915_error_state
*first_error
;
1216 struct work_struct work
;
1219 unsigned long missed_irq_rings
;
1222 * State variable controlling the reset flow and count
1224 * This is a counter which gets incremented when reset is triggered,
1225 * and again when reset has been handled. So odd values (lowest bit set)
1226 * means that reset is in progress and even values that
1227 * (reset_counter >> 1):th reset was successfully completed.
1229 * If reset is not completed succesfully, the I915_WEDGE bit is
1230 * set meaning that hardware is terminally sour and there is no
1231 * recovery. All waiters on the reset_queue will be woken when
1234 * This counter is used by the wait_seqno code to notice that reset
1235 * event happened and it needs to restart the entire ioctl (since most
1236 * likely the seqno it waited for won't ever signal anytime soon).
1238 * This is important for lock-free wait paths, where no contended lock
1239 * naturally enforces the correct ordering between the bail-out of the
1240 * waiter and the gpu reset work code.
1242 atomic_t reset_counter
;
1244 #define I915_RESET_IN_PROGRESS_FLAG 1
1245 #define I915_WEDGED (1 << 31)
1248 * Waitqueue to signal when the reset has completed. Used by clients
1249 * that wait for dev_priv->mm.wedged to settle.
1251 wait_queue_head_t reset_queue
;
1253 /* Userspace knobs for gpu hang simulation;
1254 * combines both a ring mask, and extra flags
1257 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1258 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1260 /* For missed irq/seqno simulation. */
1261 unsigned int test_irq_rings
;
1263 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1264 bool reload_in_reset
;
1267 enum modeset_restore
{
1268 MODESET_ON_LID_OPEN
,
1273 struct ddi_vbt_port_info
{
1275 * This is an index in the HDMI/DVI DDI buffer translation table.
1276 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1277 * populate this field.
1279 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1280 uint8_t hdmi_level_shift
;
1282 uint8_t supports_dvi
:1;
1283 uint8_t supports_hdmi
:1;
1284 uint8_t supports_dp
:1;
1287 enum drrs_support_type
{
1288 DRRS_NOT_SUPPORTED
= 0,
1289 STATIC_DRRS_SUPPORT
= 1,
1290 SEAMLESS_DRRS_SUPPORT
= 2
1293 struct intel_vbt_data
{
1294 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1295 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1298 unsigned int int_tv_support
:1;
1299 unsigned int lvds_dither
:1;
1300 unsigned int lvds_vbt
:1;
1301 unsigned int int_crt_support
:1;
1302 unsigned int lvds_use_ssc
:1;
1303 unsigned int display_clock_mode
:1;
1304 unsigned int fdi_rx_polarity_inverted
:1;
1305 unsigned int has_mipi
:1;
1307 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1309 enum drrs_support_type drrs_type
;
1314 int edp_preemphasis
;
1316 bool edp_initialized
;
1319 struct edp_power_seq edp_pps
;
1324 bool active_low_pwm
;
1325 u8 min_brightness
; /* min_brightness/255 of max */
1332 struct mipi_config
*config
;
1333 struct mipi_pps_data
*pps
;
1337 u8
*sequence
[MIPI_SEQ_MAX
];
1343 union child_device_config
*child_dev
;
1345 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1348 enum intel_ddb_partitioning
{
1350 INTEL_DDB_PART_5_6
, /* IVB+ */
1353 struct intel_wm_level
{
1361 struct ilk_wm_values
{
1362 uint32_t wm_pipe
[3];
1364 uint32_t wm_lp_spr
[3];
1365 uint32_t wm_linetime
[3];
1367 enum intel_ddb_partitioning partitioning
;
1371 * This struct helps tracking the state needed for runtime PM, which puts the
1372 * device in PCI D3 state. Notice that when this happens, nothing on the
1373 * graphics device works, even register access, so we don't get interrupts nor
1376 * Every piece of our code that needs to actually touch the hardware needs to
1377 * either call intel_runtime_pm_get or call intel_display_power_get with the
1378 * appropriate power domain.
1380 * Our driver uses the autosuspend delay feature, which means we'll only really
1381 * suspend if we stay with zero refcount for a certain amount of time. The
1382 * default value is currently very conservative (see intel_init_runtime_pm), but
1383 * it can be changed with the standard runtime PM files from sysfs.
1385 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1386 * goes back to false exactly before we reenable the IRQs. We use this variable
1387 * to check if someone is trying to enable/disable IRQs while they're supposed
1388 * to be disabled. This shouldn't happen and we'll print some error messages in
1391 * For more, read the Documentation/power/runtime_pm.txt.
1393 struct i915_runtime_pm
{
1395 bool _irqs_disabled
;
1398 enum intel_pipe_crc_source
{
1399 INTEL_PIPE_CRC_SOURCE_NONE
,
1400 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1401 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1402 INTEL_PIPE_CRC_SOURCE_PF
,
1403 INTEL_PIPE_CRC_SOURCE_PIPE
,
1404 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1405 INTEL_PIPE_CRC_SOURCE_TV
,
1406 INTEL_PIPE_CRC_SOURCE_DP_B
,
1407 INTEL_PIPE_CRC_SOURCE_DP_C
,
1408 INTEL_PIPE_CRC_SOURCE_DP_D
,
1409 INTEL_PIPE_CRC_SOURCE_AUTO
,
1410 INTEL_PIPE_CRC_SOURCE_MAX
,
1413 struct intel_pipe_crc_entry
{
1418 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1419 struct intel_pipe_crc
{
1421 bool opened
; /* exclusive access to the result file */
1422 struct intel_pipe_crc_entry
*entries
;
1423 enum intel_pipe_crc_source source
;
1425 wait_queue_head_t wq
;
1428 struct i915_frontbuffer_tracking
{
1432 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1439 struct drm_i915_private
{
1440 struct drm_device
*dev
;
1441 struct kmem_cache
*slab
;
1443 const struct intel_device_info info
;
1445 int relative_constants_mode
;
1449 struct intel_uncore uncore
;
1451 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1454 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1455 * controller on different i2c buses. */
1456 struct mutex gmbus_mutex
;
1459 * Base address of the gmbus and gpio block.
1461 uint32_t gpio_mmio_base
;
1463 /* MMIO base address for MIPI regs */
1464 uint32_t mipi_mmio_base
;
1466 wait_queue_head_t gmbus_wait_queue
;
1468 struct pci_dev
*bridge_dev
;
1469 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1470 struct drm_i915_gem_object
*semaphore_obj
;
1471 uint32_t last_seqno
, next_seqno
;
1473 drm_dma_handle_t
*status_page_dmah
;
1474 struct resource mch_res
;
1476 /* protects the irq masks */
1477 spinlock_t irq_lock
;
1479 /* protects the mmio flip data */
1480 spinlock_t mmio_flip_lock
;
1482 bool display_irqs_enabled
;
1484 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1485 struct pm_qos_request pm_qos
;
1487 /* DPIO indirect register protection */
1488 struct mutex dpio_lock
;
1490 /** Cached value of IMR to avoid reads in updating the bitfield */
1493 u32 de_irq_mask
[I915_MAX_PIPES
];
1498 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1500 struct work_struct hotplug_work
;
1502 unsigned long hpd_last_jiffies
;
1507 HPD_MARK_DISABLED
= 2
1509 } hpd_stats
[HPD_NUM_PINS
];
1511 struct delayed_work hotplug_reenable_work
;
1513 struct i915_fbc fbc
;
1514 struct i915_drrs drrs
;
1515 struct intel_opregion opregion
;
1516 struct intel_vbt_data vbt
;
1519 struct intel_overlay
*overlay
;
1521 /* backlight registers and fields in struct intel_panel */
1522 spinlock_t backlight_lock
;
1525 bool no_aux_handshake
;
1527 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1528 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1529 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1531 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1532 unsigned int vlv_cdclk_freq
;
1535 * wq - Driver workqueue for GEM.
1537 * NOTE: Work items scheduled here are not allowed to grab any modeset
1538 * locks, for otherwise the flushing done in the pageflip code will
1539 * result in deadlocks.
1541 struct workqueue_struct
*wq
;
1543 /* Display functions */
1544 struct drm_i915_display_funcs display
;
1546 /* PCH chipset type */
1547 enum intel_pch pch_type
;
1548 unsigned short pch_id
;
1550 unsigned long quirks
;
1552 enum modeset_restore modeset_restore
;
1553 struct mutex modeset_restore_lock
;
1555 struct list_head vm_list
; /* Global list of all address spaces */
1556 struct i915_gtt gtt
; /* VM representing the global address space */
1558 struct i915_gem_mm mm
;
1559 #if defined(CONFIG_MMU_NOTIFIER)
1560 DECLARE_HASHTABLE(mmu_notifiers
, 7);
1563 /* Kernel Modesetting */
1565 struct sdvo_device_mapping sdvo_mappings
[2];
1567 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1568 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1569 wait_queue_head_t pending_flip_queue
;
1571 #ifdef CONFIG_DEBUG_FS
1572 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1575 int num_shared_dpll
;
1576 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1577 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1580 * workarounds are currently applied at different places and
1581 * changes are being done to consolidate them so exact count is
1582 * not clear at this point, use a max value for now.
1584 #define I915_MAX_WA_REGS 16
1588 /* bitmask representing WA bits */
1590 } intel_wa_regs
[I915_MAX_WA_REGS
];
1593 /* Reclocking support */
1594 bool render_reclock_avail
;
1595 bool lvds_downclock_avail
;
1596 /* indicates the reduced downclock for LVDS*/
1599 struct i915_frontbuffer_tracking fb_tracking
;
1603 bool mchbar_need_disable
;
1605 struct intel_l3_parity l3_parity
;
1607 /* Cannot be determined by PCIID. You must always read a register. */
1610 /* gen6+ rps state */
1611 struct intel_gen6_power_mgmt rps
;
1613 /* ilk-only ips/rps state. Everything in here is protected by the global
1614 * mchdev_lock in intel_pm.c */
1615 struct intel_ilk_power_mgmt ips
;
1617 struct i915_power_domains power_domains
;
1619 struct i915_psr psr
;
1621 struct i915_gpu_error gpu_error
;
1623 struct drm_i915_gem_object
*vlv_pctx
;
1625 #ifdef CONFIG_DRM_I915_FBDEV
1626 /* list of fbdev register on this device */
1627 struct intel_fbdev
*fbdev
;
1628 struct work_struct fbdev_suspend_work
;
1631 struct drm_property
*broadcast_rgb_property
;
1632 struct drm_property
*force_audio_property
;
1634 uint32_t hw_context_size
;
1635 struct list_head context_list
;
1640 struct i915_suspend_saved_registers regfile
;
1641 struct vlv_s0ix_state vlv_s0ix_state
;
1645 * Raw watermark latency values:
1646 * in 0.1us units for WM0,
1647 * in 0.5us units for WM1+.
1650 uint16_t pri_latency
[5];
1652 uint16_t spr_latency
[5];
1654 uint16_t cur_latency
[5];
1656 /* current hardware state */
1657 struct ilk_wm_values hw
;
1660 struct i915_runtime_pm pm
;
1662 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1663 u32 long_hpd_port_mask
;
1664 u32 short_hpd_port_mask
;
1665 struct work_struct dig_port_work
;
1668 * if we get a HPD irq from DP and a HPD irq from non-DP
1669 * the non-DP HPD could block the workqueue on a mode config
1670 * mutex getting, that userspace may have taken. However
1671 * userspace is waiting on the DP workqueue to run which is
1672 * blocked behind the non-DP one.
1674 struct workqueue_struct
*dp_wq
;
1676 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1678 struct i915_dri1_state dri1
;
1679 /* Old ums support infrastructure, same warning applies. */
1680 struct i915_ums_state ums
;
1682 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1684 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1685 struct intel_engine_cs
*ring
,
1686 struct intel_context
*ctx
,
1687 struct drm_i915_gem_execbuffer2
*args
,
1688 struct list_head
*vmas
,
1689 struct drm_i915_gem_object
*batch_obj
,
1690 u64 exec_start
, u32 flags
);
1691 int (*init_rings
)(struct drm_device
*dev
);
1692 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1693 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1697 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1698 * will be rejected. Instead look for a better place.
1702 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1704 return dev
->dev_private
;
1707 /* Iterate over initialised rings */
1708 #define for_each_ring(ring__, dev_priv__, i__) \
1709 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1710 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1712 enum hdmi_force_audio
{
1713 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1714 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1715 HDMI_AUDIO_AUTO
, /* trust EDID */
1716 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1719 #define I915_GTT_OFFSET_NONE ((u32)-1)
1721 struct drm_i915_gem_object_ops
{
1722 /* Interface between the GEM object and its backing storage.
1723 * get_pages() is called once prior to the use of the associated set
1724 * of pages before to binding them into the GTT, and put_pages() is
1725 * called after we no longer need them. As we expect there to be
1726 * associated cost with migrating pages between the backing storage
1727 * and making them available for the GPU (e.g. clflush), we may hold
1728 * onto the pages after they are no longer referenced by the GPU
1729 * in case they may be used again shortly (for example migrating the
1730 * pages to a different memory domain within the GTT). put_pages()
1731 * will therefore most likely be called when the object itself is
1732 * being released or under memory pressure (where we attempt to
1733 * reap pages for the shrinker).
1735 int (*get_pages
)(struct drm_i915_gem_object
*);
1736 void (*put_pages
)(struct drm_i915_gem_object
*);
1737 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1738 void (*release
)(struct drm_i915_gem_object
*);
1742 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1743 * considered to be the frontbuffer for the given plane interface-vise. This
1744 * doesn't mean that the hw necessarily already scans it out, but that any
1745 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1747 * We have one bit per pipe and per scanout plane type.
1749 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1750 #define INTEL_FRONTBUFFER_BITS \
1751 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1752 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1753 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1754 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1755 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1756 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1757 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1758 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1759 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1760 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1761 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1763 struct drm_i915_gem_object
{
1764 struct drm_gem_object base
;
1766 const struct drm_i915_gem_object_ops
*ops
;
1768 /** List of VMAs backed by this object */
1769 struct list_head vma_list
;
1771 /** Stolen memory for this object, instead of being backed by shmem. */
1772 struct drm_mm_node
*stolen
;
1773 struct list_head global_list
;
1775 struct list_head ring_list
;
1776 /** Used in execbuf to temporarily hold a ref */
1777 struct list_head obj_exec_link
;
1780 * This is set if the object is on the active lists (has pending
1781 * rendering and so a non-zero seqno), and is not set if it i s on
1782 * inactive (ready to be unbound) list.
1784 unsigned int active
:1;
1787 * This is set if the object has been written to since last bound
1790 unsigned int dirty
:1;
1793 * Fence register bits (if any) for this object. Will be set
1794 * as needed when mapped into the GTT.
1795 * Protected by dev->struct_mutex.
1797 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1800 * Advice: are the backing pages purgeable?
1802 unsigned int madv
:2;
1805 * Current tiling mode for the object.
1807 unsigned int tiling_mode
:2;
1809 * Whether the tiling parameters for the currently associated fence
1810 * register have changed. Note that for the purposes of tracking
1811 * tiling changes we also treat the unfenced register, the register
1812 * slot that the object occupies whilst it executes a fenced
1813 * command (such as BLT on gen2/3), as a "fence".
1815 unsigned int fence_dirty
:1;
1818 * Is the object at the current location in the gtt mappable and
1819 * fenceable? Used to avoid costly recalculations.
1821 unsigned int map_and_fenceable
:1;
1824 * Whether the current gtt mapping needs to be mappable (and isn't just
1825 * mappable by accident). Track pin and fault separate for a more
1826 * accurate mappable working set.
1828 unsigned int fault_mappable
:1;
1829 unsigned int pin_mappable
:1;
1830 unsigned int pin_display
:1;
1833 * Is the object to be mapped as read-only to the GPU
1834 * Only honoured if hardware has relevant pte bit
1836 unsigned long gt_ro
:1;
1837 unsigned int cache_level
:3;
1839 unsigned int has_aliasing_ppgtt_mapping
:1;
1840 unsigned int has_global_gtt_mapping
:1;
1841 unsigned int has_dma_mapping
:1;
1843 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1845 struct sg_table
*pages
;
1846 int pages_pin_count
;
1848 /* prime dma-buf support */
1849 void *dma_buf_vmapping
;
1852 struct intel_engine_cs
*ring
;
1854 /** Breadcrumb of last rendering to the buffer. */
1855 uint32_t last_read_seqno
;
1856 uint32_t last_write_seqno
;
1857 /** Breadcrumb of last fenced GPU access to the buffer. */
1858 uint32_t last_fenced_seqno
;
1860 /** Current tiling stride for the object, if it's tiled. */
1863 /** References from framebuffers, locks out tiling changes. */
1864 unsigned long framebuffer_references
;
1866 /** Record of address bit 17 of each page at last unbind. */
1867 unsigned long *bit_17
;
1869 /** User space pin count and filp owning the pin */
1870 unsigned long user_pin_count
;
1871 struct drm_file
*pin_filp
;
1873 /** for phy allocated objects */
1874 drm_dma_handle_t
*phys_handle
;
1877 struct i915_gem_userptr
{
1879 unsigned read_only
:1;
1880 unsigned workers
:4;
1881 #define I915_GEM_USERPTR_MAX_WORKERS 15
1883 struct mm_struct
*mm
;
1884 struct i915_mmu_object
*mn
;
1885 struct work_struct
*work
;
1889 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1891 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1892 struct drm_i915_gem_object
*new,
1893 unsigned frontbuffer_bits
);
1896 * Request queue structure.
1898 * The request queue allows us to note sequence numbers that have been emitted
1899 * and may be associated with active buffers to be retired.
1901 * By keeping this list, we can avoid having to do questionable
1902 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1903 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1905 struct drm_i915_gem_request
{
1906 /** On Which ring this request was generated */
1907 struct intel_engine_cs
*ring
;
1909 /** GEM sequence number associated with this request. */
1912 /** Position in the ringbuffer of the start of the request */
1915 /** Position in the ringbuffer of the end of the request */
1918 /** Context related to this request */
1919 struct intel_context
*ctx
;
1921 /** Batch buffer related to this request if any */
1922 struct drm_i915_gem_object
*batch_obj
;
1924 /** Time at which this request was emitted, in jiffies. */
1925 unsigned long emitted_jiffies
;
1927 /** global list entry for this request */
1928 struct list_head list
;
1930 struct drm_i915_file_private
*file_priv
;
1931 /** file_priv list entry for this request */
1932 struct list_head client_list
;
1935 struct drm_i915_file_private
{
1936 struct drm_i915_private
*dev_priv
;
1937 struct drm_file
*file
;
1941 struct list_head request_list
;
1942 struct delayed_work idle_work
;
1944 struct idr context_idr
;
1946 atomic_t rps_wait_boost
;
1947 struct intel_engine_cs
*bsd_ring
;
1951 * A command that requires special handling by the command parser.
1953 struct drm_i915_cmd_descriptor
{
1955 * Flags describing how the command parser processes the command.
1957 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1958 * a length mask if not set
1959 * CMD_DESC_SKIP: The command is allowed but does not follow the
1960 * standard length encoding for the opcode range in
1962 * CMD_DESC_REJECT: The command is never allowed
1963 * CMD_DESC_REGISTER: The command should be checked against the
1964 * register whitelist for the appropriate ring
1965 * CMD_DESC_MASTER: The command is allowed if the submitting process
1969 #define CMD_DESC_FIXED (1<<0)
1970 #define CMD_DESC_SKIP (1<<1)
1971 #define CMD_DESC_REJECT (1<<2)
1972 #define CMD_DESC_REGISTER (1<<3)
1973 #define CMD_DESC_BITMASK (1<<4)
1974 #define CMD_DESC_MASTER (1<<5)
1977 * The command's unique identification bits and the bitmask to get them.
1978 * This isn't strictly the opcode field as defined in the spec and may
1979 * also include type, subtype, and/or subop fields.
1987 * The command's length. The command is either fixed length (i.e. does
1988 * not include a length field) or has a length field mask. The flag
1989 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1990 * a length mask. All command entries in a command table must include
1991 * length information.
1999 * Describes where to find a register address in the command to check
2000 * against the ring's register whitelist. Only valid if flags has the
2001 * CMD_DESC_REGISTER bit set.
2008 #define MAX_CMD_DESC_BITMASKS 3
2010 * Describes command checks where a particular dword is masked and
2011 * compared against an expected value. If the command does not match
2012 * the expected value, the parser rejects it. Only valid if flags has
2013 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2016 * If the check specifies a non-zero condition_mask then the parser
2017 * only performs the check when the bits specified by condition_mask
2024 u32 condition_offset
;
2026 } bits
[MAX_CMD_DESC_BITMASKS
];
2030 * A table of commands requiring special handling by the command parser.
2032 * Each ring has an array of tables. Each table consists of an array of command
2033 * descriptors, which must be sorted with command opcodes in ascending order.
2035 struct drm_i915_cmd_table
{
2036 const struct drm_i915_cmd_descriptor
*table
;
2040 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2041 #define __I915__(p) ({ \
2042 struct drm_i915_private *__p; \
2043 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2044 __p = (struct drm_i915_private *)p; \
2045 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2046 __p = to_i915((struct drm_device *)p); \
2051 #define INTEL_INFO(p) (&__I915__(p)->info)
2052 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2054 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2055 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2056 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2057 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2058 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2059 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2060 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2061 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2062 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2063 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2064 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2065 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2066 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2067 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2068 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2069 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2070 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2071 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2072 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2073 INTEL_DEVID(dev) == 0x0152 || \
2074 INTEL_DEVID(dev) == 0x015a)
2075 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2076 INTEL_DEVID(dev) == 0x0106 || \
2077 INTEL_DEVID(dev) == 0x010A)
2078 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2079 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2080 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2081 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2082 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2083 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2084 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2085 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2086 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2087 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2088 (INTEL_DEVID(dev) & 0xf) == 0xe))
2089 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2090 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2091 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
2092 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2093 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2094 /* ULX machines are also considered ULT. */
2095 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2096 INTEL_DEVID(dev) == 0x0A1E)
2097 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2100 * The genX designation typically refers to the render engine, so render
2101 * capability related checks should use IS_GEN, while display and other checks
2102 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2105 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2106 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2107 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2108 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2109 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2110 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2111 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2113 #define RENDER_RING (1<<RCS)
2114 #define BSD_RING (1<<VCS)
2115 #define BLT_RING (1<<BCS)
2116 #define VEBOX_RING (1<<VECS)
2117 #define BSD2_RING (1<<VCS2)
2118 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2119 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2120 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2121 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2122 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2123 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2124 to_i915(dev)->ellc_size)
2125 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2127 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2128 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2129 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2130 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2131 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2132 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2134 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2135 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2137 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2138 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2140 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2141 * even when in MSI mode. This results in spurious interrupt warnings if the
2142 * legacy irq no. is shared with another device. The kernel then disables that
2143 * interrupt source and so prevents the other device from working properly.
2145 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2146 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2148 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2149 * rows, which changed the alignment requirements and fence programming.
2151 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2153 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2154 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2155 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2156 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2157 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2159 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2160 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2161 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2163 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2165 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2166 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2167 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2168 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2169 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2171 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2172 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2173 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2174 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2175 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2176 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2178 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2179 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2180 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2181 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2182 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2183 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2185 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2187 /* DPF == dynamic parity feature */
2188 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2189 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2191 #define GT_FREQUENCY_MULTIPLIER 50
2193 #include "i915_trace.h"
2195 extern const struct drm_ioctl_desc i915_ioctls
[];
2196 extern int i915_max_ioctl
;
2198 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
2199 extern int i915_resume(struct drm_device
*dev
);
2200 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2201 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2204 struct i915_params
{
2206 int panel_ignore_lid
;
2207 unsigned int powersave
;
2209 unsigned int lvds_downclock
;
2210 int lvds_channel_mode
;
2212 int vbt_sdvo_panel_type
;
2216 int enable_execlists
;
2218 unsigned int preliminary_hw_support
;
2219 int disable_power_well
;
2221 int invert_brightness
;
2222 int enable_cmd_parser
;
2223 /* leave bools at the end to not create holes */
2224 bool enable_hangcheck
;
2226 bool prefault_disable
;
2228 bool disable_display
;
2229 bool disable_vtd_wa
;
2233 extern struct i915_params i915 __read_mostly
;
2236 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2237 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2238 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2239 extern int i915_driver_unload(struct drm_device
*);
2240 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2241 extern void i915_driver_lastclose(struct drm_device
* dev
);
2242 extern void i915_driver_preclose(struct drm_device
*dev
,
2243 struct drm_file
*file
);
2244 extern void i915_driver_postclose(struct drm_device
*dev
,
2245 struct drm_file
*file
);
2246 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2247 #ifdef CONFIG_COMPAT
2248 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2251 extern int i915_emit_box(struct drm_device
*dev
,
2252 struct drm_clip_rect
*box
,
2254 extern int intel_gpu_reset(struct drm_device
*dev
);
2255 extern int i915_reset(struct drm_device
*dev
);
2256 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2257 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2258 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2259 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2260 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2261 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2264 void i915_queue_hangcheck(struct drm_device
*dev
);
2266 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2267 const char *fmt
, ...);
2269 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2271 extern void intel_irq_init(struct drm_device
*dev
);
2272 extern void intel_hpd_init(struct drm_device
*dev
);
2274 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2275 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2276 bool restore_forcewake
);
2277 extern void intel_uncore_init(struct drm_device
*dev
);
2278 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2279 extern void intel_uncore_fini(struct drm_device
*dev
);
2280 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2283 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2287 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2290 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2291 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2294 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2295 struct drm_file
*file_priv
);
2296 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2297 struct drm_file
*file_priv
);
2298 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2299 struct drm_file
*file_priv
);
2300 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2301 struct drm_file
*file_priv
);
2302 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2303 struct drm_file
*file_priv
);
2304 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2305 struct drm_file
*file_priv
);
2306 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2307 struct drm_file
*file_priv
);
2308 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2309 struct drm_file
*file_priv
);
2310 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2311 struct intel_engine_cs
*ring
);
2312 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2313 struct drm_file
*file
,
2314 struct intel_engine_cs
*ring
,
2315 struct drm_i915_gem_object
*obj
);
2316 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2317 struct drm_file
*file
,
2318 struct intel_engine_cs
*ring
,
2319 struct intel_context
*ctx
,
2320 struct drm_i915_gem_execbuffer2
*args
,
2321 struct list_head
*vmas
,
2322 struct drm_i915_gem_object
*batch_obj
,
2323 u64 exec_start
, u32 flags
);
2324 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2325 struct drm_file
*file_priv
);
2326 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2327 struct drm_file
*file_priv
);
2328 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2329 struct drm_file
*file_priv
);
2330 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2331 struct drm_file
*file_priv
);
2332 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2333 struct drm_file
*file_priv
);
2334 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2335 struct drm_file
*file
);
2336 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2337 struct drm_file
*file
);
2338 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2339 struct drm_file
*file_priv
);
2340 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2341 struct drm_file
*file_priv
);
2342 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2343 struct drm_file
*file_priv
);
2344 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2345 struct drm_file
*file_priv
);
2346 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2347 struct drm_file
*file_priv
);
2348 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2349 struct drm_file
*file_priv
);
2350 int i915_gem_init_userptr(struct drm_device
*dev
);
2351 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2352 struct drm_file
*file
);
2353 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2354 struct drm_file
*file_priv
);
2355 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2356 struct drm_file
*file_priv
);
2357 void i915_gem_load(struct drm_device
*dev
);
2358 void *i915_gem_object_alloc(struct drm_device
*dev
);
2359 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2360 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2361 const struct drm_i915_gem_object_ops
*ops
);
2362 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2364 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2365 struct i915_address_space
*vm
);
2366 void i915_gem_free_object(struct drm_gem_object
*obj
);
2367 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2369 #define PIN_MAPPABLE 0x1
2370 #define PIN_NONBLOCK 0x2
2371 #define PIN_GLOBAL 0x4
2372 #define PIN_OFFSET_BIAS 0x8
2373 #define PIN_OFFSET_MASK (~4095)
2374 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2375 struct i915_address_space
*vm
,
2378 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2379 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2380 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2381 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2382 void i915_gem_lastclose(struct drm_device
*dev
);
2384 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2385 int *needs_clflush
);
2387 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2388 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2390 struct sg_page_iter sg_iter
;
2392 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2393 return sg_page_iter_page(&sg_iter
);
2397 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2399 BUG_ON(obj
->pages
== NULL
);
2400 obj
->pages_pin_count
++;
2402 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2404 BUG_ON(obj
->pages_pin_count
== 0);
2405 obj
->pages_pin_count
--;
2408 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2409 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2410 struct intel_engine_cs
*to
);
2411 void i915_vma_move_to_active(struct i915_vma
*vma
,
2412 struct intel_engine_cs
*ring
);
2413 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2414 struct drm_device
*dev
,
2415 struct drm_mode_create_dumb
*args
);
2416 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2417 uint32_t handle
, uint64_t *offset
);
2419 * Returns true if seq1 is later than seq2.
2422 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2424 return (int32_t)(seq1
- seq2
) >= 0;
2427 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2428 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2429 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2430 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2432 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2433 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2435 struct drm_i915_gem_request
*
2436 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2438 bool i915_gem_retire_requests(struct drm_device
*dev
);
2439 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2440 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2441 bool interruptible
);
2442 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2444 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2446 return unlikely(atomic_read(&error
->reset_counter
)
2447 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2450 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2452 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2455 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2457 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2460 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2462 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2463 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2466 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2468 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2469 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2472 void i915_gem_reset(struct drm_device
*dev
);
2473 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2474 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2475 int __must_check
i915_gem_init(struct drm_device
*dev
);
2476 int i915_gem_init_rings(struct drm_device
*dev
);
2477 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2478 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2479 void i915_gem_init_swizzling(struct drm_device
*dev
);
2480 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2481 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2482 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2483 int __i915_add_request(struct intel_engine_cs
*ring
,
2484 struct drm_file
*file
,
2485 struct drm_i915_gem_object
*batch_obj
,
2487 #define i915_add_request(ring, seqno) \
2488 __i915_add_request(ring, NULL, NULL, seqno)
2489 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2491 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2493 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2496 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2498 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2500 struct intel_engine_cs
*pipelined
);
2501 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2502 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2504 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2505 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2508 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2510 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2511 int tiling_mode
, bool fenced
);
2513 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2514 enum i915_cache_level cache_level
);
2516 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2517 struct dma_buf
*dma_buf
);
2519 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2520 struct drm_gem_object
*gem_obj
, int flags
);
2522 void i915_gem_restore_fences(struct drm_device
*dev
);
2524 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2525 struct i915_address_space
*vm
);
2526 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2527 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2528 struct i915_address_space
*vm
);
2529 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2530 struct i915_address_space
*vm
);
2531 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2532 struct i915_address_space
*vm
);
2534 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2535 struct i915_address_space
*vm
);
2537 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2538 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2539 struct i915_vma
*vma
;
2540 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2541 if (vma
->pin_count
> 0)
2546 /* Some GGTT VM helpers */
2547 #define i915_obj_to_ggtt(obj) \
2548 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2549 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2551 struct i915_address_space
*ggtt
=
2552 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2556 static inline struct i915_hw_ppgtt
*
2557 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2559 WARN_ON(i915_is_ggtt(vm
));
2561 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2565 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2567 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2570 static inline unsigned long
2571 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2573 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2576 static inline unsigned long
2577 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2579 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2582 static inline int __must_check
2583 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2587 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2588 alignment
, flags
| PIN_GLOBAL
);
2592 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2594 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2597 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2599 /* i915_gem_context.c */
2600 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2601 void i915_gem_context_fini(struct drm_device
*dev
);
2602 void i915_gem_context_reset(struct drm_device
*dev
);
2603 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2604 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2605 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2606 int i915_switch_context(struct intel_engine_cs
*ring
,
2607 struct intel_context
*to
);
2608 struct intel_context
*
2609 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2610 void i915_gem_context_free(struct kref
*ctx_ref
);
2611 struct drm_i915_gem_object
*
2612 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2613 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2615 kref_get(&ctx
->ref
);
2618 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2620 kref_put(&ctx
->ref
, i915_gem_context_free
);
2623 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2625 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2628 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2629 struct drm_file
*file
);
2630 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2631 struct drm_file
*file
);
2633 /* i915_gem_render_state.c */
2634 int i915_gem_render_state_init(struct intel_engine_cs
*ring
);
2635 /* i915_gem_evict.c */
2636 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2637 struct i915_address_space
*vm
,
2640 unsigned cache_level
,
2641 unsigned long start
,
2644 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2645 int i915_gem_evict_everything(struct drm_device
*dev
);
2647 /* belongs in i915_gem_gtt.h */
2648 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2650 if (INTEL_INFO(dev
)->gen
< 6)
2651 intel_gtt_chipset_flush();
2654 /* i915_gem_stolen.c */
2655 int i915_gem_init_stolen(struct drm_device
*dev
);
2656 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2657 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2658 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2659 struct drm_i915_gem_object
*
2660 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2661 struct drm_i915_gem_object
*
2662 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2667 /* i915_gem_tiling.c */
2668 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2670 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2672 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2673 obj
->tiling_mode
!= I915_TILING_NONE
;
2676 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2677 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2678 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2680 /* i915_gem_debug.c */
2682 int i915_verify_lists(struct drm_device
*dev
);
2684 #define i915_verify_lists(dev) 0
2687 /* i915_debugfs.c */
2688 int i915_debugfs_init(struct drm_minor
*minor
);
2689 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2690 #ifdef CONFIG_DEBUG_FS
2691 void intel_display_crc_init(struct drm_device
*dev
);
2693 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2696 /* i915_gpu_error.c */
2698 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2699 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2700 const struct i915_error_state_file_priv
*error
);
2701 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2702 struct drm_i915_private
*i915
,
2703 size_t count
, loff_t pos
);
2704 static inline void i915_error_state_buf_release(
2705 struct drm_i915_error_state_buf
*eb
)
2709 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2710 const char *error_msg
);
2711 void i915_error_state_get(struct drm_device
*dev
,
2712 struct i915_error_state_file_priv
*error_priv
);
2713 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2714 void i915_destroy_error_state(struct drm_device
*dev
);
2716 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2717 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
2719 /* i915_cmd_parser.c */
2720 int i915_cmd_parser_get_version(void);
2721 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2722 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2723 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2724 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2725 struct drm_i915_gem_object
*batch_obj
,
2726 u32 batch_start_offset
,
2729 /* i915_suspend.c */
2730 extern int i915_save_state(struct drm_device
*dev
);
2731 extern int i915_restore_state(struct drm_device
*dev
);
2734 void i915_save_display_reg(struct drm_device
*dev
);
2735 void i915_restore_display_reg(struct drm_device
*dev
);
2738 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2739 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2742 extern int intel_setup_gmbus(struct drm_device
*dev
);
2743 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2744 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2746 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2749 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2750 struct drm_i915_private
*dev_priv
, unsigned port
);
2751 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2752 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2753 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2755 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2757 extern void intel_i2c_reset(struct drm_device
*dev
);
2759 /* intel_opregion.c */
2760 struct intel_encoder
;
2762 extern int intel_opregion_setup(struct drm_device
*dev
);
2763 extern void intel_opregion_init(struct drm_device
*dev
);
2764 extern void intel_opregion_fini(struct drm_device
*dev
);
2765 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2766 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2768 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2771 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2772 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2773 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2774 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2776 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2781 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2789 extern void intel_register_dsm_handler(void);
2790 extern void intel_unregister_dsm_handler(void);
2792 static inline void intel_register_dsm_handler(void) { return; }
2793 static inline void intel_unregister_dsm_handler(void) { return; }
2794 #endif /* CONFIG_ACPI */
2797 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2798 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2799 extern void intel_modeset_init(struct drm_device
*dev
);
2800 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2801 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2802 extern void intel_connector_unregister(struct intel_connector
*);
2803 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2804 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2805 bool force_restore
);
2806 extern void i915_redisable_vga(struct drm_device
*dev
);
2807 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2808 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2809 extern void gen8_fbc_sw_flush(struct drm_device
*dev
, u32 value
);
2810 extern void intel_disable_fbc(struct drm_device
*dev
);
2811 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2812 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2813 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2814 extern void bdw_software_turbo(struct drm_device
*dev
);
2815 extern void gen8_flip_interrupt(struct drm_device
*dev
);
2816 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2817 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2819 extern void intel_detect_pch(struct drm_device
*dev
);
2820 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2821 extern int intel_enable_rc6(const struct drm_device
*dev
);
2823 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2824 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2825 struct drm_file
*file
);
2826 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2827 struct drm_file
*file
);
2829 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2832 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2833 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2834 struct intel_overlay_error_state
*error
);
2836 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2837 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2838 struct drm_device
*dev
,
2839 struct intel_display_error_state
*error
);
2841 /* On SNB platform, before reading ring registers forcewake bit
2842 * must be set to prevent GT core from power down and stale values being
2845 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2846 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2847 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2849 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2850 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2852 /* intel_sideband.c */
2853 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2854 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2855 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2856 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2857 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2858 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2859 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2860 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2861 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2862 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2863 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2864 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2865 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2866 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2867 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2868 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2869 enum intel_sbi_destination destination
);
2870 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2871 enum intel_sbi_destination destination
);
2872 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2873 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2875 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2876 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2878 #define FORCEWAKE_RENDER (1 << 0)
2879 #define FORCEWAKE_MEDIA (1 << 1)
2880 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2883 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2884 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2886 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2887 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2888 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2889 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2891 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2892 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2893 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2894 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2896 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2897 * will be implemented using 2 32-bit writes in an arbitrary order with
2898 * an arbitrary delay between them. This can cause the hardware to
2899 * act upon the intermediate value, possibly leading to corruption and
2900 * machine death. You have been warned.
2902 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2903 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2905 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2906 u32 upper = I915_READ(upper_reg); \
2907 u32 lower = I915_READ(lower_reg); \
2908 u32 tmp = I915_READ(upper_reg); \
2909 if (upper != tmp) { \
2911 lower = I915_READ(lower_reg); \
2912 WARN_ON(I915_READ(upper_reg) != upper); \
2914 (u64)upper << 32 | lower; })
2916 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2917 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2919 /* "Broadcast RGB" property */
2920 #define INTEL_BROADCAST_RGB_AUTO 0
2921 #define INTEL_BROADCAST_RGB_FULL 1
2922 #define INTEL_BROADCAST_RGB_LIMITED 2
2924 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2926 if (IS_VALLEYVIEW(dev
))
2927 return VLV_VGACNTRL
;
2928 else if (INTEL_INFO(dev
)->gen
>= 5)
2929 return CPU_VGACNTRL
;
2934 static inline void __user
*to_user_ptr(u64 address
)
2936 return (void __user
*)(uintptr_t)address
;
2939 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2941 unsigned long j
= msecs_to_jiffies(m
);
2943 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2946 static inline unsigned long
2947 timespec_to_jiffies_timeout(const struct timespec
*value
)
2949 unsigned long j
= timespec_to_jiffies(value
);
2951 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2955 * If you need to wait X milliseconds between events A and B, but event B
2956 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2957 * when event A happened, then just before event B you call this function and
2958 * pass the timestamp as the first argument, and X as the second argument.
2961 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
2963 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
2966 * Don't re-read the value of "jiffies" every time since it may change
2967 * behind our back and break the math.
2969 tmp_jiffies
= jiffies
;
2970 target_jiffies
= timestamp_jiffies
+
2971 msecs_to_jiffies_timeout(to_wait_ms
);
2973 if (time_after(target_jiffies
, tmp_jiffies
)) {
2974 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
2975 while (remaining_jiffies
)
2977 schedule_timeout_uninterruptible(remaining_jiffies
);