drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <drm/intel-gtt.h>
  40 #include <linux/backlight.h>
  41 #include <linux/intel-iommu.h>
  42
  43 /* General customization:
  44  */
  45
  46 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  47
  48 #define DRIVER_NAME             "i915"
  49 #define DRIVER_DESC             "Intel Graphics"
  50 #define DRIVER_DATE             "20080730"
  51
  52 enum pipe {
  53         PIPE_A = 0,
  54         PIPE_B,
  55         PIPE_C,
  56         I915_MAX_PIPES
  57 };
  58 #define pipe_name(p) ((p) + 'A')
  59
  60 enum plane {
  61         PLANE_A = 0,
  62         PLANE_B,
  63         PLANE_C,
  64 };
  65 #define plane_name(p) ((p) + 'A')
  66
  67 enum port {
  68         PORT_A = 0,
  69         PORT_B,
  70         PORT_C,
  71         PORT_D,
  72         PORT_E,
  73         I915_MAX_PORTS
  74 };
  75 #define port_name(p) ((p) + 'A')
  76
  77 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  78
  79 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  80
  81 struct intel_pch_pll {
  82         int refcount; /* count of number of CRTCs sharing this PLL */
  83         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  84         bool on; /* is the PLL actually active? Disabled during modeset */
  85         int pll_reg;
  86         int fp0_reg;
  87         int fp1_reg;
  88 };
  89 #define I915_NUM_PLLS 2
  90
  91 /* Interface history:
  92  *
  93  * 1.1: Original.
  94  * 1.2: Add Power Management
  95  * 1.3: Add vblank support
  96  * 1.4: Fix cmdbuffer path, add heap destroy
  97  * 1.5: Add vblank pipe configuration
  98  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  99  *      - Support vertical blank on secondary display pipe
 100  */
 101 #define DRIVER_MAJOR            1
 102 #define DRIVER_MINOR            6
 103 #define DRIVER_PATCHLEVEL       0
 104
 105 #define WATCH_COHERENCY 0
 106 #define WATCH_LISTS     0
 107
 108 #define I915_GEM_PHYS_CURSOR_0 1
 109 #define I915_GEM_PHYS_CURSOR_1 2
 110 #define I915_GEM_PHYS_OVERLAY_REGS 3
 111 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 112
 113 struct drm_i915_gem_phys_object {
 114         int id;
 115         struct page **page_list;
 116         drm_dma_handle_t *handle;
 117         struct drm_i915_gem_object *cur_obj;
 118 };
 119
 120 struct mem_block {
 121         struct mem_block *next;
 122         struct mem_block *prev;
 123         int start;
 124         int size;
 125         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 126 };
 127
 128 struct opregion_header;
 129 struct opregion_acpi;
 130 struct opregion_swsci;
 131 struct opregion_asle;
 132 struct drm_i915_private;
 133
 134 struct intel_opregion {
 135         struct opregion_header __iomem *header;
 136         struct opregion_acpi __iomem *acpi;
 137         struct opregion_swsci __iomem *swsci;
 138         struct opregion_asle __iomem *asle;
 139         void __iomem *vbt;
 140         u32 __iomem *lid_state;
 141 };
 142 #define OPREGION_SIZE            (8*1024)
 143
 144 struct intel_overlay;
 145 struct intel_overlay_error_state;
 146
 147 struct drm_i915_master_private {
 148         drm_local_map_t *sarea;
 149         struct _drm_i915_sarea *sarea_priv;
 150 };
 151 #define I915_FENCE_REG_NONE -1
 152 #define I915_MAX_NUM_FENCES 16
 153 /* 16 fences + sign bit for FENCE_REG_NONE */
 154 #define I915_MAX_NUM_FENCE_BITS 5
 155
 156 struct drm_i915_fence_reg {
 157         struct list_head lru_list;
 158         struct drm_i915_gem_object *obj;
 159         int pin_count;
 160 };
 161
 162 struct sdvo_device_mapping {
 163         u8 initialized;
 164         u8 dvo_port;
 165         u8 slave_addr;
 166         u8 dvo_wiring;
 167         u8 i2c_pin;
 168         u8 ddc_pin;
 169 };
 170
 171 struct intel_display_error_state;
 172
 173 struct drm_i915_error_state {
 174         u32 eir;
 175         u32 pgtbl_er;
 176         u32 ier;
 177         bool waiting[I915_NUM_RINGS];
 178         u32 pipestat[I915_MAX_PIPES];
 179         u32 tail[I915_NUM_RINGS];
 180         u32 head[I915_NUM_RINGS];
 181         u32 ipeir[I915_NUM_RINGS];
 182         u32 ipehr[I915_NUM_RINGS];
 183         u32 instdone[I915_NUM_RINGS];
 184         u32 acthd[I915_NUM_RINGS];
 185         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 186         /* our own tracking of ring head and tail */
 187         u32 cpu_ring_head[I915_NUM_RINGS];
 188         u32 cpu_ring_tail[I915_NUM_RINGS];
 189         u32 error; /* gen6+ */
 190         u32 instpm[I915_NUM_RINGS];
 191         u32 instps[I915_NUM_RINGS];
 192         u32 instdone1;
 193         u32 seqno[I915_NUM_RINGS];
 194         u64 bbaddr;
 195         u32 fault_reg[I915_NUM_RINGS];
 196         u32 done_reg;
 197         u32 faddr[I915_NUM_RINGS];
 198         u64 fence[I915_MAX_NUM_FENCES];
 199         struct timeval time;
 200         struct drm_i915_error_ring {
 201                 struct drm_i915_error_object {
 202                         int page_count;
 203                         u32 gtt_offset;
 204                         u32 *pages[0];
 205                 } *ringbuffer, *batchbuffer;
 206                 struct drm_i915_error_request {
 207                         long jiffies;
 208                         u32 seqno;
 209                         u32 tail;
 210                 } *requests;
 211                 int num_requests;
 212         } ring[I915_NUM_RINGS];
 213         struct drm_i915_error_buffer {
 214                 u32 size;
 215                 u32 name;
 216                 u32 seqno;
 217                 u32 gtt_offset;
 218                 u32 read_domains;
 219                 u32 write_domain;
 220                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 221                 s32 pinned:2;
 222                 u32 tiling:2;
 223                 u32 dirty:1;
 224                 u32 purgeable:1;
 225                 s32 ring:4;
 226                 u32 cache_level:2;
 227         } *active_bo, *pinned_bo;
 228         u32 active_bo_count, pinned_bo_count;
 229         struct intel_overlay_error_state *overlay;
 230         struct intel_display_error_state *display;
 231 };
 232
 233 struct drm_i915_display_funcs {
 234         void (*dpms)(struct drm_crtc *crtc, int mode);
 235         bool (*fbc_enabled)(struct drm_device *dev);
 236         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 237         void (*disable_fbc)(struct drm_device *dev);
 238         int (*get_display_clock_speed)(struct drm_device *dev);
 239         int (*get_fifo_size)(struct drm_device *dev, int plane);
 240         void (*update_wm)(struct drm_device *dev);
 241         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 242                                  uint32_t sprite_width, int pixel_size);
 243         void (*sanitize_pm)(struct drm_device *dev);
 244         int (*crtc_mode_set)(struct drm_crtc *crtc,
 245                              struct drm_display_mode *mode,
 246                              struct drm_display_mode *adjusted_mode,
 247                              int x, int y,
 248                              struct drm_framebuffer *old_fb);
 249         void (*off)(struct drm_crtc *crtc);
 250         void (*write_eld)(struct drm_connector *connector,
 251                           struct drm_crtc *crtc);
 252         void (*fdi_link_train)(struct drm_crtc *crtc);
 253         void (*init_clock_gating)(struct drm_device *dev);
 254         void (*init_pch_clock_gating)(struct drm_device *dev);
 255         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 256                           struct drm_framebuffer *fb,
 257                           struct drm_i915_gem_object *obj);
 258         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 259                             int x, int y);
 260         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 261         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 262         /* clock updates for mode set */
 263         /* cursor updates */
 264         /* render clock increase/decrease */
 265         /* display clock increase/decrease */
 266         /* pll clock increase/decrease */
 267 };
 268
 269 struct intel_device_info {
 270         u8 gen;
 271         u8 is_mobile:1;
 272         u8 is_i85x:1;
 273         u8 is_i915g:1;
 274         u8 is_i945gm:1;
 275         u8 is_g33:1;
 276         u8 need_gfx_hws:1;
 277         u8 is_g4x:1;
 278         u8 is_pineview:1;
 279         u8 is_broadwater:1;
 280         u8 is_crestline:1;
 281         u8 is_ivybridge:1;
 282         u8 is_valleyview:1;
 283         u8 has_pch_split:1;
 284         u8 is_haswell:1;
 285         u8 has_fbc:1;
 286         u8 has_pipe_cxsr:1;
 287         u8 has_hotplug:1;
 288         u8 cursor_needs_physical:1;
 289         u8 has_overlay:1;
 290         u8 overlay_needs_physical:1;
 291         u8 supports_tv:1;
 292         u8 has_bsd_ring:1;
 293         u8 has_blt_ring:1;
 294         u8 has_llc:1;
 295 };
 296
 297 #define I915_PPGTT_PD_ENTRIES 512
 298 #define I915_PPGTT_PT_ENTRIES 1024
 299 struct i915_hw_ppgtt {
 300         unsigned num_pd_entries;
 301         struct page **pt_pages;
 302         uint32_t pd_offset;
 303         dma_addr_t *pt_dma_addr;
 304         dma_addr_t scratch_page_dma_addr;
 305 };
 306
 307 enum no_fbc_reason {
 308         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 309         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 310         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 311         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 312         FBC_BAD_PLANE, /* fbc not supported on plane */
 313         FBC_NOT_TILED, /* buffer not tiled */
 314         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 315         FBC_MODULE_PARAM,
 316 };
 317
 318 enum intel_pch {
 319         PCH_IBX,        /* Ibexpeak PCH */
 320         PCH_CPT,        /* Cougarpoint PCH */
 321         PCH_LPT,        /* Lynxpoint PCH */
 322 };
 323
 324 #define QUIRK_PIPEA_FORCE (1<<0)
 325 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 326 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 327
 328 struct intel_fbdev;
 329 struct intel_fbc_work;
 330
 331 struct intel_gmbus {
 332         struct i2c_adapter adapter;
 333         bool force_bit;
 334         u32 reg0;
 335         u32 gpio_reg;
 336         struct i2c_algo_bit_data bit_algo;
 337         struct drm_i915_private *dev_priv;
 338 };
 339
 340 typedef struct drm_i915_private {
 341         struct drm_device *dev;
 342
 343         const struct intel_device_info *info;
 344
 345         int relative_constants_mode;
 346
 347         void __iomem *regs;
 348         /** gt_fifo_count and the subsequent register write are synchronized
 349          * with dev->struct_mutex. */
 350         unsigned gt_fifo_count;
 351         /** forcewake_count is protected by gt_lock */
 352         unsigned forcewake_count;
 353         /** gt_lock is also taken in irq contexts. */
 354         struct spinlock gt_lock;
 355
 356         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
 357
 358         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 359          * controller on different i2c buses. */
 360         struct mutex gmbus_mutex;
 361
 362         /**
 363          * Base address of the gmbus and gpio block.
 364          */
 365         uint32_t gpio_mmio_base;
 366
 367         struct pci_dev *bridge_dev;
 368         struct intel_ring_buffer ring[I915_NUM_RINGS];
 369         uint32_t next_seqno;
 370
 371         drm_dma_handle_t *status_page_dmah;
 372         uint32_t counter;
 373         struct drm_i915_gem_object *pwrctx;
 374         struct drm_i915_gem_object *renderctx;
 375
 376         struct resource mch_res;
 377
 378         unsigned int cpp;
 379         int back_offset;
 380         int front_offset;
 381         int current_page;
 382         int page_flipping;
 383
 384         atomic_t irq_received;
 385
 386         /* protects the irq masks */
 387         spinlock_t irq_lock;
 388
 389         /* DPIO indirect register protection */
 390         spinlock_t dpio_lock;
 391
 392         /** Cached value of IMR to avoid reads in updating the bitfield */
 393         u32 pipestat[2];
 394         u32 irq_mask;
 395         u32 gt_irq_mask;
 396         u32 pch_irq_mask;
 397
 398         u32 hotplug_supported_mask;
 399         struct work_struct hotplug_work;
 400
 401         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 402         int num_pipe;
 403         int num_pch_pll;
 404
 405         /* For hangcheck timer */
 406 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 407         struct timer_list hangcheck_timer;
 408         int hangcheck_count;
 409         uint32_t last_acthd;
 410         uint32_t last_acthd_bsd;
 411         uint32_t last_acthd_blt;
 412         uint32_t last_instdone;
 413         uint32_t last_instdone1;
 414
 415         unsigned int stop_rings;
 416
 417         unsigned long cfb_size;
 418         unsigned int cfb_fb;
 419         enum plane cfb_plane;
 420         int cfb_y;
 421         struct intel_fbc_work *fbc_work;
 422
 423         struct intel_opregion opregion;
 424
 425         /* overlay */
 426         struct intel_overlay *overlay;
 427         bool sprite_scaling_enabled;
 428
 429         /* LVDS info */
 430         int backlight_level;  /* restore backlight to this value */
 431         bool backlight_enabled;
 432         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 433         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 434
 435         /* Feature bits from the VBIOS */
 436         unsigned int int_tv_support:1;
 437         unsigned int lvds_dither:1;
 438         unsigned int lvds_vbt:1;
 439         unsigned int int_crt_support:1;
 440         unsigned int lvds_use_ssc:1;
 441         unsigned int display_clock_mode:1;
 442         int lvds_ssc_freq;
 443         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 444         unsigned int lvds_val; /* used for checking LVDS channel mode */
 445         struct {
 446                 int rate;
 447                 int lanes;
 448                 int preemphasis;
 449                 int vswing;
 450
 451                 bool initialized;
 452                 bool support;
 453                 int bpp;
 454                 struct edp_power_seq pps;
 455         } edp;
 456         bool no_aux_handshake;
 457
 458         struct notifier_block lid_notifier;
 459
 460         int crt_ddc_pin;
 461         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 462         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 463         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 464
 465         unsigned int fsb_freq, mem_freq, is_ddr3;
 466
 467         spinlock_t error_lock;
 468         struct drm_i915_error_state *first_error;
 469         struct work_struct error_work;
 470         struct completion error_completion;
 471         struct workqueue_struct *wq;
 472
 473         /* Display functions */
 474         struct drm_i915_display_funcs display;
 475
 476         /* PCH chipset type */
 477         enum intel_pch pch_type;
 478
 479         unsigned long quirks;
 480
 481         /* Register state */
 482         bool modeset_on_lid;
 483         u8 saveLBB;
 484         u32 saveDSPACNTR;
 485         u32 saveDSPBCNTR;
 486         u32 saveDSPARB;
 487         u32 saveHWS;
 488         u32 savePIPEACONF;
 489         u32 savePIPEBCONF;
 490         u32 savePIPEASRC;
 491         u32 savePIPEBSRC;
 492         u32 saveFPA0;
 493         u32 saveFPA1;
 494         u32 saveDPLL_A;
 495         u32 saveDPLL_A_MD;
 496         u32 saveHTOTAL_A;
 497         u32 saveHBLANK_A;
 498         u32 saveHSYNC_A;
 499         u32 saveVTOTAL_A;
 500         u32 saveVBLANK_A;
 501         u32 saveVSYNC_A;
 502         u32 saveBCLRPAT_A;
 503         u32 saveTRANSACONF;
 504         u32 saveTRANS_HTOTAL_A;
 505         u32 saveTRANS_HBLANK_A;
 506         u32 saveTRANS_HSYNC_A;
 507         u32 saveTRANS_VTOTAL_A;
 508         u32 saveTRANS_VBLANK_A;
 509         u32 saveTRANS_VSYNC_A;
 510         u32 savePIPEASTAT;
 511         u32 saveDSPASTRIDE;
 512         u32 saveDSPASIZE;
 513         u32 saveDSPAPOS;
 514         u32 saveDSPAADDR;
 515         u32 saveDSPASURF;
 516         u32 saveDSPATILEOFF;
 517         u32 savePFIT_PGM_RATIOS;
 518         u32 saveBLC_HIST_CTL;
 519         u32 saveBLC_PWM_CTL;
 520         u32 saveBLC_PWM_CTL2;
 521         u32 saveBLC_CPU_PWM_CTL;
 522         u32 saveBLC_CPU_PWM_CTL2;
 523         u32 saveFPB0;
 524         u32 saveFPB1;
 525         u32 saveDPLL_B;
 526         u32 saveDPLL_B_MD;
 527         u32 saveHTOTAL_B;
 528         u32 saveHBLANK_B;
 529         u32 saveHSYNC_B;
 530         u32 saveVTOTAL_B;
 531         u32 saveVBLANK_B;
 532         u32 saveVSYNC_B;
 533         u32 saveBCLRPAT_B;
 534         u32 saveTRANSBCONF;
 535         u32 saveTRANS_HTOTAL_B;
 536         u32 saveTRANS_HBLANK_B;
 537         u32 saveTRANS_HSYNC_B;
 538         u32 saveTRANS_VTOTAL_B;
 539         u32 saveTRANS_VBLANK_B;
 540         u32 saveTRANS_VSYNC_B;
 541         u32 savePIPEBSTAT;
 542         u32 saveDSPBSTRIDE;
 543         u32 saveDSPBSIZE;
 544         u32 saveDSPBPOS;
 545         u32 saveDSPBADDR;
 546         u32 saveDSPBSURF;
 547         u32 saveDSPBTILEOFF;
 548         u32 saveVGA0;
 549         u32 saveVGA1;
 550         u32 saveVGA_PD;
 551         u32 saveVGACNTRL;
 552         u32 saveADPA;
 553         u32 saveLVDS;
 554         u32 savePP_ON_DELAYS;
 555         u32 savePP_OFF_DELAYS;
 556         u32 saveDVOA;
 557         u32 saveDVOB;
 558         u32 saveDVOC;
 559         u32 savePP_ON;
 560         u32 savePP_OFF;
 561         u32 savePP_CONTROL;
 562         u32 savePP_DIVISOR;
 563         u32 savePFIT_CONTROL;
 564         u32 save_palette_a[256];
 565         u32 save_palette_b[256];
 566         u32 saveDPFC_CB_BASE;
 567         u32 saveFBC_CFB_BASE;
 568         u32 saveFBC_LL_BASE;
 569         u32 saveFBC_CONTROL;
 570         u32 saveFBC_CONTROL2;
 571         u32 saveIER;
 572         u32 saveIIR;
 573         u32 saveIMR;
 574         u32 saveDEIER;
 575         u32 saveDEIMR;
 576         u32 saveGTIER;
 577         u32 saveGTIMR;
 578         u32 saveFDI_RXA_IMR;
 579         u32 saveFDI_RXB_IMR;
 580         u32 saveCACHE_MODE_0;
 581         u32 saveMI_ARB_STATE;
 582         u32 saveSWF0[16];
 583         u32 saveSWF1[16];
 584         u32 saveSWF2[3];
 585         u8 saveMSR;
 586         u8 saveSR[8];
 587         u8 saveGR[25];
 588         u8 saveAR_INDEX;
 589         u8 saveAR[21];
 590         u8 saveDACMASK;
 591         u8 saveCR[37];
 592         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 593         u32 saveCURACNTR;
 594         u32 saveCURAPOS;
 595         u32 saveCURABASE;
 596         u32 saveCURBCNTR;
 597         u32 saveCURBPOS;
 598         u32 saveCURBBASE;
 599         u32 saveCURSIZE;
 600         u32 saveDP_B;
 601         u32 saveDP_C;
 602         u32 saveDP_D;
 603         u32 savePIPEA_GMCH_DATA_M;
 604         u32 savePIPEB_GMCH_DATA_M;
 605         u32 savePIPEA_GMCH_DATA_N;
 606         u32 savePIPEB_GMCH_DATA_N;
 607         u32 savePIPEA_DP_LINK_M;
 608         u32 savePIPEB_DP_LINK_M;
 609         u32 savePIPEA_DP_LINK_N;
 610         u32 savePIPEB_DP_LINK_N;
 611         u32 saveFDI_RXA_CTL;
 612         u32 saveFDI_TXA_CTL;
 613         u32 saveFDI_RXB_CTL;
 614         u32 saveFDI_TXB_CTL;
 615         u32 savePFA_CTL_1;
 616         u32 savePFB_CTL_1;
 617         u32 savePFA_WIN_SZ;
 618         u32 savePFB_WIN_SZ;
 619         u32 savePFA_WIN_POS;
 620         u32 savePFB_WIN_POS;
 621         u32 savePCH_DREF_CONTROL;
 622         u32 saveDISP_ARB_CTL;
 623         u32 savePIPEA_DATA_M1;
 624         u32 savePIPEA_DATA_N1;
 625         u32 savePIPEA_LINK_M1;
 626         u32 savePIPEA_LINK_N1;
 627         u32 savePIPEB_DATA_M1;
 628         u32 savePIPEB_DATA_N1;
 629         u32 savePIPEB_LINK_M1;
 630         u32 savePIPEB_LINK_N1;
 631         u32 saveMCHBAR_RENDER_STANDBY;
 632         u32 savePCH_PORT_HOTPLUG;
 633
 634         struct {
 635                 /** Bridge to intel-gtt-ko */
 636                 const struct intel_gtt *gtt;
 637                 /** Memory allocator for GTT stolen memory */
 638                 struct drm_mm stolen;
 639                 /** Memory allocator for GTT */
 640                 struct drm_mm gtt_space;
 641                 /** List of all objects in gtt_space. Used to restore gtt
 642                  * mappings on resume */
 643                 struct list_head gtt_list;
 644
 645                 /** Usable portion of the GTT for GEM */
 646                 unsigned long gtt_start;
 647                 unsigned long gtt_mappable_end;
 648                 unsigned long gtt_end;
 649
 650                 struct io_mapping *gtt_mapping;
 651                 int gtt_mtrr;
 652
 653                 /** PPGTT used for aliasing the PPGTT with the GTT */
 654                 struct i915_hw_ppgtt *aliasing_ppgtt;
 655
 656                 struct shrinker inactive_shrinker;
 657
 658                 /**
 659                  * List of objects currently involved in rendering.
 660                  *
 661                  * Includes buffers having the contents of their GPU caches
 662                  * flushed, not necessarily primitives.  last_rendering_seqno
 663                  * represents when the rendering involved will be completed.
 664                  *
 665                  * A reference is held on the buffer while on this list.
 666                  */
 667                 struct list_head active_list;
 668
 669                 /**
 670                  * List of objects which are not in the ringbuffer but which
 671                  * still have a write_domain which needs to be flushed before
 672                  * unbinding.
 673                  *
 674                  * last_rendering_seqno is 0 while an object is in this list.
 675                  *
 676                  * A reference is held on the buffer while on this list.
 677                  */
 678                 struct list_head flushing_list;
 679
 680                 /**
 681                  * LRU list of objects which are not in the ringbuffer and
 682                  * are ready to unbind, but are still in the GTT.
 683                  *
 684                  * last_rendering_seqno is 0 while an object is in this list.
 685                  *
 686                  * A reference is not held on the buffer while on this list,
 687                  * as merely being GTT-bound shouldn't prevent its being
 688                  * freed, and we'll pull it off the list in the free path.
 689                  */
 690                 struct list_head inactive_list;
 691
 692                 /** LRU list of objects with fence regs on them. */
 693                 struct list_head fence_list;
 694
 695                 /**
 696                  * We leave the user IRQ off as much as possible,
 697                  * but this means that requests will finish and never
 698                  * be retired once the system goes idle. Set a timer to
 699                  * fire periodically while the ring is running. When it
 700                  * fires, go retire requests.
 701                  */
 702                 struct delayed_work retire_work;
 703
 704                 /**
 705                  * Are we in a non-interruptible section of code like
 706                  * modesetting?
 707                  */
 708                 bool interruptible;
 709
 710                 /**
 711                  * Flag if the X Server, and thus DRM, is not currently in
 712                  * control of the device.
 713                  *
 714                  * This is set between LeaveVT and EnterVT.  It needs to be
 715                  * replaced with a semaphore.  It also needs to be
 716                  * transitioned away from for kernel modesetting.
 717                  */
 718                 int suspended;
 719
 720                 /**
 721                  * Flag if the hardware appears to be wedged.
 722                  *
 723                  * This is set when attempts to idle the device timeout.
 724                  * It prevents command submission from occurring and makes
 725                  * every pending request fail
 726                  */
 727                 atomic_t wedged;
 728
 729                 /** Bit 6 swizzling required for X tiling */
 730                 uint32_t bit_6_swizzle_x;
 731                 /** Bit 6 swizzling required for Y tiling */
 732                 uint32_t bit_6_swizzle_y;
 733
 734                 /* storage for physical objects */
 735                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 736
 737                 /* accounting, useful for userland debugging */
 738                 size_t gtt_total;
 739                 size_t mappable_gtt_total;
 740                 size_t object_memory;
 741                 u32 object_count;
 742         } mm;
 743
 744         /* Old dri1 support infrastructure, beware the dragons ya fools entering
 745          * here! */
 746         struct {
 747                 unsigned allow_batchbuffer : 1;
 748                 u32 __iomem *gfx_hws_cpu_addr;
 749         } dri1;
 750
 751         /* Kernel Modesetting */
 752
 753         struct sdvo_device_mapping sdvo_mappings[2];
 754         /* indicate whether the LVDS_BORDER should be enabled or not */
 755         unsigned int lvds_border_bits;
 756         /* Panel fitter placement and size for Ironlake+ */
 757         u32 pch_pf_pos, pch_pf_size;
 758
 759         struct drm_crtc *plane_to_crtc_mapping[3];
 760         struct drm_crtc *pipe_to_crtc_mapping[3];
 761         wait_queue_head_t pending_flip_queue;
 762
 763         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
 764
 765         /* Reclocking support */
 766         bool render_reclock_avail;
 767         bool lvds_downclock_avail;
 768         /* indicates the reduced downclock for LVDS*/
 769         int lvds_downclock;
 770         struct work_struct idle_work;
 771         struct timer_list idle_timer;
 772         bool busy;
 773         u16 orig_clock;
 774         int child_dev_num;
 775         struct child_device_config *child_dev;
 776         struct drm_connector *int_lvds_connector;
 777         struct drm_connector *int_edp_connector;
 778
 779         bool mchbar_need_disable;
 780
 781         struct work_struct rps_work;
 782         spinlock_t rps_lock;
 783         u32 pm_iir;
 784
 785         u8 cur_delay;
 786         u8 min_delay;
 787         u8 max_delay;
 788         u8 fmax;
 789         u8 fstart;
 790
 791         u64 last_count1;
 792         unsigned long last_time1;
 793         unsigned long chipset_power;
 794         u64 last_count2;
 795         struct timespec last_time2;
 796         unsigned long gfx_power;
 797         int c_m;
 798         int r_t;
 799         u8 corr;
 800         spinlock_t *mchdev_lock;
 801
 802         enum no_fbc_reason no_fbc_reason;
 803
 804         struct drm_mm_node *compressed_fb;
 805         struct drm_mm_node *compressed_llb;
 806
 807         unsigned long last_gpu_reset;
 808
 809         /* list of fbdev register on this device */
 810         struct intel_fbdev *fbdev;
 811
 812         struct backlight_device *backlight;
 813
 814         struct drm_property *broadcast_rgb_property;
 815         struct drm_property *force_audio_property;
 816 } drm_i915_private_t;
 817
 818 enum hdmi_force_audio {
 819         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
 820         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
 821         HDMI_AUDIO_AUTO,                /* trust EDID */
 822         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 823 };
 824
 825 enum i915_cache_level {
 826         I915_CACHE_NONE,
 827         I915_CACHE_LLC,
 828         I915_CACHE_LLC_MLC, /* gen6+ */
 829 };
 830
 831 struct drm_i915_gem_object {
 832         struct drm_gem_object base;
 833
 834         /** Current space allocated to this object in the GTT, if any. */
 835         struct drm_mm_node *gtt_space;
 836         struct list_head gtt_list;
 837
 838         /** This object's place on the active/flushing/inactive lists */
 839         struct list_head ring_list;
 840         struct list_head mm_list;
 841         /** This object's place on GPU write list */
 842         struct list_head gpu_write_list;
 843         /** This object's place in the batchbuffer or on the eviction list */
 844         struct list_head exec_list;
 845
 846         /**
 847          * This is set if the object is on the active or flushing lists
 848          * (has pending rendering), and is not set if it's on inactive (ready
 849          * to be unbound).
 850          */
 851         unsigned int active:1;
 852
 853         /**
 854          * This is set if the object has been written to since last bound
 855          * to the GTT
 856          */
 857         unsigned int dirty:1;
 858
 859         /**
 860          * This is set if the object has been written to since the last
 861          * GPU flush.
 862          */
 863         unsigned int pending_gpu_write:1;
 864
 865         /**
 866          * Fence register bits (if any) for this object.  Will be set
 867          * as needed when mapped into the GTT.
 868          * Protected by dev->struct_mutex.
 869          */
 870         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 871
 872         /**
 873          * Advice: are the backing pages purgeable?
 874          */
 875         unsigned int madv:2;
 876
 877         /**
 878          * Current tiling mode for the object.
 879          */
 880         unsigned int tiling_mode:2;
 881         /**
 882          * Whether the tiling parameters for the currently associated fence
 883          * register have changed. Note that for the purposes of tracking
 884          * tiling changes we also treat the unfenced register, the register
 885          * slot that the object occupies whilst it executes a fenced
 886          * command (such as BLT on gen2/3), as a "fence".
 887          */
 888         unsigned int fence_dirty:1;
 889
 890         /** How many users have pinned this object in GTT space. The following
 891          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 892          * (via user_pin_count), execbuffer (objects are not allowed multiple
 893          * times for the same batchbuffer), and the framebuffer code. When
 894          * switching/pageflipping, the framebuffer code has at most two buffers
 895          * pinned per crtc.
 896          *
 897          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 898          * bits with absolutely no headroom. So use 4 bits. */
 899         unsigned int pin_count:4;
 900 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 901
 902         /**
 903          * Is the object at the current location in the gtt mappable and
 904          * fenceable? Used to avoid costly recalculations.
 905          */
 906         unsigned int map_and_fenceable:1;
 907
 908         /**
 909          * Whether the current gtt mapping needs to be mappable (and isn't just
 910          * mappable by accident). Track pin and fault separate for a more
 911          * accurate mappable working set.
 912          */
 913         unsigned int fault_mappable:1;
 914         unsigned int pin_mappable:1;
 915
 916         /*
 917          * Is the GPU currently using a fence to access this buffer,
 918          */
 919         unsigned int pending_fenced_gpu_access:1;
 920         unsigned int fenced_gpu_access:1;
 921
 922         unsigned int cache_level:2;
 923
 924         unsigned int has_aliasing_ppgtt_mapping:1;
 925         unsigned int has_global_gtt_mapping:1;
 926
 927         struct page **pages;
 928
 929         /**
 930          * DMAR support
 931          */
 932         struct scatterlist *sg_list;
 933         int num_sg;
 934
 935         /**
 936          * Used for performing relocations during execbuffer insertion.
 937          */
 938         struct hlist_node exec_node;
 939         unsigned long exec_handle;
 940         struct drm_i915_gem_exec_object2 *exec_entry;
 941
 942         /**
 943          * Current offset of the object in GTT space.
 944          *
 945          * This is the same as gtt_space->start
 946          */
 947         uint32_t gtt_offset;
 948
 949         struct intel_ring_buffer *ring;
 950
 951         /** Breadcrumb of last rendering to the buffer. */
 952         uint32_t last_rendering_seqno;
 953         /** Breadcrumb of last fenced GPU access to the buffer. */
 954         uint32_t last_fenced_seqno;
 955
 956         /** Current tiling stride for the object, if it's tiled. */
 957         uint32_t stride;
 958
 959         /** Record of address bit 17 of each page at last unbind. */
 960         unsigned long *bit_17;
 961
 962         /** User space pin count and filp owning the pin */
 963         uint32_t user_pin_count;
 964         struct drm_file *pin_filp;
 965
 966         /** for phy allocated objects */
 967         struct drm_i915_gem_phys_object *phys_obj;
 968
 969         /**
 970          * Number of crtcs where this object is currently the fb, but
 971          * will be page flipped away on the next vblank.  When it
 972          * reaches 0, dev_priv->pending_flip_queue will be woken up.
 973          */
 974         atomic_t pending_flip;
 975 };
 976
 977 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 978
 979 /**
 980  * Request queue structure.
 981  *
 982  * The request queue allows us to note sequence numbers that have been emitted
 983  * and may be associated with active buffers to be retired.
 984  *
 985  * By keeping this list, we can avoid having to do questionable
 986  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 987  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 988  */
 989 struct drm_i915_gem_request {
 990         /** On Which ring this request was generated */
 991         struct intel_ring_buffer *ring;
 992
 993         /** GEM sequence number associated with this request. */
 994         uint32_t seqno;
 995
 996         /** Postion in the ringbuffer of the end of the request */
 997         u32 tail;
 998
 999         /** Time at which this request was emitted, in jiffies. */
1000         unsigned long emitted_jiffies;
1001
1002         /** global list entry for this request */
1003         struct list_head list;
1004
1005         struct drm_i915_file_private *file_priv;
1006         /** file_priv list entry for this request */
1007         struct list_head client_list;
1008 };
1009
1010 struct drm_i915_file_private {
1011         struct {
1012                 struct spinlock lock;
1013                 struct list_head request_list;
1014         } mm;
1015 };
1016
1017 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1018
1019 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1020 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1021 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1022 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1023 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1024 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1025 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1026 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1027 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1028 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1029 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1030 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1031 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1032 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1033 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1034 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1035 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1036 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1037 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1038 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1039 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1040 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1041
1042 /*
1043  * The genX designation typically refers to the render engine, so render
1044  * capability related checks should use IS_GEN, while display and other checks
1045  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1046  * chips, etc.).
1047  */
1048 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1049 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1050 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1051 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1052 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1053 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1054
1055 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1056 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1057 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1058 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1059
1060 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1061
1062 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1063 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1064
1065 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1066  * rows, which changed the alignment requirements and fence programming.
1067  */
1068 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1069                                                       IS_I915GM(dev)))
1070 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1071 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1072 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1073 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1074 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1075 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1076 /* dsparb controlled by hw only */
1077 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1078
1079 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1080 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1081 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1082
1083 #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
1084 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1085
1086 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1087 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1088 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1089 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1090
1091 #include "i915_trace.h"
1092
1093 /**
1094  * RC6 is a special power stage which allows the GPU to enter an very
1095  * low-voltage mode when idle, using down to 0V while at this stage.  This
1096  * stage is entered automatically when the GPU is idle when RC6 support is
1097  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1098  *
1099  * There are different RC6 modes available in Intel GPU, which differentiate
1100  * among each other with the latency required to enter and leave RC6 and
1101  * voltage consumed by the GPU in different states.
1102  *
1103  * The combination of the following flags define which states GPU is allowed
1104  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1105  * RC6pp is deepest RC6. Their support by hardware varies according to the
1106  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1107  * which brings the most power savings; deeper states save more power, but
1108  * require higher latency to switch to and wake up.
1109  */
1110 #define INTEL_RC6_ENABLE                        (1<<0)
1111 #define INTEL_RC6p_ENABLE                       (1<<1)
1112 #define INTEL_RC6pp_ENABLE                      (1<<2)
1113
1114 extern struct drm_ioctl_desc i915_ioctls[];
1115 extern int i915_max_ioctl;
1116 extern unsigned int i915_fbpercrtc __always_unused;
1117 extern int i915_panel_ignore_lid __read_mostly;
1118 extern unsigned int i915_powersave __read_mostly;
1119 extern int i915_semaphores __read_mostly;
1120 extern unsigned int i915_lvds_downclock __read_mostly;
1121 extern int i915_lvds_channel_mode __read_mostly;
1122 extern int i915_panel_use_ssc __read_mostly;
1123 extern int i915_vbt_sdvo_panel_type __read_mostly;
1124 extern int i915_enable_rc6 __read_mostly;
1125 extern int i915_enable_fbc __read_mostly;
1126 extern bool i915_enable_hangcheck __read_mostly;
1127 extern int i915_enable_ppgtt __read_mostly;
1128
1129 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1130 extern int i915_resume(struct drm_device *dev);
1131 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1132 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1133
1134                                 /* i915_dma.c */
1135 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1136 extern void i915_kernel_lost_context(struct drm_device * dev);
1137 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1138 extern int i915_driver_unload(struct drm_device *);
1139 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1140 extern void i915_driver_lastclose(struct drm_device * dev);
1141 extern void i915_driver_preclose(struct drm_device *dev,
1142                                  struct drm_file *file_priv);
1143 extern void i915_driver_postclose(struct drm_device *dev,
1144                                   struct drm_file *file_priv);
1145 extern int i915_driver_device_is_agp(struct drm_device * dev);
1146 #ifdef CONFIG_COMPAT
1147 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1148                               unsigned long arg);
1149 #endif
1150 extern int i915_emit_box(struct drm_device *dev,
1151                          struct drm_clip_rect *box,
1152                          int DR1, int DR4);
1153 extern int i915_reset(struct drm_device *dev, u8 flags);
1154 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1155 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1156 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1157 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1158
1159
1160 /* i915_irq.c */
1161 void i915_hangcheck_elapsed(unsigned long data);
1162 void i915_handle_error(struct drm_device *dev, bool wedged);
1163
1164 extern void intel_irq_init(struct drm_device *dev);
1165
1166 void
1167 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1168
1169 void
1170 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1171
1172 void intel_enable_asle(struct drm_device *dev);
1173
1174 #ifdef CONFIG_DEBUG_FS
1175 extern void i915_destroy_error_state(struct drm_device *dev);
1176 #else
1177 #define i915_destroy_error_state(x)
1178 #endif
1179
1180
1181 /* i915_gem.c */
1182 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1183                         struct drm_file *file_priv);
1184 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1185                           struct drm_file *file_priv);
1186 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1187                          struct drm_file *file_priv);
1188 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1189                           struct drm_file *file_priv);
1190 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1191                         struct drm_file *file_priv);
1192 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1193                         struct drm_file *file_priv);
1194 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1195                               struct drm_file *file_priv);
1196 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1197                              struct drm_file *file_priv);
1198 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1199                         struct drm_file *file_priv);
1200 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1201                          struct drm_file *file_priv);
1202 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1203                        struct drm_file *file_priv);
1204 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1205                          struct drm_file *file_priv);
1206 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1207                         struct drm_file *file_priv);
1208 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1209                             struct drm_file *file_priv);
1210 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1211                            struct drm_file *file_priv);
1212 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1213                            struct drm_file *file_priv);
1214 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1215                            struct drm_file *file_priv);
1216 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1217                         struct drm_file *file_priv);
1218 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1219                         struct drm_file *file_priv);
1220 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1221                                 struct drm_file *file_priv);
1222 void i915_gem_load(struct drm_device *dev);
1223 int i915_gem_init_object(struct drm_gem_object *obj);
1224 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1225                                      uint32_t invalidate_domains,
1226                                      uint32_t flush_domains);
1227 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1228                                                   size_t size);
1229 void i915_gem_free_object(struct drm_gem_object *obj);
1230 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1231                                      uint32_t alignment,
1232                                      bool map_and_fenceable);
1233 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1234 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1235 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1236 void i915_gem_lastclose(struct drm_device *dev);
1237
1238 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1239 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1240 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1241                          struct intel_ring_buffer *to);
1242 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1243                                     struct intel_ring_buffer *ring,
1244                                     u32 seqno);
1245
1246 int i915_gem_dumb_create(struct drm_file *file_priv,
1247                          struct drm_device *dev,
1248                          struct drm_mode_create_dumb *args);
1249 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1250                       uint32_t handle, uint64_t *offset);
1251 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1252                           uint32_t handle);
1253 /**
1254  * Returns true if seq1 is later than seq2.
1255  */
1256 static inline bool
1257 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1258 {
1259         return (int32_t)(seq1 - seq2) >= 0;
1260 }
1261
1262 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1263
1264 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1265 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1266
1267 static inline bool
1268 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1269 {
1270         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1271                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1272                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1273                 return true;
1274         } else
1275                 return false;
1276 }
1277
1278 static inline void
1279 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1280 {
1281         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1282                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1283                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1284         }
1285 }
1286
1287 void i915_gem_retire_requests(struct drm_device *dev);
1288 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1289
1290 void i915_gem_reset(struct drm_device *dev);
1291 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1292 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1293                                             uint32_t read_domains,
1294                                             uint32_t write_domain);
1295 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1296 int __must_check i915_gem_init(struct drm_device *dev);
1297 int __must_check i915_gem_init_hw(struct drm_device *dev);
1298 void i915_gem_init_swizzling(struct drm_device *dev);
1299 void i915_gem_init_ppgtt(struct drm_device *dev);
1300 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1301 int __must_check i915_gpu_idle(struct drm_device *dev);
1302 int __must_check i915_gem_idle(struct drm_device *dev);
1303 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1304                                   struct drm_file *file,
1305                                   struct drm_i915_gem_request *request);
1306 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1307                                    uint32_t seqno);
1308 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1309 int __must_check
1310 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1311                                   bool write);
1312 int __must_check
1313 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1314 int __must_check
1315 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1316                                      u32 alignment,
1317                                      struct intel_ring_buffer *pipelined);
1318 int i915_gem_attach_phys_object(struct drm_device *dev,
1319                                 struct drm_i915_gem_object *obj,
1320                                 int id,
1321                                 int align);
1322 void i915_gem_detach_phys_object(struct drm_device *dev,
1323                                  struct drm_i915_gem_object *obj);
1324 void i915_gem_free_all_phys_object(struct drm_device *dev);
1325 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1326
1327 uint32_t
1328 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1329                                     uint32_t size,
1330                                     int tiling_mode);
1331
1332 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1333                                     enum i915_cache_level cache_level);
1334
1335 /* i915_gem_gtt.c */
1336 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1337 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1338 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1339                             struct drm_i915_gem_object *obj,
1340                             enum i915_cache_level cache_level);
1341 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1342                               struct drm_i915_gem_object *obj);
1343
1344 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1345 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1346 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1347                                 enum i915_cache_level cache_level);
1348 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1349 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1350 void i915_gem_init_global_gtt(struct drm_device *dev,
1351                               unsigned long start,
1352                               unsigned long mappable_end,
1353                               unsigned long end);
1354
1355 /* i915_gem_evict.c */
1356 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1357                                           unsigned alignment, bool mappable);
1358 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1359
1360 /* i915_gem_stolen.c */
1361 int i915_gem_init_stolen(struct drm_device *dev);
1362 void i915_gem_cleanup_stolen(struct drm_device *dev);
1363
1364 /* i915_gem_tiling.c */
1365 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1366 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1367 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1368
1369 /* i915_gem_debug.c */
1370 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1371                           const char *where, uint32_t mark);
1372 #if WATCH_LISTS
1373 int i915_verify_lists(struct drm_device *dev);
1374 #else
1375 #define i915_verify_lists(dev) 0
1376 #endif
1377 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1378                                      int handle);
1379 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1380                           const char *where, uint32_t mark);
1381
1382 /* i915_debugfs.c */
1383 int i915_debugfs_init(struct drm_minor *minor);
1384 void i915_debugfs_cleanup(struct drm_minor *minor);
1385
1386 /* i915_suspend.c */
1387 extern int i915_save_state(struct drm_device *dev);
1388 extern int i915_restore_state(struct drm_device *dev);
1389
1390 /* i915_suspend.c */
1391 extern int i915_save_state(struct drm_device *dev);
1392 extern int i915_restore_state(struct drm_device *dev);
1393
1394 /* i915_sysfs.c */
1395 void i915_setup_sysfs(struct drm_device *dev_priv);
1396 void i915_teardown_sysfs(struct drm_device *dev_priv);
1397
1398 /* intel_i2c.c */
1399 extern int intel_setup_gmbus(struct drm_device *dev);
1400 extern void intel_teardown_gmbus(struct drm_device *dev);
1401 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1402 {
1403         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1404 }
1405
1406 extern struct i2c_adapter *intel_gmbus_get_adapter(
1407                 struct drm_i915_private *dev_priv, unsigned port);
1408 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1409 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1410 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1411 {
1412         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1413 }
1414 extern void intel_i2c_reset(struct drm_device *dev);
1415
1416 /* intel_opregion.c */
1417 extern int intel_opregion_setup(struct drm_device *dev);
1418 #ifdef CONFIG_ACPI
1419 extern void intel_opregion_init(struct drm_device *dev);
1420 extern void intel_opregion_fini(struct drm_device *dev);
1421 extern void intel_opregion_asle_intr(struct drm_device *dev);
1422 extern void intel_opregion_gse_intr(struct drm_device *dev);
1423 extern void intel_opregion_enable_asle(struct drm_device *dev);
1424 #else
1425 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1426 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1427 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1428 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1429 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1430 #endif
1431
1432 /* intel_acpi.c */
1433 #ifdef CONFIG_ACPI
1434 extern void intel_register_dsm_handler(void);
1435 extern void intel_unregister_dsm_handler(void);
1436 #else
1437 static inline void intel_register_dsm_handler(void) { return; }
1438 static inline void intel_unregister_dsm_handler(void) { return; }
1439 #endif /* CONFIG_ACPI */
1440
1441 /* modesetting */
1442 extern void intel_modeset_init_hw(struct drm_device *dev);
1443 extern void intel_modeset_init(struct drm_device *dev);
1444 extern void intel_modeset_gem_init(struct drm_device *dev);
1445 extern void intel_modeset_cleanup(struct drm_device *dev);
1446 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1447 extern bool intel_fbc_enabled(struct drm_device *dev);
1448 extern void intel_disable_fbc(struct drm_device *dev);
1449 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1450 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1451 extern void ironlake_enable_rc6(struct drm_device *dev);
1452 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1453 extern void intel_detect_pch(struct drm_device *dev);
1454 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1455 extern int intel_enable_rc6(const struct drm_device *dev);
1456
1457 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1458 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1459 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1460 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1461 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1462
1463 extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
1464 extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
1465
1466 /* overlay */
1467 #ifdef CONFIG_DEBUG_FS
1468 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1469 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1470
1471 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1472 extern void intel_display_print_error_state(struct seq_file *m,
1473                                             struct drm_device *dev,
1474                                             struct intel_display_error_state *error);
1475 #endif
1476
1477 /* On SNB platform, before reading ring registers forcewake bit
1478  * must be set to prevent GT core from power down and stale values being
1479  * returned.
1480  */
1481 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1482 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1483 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1484
1485 #define __i915_read(x, y) \
1486         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1487
1488 __i915_read(8, b)
1489 __i915_read(16, w)
1490 __i915_read(32, l)
1491 __i915_read(64, q)
1492 #undef __i915_read
1493
1494 #define __i915_write(x, y) \
1495         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1496
1497 __i915_write(8, b)
1498 __i915_write(16, w)
1499 __i915_write(32, l)
1500 __i915_write(64, q)
1501 #undef __i915_write
1502
1503 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1504 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1505
1506 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1507 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1508 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1509 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1510
1511 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1512 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1513 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1514 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1515
1516 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1517 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1518
1519 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1520 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1521
1522
1523 #endif