drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include "i915_reg.h"
  36 #include "intel_bios.h"
  37 #include "intel_ringbuffer.h"
  38 #include <linux/io-mapping.h>
  39 #include <linux/i2c.h>
  40 #include <linux/i2c-algo-bit.h>
  41 #include <drm/intel-gtt.h>
  42 #include <linux/backlight.h>
  43 #include <linux/intel-iommu.h>
  44 #include <linux/kref.h>
  45 #include <linux/pm_qos.h>
  46
  47 /* General customization:
  48  */
  49
  50 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  51
  52 #define DRIVER_NAME             "i915"
  53 #define DRIVER_DESC             "Intel Graphics"
  54 #define DRIVER_DATE             "20080730"
  55
  56 enum pipe {
  57         PIPE_A = 0,
  58         PIPE_B,
  59         PIPE_C,
  60         I915_MAX_PIPES
  61 };
  62 #define pipe_name(p) ((p) + 'A')
  63
  64 enum transcoder {
  65         TRANSCODER_A = 0,
  66         TRANSCODER_B,
  67         TRANSCODER_C,
  68         TRANSCODER_EDP = 0xF,
  69 };
  70 #define transcoder_name(t) ((t) + 'A')
  71
  72 enum plane {
  73         PLANE_A = 0,
  74         PLANE_B,
  75         PLANE_C,
  76 };
  77 #define plane_name(p) ((p) + 'A')
  78
  79 enum port {
  80         PORT_A = 0,
  81         PORT_B,
  82         PORT_C,
  83         PORT_D,
  84         PORT_E,
  85         I915_MAX_PORTS
  86 };
  87 #define port_name(p) ((p) + 'A')
  88
  89 #define I915_GEM_GPU_DOMAINS \
  90         (I915_GEM_DOMAIN_RENDER | \
  91          I915_GEM_DOMAIN_SAMPLER | \
  92          I915_GEM_DOMAIN_COMMAND | \
  93          I915_GEM_DOMAIN_INSTRUCTION | \
  94          I915_GEM_DOMAIN_VERTEX)
  95
  96 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
  97
  98 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
  99         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 100                 if ((intel_encoder)->base.crtc == (__crtc))
 101
 102 struct intel_pch_pll {
 103         int refcount; /* count of number of CRTCs sharing this PLL */
 104         int active; /* count of number of active CRTCs (i.e. DPMS on) */
 105         bool on; /* is the PLL actually active? Disabled during modeset */
 106         int pll_reg;
 107         int fp0_reg;
 108         int fp1_reg;
 109 };
 110 #define I915_NUM_PLLS 2
 111
 112 /* Used by dp and fdi links */
 113 struct intel_link_m_n {
 114         uint32_t        tu;
 115         uint32_t        gmch_m;
 116         uint32_t        gmch_n;
 117         uint32_t        link_m;
 118         uint32_t        link_n;
 119 };
 120
 121 void intel_link_compute_m_n(int bpp, int nlanes,
 122                             int pixel_clock, int link_clock,
 123                             struct intel_link_m_n *m_n);
 124
 125 struct intel_ddi_plls {
 126         int spll_refcount;
 127         int wrpll1_refcount;
 128         int wrpll2_refcount;
 129 };
 130
 131 /* Interface history:
 132  *
 133  * 1.1: Original.
 134  * 1.2: Add Power Management
 135  * 1.3: Add vblank support
 136  * 1.4: Fix cmdbuffer path, add heap destroy
 137  * 1.5: Add vblank pipe configuration
 138  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 139  *      - Support vertical blank on secondary display pipe
 140  */
 141 #define DRIVER_MAJOR            1
 142 #define DRIVER_MINOR            6
 143 #define DRIVER_PATCHLEVEL       0
 144
 145 #define WATCH_COHERENCY 0
 146 #define WATCH_LISTS     0
 147 #define WATCH_GTT       0
 148
 149 #define I915_GEM_PHYS_CURSOR_0 1
 150 #define I915_GEM_PHYS_CURSOR_1 2
 151 #define I915_GEM_PHYS_OVERLAY_REGS 3
 152 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 153
 154 struct drm_i915_gem_phys_object {
 155         int id;
 156         struct page **page_list;
 157         drm_dma_handle_t *handle;
 158         struct drm_i915_gem_object *cur_obj;
 159 };
 160
 161 struct opregion_header;
 162 struct opregion_acpi;
 163 struct opregion_swsci;
 164 struct opregion_asle;
 165 struct drm_i915_private;
 166
 167 struct intel_opregion {
 168         struct opregion_header __iomem *header;
 169         struct opregion_acpi __iomem *acpi;
 170         struct opregion_swsci __iomem *swsci;
 171         struct opregion_asle __iomem *asle;
 172         void __iomem *vbt;
 173         u32 __iomem *lid_state;
 174 };
 175 #define OPREGION_SIZE            (8*1024)
 176
 177 struct intel_overlay;
 178 struct intel_overlay_error_state;
 179
 180 struct drm_i915_master_private {
 181         drm_local_map_t *sarea;
 182         struct _drm_i915_sarea *sarea_priv;
 183 };
 184 #define I915_FENCE_REG_NONE -1
 185 #define I915_MAX_NUM_FENCES 16
 186 /* 16 fences + sign bit for FENCE_REG_NONE */
 187 #define I915_MAX_NUM_FENCE_BITS 5
 188
 189 struct drm_i915_fence_reg {
 190         struct list_head lru_list;
 191         struct drm_i915_gem_object *obj;
 192         int pin_count;
 193 };
 194
 195 struct sdvo_device_mapping {
 196         u8 initialized;
 197         u8 dvo_port;
 198         u8 slave_addr;
 199         u8 dvo_wiring;
 200         u8 i2c_pin;
 201         u8 ddc_pin;
 202 };
 203
 204 struct intel_display_error_state;
 205
 206 struct drm_i915_error_state {
 207         struct kref ref;
 208         u32 eir;
 209         u32 pgtbl_er;
 210         u32 ier;
 211         u32 ccid;
 212         u32 derrmr;
 213         u32 forcewake;
 214         bool waiting[I915_NUM_RINGS];
 215         u32 pipestat[I915_MAX_PIPES];
 216         u32 tail[I915_NUM_RINGS];
 217         u32 head[I915_NUM_RINGS];
 218         u32 ctl[I915_NUM_RINGS];
 219         u32 ipeir[I915_NUM_RINGS];
 220         u32 ipehr[I915_NUM_RINGS];
 221         u32 instdone[I915_NUM_RINGS];
 222         u32 acthd[I915_NUM_RINGS];
 223         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 224         u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 225         u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
 226         /* our own tracking of ring head and tail */
 227         u32 cpu_ring_head[I915_NUM_RINGS];
 228         u32 cpu_ring_tail[I915_NUM_RINGS];
 229         u32 error; /* gen6+ */
 230         u32 err_int; /* gen7 */
 231         u32 instpm[I915_NUM_RINGS];
 232         u32 instps[I915_NUM_RINGS];
 233         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 234         u32 seqno[I915_NUM_RINGS];
 235         u64 bbaddr;
 236         u32 fault_reg[I915_NUM_RINGS];
 237         u32 done_reg;
 238         u32 faddr[I915_NUM_RINGS];
 239         u64 fence[I915_MAX_NUM_FENCES];
 240         struct timeval time;
 241         struct drm_i915_error_ring {
 242                 struct drm_i915_error_object {
 243                         int page_count;
 244                         u32 gtt_offset;
 245                         u32 *pages[0];
 246                 } *ringbuffer, *batchbuffer, *ctx;
 247                 struct drm_i915_error_request {
 248                         long jiffies;
 249                         u32 seqno;
 250                         u32 tail;
 251                 } *requests;
 252                 int num_requests;
 253         } ring[I915_NUM_RINGS];
 254         struct drm_i915_error_buffer {
 255                 u32 size;
 256                 u32 name;
 257                 u32 rseqno, wseqno;
 258                 u32 gtt_offset;
 259                 u32 read_domains;
 260                 u32 write_domain;
 261                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 262                 s32 pinned:2;
 263                 u32 tiling:2;
 264                 u32 dirty:1;
 265                 u32 purgeable:1;
 266                 s32 ring:4;
 267                 u32 cache_level:2;
 268         } *active_bo, *pinned_bo;
 269         u32 active_bo_count, pinned_bo_count;
 270         struct intel_overlay_error_state *overlay;
 271         struct intel_display_error_state *display;
 272 };
 273
 274 struct drm_i915_display_funcs {
 275         bool (*fbc_enabled)(struct drm_device *dev);
 276         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 277         void (*disable_fbc)(struct drm_device *dev);
 278         int (*get_display_clock_speed)(struct drm_device *dev);
 279         int (*get_fifo_size)(struct drm_device *dev, int plane);
 280         void (*update_wm)(struct drm_device *dev);
 281         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 282                                  uint32_t sprite_width, int pixel_size);
 283         void (*update_linetime_wm)(struct drm_device *dev, int pipe,
 284                                  struct drm_display_mode *mode);
 285         void (*modeset_global_resources)(struct drm_device *dev);
 286         int (*crtc_mode_set)(struct drm_crtc *crtc,
 287                              struct drm_display_mode *mode,
 288                              struct drm_display_mode *adjusted_mode,
 289                              int x, int y,
 290                              struct drm_framebuffer *old_fb);
 291         void (*crtc_enable)(struct drm_crtc *crtc);
 292         void (*crtc_disable)(struct drm_crtc *crtc);
 293         void (*off)(struct drm_crtc *crtc);
 294         void (*write_eld)(struct drm_connector *connector,
 295                           struct drm_crtc *crtc);
 296         void (*fdi_link_train)(struct drm_crtc *crtc);
 297         void (*init_clock_gating)(struct drm_device *dev);
 298         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 299                           struct drm_framebuffer *fb,
 300                           struct drm_i915_gem_object *obj);
 301         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 302                             int x, int y);
 303         void (*hpd_irq_setup)(struct drm_device *dev);
 304         /* clock updates for mode set */
 305         /* cursor updates */
 306         /* render clock increase/decrease */
 307         /* display clock increase/decrease */
 308         /* pll clock increase/decrease */
 309 };
 310
 311 struct drm_i915_gt_funcs {
 312         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 313         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 314 };
 315
 316 #define DEV_INFO_FLAGS \
 317         DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
 318         DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
 319         DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
 320         DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
 321         DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
 322         DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
 323         DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
 324         DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
 325         DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
 326         DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
 327         DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
 328         DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
 329         DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
 330         DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
 331         DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
 332         DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
 333         DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
 334         DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
 335         DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
 336         DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
 337         DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
 338         DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
 339         DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
 340         DEV_INFO_FLAG(has_llc)
 341
 342 struct intel_device_info {
 343         u32 display_mmio_offset;
 344         u8 num_pipes:3;
 345         u8 gen;
 346         u8 is_mobile:1;
 347         u8 is_i85x:1;
 348         u8 is_i915g:1;
 349         u8 is_i945gm:1;
 350         u8 is_g33:1;
 351         u8 need_gfx_hws:1;
 352         u8 is_g4x:1;
 353         u8 is_pineview:1;
 354         u8 is_broadwater:1;
 355         u8 is_crestline:1;
 356         u8 is_ivybridge:1;
 357         u8 is_valleyview:1;
 358         u8 has_force_wake:1;
 359         u8 is_haswell:1;
 360         u8 has_fbc:1;
 361         u8 has_pipe_cxsr:1;
 362         u8 has_hotplug:1;
 363         u8 cursor_needs_physical:1;
 364         u8 has_overlay:1;
 365         u8 overlay_needs_physical:1;
 366         u8 supports_tv:1;
 367         u8 has_bsd_ring:1;
 368         u8 has_blt_ring:1;
 369         u8 has_llc:1;
 370 };
 371
 372 enum i915_cache_level {
 373         I915_CACHE_NONE = 0,
 374         I915_CACHE_LLC,
 375         I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
 376 };
 377
 378 /* The Graphics Translation Table is the way in which GEN hardware translates a
 379  * Graphics Virtual Address into a Physical Address. In addition to the normal
 380  * collateral associated with any va->pa translations GEN hardware also has a
 381  * portion of the GTT which can be mapped by the CPU and remain both coherent
 382  * and correct (in cases like swizzling). That region is referred to as GMADR in
 383  * the spec.
 384  */
 385 struct i915_gtt {
 386         unsigned long start;            /* Start offset of used GTT */
 387         size_t total;                   /* Total size GTT can map */
 388         size_t stolen_size;             /* Total size of stolen memory */
 389
 390         unsigned long mappable_end;     /* End offset that we can CPU map */
 391         struct io_mapping *mappable;    /* Mapping to our CPU mappable region */
 392         phys_addr_t mappable_base;      /* PA of our GMADR */
 393
 394         /** "Graphics Stolen Memory" holds the global PTEs */
 395         void __iomem *gsm;
 396
 397         bool do_idle_maps;
 398         dma_addr_t scratch_page_dma;
 399         struct page *scratch_page;
 400
 401         /* global gtt ops */
 402         int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
 403                           size_t *stolen, phys_addr_t *mappable_base,
 404                           unsigned long *mappable_end);
 405         void (*gtt_remove)(struct drm_device *dev);
 406         void (*gtt_clear_range)(struct drm_device *dev,
 407                                 unsigned int first_entry,
 408                                 unsigned int num_entries);
 409         void (*gtt_insert_entries)(struct drm_device *dev,
 410                                    struct sg_table *st,
 411                                    unsigned int pg_start,
 412                                    enum i915_cache_level cache_level);
 413 };
 414 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
 415
 416 #define I915_PPGTT_PD_ENTRIES 512
 417 #define I915_PPGTT_PT_ENTRIES 1024
 418 struct i915_hw_ppgtt {
 419         struct drm_device *dev;
 420         unsigned num_pd_entries;
 421         struct page **pt_pages;
 422         uint32_t pd_offset;
 423         dma_addr_t *pt_dma_addr;
 424         dma_addr_t scratch_page_dma_addr;
 425
 426         /* pte functions, mirroring the interface of the global gtt. */
 427         void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
 428                             unsigned int first_entry,
 429                             unsigned int num_entries);
 430         void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
 431                                struct sg_table *st,
 432                                unsigned int pg_start,
 433                                enum i915_cache_level cache_level);
 434         void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
 435 };
 436
 437
 438 /* This must match up with the value previously used for execbuf2.rsvd1. */
 439 #define DEFAULT_CONTEXT_ID 0
 440 struct i915_hw_context {
 441         int id;
 442         bool is_initialized;
 443         struct drm_i915_file_private *file_priv;
 444         struct intel_ring_buffer *ring;
 445         struct drm_i915_gem_object *obj;
 446 };
 447
 448 enum no_fbc_reason {
 449         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 450         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 451         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 452         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 453         FBC_BAD_PLANE, /* fbc not supported on plane */
 454         FBC_NOT_TILED, /* buffer not tiled */
 455         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 456         FBC_MODULE_PARAM,
 457 };
 458
 459 enum intel_pch {
 460         PCH_NONE = 0,   /* No PCH present */
 461         PCH_IBX,        /* Ibexpeak PCH */
 462         PCH_CPT,        /* Cougarpoint PCH */
 463         PCH_LPT,        /* Lynxpoint PCH */
 464 };
 465
 466 enum intel_sbi_destination {
 467         SBI_ICLK,
 468         SBI_MPHY,
 469 };
 470
 471 #define QUIRK_PIPEA_FORCE (1<<0)
 472 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 473 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 474
 475 struct intel_fbdev;
 476 struct intel_fbc_work;
 477
 478 struct intel_gmbus {
 479         struct i2c_adapter adapter;
 480         u32 force_bit;
 481         u32 reg0;
 482         u32 gpio_reg;
 483         struct i2c_algo_bit_data bit_algo;
 484         struct drm_i915_private *dev_priv;
 485 };
 486
 487 struct i915_suspend_saved_registers {
 488         u8 saveLBB;
 489         u32 saveDSPACNTR;
 490         u32 saveDSPBCNTR;
 491         u32 saveDSPARB;
 492         u32 savePIPEACONF;
 493         u32 savePIPEBCONF;
 494         u32 savePIPEASRC;
 495         u32 savePIPEBSRC;
 496         u32 saveFPA0;
 497         u32 saveFPA1;
 498         u32 saveDPLL_A;
 499         u32 saveDPLL_A_MD;
 500         u32 saveHTOTAL_A;
 501         u32 saveHBLANK_A;
 502         u32 saveHSYNC_A;
 503         u32 saveVTOTAL_A;
 504         u32 saveVBLANK_A;
 505         u32 saveVSYNC_A;
 506         u32 saveBCLRPAT_A;
 507         u32 saveTRANSACONF;
 508         u32 saveTRANS_HTOTAL_A;
 509         u32 saveTRANS_HBLANK_A;
 510         u32 saveTRANS_HSYNC_A;
 511         u32 saveTRANS_VTOTAL_A;
 512         u32 saveTRANS_VBLANK_A;
 513         u32 saveTRANS_VSYNC_A;
 514         u32 savePIPEASTAT;
 515         u32 saveDSPASTRIDE;
 516         u32 saveDSPASIZE;
 517         u32 saveDSPAPOS;
 518         u32 saveDSPAADDR;
 519         u32 saveDSPASURF;
 520         u32 saveDSPATILEOFF;
 521         u32 savePFIT_PGM_RATIOS;
 522         u32 saveBLC_HIST_CTL;
 523         u32 saveBLC_PWM_CTL;
 524         u32 saveBLC_PWM_CTL2;
 525         u32 saveBLC_CPU_PWM_CTL;
 526         u32 saveBLC_CPU_PWM_CTL2;
 527         u32 saveFPB0;
 528         u32 saveFPB1;
 529         u32 saveDPLL_B;
 530         u32 saveDPLL_B_MD;
 531         u32 saveHTOTAL_B;
 532         u32 saveHBLANK_B;
 533         u32 saveHSYNC_B;
 534         u32 saveVTOTAL_B;
 535         u32 saveVBLANK_B;
 536         u32 saveVSYNC_B;
 537         u32 saveBCLRPAT_B;
 538         u32 saveTRANSBCONF;
 539         u32 saveTRANS_HTOTAL_B;
 540         u32 saveTRANS_HBLANK_B;
 541         u32 saveTRANS_HSYNC_B;
 542         u32 saveTRANS_VTOTAL_B;
 543         u32 saveTRANS_VBLANK_B;
 544         u32 saveTRANS_VSYNC_B;
 545         u32 savePIPEBSTAT;
 546         u32 saveDSPBSTRIDE;
 547         u32 saveDSPBSIZE;
 548         u32 saveDSPBPOS;
 549         u32 saveDSPBADDR;
 550         u32 saveDSPBSURF;
 551         u32 saveDSPBTILEOFF;
 552         u32 saveVGA0;
 553         u32 saveVGA1;
 554         u32 saveVGA_PD;
 555         u32 saveVGACNTRL;
 556         u32 saveADPA;
 557         u32 saveLVDS;
 558         u32 savePP_ON_DELAYS;
 559         u32 savePP_OFF_DELAYS;
 560         u32 saveDVOA;
 561         u32 saveDVOB;
 562         u32 saveDVOC;
 563         u32 savePP_ON;
 564         u32 savePP_OFF;
 565         u32 savePP_CONTROL;
 566         u32 savePP_DIVISOR;
 567         u32 savePFIT_CONTROL;
 568         u32 save_palette_a[256];
 569         u32 save_palette_b[256];
 570         u32 saveDPFC_CB_BASE;
 571         u32 saveFBC_CFB_BASE;
 572         u32 saveFBC_LL_BASE;
 573         u32 saveFBC_CONTROL;
 574         u32 saveFBC_CONTROL2;
 575         u32 saveIER;
 576         u32 saveIIR;
 577         u32 saveIMR;
 578         u32 saveDEIER;
 579         u32 saveDEIMR;
 580         u32 saveGTIER;
 581         u32 saveGTIMR;
 582         u32 saveFDI_RXA_IMR;
 583         u32 saveFDI_RXB_IMR;
 584         u32 saveCACHE_MODE_0;
 585         u32 saveMI_ARB_STATE;
 586         u32 saveSWF0[16];
 587         u32 saveSWF1[16];
 588         u32 saveSWF2[3];
 589         u8 saveMSR;
 590         u8 saveSR[8];
 591         u8 saveGR[25];
 592         u8 saveAR_INDEX;
 593         u8 saveAR[21];
 594         u8 saveDACMASK;
 595         u8 saveCR[37];
 596         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 597         u32 saveCURACNTR;
 598         u32 saveCURAPOS;
 599         u32 saveCURABASE;
 600         u32 saveCURBCNTR;
 601         u32 saveCURBPOS;
 602         u32 saveCURBBASE;
 603         u32 saveCURSIZE;
 604         u32 saveDP_B;
 605         u32 saveDP_C;
 606         u32 saveDP_D;
 607         u32 savePIPEA_GMCH_DATA_M;
 608         u32 savePIPEB_GMCH_DATA_M;
 609         u32 savePIPEA_GMCH_DATA_N;
 610         u32 savePIPEB_GMCH_DATA_N;
 611         u32 savePIPEA_DP_LINK_M;
 612         u32 savePIPEB_DP_LINK_M;
 613         u32 savePIPEA_DP_LINK_N;
 614         u32 savePIPEB_DP_LINK_N;
 615         u32 saveFDI_RXA_CTL;
 616         u32 saveFDI_TXA_CTL;
 617         u32 saveFDI_RXB_CTL;
 618         u32 saveFDI_TXB_CTL;
 619         u32 savePFA_CTL_1;
 620         u32 savePFB_CTL_1;
 621         u32 savePFA_WIN_SZ;
 622         u32 savePFB_WIN_SZ;
 623         u32 savePFA_WIN_POS;
 624         u32 savePFB_WIN_POS;
 625         u32 savePCH_DREF_CONTROL;
 626         u32 saveDISP_ARB_CTL;
 627         u32 savePIPEA_DATA_M1;
 628         u32 savePIPEA_DATA_N1;
 629         u32 savePIPEA_LINK_M1;
 630         u32 savePIPEA_LINK_N1;
 631         u32 savePIPEB_DATA_M1;
 632         u32 savePIPEB_DATA_N1;
 633         u32 savePIPEB_LINK_M1;
 634         u32 savePIPEB_LINK_N1;
 635         u32 saveMCHBAR_RENDER_STANDBY;
 636         u32 savePCH_PORT_HOTPLUG;
 637 };
 638
 639 struct intel_gen6_power_mgmt {
 640         struct work_struct work;
 641         u32 pm_iir;
 642         /* lock - irqsave spinlock that protectects the work_struct and
 643          * pm_iir. */
 644         spinlock_t lock;
 645
 646         /* The below variables an all the rps hw state are protected by
 647          * dev->struct mutext. */
 648         u8 cur_delay;
 649         u8 min_delay;
 650         u8 max_delay;
 651
 652         struct delayed_work delayed_resume_work;
 653
 654         /*
 655          * Protects RPS/RC6 register access and PCU communication.
 656          * Must be taken after struct_mutex if nested.
 657          */
 658         struct mutex hw_lock;
 659 };
 660
 661 /* defined intel_pm.c */
 662 extern spinlock_t mchdev_lock;
 663
 664 struct intel_ilk_power_mgmt {
 665         u8 cur_delay;
 666         u8 min_delay;
 667         u8 max_delay;
 668         u8 fmax;
 669         u8 fstart;
 670
 671         u64 last_count1;
 672         unsigned long last_time1;
 673         unsigned long chipset_power;
 674         u64 last_count2;
 675         struct timespec last_time2;
 676         unsigned long gfx_power;
 677         u8 corr;
 678
 679         int c_m;
 680         int r_t;
 681
 682         struct drm_i915_gem_object *pwrctx;
 683         struct drm_i915_gem_object *renderctx;
 684 };
 685
 686 struct i915_dri1_state {
 687         unsigned allow_batchbuffer : 1;
 688         u32 __iomem *gfx_hws_cpu_addr;
 689
 690         unsigned int cpp;
 691         int back_offset;
 692         int front_offset;
 693         int current_page;
 694         int page_flipping;
 695
 696         uint32_t counter;
 697 };
 698
 699 struct intel_l3_parity {
 700         u32 *remap_info;
 701         struct work_struct error_work;
 702 };
 703
 704 struct i915_gem_mm {
 705         /** Memory allocator for GTT stolen memory */
 706         struct drm_mm stolen;
 707         /** Memory allocator for GTT */
 708         struct drm_mm gtt_space;
 709         /** List of all objects in gtt_space. Used to restore gtt
 710          * mappings on resume */
 711         struct list_head bound_list;
 712         /**
 713          * List of objects which are not bound to the GTT (thus
 714          * are idle and not used by the GPU) but still have
 715          * (presumably uncached) pages still attached.
 716          */
 717         struct list_head unbound_list;
 718
 719         /** Usable portion of the GTT for GEM */
 720         unsigned long stolen_base; /* limited to low memory (32-bit) */
 721
 722         int gtt_mtrr;
 723
 724         /** PPGTT used for aliasing the PPGTT with the GTT */
 725         struct i915_hw_ppgtt *aliasing_ppgtt;
 726
 727         struct shrinker inactive_shrinker;
 728         bool shrinker_no_lock_stealing;
 729
 730         /**
 731          * List of objects currently involved in rendering.
 732          *
 733          * Includes buffers having the contents of their GPU caches
 734          * flushed, not necessarily primitives.  last_rendering_seqno
 735          * represents when the rendering involved will be completed.
 736          *
 737          * A reference is held on the buffer while on this list.
 738          */
 739         struct list_head active_list;
 740
 741         /**
 742          * LRU list of objects which are not in the ringbuffer and
 743          * are ready to unbind, but are still in the GTT.
 744          *
 745          * last_rendering_seqno is 0 while an object is in this list.
 746          *
 747          * A reference is not held on the buffer while on this list,
 748          * as merely being GTT-bound shouldn't prevent its being
 749          * freed, and we'll pull it off the list in the free path.
 750          */
 751         struct list_head inactive_list;
 752
 753         /** LRU list of objects with fence regs on them. */
 754         struct list_head fence_list;
 755
 756         /**
 757          * We leave the user IRQ off as much as possible,
 758          * but this means that requests will finish and never
 759          * be retired once the system goes idle. Set a timer to
 760          * fire periodically while the ring is running. When it
 761          * fires, go retire requests.
 762          */
 763         struct delayed_work retire_work;
 764
 765         /**
 766          * Are we in a non-interruptible section of code like
 767          * modesetting?
 768          */
 769         bool interruptible;
 770
 771         /**
 772          * Flag if the X Server, and thus DRM, is not currently in
 773          * control of the device.
 774          *
 775          * This is set between LeaveVT and EnterVT.  It needs to be
 776          * replaced with a semaphore.  It also needs to be
 777          * transitioned away from for kernel modesetting.
 778          */
 779         int suspended;
 780
 781         /** Bit 6 swizzling required for X tiling */
 782         uint32_t bit_6_swizzle_x;
 783         /** Bit 6 swizzling required for Y tiling */
 784         uint32_t bit_6_swizzle_y;
 785
 786         /* storage for physical objects */
 787         struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 788
 789         /* accounting, useful for userland debugging */
 790         size_t object_memory;
 791         u32 object_count;
 792 };
 793
 794 struct i915_gpu_error {
 795         /* For hangcheck timer */
 796 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 797 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
 798         struct timer_list hangcheck_timer;
 799         int hangcheck_count;
 800         uint32_t last_acthd[I915_NUM_RINGS];
 801         uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
 802
 803         /* For reset and error_state handling. */
 804         spinlock_t lock;
 805         /* Protected by the above dev->gpu_error.lock. */
 806         struct drm_i915_error_state *first_error;
 807         struct work_struct work;
 808
 809         unsigned long last_reset;
 810
 811         /**
 812          * State variable and reset counter controlling the reset flow
 813          *
 814          * Upper bits are for the reset counter.  This counter is used by the
 815          * wait_seqno code to race-free noticed that a reset event happened and
 816          * that it needs to restart the entire ioctl (since most likely the
 817          * seqno it waited for won't ever signal anytime soon).
 818          *
 819          * This is important for lock-free wait paths, where no contended lock
 820          * naturally enforces the correct ordering between the bail-out of the
 821          * waiter and the gpu reset work code.
 822          *
 823          * Lowest bit controls the reset state machine: Set means a reset is in
 824          * progress. This state will (presuming we don't have any bugs) decay
 825          * into either unset (successful reset) or the special WEDGED value (hw
 826          * terminally sour). All waiters on the reset_queue will be woken when
 827          * that happens.
 828          */
 829         atomic_t reset_counter;
 830
 831         /**
 832          * Special values/flags for reset_counter
 833          *
 834          * Note that the code relies on
 835          *      I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
 836          * being true.
 837          */
 838 #define I915_RESET_IN_PROGRESS_FLAG     1
 839 #define I915_WEDGED                     0xffffffff
 840
 841         /**
 842          * Waitqueue to signal when the reset has completed. Used by clients
 843          * that wait for dev_priv->mm.wedged to settle.
 844          */
 845         wait_queue_head_t reset_queue;
 846
 847         /* For gpu hang simulation. */
 848         unsigned int stop_rings;
 849 };
 850
 851 enum modeset_restore {
 852         MODESET_ON_LID_OPEN,
 853         MODESET_DONE,
 854         MODESET_SUSPENDED,
 855 };
 856
 857 typedef struct drm_i915_private {
 858         struct drm_device *dev;
 859         struct kmem_cache *slab;
 860
 861         const struct intel_device_info *info;
 862
 863         int relative_constants_mode;
 864
 865         void __iomem *regs;
 866
 867         struct drm_i915_gt_funcs gt;
 868         /** gt_fifo_count and the subsequent register write are synchronized
 869          * with dev->struct_mutex. */
 870         unsigned gt_fifo_count;
 871         /** forcewake_count is protected by gt_lock */
 872         unsigned forcewake_count;
 873         /** gt_lock is also taken in irq contexts. */
 874         spinlock_t gt_lock;
 875
 876         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
 877
 878
 879         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 880          * controller on different i2c buses. */
 881         struct mutex gmbus_mutex;
 882
 883         /**
 884          * Base address of the gmbus and gpio block.
 885          */
 886         uint32_t gpio_mmio_base;
 887
 888         wait_queue_head_t gmbus_wait_queue;
 889
 890         struct pci_dev *bridge_dev;
 891         struct intel_ring_buffer ring[I915_NUM_RINGS];
 892         uint32_t last_seqno, next_seqno;
 893
 894         drm_dma_handle_t *status_page_dmah;
 895         struct resource mch_res;
 896
 897         atomic_t irq_received;
 898
 899         /* protects the irq masks */
 900         spinlock_t irq_lock;
 901
 902         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
 903         struct pm_qos_request pm_qos;
 904
 905         /* DPIO indirect register protection */
 906         struct mutex dpio_lock;
 907
 908         /** Cached value of IMR to avoid reads in updating the bitfield */
 909         u32 irq_mask;
 910         u32 gt_irq_mask;
 911
 912         u32 hotplug_supported_mask;
 913         struct work_struct hotplug_work;
 914         bool enable_hotplug_processing;
 915
 916         int num_pch_pll;
 917
 918         unsigned long cfb_size;
 919         unsigned int cfb_fb;
 920         enum plane cfb_plane;
 921         int cfb_y;
 922         struct intel_fbc_work *fbc_work;
 923
 924         struct intel_opregion opregion;
 925
 926         /* overlay */
 927         struct intel_overlay *overlay;
 928         unsigned int sprite_scaling_enabled;
 929
 930         /* LVDS info */
 931         int backlight_level;  /* restore backlight to this value */
 932         bool backlight_enabled;
 933         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 934         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 935
 936         /* Feature bits from the VBIOS */
 937         unsigned int int_tv_support:1;
 938         unsigned int lvds_dither:1;
 939         unsigned int lvds_vbt:1;
 940         unsigned int int_crt_support:1;
 941         unsigned int lvds_use_ssc:1;
 942         unsigned int display_clock_mode:1;
 943         int lvds_ssc_freq;
 944         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 945         struct {
 946                 int rate;
 947                 int lanes;
 948                 int preemphasis;
 949                 int vswing;
 950
 951                 bool initialized;
 952                 bool support;
 953                 int bpp;
 954                 struct edp_power_seq pps;
 955         } edp;
 956         bool no_aux_handshake;
 957
 958         int crt_ddc_pin;
 959         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 960         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 961         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 962
 963         unsigned int fsb_freq, mem_freq, is_ddr3;
 964
 965         struct workqueue_struct *wq;
 966
 967         /* Display functions */
 968         struct drm_i915_display_funcs display;
 969
 970         /* PCH chipset type */
 971         enum intel_pch pch_type;
 972         unsigned short pch_id;
 973
 974         unsigned long quirks;
 975
 976         enum modeset_restore modeset_restore;
 977         struct mutex modeset_restore_lock;
 978
 979         struct i915_gtt gtt;
 980
 981         struct i915_gem_mm mm;
 982
 983         /* Kernel Modesetting */
 984
 985         struct sdvo_device_mapping sdvo_mappings[2];
 986         /* indicate whether the LVDS_BORDER should be enabled or not */
 987         unsigned int lvds_border_bits;
 988         /* Panel fitter placement and size for Ironlake+ */
 989         u32 pch_pf_pos, pch_pf_size;
 990
 991         struct drm_crtc *plane_to_crtc_mapping[3];
 992         struct drm_crtc *pipe_to_crtc_mapping[3];
 993         wait_queue_head_t pending_flip_queue;
 994
 995         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
 996         struct intel_ddi_plls ddi_plls;
 997
 998         /* Reclocking support */
 999         bool render_reclock_avail;
1000         bool lvds_downclock_avail;
1001         /* indicates the reduced downclock for LVDS*/
1002         int lvds_downclock;
1003         u16 orig_clock;
1004         int child_dev_num;
1005         struct child_device_config *child_dev;
1006
1007         bool mchbar_need_disable;
1008
1009         struct intel_l3_parity l3_parity;
1010
1011         /* gen6+ rps state */
1012         struct intel_gen6_power_mgmt rps;
1013
1014         /* ilk-only ips/rps state. Everything in here is protected by the global
1015          * mchdev_lock in intel_pm.c */
1016         struct intel_ilk_power_mgmt ips;
1017
1018         enum no_fbc_reason no_fbc_reason;
1019
1020         struct drm_mm_node *compressed_fb;
1021         struct drm_mm_node *compressed_llb;
1022
1023         struct i915_gpu_error gpu_error;
1024
1025         /* list of fbdev register on this device */
1026         struct intel_fbdev *fbdev;
1027
1028         /*
1029          * The console may be contended at resume, but we don't
1030          * want it to block on it.
1031          */
1032         struct work_struct console_resume_work;
1033
1034         struct backlight_device *backlight;
1035
1036         struct drm_property *broadcast_rgb_property;
1037         struct drm_property *force_audio_property;
1038
1039         bool hw_contexts_disabled;
1040         uint32_t hw_context_size;
1041
1042         u32 fdi_rx_config;
1043
1044         struct i915_suspend_saved_registers regfile;
1045
1046         /* Old dri1 support infrastructure, beware the dragons ya fools entering
1047          * here! */
1048         struct i915_dri1_state dri1;
1049 } drm_i915_private_t;
1050
1051 /* Iterate over initialised rings */
1052 #define for_each_ring(ring__, dev_priv__, i__) \
1053         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1054                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1055
1056 enum hdmi_force_audio {
1057         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
1058         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
1059         HDMI_AUDIO_AUTO,                /* trust EDID */
1060         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
1061 };
1062
1063 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1064
1065 struct drm_i915_gem_object_ops {
1066         /* Interface between the GEM object and its backing storage.
1067          * get_pages() is called once prior to the use of the associated set
1068          * of pages before to binding them into the GTT, and put_pages() is
1069          * called after we no longer need them. As we expect there to be
1070          * associated cost with migrating pages between the backing storage
1071          * and making them available for the GPU (e.g. clflush), we may hold
1072          * onto the pages after they are no longer referenced by the GPU
1073          * in case they may be used again shortly (for example migrating the
1074          * pages to a different memory domain within the GTT). put_pages()
1075          * will therefore most likely be called when the object itself is
1076          * being released or under memory pressure (where we attempt to
1077          * reap pages for the shrinker).
1078          */
1079         int (*get_pages)(struct drm_i915_gem_object *);
1080         void (*put_pages)(struct drm_i915_gem_object *);
1081 };
1082
1083 struct drm_i915_gem_object {
1084         struct drm_gem_object base;
1085
1086         const struct drm_i915_gem_object_ops *ops;
1087
1088         /** Current space allocated to this object in the GTT, if any. */
1089         struct drm_mm_node *gtt_space;
1090         /** Stolen memory for this object, instead of being backed by shmem. */
1091         struct drm_mm_node *stolen;
1092         struct list_head gtt_list;
1093
1094         /** This object's place on the active/inactive lists */
1095         struct list_head ring_list;
1096         struct list_head mm_list;
1097         /** This object's place in the batchbuffer or on the eviction list */
1098         struct list_head exec_list;
1099
1100         /**
1101          * This is set if the object is on the active lists (has pending
1102          * rendering and so a non-zero seqno), and is not set if it i s on
1103          * inactive (ready to be unbound) list.
1104          */
1105         unsigned int active:1;
1106
1107         /**
1108          * This is set if the object has been written to since last bound
1109          * to the GTT
1110          */
1111         unsigned int dirty:1;
1112
1113         /**
1114          * Fence register bits (if any) for this object.  Will be set
1115          * as needed when mapped into the GTT.
1116          * Protected by dev->struct_mutex.
1117          */
1118         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1119
1120         /**
1121          * Advice: are the backing pages purgeable?
1122          */
1123         unsigned int madv:2;
1124
1125         /**
1126          * Current tiling mode for the object.
1127          */
1128         unsigned int tiling_mode:2;
1129         /**
1130          * Whether the tiling parameters for the currently associated fence
1131          * register have changed. Note that for the purposes of tracking
1132          * tiling changes we also treat the unfenced register, the register
1133          * slot that the object occupies whilst it executes a fenced
1134          * command (such as BLT on gen2/3), as a "fence".
1135          */
1136         unsigned int fence_dirty:1;
1137
1138         /** How many users have pinned this object in GTT space. The following
1139          * users can each hold at most one reference: pwrite/pread, pin_ioctl
1140          * (via user_pin_count), execbuffer (objects are not allowed multiple
1141          * times for the same batchbuffer), and the framebuffer code. When
1142          * switching/pageflipping, the framebuffer code has at most two buffers
1143          * pinned per crtc.
1144          *
1145          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1146          * bits with absolutely no headroom. So use 4 bits. */
1147         unsigned int pin_count:4;
1148 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1149
1150         /**
1151          * Is the object at the current location in the gtt mappable and
1152          * fenceable? Used to avoid costly recalculations.
1153          */
1154         unsigned int map_and_fenceable:1;
1155
1156         /**
1157          * Whether the current gtt mapping needs to be mappable (and isn't just
1158          * mappable by accident). Track pin and fault separate for a more
1159          * accurate mappable working set.
1160          */
1161         unsigned int fault_mappable:1;
1162         unsigned int pin_mappable:1;
1163
1164         /*
1165          * Is the GPU currently using a fence to access this buffer,
1166          */
1167         unsigned int pending_fenced_gpu_access:1;
1168         unsigned int fenced_gpu_access:1;
1169
1170         unsigned int cache_level:2;
1171
1172         unsigned int has_aliasing_ppgtt_mapping:1;
1173         unsigned int has_global_gtt_mapping:1;
1174         unsigned int has_dma_mapping:1;
1175
1176         struct sg_table *pages;
1177         int pages_pin_count;
1178
1179         /* prime dma-buf support */
1180         void *dma_buf_vmapping;
1181         int vmapping_count;
1182
1183         /**
1184          * Used for performing relocations during execbuffer insertion.
1185          */
1186         struct hlist_node exec_node;
1187         unsigned long exec_handle;
1188         struct drm_i915_gem_exec_object2 *exec_entry;
1189
1190         /**
1191          * Current offset of the object in GTT space.
1192          *
1193          * This is the same as gtt_space->start
1194          */
1195         uint32_t gtt_offset;
1196
1197         struct intel_ring_buffer *ring;
1198
1199         /** Breadcrumb of last rendering to the buffer. */
1200         uint32_t last_read_seqno;
1201         uint32_t last_write_seqno;
1202         /** Breadcrumb of last fenced GPU access to the buffer. */
1203         uint32_t last_fenced_seqno;
1204
1205         /** Current tiling stride for the object, if it's tiled. */
1206         uint32_t stride;
1207
1208         /** Record of address bit 17 of each page at last unbind. */
1209         unsigned long *bit_17;
1210
1211         /** User space pin count and filp owning the pin */
1212         uint32_t user_pin_count;
1213         struct drm_file *pin_filp;
1214
1215         /** for phy allocated objects */
1216         struct drm_i915_gem_phys_object *phys_obj;
1217 };
1218 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1219
1220 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1221
1222 /**
1223  * Request queue structure.
1224  *
1225  * The request queue allows us to note sequence numbers that have been emitted
1226  * and may be associated with active buffers to be retired.
1227  *
1228  * By keeping this list, we can avoid having to do questionable
1229  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1230  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1231  */
1232 struct drm_i915_gem_request {
1233         /** On Which ring this request was generated */
1234         struct intel_ring_buffer *ring;
1235
1236         /** GEM sequence number associated with this request. */
1237         uint32_t seqno;
1238
1239         /** Postion in the ringbuffer of the end of the request */
1240         u32 tail;
1241
1242         /** Time at which this request was emitted, in jiffies. */
1243         unsigned long emitted_jiffies;
1244
1245         /** global list entry for this request */
1246         struct list_head list;
1247
1248         struct drm_i915_file_private *file_priv;
1249         /** file_priv list entry for this request */
1250         struct list_head client_list;
1251 };
1252
1253 struct drm_i915_file_private {
1254         struct {
1255                 spinlock_t lock;
1256                 struct list_head request_list;
1257         } mm;
1258         struct idr context_idr;
1259 };
1260
1261 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1262
1263 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1264 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1265 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1266 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1267 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1268 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1269 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1270 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1271 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1272 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1273 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1274 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1275 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1276 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1277 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1278 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1279 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1280 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1281 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1282 #define IS_IVB_GT1(dev)         ((dev)->pci_device == 0x0156 || \
1283                                  (dev)->pci_device == 0x0152 || \
1284                                  (dev)->pci_device == 0x015a)
1285 #define IS_SNB_GT1(dev)         ((dev)->pci_device == 0x0102 || \
1286                                  (dev)->pci_device == 0x0106 || \
1287                                  (dev)->pci_device == 0x010A)
1288 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1289 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1290 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1291 #define IS_ULT(dev)             (IS_HASWELL(dev) && \
1292                                  ((dev)->pci_device & 0xFF00) == 0x0A00)
1293
1294 /*
1295  * The genX designation typically refers to the render engine, so render
1296  * capability related checks should use IS_GEN, while display and other checks
1297  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1298  * chips, etc.).
1299  */
1300 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1301 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1302 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1303 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1304 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1305 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1306
1307 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1308 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1309 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1310 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1311
1312 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1313 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1314
1315 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1316 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1317
1318 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1319 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
1320
1321 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1322  * rows, which changed the alignment requirements and fence programming.
1323  */
1324 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1325                                                       IS_I915GM(dev)))
1326 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1327 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1328 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1329 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1330 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1331 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1332 /* dsparb controlled by hw only */
1333 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1334
1335 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1336 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1337 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1338
1339 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1340
1341 #define HAS_DDI(dev)            (IS_HASWELL(dev))
1342 #define HAS_POWER_WELL(dev)     (IS_HASWELL(dev))
1343
1344 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
1345 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
1346 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
1347 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
1348 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
1349 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
1350
1351 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1352 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1353 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1354 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1355 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1356
1357 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1358
1359 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1360
1361 #define GT_FREQUENCY_MULTIPLIER 50
1362
1363 #include "i915_trace.h"
1364
1365 /**
1366  * RC6 is a special power stage which allows the GPU to enter an very
1367  * low-voltage mode when idle, using down to 0V while at this stage.  This
1368  * stage is entered automatically when the GPU is idle when RC6 support is
1369  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1370  *
1371  * There are different RC6 modes available in Intel GPU, which differentiate
1372  * among each other with the latency required to enter and leave RC6 and
1373  * voltage consumed by the GPU in different states.
1374  *
1375  * The combination of the following flags define which states GPU is allowed
1376  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1377  * RC6pp is deepest RC6. Their support by hardware varies according to the
1378  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1379  * which brings the most power savings; deeper states save more power, but
1380  * require higher latency to switch to and wake up.
1381  */
1382 #define INTEL_RC6_ENABLE                        (1<<0)
1383 #define INTEL_RC6p_ENABLE                       (1<<1)
1384 #define INTEL_RC6pp_ENABLE                      (1<<2)
1385
1386 extern struct drm_ioctl_desc i915_ioctls[];
1387 extern int i915_max_ioctl;
1388 extern unsigned int i915_fbpercrtc __always_unused;
1389 extern int i915_panel_ignore_lid __read_mostly;
1390 extern unsigned int i915_powersave __read_mostly;
1391 extern int i915_semaphores __read_mostly;
1392 extern unsigned int i915_lvds_downclock __read_mostly;
1393 extern int i915_lvds_channel_mode __read_mostly;
1394 extern int i915_panel_use_ssc __read_mostly;
1395 extern int i915_vbt_sdvo_panel_type __read_mostly;
1396 extern int i915_enable_rc6 __read_mostly;
1397 extern int i915_enable_fbc __read_mostly;
1398 extern bool i915_enable_hangcheck __read_mostly;
1399 extern int i915_enable_ppgtt __read_mostly;
1400 extern unsigned int i915_preliminary_hw_support __read_mostly;
1401
1402 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1403 extern int i915_resume(struct drm_device *dev);
1404 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1405 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1406
1407                                 /* i915_dma.c */
1408 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1409 extern void i915_kernel_lost_context(struct drm_device * dev);
1410 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1411 extern int i915_driver_unload(struct drm_device *);
1412 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1413 extern void i915_driver_lastclose(struct drm_device * dev);
1414 extern void i915_driver_preclose(struct drm_device *dev,
1415                                  struct drm_file *file_priv);
1416 extern void i915_driver_postclose(struct drm_device *dev,
1417                                   struct drm_file *file_priv);
1418 extern int i915_driver_device_is_agp(struct drm_device * dev);
1419 #ifdef CONFIG_COMPAT
1420 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1421                               unsigned long arg);
1422 #endif
1423 extern int i915_emit_box(struct drm_device *dev,
1424                          struct drm_clip_rect *box,
1425                          int DR1, int DR4);
1426 extern int intel_gpu_reset(struct drm_device *dev);
1427 extern int i915_reset(struct drm_device *dev);
1428 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1429 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1430 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1431 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1432
1433 extern void intel_console_resume(struct work_struct *work);
1434
1435 /* i915_irq.c */
1436 void i915_hangcheck_elapsed(unsigned long data);
1437 void i915_handle_error(struct drm_device *dev, bool wedged);
1438
1439 extern void intel_irq_init(struct drm_device *dev);
1440 extern void intel_hpd_init(struct drm_device *dev);
1441 extern void intel_gt_init(struct drm_device *dev);
1442 extern void intel_gt_reset(struct drm_device *dev);
1443
1444 void i915_error_state_free(struct kref *error_ref);
1445
1446 void
1447 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1448
1449 void
1450 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1451
1452 void intel_enable_asle(struct drm_device *dev);
1453
1454 #ifdef CONFIG_DEBUG_FS
1455 extern void i915_destroy_error_state(struct drm_device *dev);
1456 #else
1457 #define i915_destroy_error_state(x)
1458 #endif
1459
1460
1461 /* i915_gem.c */
1462 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1463                         struct drm_file *file_priv);
1464 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1465                           struct drm_file *file_priv);
1466 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1467                          struct drm_file *file_priv);
1468 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1469                           struct drm_file *file_priv);
1470 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1471                         struct drm_file *file_priv);
1472 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1473                         struct drm_file *file_priv);
1474 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1475                               struct drm_file *file_priv);
1476 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1477                              struct drm_file *file_priv);
1478 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1479                         struct drm_file *file_priv);
1480 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1481                          struct drm_file *file_priv);
1482 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1483                        struct drm_file *file_priv);
1484 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1485                          struct drm_file *file_priv);
1486 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1487                         struct drm_file *file_priv);
1488 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1489                                struct drm_file *file);
1490 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1491                                struct drm_file *file);
1492 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1493                             struct drm_file *file_priv);
1494 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1495                            struct drm_file *file_priv);
1496 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1497                            struct drm_file *file_priv);
1498 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1499                            struct drm_file *file_priv);
1500 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1501                         struct drm_file *file_priv);
1502 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1503                         struct drm_file *file_priv);
1504 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1505                                 struct drm_file *file_priv);
1506 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1507                         struct drm_file *file_priv);
1508 void i915_gem_load(struct drm_device *dev);
1509 void *i915_gem_object_alloc(struct drm_device *dev);
1510 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1511 int i915_gem_init_object(struct drm_gem_object *obj);
1512 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1513                          const struct drm_i915_gem_object_ops *ops);
1514 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1515                                                   size_t size);
1516 void i915_gem_free_object(struct drm_gem_object *obj);
1517
1518 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1519                                      uint32_t alignment,
1520                                      bool map_and_fenceable,
1521                                      bool nonblocking);
1522 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1523 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1524 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1525 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1526 void i915_gem_lastclose(struct drm_device *dev);
1527
1528 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1529 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1530 {
1531         struct sg_page_iter sg_iter;
1532
1533         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
1534                 return sg_iter.page;
1535
1536         return NULL;
1537 }
1538 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1539 {
1540         BUG_ON(obj->pages == NULL);
1541         obj->pages_pin_count++;
1542 }
1543 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1544 {
1545         BUG_ON(obj->pages_pin_count == 0);
1546         obj->pages_pin_count--;
1547 }
1548
1549 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1550 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1551                          struct intel_ring_buffer *to);
1552 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1553                                     struct intel_ring_buffer *ring);
1554
1555 int i915_gem_dumb_create(struct drm_file *file_priv,
1556                          struct drm_device *dev,
1557                          struct drm_mode_create_dumb *args);
1558 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1559                       uint32_t handle, uint64_t *offset);
1560 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1561                           uint32_t handle);
1562 /**
1563  * Returns true if seq1 is later than seq2.
1564  */
1565 static inline bool
1566 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1567 {
1568         return (int32_t)(seq1 - seq2) >= 0;
1569 }
1570
1571 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1572 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1573 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1574 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1575
1576 static inline bool
1577 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1578 {
1579         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1580                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1581                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1582                 return true;
1583         } else
1584                 return false;
1585 }
1586
1587 static inline void
1588 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1589 {
1590         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1591                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1592                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1593         }
1594 }
1595
1596 void i915_gem_retire_requests(struct drm_device *dev);
1597 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1598 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
1599                                       bool interruptible);
1600 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
1601 {
1602         return unlikely(atomic_read(&error->reset_counter)
1603                         & I915_RESET_IN_PROGRESS_FLAG);
1604 }
1605
1606 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
1607 {
1608         return atomic_read(&error->reset_counter) == I915_WEDGED;
1609 }
1610
1611 void i915_gem_reset(struct drm_device *dev);
1612 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1613 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1614                                             uint32_t read_domains,
1615                                             uint32_t write_domain);
1616 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1617 int __must_check i915_gem_init(struct drm_device *dev);
1618 int __must_check i915_gem_init_hw(struct drm_device *dev);
1619 void i915_gem_l3_remap(struct drm_device *dev);
1620 void i915_gem_init_swizzling(struct drm_device *dev);
1621 void i915_gem_init_ppgtt(struct drm_device *dev);
1622 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1623 int __must_check i915_gpu_idle(struct drm_device *dev);
1624 int __must_check i915_gem_idle(struct drm_device *dev);
1625 int i915_add_request(struct intel_ring_buffer *ring,
1626                      struct drm_file *file,
1627                      u32 *seqno);
1628 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1629                                  uint32_t seqno);
1630 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1631 int __must_check
1632 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1633                                   bool write);
1634 int __must_check
1635 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1636 int __must_check
1637 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1638                                      u32 alignment,
1639                                      struct intel_ring_buffer *pipelined);
1640 int i915_gem_attach_phys_object(struct drm_device *dev,
1641                                 struct drm_i915_gem_object *obj,
1642                                 int id,
1643                                 int align);
1644 void i915_gem_detach_phys_object(struct drm_device *dev,
1645                                  struct drm_i915_gem_object *obj);
1646 void i915_gem_free_all_phys_object(struct drm_device *dev);
1647 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1648
1649 uint32_t
1650 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1651 uint32_t
1652 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1653                             int tiling_mode, bool fenced);
1654
1655 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1656                                     enum i915_cache_level cache_level);
1657
1658 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1659                                 struct dma_buf *dma_buf);
1660
1661 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1662                                 struct drm_gem_object *gem_obj, int flags);
1663
1664 /* i915_gem_context.c */
1665 void i915_gem_context_init(struct drm_device *dev);
1666 void i915_gem_context_fini(struct drm_device *dev);
1667 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1668 int i915_switch_context(struct intel_ring_buffer *ring,
1669                         struct drm_file *file, int to_id);
1670 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1671                                   struct drm_file *file);
1672 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1673                                    struct drm_file *file);
1674
1675 /* i915_gem_gtt.c */
1676 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1677 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1678                             struct drm_i915_gem_object *obj,
1679                             enum i915_cache_level cache_level);
1680 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1681                               struct drm_i915_gem_object *obj);
1682
1683 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1684 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1685 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1686                                 enum i915_cache_level cache_level);
1687 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1688 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1689 void i915_gem_init_global_gtt(struct drm_device *dev);
1690 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1691                                unsigned long mappable_end, unsigned long end);
1692 int i915_gem_gtt_init(struct drm_device *dev);
1693 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1694 {
1695         if (INTEL_INFO(dev)->gen < 6)
1696                 intel_gtt_chipset_flush();
1697 }
1698
1699
1700 /* i915_gem_evict.c */
1701 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1702                                           unsigned alignment,
1703                                           unsigned cache_level,
1704                                           bool mappable,
1705                                           bool nonblock);
1706 int i915_gem_evict_everything(struct drm_device *dev);
1707
1708 /* i915_gem_stolen.c */
1709 int i915_gem_init_stolen(struct drm_device *dev);
1710 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1711 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1712 void i915_gem_cleanup_stolen(struct drm_device *dev);
1713 struct drm_i915_gem_object *
1714 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1715 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1716
1717 /* i915_gem_tiling.c */
1718 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1719 {
1720         drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1721
1722         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1723                 obj->tiling_mode != I915_TILING_NONE;
1724 }
1725
1726 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1727 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1728 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1729
1730 /* i915_gem_debug.c */
1731 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1732                           const char *where, uint32_t mark);
1733 #if WATCH_LISTS
1734 int i915_verify_lists(struct drm_device *dev);
1735 #else
1736 #define i915_verify_lists(dev) 0
1737 #endif
1738 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1739                                      int handle);
1740 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1741                           const char *where, uint32_t mark);
1742
1743 /* i915_debugfs.c */
1744 int i915_debugfs_init(struct drm_minor *minor);
1745 void i915_debugfs_cleanup(struct drm_minor *minor);
1746
1747 /* i915_suspend.c */
1748 extern int i915_save_state(struct drm_device *dev);
1749 extern int i915_restore_state(struct drm_device *dev);
1750
1751 /* i915_ums.c */
1752 void i915_save_display_reg(struct drm_device *dev);
1753 void i915_restore_display_reg(struct drm_device *dev);
1754
1755 /* i915_sysfs.c */
1756 void i915_setup_sysfs(struct drm_device *dev_priv);
1757 void i915_teardown_sysfs(struct drm_device *dev_priv);
1758
1759 /* intel_i2c.c */
1760 extern int intel_setup_gmbus(struct drm_device *dev);
1761 extern void intel_teardown_gmbus(struct drm_device *dev);
1762 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1763 {
1764         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1765 }
1766
1767 extern struct i2c_adapter *intel_gmbus_get_adapter(
1768                 struct drm_i915_private *dev_priv, unsigned port);
1769 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1770 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1771 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1772 {
1773         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1774 }
1775 extern void intel_i2c_reset(struct drm_device *dev);
1776
1777 /* intel_opregion.c */
1778 extern int intel_opregion_setup(struct drm_device *dev);
1779 #ifdef CONFIG_ACPI
1780 extern void intel_opregion_init(struct drm_device *dev);
1781 extern void intel_opregion_fini(struct drm_device *dev);
1782 extern void intel_opregion_asle_intr(struct drm_device *dev);
1783 extern void intel_opregion_gse_intr(struct drm_device *dev);
1784 extern void intel_opregion_enable_asle(struct drm_device *dev);
1785 #else
1786 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1787 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1788 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1789 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1790 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1791 #endif
1792
1793 /* intel_acpi.c */
1794 #ifdef CONFIG_ACPI
1795 extern void intel_register_dsm_handler(void);
1796 extern void intel_unregister_dsm_handler(void);
1797 #else
1798 static inline void intel_register_dsm_handler(void) { return; }
1799 static inline void intel_unregister_dsm_handler(void) { return; }
1800 #endif /* CONFIG_ACPI */
1801
1802 /* modesetting */
1803 extern void intel_modeset_init_hw(struct drm_device *dev);
1804 extern void intel_modeset_init(struct drm_device *dev);
1805 extern void intel_modeset_gem_init(struct drm_device *dev);
1806 extern void intel_modeset_cleanup(struct drm_device *dev);
1807 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1808 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1809                                          bool force_restore);
1810 extern void i915_redisable_vga(struct drm_device *dev);
1811 extern bool intel_fbc_enabled(struct drm_device *dev);
1812 extern void intel_disable_fbc(struct drm_device *dev);
1813 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1814 extern void intel_init_pch_refclk(struct drm_device *dev);
1815 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1816 extern void intel_detect_pch(struct drm_device *dev);
1817 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1818 extern int intel_enable_rc6(const struct drm_device *dev);
1819
1820 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1821 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1822                         struct drm_file *file);
1823
1824 /* overlay */
1825 #ifdef CONFIG_DEBUG_FS
1826 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1827 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1828
1829 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1830 extern void intel_display_print_error_state(struct seq_file *m,
1831                                             struct drm_device *dev,
1832                                             struct intel_display_error_state *error);
1833 #endif
1834
1835 /* On SNB platform, before reading ring registers forcewake bit
1836  * must be set to prevent GT core from power down and stale values being
1837  * returned.
1838  */
1839 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1840 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1841 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1842
1843 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1844 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1845
1846 #define __i915_read(x, y) \
1847         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1848
1849 __i915_read(8, b)
1850 __i915_read(16, w)
1851 __i915_read(32, l)
1852 __i915_read(64, q)
1853 #undef __i915_read
1854
1855 #define __i915_write(x, y) \
1856         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1857
1858 __i915_write(8, b)
1859 __i915_write(16, w)
1860 __i915_write(32, l)
1861 __i915_write(64, q)
1862 #undef __i915_write
1863
1864 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1865 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1866
1867 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1868 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1869 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1870 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1871
1872 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1873 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1874 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1875 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1876
1877 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1878 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1879
1880 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1881 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1882
1883 /* "Broadcast RGB" property */
1884 #define INTEL_BROADCAST_RGB_AUTO 0
1885 #define INTEL_BROADCAST_RGB_FULL 1
1886 #define INTEL_BROADCAST_RGB_LIMITED 2
1887
1888 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
1889 {
1890         if (HAS_PCH_SPLIT(dev))
1891                 return CPU_VGACNTRL;
1892         else if (IS_VALLEYVIEW(dev))
1893                 return VLV_VGACNTRL;
1894         else
1895                 return VGACNTRL;
1896 }
1897
1898 static inline void __user *to_user_ptr(u64 address)
1899 {
1900         return (void __user *)(uintptr_t)address;
1901 }
1902
1903 #endif