1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
40 /* General customization:
43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45 #define DRIVER_NAME "i915"
46 #define DRIVER_DESC "Intel Graphics"
47 #define DRIVER_DATE "20080730"
55 #define pipe_name(p) ((p) + 'A')
62 #define plane_name(p) ((p) + 'A')
64 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
71 * 1.2: Add Power Management
72 * 1.3: Add vblank support
73 * 1.4: Fix cmdbuffer path, add heap destroy
74 * 1.5: Add vblank pipe configuration
75 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
76 * - Support vertical blank on secondary display pipe
78 #define DRIVER_MAJOR 1
79 #define DRIVER_MINOR 6
80 #define DRIVER_PATCHLEVEL 0
82 #define WATCH_COHERENCY 0
85 #define I915_GEM_PHYS_CURSOR_0 1
86 #define I915_GEM_PHYS_CURSOR_1 2
87 #define I915_GEM_PHYS_OVERLAY_REGS 3
88 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90 struct drm_i915_gem_phys_object
{
92 struct page
**page_list
;
93 drm_dma_handle_t
*handle
;
94 struct drm_i915_gem_object
*cur_obj
;
98 struct mem_block
*next
;
99 struct mem_block
*prev
;
102 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
105 struct opregion_header
;
106 struct opregion_acpi
;
107 struct opregion_swsci
;
108 struct opregion_asle
;
110 struct intel_opregion
{
111 struct opregion_header
*header
;
112 struct opregion_acpi
*acpi
;
113 struct opregion_swsci
*swsci
;
114 struct opregion_asle
*asle
;
116 u32 __iomem
*lid_state
;
118 #define OPREGION_SIZE (8*1024)
120 struct intel_overlay
;
121 struct intel_overlay_error_state
;
123 struct drm_i915_master_private
{
124 drm_local_map_t
*sarea
;
125 struct _drm_i915_sarea
*sarea_priv
;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg
{
130 struct list_head lru_list
;
131 struct drm_i915_gem_object
*obj
;
132 uint32_t setup_seqno
;
135 struct sdvo_device_mapping
{
145 struct intel_display_error_state
;
147 struct drm_i915_error_state
{
150 u32 pipestat
[I915_MAX_PIPES
];
155 u32 error
; /* gen6+ */
156 u32 bcs_acthd
; /* gen6+ blt engine */
161 u32 vcs_acthd
; /* gen6+ bsd engine */
173 struct drm_i915_error_object
{
177 } *ringbuffer
[I915_NUM_RINGS
], *batchbuffer
[I915_NUM_RINGS
];
178 struct drm_i915_error_buffer
{
192 } *active_bo
, *pinned_bo
;
193 u32 active_bo_count
, pinned_bo_count
;
194 struct intel_overlay_error_state
*overlay
;
195 struct intel_display_error_state
*display
;
198 struct drm_i915_display_funcs
{
199 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
200 bool (*fbc_enabled
)(struct drm_device
*dev
);
201 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
202 void (*disable_fbc
)(struct drm_device
*dev
);
203 int (*get_display_clock_speed
)(struct drm_device
*dev
);
204 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
205 void (*update_wm
)(struct drm_device
*dev
);
206 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
207 struct drm_display_mode
*mode
,
208 struct drm_display_mode
*adjusted_mode
,
210 struct drm_framebuffer
*old_fb
);
211 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
212 void (*init_clock_gating
)(struct drm_device
*dev
);
213 void (*init_pch_clock_gating
)(struct drm_device
*dev
);
214 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
215 struct drm_framebuffer
*fb
,
216 struct drm_i915_gem_object
*obj
);
217 /* clock updates for mode set */
219 /* render clock increase/decrease */
220 /* display clock increase/decrease */
221 /* pll clock increase/decrease */
224 struct intel_device_info
{
234 u8 is_broadwater
: 1;
238 u8 has_pipe_cxsr
: 1;
240 u8 cursor_needs_physical
: 1;
242 u8 overlay_needs_physical
: 1;
249 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
250 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
251 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
252 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
253 FBC_BAD_PLANE
, /* fbc not supported on plane */
254 FBC_NOT_TILED
, /* buffer not tiled */
255 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
260 PCH_IBX
, /* Ibexpeak PCH */
261 PCH_CPT
, /* Cougarpoint PCH */
264 #define QUIRK_PIPEA_FORCE (1<<0)
268 typedef struct drm_i915_private
{
269 struct drm_device
*dev
;
271 const struct intel_device_info
*info
;
274 int relative_constants_mode
;
279 struct i2c_adapter adapter
;
280 struct i2c_adapter
*force_bit
;
284 struct pci_dev
*bridge_dev
;
285 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
288 drm_dma_handle_t
*status_page_dmah
;
290 drm_local_map_t hws_map
;
291 struct drm_i915_gem_object
*pwrctx
;
292 struct drm_i915_gem_object
*renderctx
;
294 struct resource mch_res
;
302 atomic_t irq_received
;
304 /* protects the irq masks */
306 /** Cached value of IMR to avoid reads in updating the bitfield */
312 u32 hotplug_supported_mask
;
313 struct work_struct hotplug_work
;
315 int tex_lru_log_granularity
;
316 int allow_batchbuffer
;
317 struct mem_block
*agp_heap
;
318 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
322 /* For hangcheck timer */
323 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
324 struct timer_list hangcheck_timer
;
327 uint32_t last_instdone
;
328 uint32_t last_instdone1
;
330 unsigned long cfb_size
;
331 unsigned long cfb_pitch
;
332 unsigned long cfb_offset
;
337 struct intel_opregion opregion
;
340 struct intel_overlay
*overlay
;
343 int backlight_level
; /* restore backlight to this value */
344 bool backlight_enabled
;
345 struct drm_display_mode
*panel_fixed_mode
;
346 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
347 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
349 /* Feature bits from the VBIOS */
350 unsigned int int_tv_support
:1;
351 unsigned int lvds_dither
:1;
352 unsigned int lvds_vbt
:1;
353 unsigned int int_crt_support
:1;
354 unsigned int lvds_use_ssc
:1;
365 struct edp_power_seq pps
;
367 bool no_aux_handshake
;
369 struct notifier_block lid_notifier
;
372 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
373 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
374 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
376 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
378 spinlock_t error_lock
;
379 struct drm_i915_error_state
*first_error
;
380 struct work_struct error_work
;
381 struct completion error_completion
;
382 struct workqueue_struct
*wq
;
384 /* Display functions */
385 struct drm_i915_display_funcs display
;
387 /* PCH chipset type */
388 enum intel_pch pch_type
;
390 unsigned long quirks
;
415 u32 saveTRANS_HTOTAL_A
;
416 u32 saveTRANS_HBLANK_A
;
417 u32 saveTRANS_HSYNC_A
;
418 u32 saveTRANS_VTOTAL_A
;
419 u32 saveTRANS_VBLANK_A
;
420 u32 saveTRANS_VSYNC_A
;
428 u32 savePFIT_PGM_RATIOS
;
429 u32 saveBLC_HIST_CTL
;
431 u32 saveBLC_PWM_CTL2
;
432 u32 saveBLC_CPU_PWM_CTL
;
433 u32 saveBLC_CPU_PWM_CTL2
;
446 u32 saveTRANS_HTOTAL_B
;
447 u32 saveTRANS_HBLANK_B
;
448 u32 saveTRANS_HSYNC_B
;
449 u32 saveTRANS_VTOTAL_B
;
450 u32 saveTRANS_VBLANK_B
;
451 u32 saveTRANS_VSYNC_B
;
465 u32 savePP_ON_DELAYS
;
466 u32 savePP_OFF_DELAYS
;
474 u32 savePFIT_CONTROL
;
475 u32 save_palette_a
[256];
476 u32 save_palette_b
[256];
477 u32 saveDPFC_CB_BASE
;
478 u32 saveFBC_CFB_BASE
;
481 u32 saveFBC_CONTROL2
;
491 u32 saveCACHE_MODE_0
;
492 u32 saveMI_ARB_STATE
;
503 uint64_t saveFENCE
[16];
514 u32 savePIPEA_GMCH_DATA_M
;
515 u32 savePIPEB_GMCH_DATA_M
;
516 u32 savePIPEA_GMCH_DATA_N
;
517 u32 savePIPEB_GMCH_DATA_N
;
518 u32 savePIPEA_DP_LINK_M
;
519 u32 savePIPEB_DP_LINK_M
;
520 u32 savePIPEA_DP_LINK_N
;
521 u32 savePIPEB_DP_LINK_N
;
532 u32 savePCH_DREF_CONTROL
;
533 u32 saveDISP_ARB_CTL
;
534 u32 savePIPEA_DATA_M1
;
535 u32 savePIPEA_DATA_N1
;
536 u32 savePIPEA_LINK_M1
;
537 u32 savePIPEA_LINK_N1
;
538 u32 savePIPEB_DATA_M1
;
539 u32 savePIPEB_DATA_N1
;
540 u32 savePIPEB_LINK_M1
;
541 u32 savePIPEB_LINK_N1
;
542 u32 saveMCHBAR_RENDER_STANDBY
;
545 /** Bridge to intel-gtt-ko */
546 const struct intel_gtt
*gtt
;
547 /** Memory allocator for GTT stolen memory */
548 struct drm_mm stolen
;
549 /** Memory allocator for GTT */
550 struct drm_mm gtt_space
;
551 /** List of all objects in gtt_space. Used to restore gtt
552 * mappings on resume */
553 struct list_head gtt_list
;
555 /** Usable portion of the GTT for GEM */
556 unsigned long gtt_start
;
557 unsigned long gtt_mappable_end
;
558 unsigned long gtt_end
;
560 struct io_mapping
*gtt_mapping
;
563 struct shrinker inactive_shrinker
;
566 * List of objects currently involved in rendering.
568 * Includes buffers having the contents of their GPU caches
569 * flushed, not necessarily primitives. last_rendering_seqno
570 * represents when the rendering involved will be completed.
572 * A reference is held on the buffer while on this list.
574 struct list_head active_list
;
577 * List of objects which are not in the ringbuffer but which
578 * still have a write_domain which needs to be flushed before
581 * last_rendering_seqno is 0 while an object is in this list.
583 * A reference is held on the buffer while on this list.
585 struct list_head flushing_list
;
588 * LRU list of objects which are not in the ringbuffer and
589 * are ready to unbind, but are still in the GTT.
591 * last_rendering_seqno is 0 while an object is in this list.
593 * A reference is not held on the buffer while on this list,
594 * as merely being GTT-bound shouldn't prevent its being
595 * freed, and we'll pull it off the list in the free path.
597 struct list_head inactive_list
;
600 * LRU list of objects which are not in the ringbuffer but
601 * are still pinned in the GTT.
603 struct list_head pinned_list
;
605 /** LRU list of objects with fence regs on them. */
606 struct list_head fence_list
;
609 * List of objects currently pending being freed.
611 * These objects are no longer in use, but due to a signal
612 * we were prevented from freeing them at the appointed time.
614 struct list_head deferred_free_list
;
617 * We leave the user IRQ off as much as possible,
618 * but this means that requests will finish and never
619 * be retired once the system goes idle. Set a timer to
620 * fire periodically while the ring is running. When it
621 * fires, go retire requests.
623 struct delayed_work retire_work
;
626 * Are we in a non-interruptible section of code like
632 * Flag if the X Server, and thus DRM, is not currently in
633 * control of the device.
635 * This is set between LeaveVT and EnterVT. It needs to be
636 * replaced with a semaphore. It also needs to be
637 * transitioned away from for kernel modesetting.
642 * Flag if the hardware appears to be wedged.
644 * This is set when attempts to idle the device timeout.
645 * It prevents command submission from occurring and makes
646 * every pending request fail
650 /** Bit 6 swizzling required for X tiling */
651 uint32_t bit_6_swizzle_x
;
652 /** Bit 6 swizzling required for Y tiling */
653 uint32_t bit_6_swizzle_y
;
655 /* storage for physical objects */
656 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
658 /* accounting, useful for userland debugging */
660 size_t mappable_gtt_total
;
661 size_t object_memory
;
664 struct sdvo_device_mapping sdvo_mappings
[2];
665 /* indicate whether the LVDS_BORDER should be enabled or not */
666 unsigned int lvds_border_bits
;
667 /* Panel fitter placement and size for Ironlake+ */
668 u32 pch_pf_pos
, pch_pf_size
;
669 int panel_t3
, panel_t12
;
671 struct drm_crtc
*plane_to_crtc_mapping
[2];
672 struct drm_crtc
*pipe_to_crtc_mapping
[2];
673 wait_queue_head_t pending_flip_queue
;
674 bool flip_pending_is_done
;
676 /* Reclocking support */
677 bool render_reclock_avail
;
678 bool lvds_downclock_avail
;
679 /* indicates the reduced downclock for LVDS*/
681 struct work_struct idle_work
;
682 struct timer_list idle_timer
;
686 struct child_device_config
*child_dev
;
687 struct drm_connector
*int_lvds_connector
;
689 bool mchbar_need_disable
;
691 struct work_struct rps_work
;
702 unsigned long last_time1
;
704 struct timespec last_time2
;
705 unsigned long gfx_power
;
709 spinlock_t
*mchdev_lock
;
711 enum no_fbc_reason no_fbc_reason
;
713 struct drm_mm_node
*compressed_fb
;
714 struct drm_mm_node
*compressed_llb
;
716 unsigned long last_gpu_reset
;
718 /* list of fbdev register on this device */
719 struct intel_fbdev
*fbdev
;
721 struct drm_property
*broadcast_rgb_property
;
722 struct drm_property
*force_audio_property
;
724 atomic_t forcewake_count
;
725 } drm_i915_private_t
;
727 enum i915_cache_level
{
730 I915_CACHE_LLC_MLC
, /* gen6+ */
733 struct drm_i915_gem_object
{
734 struct drm_gem_object base
;
736 /** Current space allocated to this object in the GTT, if any. */
737 struct drm_mm_node
*gtt_space
;
738 struct list_head gtt_list
;
740 /** This object's place on the active/flushing/inactive lists */
741 struct list_head ring_list
;
742 struct list_head mm_list
;
743 /** This object's place on GPU write list */
744 struct list_head gpu_write_list
;
745 /** This object's place in the batchbuffer or on the eviction list */
746 struct list_head exec_list
;
749 * This is set if the object is on the active or flushing lists
750 * (has pending rendering), and is not set if it's on inactive (ready
753 unsigned int active
: 1;
756 * This is set if the object has been written to since last bound
759 unsigned int dirty
: 1;
762 * This is set if the object has been written to since the last
765 unsigned int pending_gpu_write
: 1;
768 * Fence register bits (if any) for this object. Will be set
769 * as needed when mapped into the GTT.
770 * Protected by dev->struct_mutex.
772 * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
774 signed int fence_reg
: 5;
777 * Advice: are the backing pages purgeable?
779 unsigned int madv
: 2;
782 * Current tiling mode for the object.
784 unsigned int tiling_mode
: 2;
785 unsigned int tiling_changed
: 1;
787 /** How many users have pinned this object in GTT space. The following
788 * users can each hold at most one reference: pwrite/pread, pin_ioctl
789 * (via user_pin_count), execbuffer (objects are not allowed multiple
790 * times for the same batchbuffer), and the framebuffer code. When
791 * switching/pageflipping, the framebuffer code has at most two buffers
794 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
795 * bits with absolutely no headroom. So use 4 bits. */
796 unsigned int pin_count
: 4;
797 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
800 * Is the object at the current location in the gtt mappable and
801 * fenceable? Used to avoid costly recalculations.
803 unsigned int map_and_fenceable
: 1;
806 * Whether the current gtt mapping needs to be mappable (and isn't just
807 * mappable by accident). Track pin and fault separate for a more
808 * accurate mappable working set.
810 unsigned int fault_mappable
: 1;
811 unsigned int pin_mappable
: 1;
814 * Is the GPU currently using a fence to access this buffer,
816 unsigned int pending_fenced_gpu_access
:1;
817 unsigned int fenced_gpu_access
:1;
819 unsigned int cache_level
:2;
826 struct scatterlist
*sg_list
;
830 * Used for performing relocations during execbuffer insertion.
832 struct hlist_node exec_node
;
833 unsigned long exec_handle
;
834 struct drm_i915_gem_exec_object2
*exec_entry
;
837 * Current offset of the object in GTT space.
839 * This is the same as gtt_space->start
843 /** Breadcrumb of last rendering to the buffer. */
844 uint32_t last_rendering_seqno
;
845 struct intel_ring_buffer
*ring
;
847 /** Breadcrumb of last fenced GPU access to the buffer. */
848 uint32_t last_fenced_seqno
;
849 struct intel_ring_buffer
*last_fenced_ring
;
851 /** Current tiling stride for the object, if it's tiled. */
854 /** Record of address bit 17 of each page at last unbind. */
855 unsigned long *bit_17
;
859 * If present, while GEM_DOMAIN_CPU is in the read domain this array
860 * flags which individual pages are valid.
862 uint8_t *page_cpu_valid
;
864 /** User space pin count and filp owning the pin */
865 uint32_t user_pin_count
;
866 struct drm_file
*pin_filp
;
868 /** for phy allocated objects */
869 struct drm_i915_gem_phys_object
*phys_obj
;
872 * Number of crtcs where this object is currently the fb, but
873 * will be page flipped away on the next vblank. When it
874 * reaches 0, dev_priv->pending_flip_queue will be woken up.
876 atomic_t pending_flip
;
879 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
882 * Request queue structure.
884 * The request queue allows us to note sequence numbers that have been emitted
885 * and may be associated with active buffers to be retired.
887 * By keeping this list, we can avoid having to do questionable
888 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
889 * an emission time with seqnos for tracking how far ahead of the GPU we are.
891 struct drm_i915_gem_request
{
892 /** On Which ring this request was generated */
893 struct intel_ring_buffer
*ring
;
895 /** GEM sequence number associated with this request. */
898 /** Time at which this request was emitted, in jiffies. */
899 unsigned long emitted_jiffies
;
901 /** global list entry for this request */
902 struct list_head list
;
904 struct drm_i915_file_private
*file_priv
;
905 /** file_priv list entry for this request */
906 struct list_head client_list
;
909 struct drm_i915_file_private
{
911 struct spinlock lock
;
912 struct list_head request_list
;
916 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
918 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
919 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
920 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
921 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
922 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
923 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
924 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
925 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
926 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
927 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
928 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
929 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
930 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
931 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
932 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
933 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
934 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
935 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
936 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
937 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
940 * The genX designation typically refers to the render engine, so render
941 * capability related checks should use IS_GEN, while display and other checks
942 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
945 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
946 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
947 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
948 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
949 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
950 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
952 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
953 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
954 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
956 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
957 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
959 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
960 * rows, which changed the alignment requirements and fence programming.
962 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
964 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
965 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
966 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
967 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
968 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
969 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
970 /* dsparb controlled by hw only */
971 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
973 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
974 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
975 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
977 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
978 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
980 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
981 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
982 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
984 #include "i915_trace.h"
986 extern struct drm_ioctl_desc i915_ioctls
[];
987 extern int i915_max_ioctl
;
988 extern unsigned int i915_fbpercrtc
;
989 extern int i915_panel_ignore_lid
;
990 extern unsigned int i915_powersave
;
991 extern unsigned int i915_semaphores
;
992 extern unsigned int i915_lvds_downclock
;
993 extern unsigned int i915_panel_use_ssc
;
994 extern int i915_vbt_sdvo_panel_type
;
995 extern unsigned int i915_enable_rc6
;
996 extern unsigned int i915_enable_fbc
;
998 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
999 extern int i915_resume(struct drm_device
*dev
);
1000 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1001 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1004 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1005 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1006 extern int i915_driver_unload(struct drm_device
*);
1007 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1008 extern void i915_driver_lastclose(struct drm_device
* dev
);
1009 extern void i915_driver_preclose(struct drm_device
*dev
,
1010 struct drm_file
*file_priv
);
1011 extern void i915_driver_postclose(struct drm_device
*dev
,
1012 struct drm_file
*file_priv
);
1013 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1014 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1016 extern int i915_emit_box(struct drm_device
*dev
,
1017 struct drm_clip_rect
*box
,
1019 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
1020 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1021 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1022 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1023 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1027 void i915_hangcheck_elapsed(unsigned long data
);
1028 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1029 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
1030 struct drm_file
*file_priv
);
1031 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
1032 struct drm_file
*file_priv
);
1034 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
1035 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
1036 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
1037 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
1039 extern irqreturn_t
ironlake_irq_handler(DRM_IRQ_ARGS
);
1040 extern void ironlake_irq_preinstall(struct drm_device
*dev
);
1041 extern int ironlake_irq_postinstall(struct drm_device
*dev
);
1042 extern void ironlake_irq_uninstall(struct drm_device
*dev
);
1044 extern irqreturn_t
ivybridge_irq_handler(DRM_IRQ_ARGS
);
1045 extern void ivybridge_irq_preinstall(struct drm_device
*dev
);
1046 extern int ivybridge_irq_postinstall(struct drm_device
*dev
);
1047 extern void ivybridge_irq_uninstall(struct drm_device
*dev
);
1049 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1050 struct drm_file
*file_priv
);
1051 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1052 struct drm_file
*file_priv
);
1053 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
1054 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
1055 extern int ironlake_enable_vblank(struct drm_device
*dev
, int crtc
);
1056 extern void ironlake_disable_vblank(struct drm_device
*dev
, int crtc
);
1057 extern int ivybridge_enable_vblank(struct drm_device
*dev
, int crtc
);
1058 extern void ivybridge_disable_vblank(struct drm_device
*dev
, int crtc
);
1059 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
1060 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
1061 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1062 struct drm_file
*file_priv
);
1065 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1068 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1070 void intel_enable_asle (struct drm_device
*dev
);
1071 int i915_get_vblank_timestamp(struct drm_device
*dev
, int crtc
,
1073 struct timeval
*vblank_time
,
1076 int i915_get_crtc_scanoutpos(struct drm_device
*dev
, int pipe
,
1077 int *vpos
, int *hpos
);
1079 #ifdef CONFIG_DEBUG_FS
1080 extern void i915_destroy_error_state(struct drm_device
*dev
);
1082 #define i915_destroy_error_state(x)
1087 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
1088 struct drm_file
*file_priv
);
1089 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
1090 struct drm_file
*file_priv
);
1091 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
1092 struct drm_file
*file_priv
);
1093 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
1094 struct drm_file
*file_priv
);
1095 extern void i915_mem_takedown(struct mem_block
**heap
);
1096 extern void i915_mem_release(struct drm_device
* dev
,
1097 struct drm_file
*file_priv
, struct mem_block
*heap
);
1099 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1100 struct drm_file
*file_priv
);
1101 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1102 struct drm_file
*file_priv
);
1103 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1104 struct drm_file
*file_priv
);
1105 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1106 struct drm_file
*file_priv
);
1107 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1108 struct drm_file
*file_priv
);
1109 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1110 struct drm_file
*file_priv
);
1111 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1112 struct drm_file
*file_priv
);
1113 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1114 struct drm_file
*file_priv
);
1115 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1116 struct drm_file
*file_priv
);
1117 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1118 struct drm_file
*file_priv
);
1119 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1120 struct drm_file
*file_priv
);
1121 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1122 struct drm_file
*file_priv
);
1123 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1124 struct drm_file
*file_priv
);
1125 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1126 struct drm_file
*file_priv
);
1127 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1128 struct drm_file
*file_priv
);
1129 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1130 struct drm_file
*file_priv
);
1131 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1132 struct drm_file
*file_priv
);
1133 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1134 struct drm_file
*file_priv
);
1135 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1136 struct drm_file
*file_priv
);
1137 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1138 struct drm_file
*file_priv
);
1139 void i915_gem_load(struct drm_device
*dev
);
1140 int i915_gem_init_object(struct drm_gem_object
*obj
);
1141 int __must_check
i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
1142 uint32_t invalidate_domains
,
1143 uint32_t flush_domains
);
1144 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1146 void i915_gem_free_object(struct drm_gem_object
*obj
);
1147 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1149 bool map_and_fenceable
);
1150 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1151 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1152 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1153 void i915_gem_lastclose(struct drm_device
*dev
);
1155 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1156 int __must_check
i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
);
1157 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1158 struct intel_ring_buffer
*ring
,
1161 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1162 struct drm_device
*dev
,
1163 struct drm_mode_create_dumb
*args
);
1164 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1165 uint32_t handle
, uint64_t *offset
);
1166 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1169 * Returns true if seq1 is later than seq2.
1172 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1174 return (int32_t)(seq1
- seq2
) >= 0;
1178 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1180 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1181 return ring
->outstanding_lazy_request
= dev_priv
->next_seqno
;
1184 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
1185 struct intel_ring_buffer
*pipelined
);
1186 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1188 void i915_gem_retire_requests(struct drm_device
*dev
);
1189 void i915_gem_reset(struct drm_device
*dev
);
1190 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1191 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1192 uint32_t read_domains
,
1193 uint32_t write_domain
);
1194 int __must_check
i915_gem_object_flush_gpu(struct drm_i915_gem_object
*obj
);
1195 int __must_check
i915_gem_init_ringbuffer(struct drm_device
*dev
);
1196 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1197 void i915_gem_do_init(struct drm_device
*dev
,
1198 unsigned long start
,
1199 unsigned long mappable_end
,
1201 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1202 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1203 int __must_check
i915_add_request(struct intel_ring_buffer
*ring
,
1204 struct drm_file
*file
,
1205 struct drm_i915_gem_request
*request
);
1206 int __must_check
i915_wait_request(struct intel_ring_buffer
*ring
,
1208 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1210 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1213 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object
*obj
,
1214 struct intel_ring_buffer
*pipelined
);
1215 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1216 struct drm_i915_gem_object
*obj
,
1219 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1220 struct drm_i915_gem_object
*obj
);
1221 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1222 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1225 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object
*obj
);
1227 /* i915_gem_gtt.c */
1228 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1229 int __must_check
i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
);
1230 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1232 /* i915_gem_evict.c */
1233 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1234 unsigned alignment
, bool mappable
);
1235 int __must_check
i915_gem_evict_everything(struct drm_device
*dev
,
1236 bool purgeable_only
);
1237 int __must_check
i915_gem_evict_inactive(struct drm_device
*dev
,
1238 bool purgeable_only
);
1240 /* i915_gem_tiling.c */
1241 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1242 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1243 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1245 /* i915_gem_debug.c */
1246 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1247 const char *where
, uint32_t mark
);
1249 int i915_verify_lists(struct drm_device
*dev
);
1251 #define i915_verify_lists(dev) 0
1253 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1255 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1256 const char *where
, uint32_t mark
);
1258 /* i915_debugfs.c */
1259 int i915_debugfs_init(struct drm_minor
*minor
);
1260 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1262 /* i915_suspend.c */
1263 extern int i915_save_state(struct drm_device
*dev
);
1264 extern int i915_restore_state(struct drm_device
*dev
);
1266 /* i915_suspend.c */
1267 extern int i915_save_state(struct drm_device
*dev
);
1268 extern int i915_restore_state(struct drm_device
*dev
);
1271 extern int intel_setup_gmbus(struct drm_device
*dev
);
1272 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1273 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1274 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1275 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1277 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1279 extern void intel_i2c_reset(struct drm_device
*dev
);
1281 /* intel_opregion.c */
1282 extern int intel_opregion_setup(struct drm_device
*dev
);
1284 extern void intel_opregion_init(struct drm_device
*dev
);
1285 extern void intel_opregion_fini(struct drm_device
*dev
);
1286 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1287 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1288 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1290 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1291 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1292 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1293 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1294 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1299 extern void intel_register_dsm_handler(void);
1300 extern void intel_unregister_dsm_handler(void);
1302 static inline void intel_register_dsm_handler(void) { return; }
1303 static inline void intel_unregister_dsm_handler(void) { return; }
1304 #endif /* CONFIG_ACPI */
1307 extern void intel_modeset_init(struct drm_device
*dev
);
1308 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1309 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1310 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1311 extern void i8xx_disable_fbc(struct drm_device
*dev
);
1312 extern void g4x_disable_fbc(struct drm_device
*dev
);
1313 extern void ironlake_disable_fbc(struct drm_device
*dev
);
1314 extern void intel_disable_fbc(struct drm_device
*dev
);
1315 extern void intel_enable_fbc(struct drm_crtc
*crtc
, unsigned long interval
);
1316 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1317 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1318 extern void ironlake_enable_rc6(struct drm_device
*dev
);
1319 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1320 extern void intel_detect_pch (struct drm_device
*dev
);
1321 extern int intel_trans_dp_port_sel (struct drm_crtc
*crtc
);
1324 #ifdef CONFIG_DEBUG_FS
1325 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1326 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1328 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1329 extern void intel_display_print_error_state(struct seq_file
*m
,
1330 struct drm_device
*dev
,
1331 struct intel_display_error_state
*error
);
1334 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1336 #define BEGIN_LP_RING(n) \
1337 intel_ring_begin(LP_RING(dev_priv), (n))
1339 #define OUT_RING(x) \
1340 intel_ring_emit(LP_RING(dev_priv), x)
1342 #define ADVANCE_LP_RING() \
1343 intel_ring_advance(LP_RING(dev_priv))
1346 * Lock test for when it's just for synchronization of ring access.
1348 * In that case, we don't need to do it when GEM is initialized as nobody else
1349 * has access to the ring.
1351 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1352 if (LP_RING(dev->dev_private)->obj == NULL) \
1353 LOCK_TEST_WITH_RETURN(dev, file); \
1356 /* On SNB platform, before reading ring registers forcewake bit
1357 * must be set to prevent GT core from power down and stale values being
1360 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1361 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1362 void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1364 /* We give fast paths for the really cool registers */
1365 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1366 (((dev_priv)->info->gen >= 6) && \
1367 ((reg) < 0x40000) && \
1368 ((reg) != FORCEWAKE))
1370 #define __i915_read(x, y) \
1371 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1373 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1374 gen6_gt_force_wake_get(dev_priv); \
1375 val = read##y(dev_priv->regs + reg); \
1376 gen6_gt_force_wake_put(dev_priv); \
1378 val = read##y(dev_priv->regs + reg); \
1380 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1390 #define __i915_write(x, y) \
1391 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1392 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1393 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1394 __gen6_gt_wait_for_fifo(dev_priv); \
1396 write##y(val, dev_priv->regs + reg); \
1404 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1405 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1407 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1408 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1409 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1410 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1412 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1413 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1414 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1415 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1417 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1418 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1420 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1421 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)