1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
65 #include "intel_gvt.h"
67 /* General customization:
70 #define DRIVER_NAME "i915"
71 #define DRIVER_DESC "Intel Graphics"
72 #define DRIVER_DATE "20160711"
75 /* Many gcc seem to no see through this and fall over :( */
77 #define WARN_ON(x) ({ \
78 bool __i915_warn_cond = (x); \
79 if (__builtin_constant_p(__i915_warn_cond)) \
80 BUILD_BUG_ON(__i915_warn_cond); \
81 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
83 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
87 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
89 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
90 (long) (x), __func__);
92 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
93 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
94 * which may not necessarily be a user visible problem. This will either
95 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
96 * enable distros and users to tailor their preferred amount of i915 abrt
99 #define I915_STATE_WARN(condition, format...) ({ \
100 int __ret_warn_on = !!(condition); \
101 if (unlikely(__ret_warn_on)) \
102 if (!WARN(i915.verbose_state_checks, format)) \
104 unlikely(__ret_warn_on); \
107 #define I915_STATE_WARN_ON(x) \
108 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
110 bool __i915_inject_load_failure(const char *func
, int line
);
111 #define i915_inject_load_failure() \
112 __i915_inject_load_failure(__func__, __LINE__)
114 static inline const char *yesno(bool v
)
116 return v
? "yes" : "no";
119 static inline const char *onoff(bool v
)
121 return v
? "on" : "off";
130 I915_MAX_PIPES
= _PIPE_EDP
132 #define pipe_name(p) ((p) + 'A')
144 static inline const char *transcoder_name(enum transcoder transcoder
)
146 switch (transcoder
) {
155 case TRANSCODER_DSI_A
:
157 case TRANSCODER_DSI_C
:
164 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
166 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
170 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
171 * number of planes per CRTC. Not all platforms really have this many planes,
172 * which means some arrays of size I915_MAX_PLANES may have unused entries
173 * between the topmost sprite plane and the cursor plane.
182 #define plane_name(p) ((p) + 'A')
184 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
194 #define port_name(p) ((p) + 'A')
196 #define I915_NUM_PHYS_VLV 2
208 enum intel_display_power_domain
{
212 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
213 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
214 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
215 POWER_DOMAIN_TRANSCODER_A
,
216 POWER_DOMAIN_TRANSCODER_B
,
217 POWER_DOMAIN_TRANSCODER_C
,
218 POWER_DOMAIN_TRANSCODER_EDP
,
219 POWER_DOMAIN_TRANSCODER_DSI_A
,
220 POWER_DOMAIN_TRANSCODER_DSI_C
,
221 POWER_DOMAIN_PORT_DDI_A_LANES
,
222 POWER_DOMAIN_PORT_DDI_B_LANES
,
223 POWER_DOMAIN_PORT_DDI_C_LANES
,
224 POWER_DOMAIN_PORT_DDI_D_LANES
,
225 POWER_DOMAIN_PORT_DDI_E_LANES
,
226 POWER_DOMAIN_PORT_DSI
,
227 POWER_DOMAIN_PORT_CRT
,
228 POWER_DOMAIN_PORT_OTHER
,
237 POWER_DOMAIN_MODESET
,
243 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
244 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
245 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
246 #define POWER_DOMAIN_TRANSCODER(tran) \
247 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
248 (tran) + POWER_DOMAIN_TRANSCODER_A)
252 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
264 #define for_each_hpd_pin(__pin) \
265 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
267 struct i915_hotplug
{
268 struct work_struct hotplug_work
;
271 unsigned long last_jiffies
;
276 HPD_MARK_DISABLED
= 2
278 } stats
[HPD_NUM_PINS
];
280 struct delayed_work reenable_work
;
282 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
285 struct work_struct dig_port_work
;
287 struct work_struct poll_init_work
;
291 * if we get a HPD irq from DP and a HPD irq from non-DP
292 * the non-DP HPD could block the workqueue on a mode config
293 * mutex getting, that userspace may have taken. However
294 * userspace is waiting on the DP workqueue to run which is
295 * blocked behind the non-DP one.
297 struct workqueue_struct
*dp_wq
;
300 #define I915_GEM_GPU_DOMAINS \
301 (I915_GEM_DOMAIN_RENDER | \
302 I915_GEM_DOMAIN_SAMPLER | \
303 I915_GEM_DOMAIN_COMMAND | \
304 I915_GEM_DOMAIN_INSTRUCTION | \
305 I915_GEM_DOMAIN_VERTEX)
307 #define for_each_pipe(__dev_priv, __p) \
308 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
309 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
310 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
311 for_each_if ((__mask) & (1 << (__p)))
312 #define for_each_plane(__dev_priv, __pipe, __p) \
314 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
316 #define for_each_sprite(__dev_priv, __p, __s) \
318 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
321 #define for_each_port_masked(__port, __ports_mask) \
322 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
323 for_each_if ((__ports_mask) & (1 << (__port)))
325 #define for_each_crtc(dev, crtc) \
326 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
328 #define for_each_intel_plane(dev, intel_plane) \
329 list_for_each_entry(intel_plane, \
330 &(dev)->mode_config.plane_list, \
333 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
334 list_for_each_entry(intel_plane, \
335 &(dev)->mode_config.plane_list, \
337 for_each_if ((plane_mask) & \
338 (1 << drm_plane_index(&intel_plane->base)))
340 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
341 list_for_each_entry(intel_plane, \
342 &(dev)->mode_config.plane_list, \
344 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
346 #define for_each_intel_crtc(dev, intel_crtc) \
347 list_for_each_entry(intel_crtc, \
348 &(dev)->mode_config.crtc_list, \
351 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
352 list_for_each_entry(intel_crtc, \
353 &(dev)->mode_config.crtc_list, \
355 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
357 #define for_each_intel_encoder(dev, intel_encoder) \
358 list_for_each_entry(intel_encoder, \
359 &(dev)->mode_config.encoder_list, \
362 #define for_each_intel_connector(dev, intel_connector) \
363 list_for_each_entry(intel_connector, \
364 &(dev)->mode_config.connector_list, \
367 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
368 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
369 for_each_if ((intel_encoder)->base.crtc == (__crtc))
371 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
372 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
373 for_each_if ((intel_connector)->base.encoder == (__encoder))
375 #define for_each_power_domain(domain, mask) \
376 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
377 for_each_if ((1 << (domain)) & (mask))
379 struct drm_i915_private
;
380 struct i915_mm_struct
;
381 struct i915_mmu_object
;
383 struct drm_i915_file_private
{
384 struct drm_i915_private
*dev_priv
;
385 struct drm_file
*file
;
389 struct list_head request_list
;
390 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
391 * chosen to prevent the CPU getting more than a frame ahead of the GPU
392 * (when using lax throttling for the frontbuffer). We also use it to
393 * offer free GPU waitboosts for severely congested workloads.
395 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
397 struct idr context_idr
;
399 struct intel_rps_client
{
400 struct list_head link
;
404 unsigned int bsd_ring
;
407 /* Used by dp and fdi links */
408 struct intel_link_m_n
{
416 void intel_link_compute_m_n(int bpp
, int nlanes
,
417 int pixel_clock
, int link_clock
,
418 struct intel_link_m_n
*m_n
);
420 /* Interface history:
423 * 1.2: Add Power Management
424 * 1.3: Add vblank support
425 * 1.4: Fix cmdbuffer path, add heap destroy
426 * 1.5: Add vblank pipe configuration
427 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
428 * - Support vertical blank on secondary display pipe
430 #define DRIVER_MAJOR 1
431 #define DRIVER_MINOR 6
432 #define DRIVER_PATCHLEVEL 0
434 #define WATCH_LISTS 0
436 struct opregion_header
;
437 struct opregion_acpi
;
438 struct opregion_swsci
;
439 struct opregion_asle
;
441 struct intel_opregion
{
442 struct opregion_header
*header
;
443 struct opregion_acpi
*acpi
;
444 struct opregion_swsci
*swsci
;
445 u32 swsci_gbda_sub_functions
;
446 u32 swsci_sbcb_sub_functions
;
447 struct opregion_asle
*asle
;
452 struct work_struct asle_work
;
454 #define OPREGION_SIZE (8*1024)
456 struct intel_overlay
;
457 struct intel_overlay_error_state
;
459 #define I915_FENCE_REG_NONE -1
460 #define I915_MAX_NUM_FENCES 32
461 /* 32 fences + sign bit for FENCE_REG_NONE */
462 #define I915_MAX_NUM_FENCE_BITS 6
464 struct drm_i915_fence_reg
{
465 struct list_head lru_list
;
466 struct drm_i915_gem_object
*obj
;
470 struct sdvo_device_mapping
{
479 struct intel_display_error_state
;
481 struct drm_i915_error_state
{
491 /* Generic register state */
499 u32 error
; /* gen6+ */
500 u32 err_int
; /* gen7 */
501 u32 fault_data0
; /* gen8, gen9 */
502 u32 fault_data1
; /* gen8, gen9 */
508 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
509 u64 fence
[I915_MAX_NUM_FENCES
];
510 struct intel_overlay_error_state
*overlay
;
511 struct intel_display_error_state
*display
;
512 struct drm_i915_error_object
*semaphore_obj
;
514 struct drm_i915_error_ring
{
516 /* Software tracked state */
520 enum intel_ring_hangcheck_action hangcheck_action
;
523 /* our own tracking of ring head and tail */
528 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
547 u32 rc_psmi
; /* sleep state */
548 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
550 struct drm_i915_error_object
{
554 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
556 struct drm_i915_error_object
*wa_ctx
;
558 struct drm_i915_error_request
{
564 struct drm_i915_error_waiter
{
565 char comm
[TASK_COMM_LEN
];
579 char comm
[TASK_COMM_LEN
];
580 } ring
[I915_NUM_ENGINES
];
582 struct drm_i915_error_buffer
{
585 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
589 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
597 } **active_bo
, **pinned_bo
;
599 u32
*active_bo_count
, *pinned_bo_count
;
603 struct intel_connector
;
604 struct intel_encoder
;
605 struct intel_crtc_state
;
606 struct intel_initial_plane_config
;
611 struct drm_i915_display_funcs
{
612 int (*get_display_clock_speed
)(struct drm_device
*dev
);
613 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
614 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
615 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
616 struct intel_crtc
*intel_crtc
,
617 struct intel_crtc_state
*newstate
);
618 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
619 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
620 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
621 void (*update_wm
)(struct drm_crtc
*crtc
);
622 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
623 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
624 /* Returns the active state of the crtc, and if the crtc is active,
625 * fills out the pipe-config with the hw state. */
626 bool (*get_pipe_config
)(struct intel_crtc
*,
627 struct intel_crtc_state
*);
628 void (*get_initial_plane_config
)(struct intel_crtc
*,
629 struct intel_initial_plane_config
*);
630 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
631 struct intel_crtc_state
*crtc_state
);
632 void (*crtc_enable
)(struct drm_crtc
*crtc
);
633 void (*crtc_disable
)(struct drm_crtc
*crtc
);
634 void (*audio_codec_enable
)(struct drm_connector
*connector
,
635 struct intel_encoder
*encoder
,
636 const struct drm_display_mode
*adjusted_mode
);
637 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
638 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
639 void (*init_clock_gating
)(struct drm_device
*dev
);
640 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
641 struct drm_framebuffer
*fb
,
642 struct drm_i915_gem_object
*obj
,
643 struct drm_i915_gem_request
*req
,
645 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
646 /* clock updates for mode set */
648 /* render clock increase/decrease */
649 /* display clock increase/decrease */
650 /* pll clock increase/decrease */
652 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
653 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
656 enum forcewake_domain_id
{
657 FW_DOMAIN_ID_RENDER
= 0,
658 FW_DOMAIN_ID_BLITTER
,
664 enum forcewake_domains
{
665 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
666 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
667 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
668 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
673 #define FW_REG_READ (1)
674 #define FW_REG_WRITE (2)
676 enum forcewake_domains
677 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
678 i915_reg_t reg
, unsigned int op
);
680 struct intel_uncore_funcs
{
681 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
682 enum forcewake_domains domains
);
683 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
684 enum forcewake_domains domains
);
686 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
687 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
688 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
689 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
691 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
692 uint8_t val
, bool trace
);
693 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
694 uint16_t val
, bool trace
);
695 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
696 uint32_t val
, bool trace
);
697 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
698 uint64_t val
, bool trace
);
701 struct intel_uncore
{
702 spinlock_t lock
; /** lock is also taken in irq contexts. */
704 struct intel_uncore_funcs funcs
;
707 enum forcewake_domains fw_domains
;
709 struct intel_uncore_forcewake_domain
{
710 struct drm_i915_private
*i915
;
711 enum forcewake_domain_id id
;
712 enum forcewake_domains mask
;
714 struct hrtimer timer
;
721 } fw_domain
[FW_DOMAIN_ID_COUNT
];
723 int unclaimed_mmio_check
;
726 /* Iterate over initialised fw domains */
727 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
728 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
729 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
731 for_each_if ((mask__) & (domain__)->mask)
733 #define for_each_fw_domain(domain__, dev_priv__) \
734 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
736 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
737 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
738 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
741 struct work_struct work
;
743 uint32_t *dmc_payload
;
744 uint32_t dmc_fw_size
;
747 i915_reg_t mmioaddr
[8];
748 uint32_t mmiodata
[8];
750 uint32_t allowed_dc_mask
;
753 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
754 func(is_mobile) sep \
757 func(is_i945gm) sep \
759 func(need_gfx_hws) sep \
761 func(is_pineview) sep \
762 func(is_broadwater) sep \
763 func(is_crestline) sep \
764 func(is_ivybridge) sep \
765 func(is_valleyview) sep \
766 func(is_cherryview) sep \
767 func(is_haswell) sep \
768 func(is_broadwell) sep \
769 func(is_skylake) sep \
770 func(is_broxton) sep \
771 func(is_kabylake) sep \
772 func(is_preliminary) sep \
774 func(has_pipe_cxsr) sep \
775 func(has_hotplug) sep \
776 func(cursor_needs_physical) sep \
777 func(has_overlay) sep \
778 func(overlay_needs_physical) sep \
779 func(supports_tv) sep \
781 func(has_snoop) sep \
783 func(has_fpga_dbg) sep \
786 #define DEFINE_FLAG(name) u8 name:1
787 #define SEP_SEMICOLON ;
789 struct intel_device_info
{
790 u32 display_mmio_offset
;
793 u8 num_sprites
[I915_MAX_PIPES
];
796 u8 ring_mask
; /* Rings supported by the HW */
797 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
798 /* Register offsets for the various display pipes and transcoders */
799 int pipe_offsets
[I915_MAX_TRANSCODERS
];
800 int trans_offsets
[I915_MAX_TRANSCODERS
];
801 int palette_offsets
[I915_MAX_PIPES
];
802 int cursor_offsets
[I915_MAX_PIPES
];
804 /* Slice/subslice/EU info */
807 u8 subslice_per_slice
;
811 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
814 u8 has_subslice_pg
:1;
818 u16 degamma_lut_size
;
826 enum i915_cache_level
{
828 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
829 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
830 caches, eg sampler/render caches, and the
831 large Last-Level-Cache. LLC is coherent with
832 the CPU, but L3 is only visible to the GPU. */
833 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
836 struct i915_ctx_hang_stats
{
837 /* This context had batch pending when hang was declared */
838 unsigned batch_pending
;
840 /* This context had batch active when hang was declared */
841 unsigned batch_active
;
843 /* Time when this context was last blamed for a GPU reset */
844 unsigned long guilty_ts
;
846 /* If the contexts causes a second GPU hang within this time,
847 * it is permanently banned from submitting any more work.
849 unsigned long ban_period_seconds
;
851 /* This context is banned to submit more work */
855 /* This must match up with the value previously used for execbuf2.rsvd1. */
856 #define DEFAULT_CONTEXT_HANDLE 0
859 * struct i915_gem_context - as the name implies, represents a context.
860 * @ref: reference count.
861 * @user_handle: userspace tracking identity for this context.
862 * @remap_slice: l3 row remapping information.
863 * @flags: context specific flags:
864 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
865 * @file_priv: filp associated with this context (NULL for global default
867 * @hang_stats: information about the role of this context in possible GPU
869 * @ppgtt: virtual memory space used by this context.
870 * @legacy_hw_ctx: render context backing object and whether it is correctly
871 * initialized (legacy ring submission mechanism only).
872 * @link: link in the global list of contexts.
874 * Contexts are memory images used by the hardware to store copies of their
877 struct i915_gem_context
{
879 struct drm_i915_private
*i915
;
880 struct drm_i915_file_private
*file_priv
;
881 struct i915_hw_ppgtt
*ppgtt
;
883 struct i915_ctx_hang_stats hang_stats
;
885 /* Unique identifier for this context, used by the hw for tracking */
887 #define CONTEXT_NO_ZEROMAP BIT(0)
888 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
894 struct intel_context
{
895 struct drm_i915_gem_object
*state
;
896 struct intel_ringbuffer
*ringbuf
;
897 struct i915_vma
*lrc_vma
;
898 uint32_t *lrc_reg_state
;
902 } engine
[I915_NUM_ENGINES
];
905 struct atomic_notifier_head status_notifier
;
906 bool execlists_force_single_submission
;
908 struct list_head link
;
922 /* This is always the inner lock when overlapping with struct_mutex and
923 * it's the outer lock when overlapping with stolen_lock. */
926 unsigned int possible_framebuffer_bits
;
927 unsigned int busy_bits
;
928 unsigned int visible_pipes_mask
;
929 struct intel_crtc
*crtc
;
931 struct drm_mm_node compressed_fb
;
932 struct drm_mm_node
*compressed_llb
;
939 struct intel_fbc_state_cache
{
941 unsigned int mode_flags
;
942 uint32_t hsw_bdw_pixel_rate
;
946 unsigned int rotation
;
954 uint32_t pixel_format
;
957 unsigned int tiling_mode
;
961 struct intel_fbc_reg_params
{
965 unsigned int fence_y_offset
;
970 uint32_t pixel_format
;
978 struct intel_fbc_work
{
980 u32 scheduled_vblank
;
981 struct work_struct work
;
984 const char *no_fbc_reason
;
988 * HIGH_RR is the highest eDP panel refresh rate read from EDID
989 * LOW_RR is the lowest eDP panel refresh rate found from EDID
990 * parsing for same resolution.
992 enum drrs_refresh_rate_type
{
995 DRRS_MAX_RR
, /* RR count */
998 enum drrs_support_type
{
999 DRRS_NOT_SUPPORTED
= 0,
1000 STATIC_DRRS_SUPPORT
= 1,
1001 SEAMLESS_DRRS_SUPPORT
= 2
1007 struct delayed_work work
;
1008 struct intel_dp
*dp
;
1009 unsigned busy_frontbuffer_bits
;
1010 enum drrs_refresh_rate_type refresh_rate_type
;
1011 enum drrs_support_type type
;
1018 struct intel_dp
*enabled
;
1020 struct delayed_work work
;
1021 unsigned busy_frontbuffer_bits
;
1023 bool aux_frame_sync
;
1028 PCH_NONE
= 0, /* No PCH present */
1029 PCH_IBX
, /* Ibexpeak PCH */
1030 PCH_CPT
, /* Cougarpoint PCH */
1031 PCH_LPT
, /* Lynxpoint PCH */
1032 PCH_SPT
, /* Sunrisepoint PCH */
1033 PCH_KBP
, /* Kabypoint PCH */
1037 enum intel_sbi_destination
{
1042 #define QUIRK_PIPEA_FORCE (1<<0)
1043 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1044 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1045 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1046 #define QUIRK_PIPEB_FORCE (1<<4)
1047 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1050 struct intel_fbc_work
;
1052 struct intel_gmbus
{
1053 struct i2c_adapter adapter
;
1054 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1057 i915_reg_t gpio_reg
;
1058 struct i2c_algo_bit_data bit_algo
;
1059 struct drm_i915_private
*dev_priv
;
1062 struct i915_suspend_saved_registers
{
1065 u32 savePP_ON_DELAYS
;
1066 u32 savePP_OFF_DELAYS
;
1071 u32 saveFBC_CONTROL
;
1072 u32 saveCACHE_MODE_0
;
1073 u32 saveMI_ARB_STATE
;
1077 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1078 u32 savePCH_PORT_HOTPLUG
;
1082 struct vlv_s0ix_state
{
1089 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1090 u32 media_max_req_count
;
1091 u32 gfx_max_req_count
;
1117 u32 rp_down_timeout
;
1123 /* Display 1 CZ domain */
1128 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1130 /* GT SA CZ domain */
1137 /* Display 2 CZ domain */
1141 u32 clock_gate_dis2
;
1144 struct intel_rps_ei
{
1150 struct intel_gen6_power_mgmt
{
1152 * work, interrupts_enabled and pm_iir are protected by
1153 * dev_priv->irq_lock
1155 struct work_struct work
;
1156 bool interrupts_enabled
;
1161 /* Frequencies are stored in potentially platform dependent multiples.
1162 * In other words, *_freq needs to be multiplied by X to be interesting.
1163 * Soft limits are those which are used for the dynamic reclocking done
1164 * by the driver (raise frequencies under heavy loads, and lower for
1165 * lighter loads). Hard limits are those imposed by the hardware.
1167 * A distinction is made for overclocking, which is never enabled by
1168 * default, and is considered to be above the hard limit if it's
1171 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1172 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1173 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1174 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1175 u8 min_freq
; /* AKA RPn. Minimum frequency */
1176 u8 boost_freq
; /* Frequency to request when wait boosting */
1177 u8 idle_freq
; /* Frequency to request when we are idle */
1178 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1179 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1180 u8 rp0_freq
; /* Non-overclocked max frequency. */
1181 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1183 u8 up_threshold
; /* Current %busy required to uplock */
1184 u8 down_threshold
; /* Current %busy required to downclock */
1187 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1189 spinlock_t client_lock
;
1190 struct list_head clients
;
1194 struct delayed_work autoenable_work
;
1197 struct intel_rps_client semaphores
, mmioflips
;
1199 /* manual wa residency calculations */
1200 struct intel_rps_ei up_ei
, down_ei
;
1203 * Protects RPS/RC6 register access and PCU communication.
1204 * Must be taken after struct_mutex if nested. Note that
1205 * this lock may be held for long periods of time when
1206 * talking to hw - so only take it when talking to hw!
1208 struct mutex hw_lock
;
1211 /* defined intel_pm.c */
1212 extern spinlock_t mchdev_lock
;
1214 struct intel_ilk_power_mgmt
{
1222 unsigned long last_time1
;
1223 unsigned long chipset_power
;
1226 unsigned long gfx_power
;
1233 struct drm_i915_private
;
1234 struct i915_power_well
;
1236 struct i915_power_well_ops
{
1238 * Synchronize the well's hw state to match the current sw state, for
1239 * example enable/disable it based on the current refcount. Called
1240 * during driver init and resume time, possibly after first calling
1241 * the enable/disable handlers.
1243 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1244 struct i915_power_well
*power_well
);
1246 * Enable the well and resources that depend on it (for example
1247 * interrupts located on the well). Called after the 0->1 refcount
1250 void (*enable
)(struct drm_i915_private
*dev_priv
,
1251 struct i915_power_well
*power_well
);
1253 * Disable the well and resources that depend on it. Called after
1254 * the 1->0 refcount transition.
1256 void (*disable
)(struct drm_i915_private
*dev_priv
,
1257 struct i915_power_well
*power_well
);
1258 /* Returns the hw enabled state. */
1259 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1260 struct i915_power_well
*power_well
);
1263 /* Power well structure for haswell */
1264 struct i915_power_well
{
1267 /* power well enable/disable usage count */
1269 /* cached hw enabled state */
1271 unsigned long domains
;
1273 const struct i915_power_well_ops
*ops
;
1276 struct i915_power_domains
{
1278 * Power wells needed for initialization at driver init and suspend
1279 * time are on. They are kept on until after the first modeset.
1283 int power_well_count
;
1286 int domain_use_count
[POWER_DOMAIN_NUM
];
1287 struct i915_power_well
*power_wells
;
1290 #define MAX_L3_SLICES 2
1291 struct intel_l3_parity
{
1292 u32
*remap_info
[MAX_L3_SLICES
];
1293 struct work_struct error_work
;
1297 struct i915_gem_mm
{
1298 /** Memory allocator for GTT stolen memory */
1299 struct drm_mm stolen
;
1300 /** Protects the usage of the GTT stolen memory allocator. This is
1301 * always the inner lock when overlapping with struct_mutex. */
1302 struct mutex stolen_lock
;
1304 /** List of all objects in gtt_space. Used to restore gtt
1305 * mappings on resume */
1306 struct list_head bound_list
;
1308 * List of objects which are not bound to the GTT (thus
1309 * are idle and not used by the GPU) but still have
1310 * (presumably uncached) pages still attached.
1312 struct list_head unbound_list
;
1314 /** Usable portion of the GTT for GEM */
1315 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1317 /** PPGTT used for aliasing the PPGTT with the GTT */
1318 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1320 struct notifier_block oom_notifier
;
1321 struct notifier_block vmap_notifier
;
1322 struct shrinker shrinker
;
1323 bool shrinker_no_lock_stealing
;
1325 /** LRU list of objects with fence regs on them. */
1326 struct list_head fence_list
;
1329 * Are we in a non-interruptible section of code like
1334 /* the indicator for dispatch video commands on two BSD rings */
1335 unsigned int bsd_ring_dispatch_index
;
1337 /** Bit 6 swizzling required for X tiling */
1338 uint32_t bit_6_swizzle_x
;
1339 /** Bit 6 swizzling required for Y tiling */
1340 uint32_t bit_6_swizzle_y
;
1342 /* accounting, useful for userland debugging */
1343 spinlock_t object_stat_lock
;
1344 size_t object_memory
;
1348 struct drm_i915_error_state_buf
{
1349 struct drm_i915_private
*i915
;
1358 struct i915_error_state_file_priv
{
1359 struct drm_device
*dev
;
1360 struct drm_i915_error_state
*error
;
1363 struct i915_gpu_error
{
1364 /* For hangcheck timer */
1365 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1366 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1367 /* Hang gpu twice in this window and your context gets banned */
1368 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1370 struct delayed_work hangcheck_work
;
1372 /* For reset and error_state handling. */
1374 /* Protected by the above dev->gpu_error.lock. */
1375 struct drm_i915_error_state
*first_error
;
1377 unsigned long missed_irq_rings
;
1380 * State variable controlling the reset flow and count
1382 * This is a counter which gets incremented when reset is triggered,
1383 * and again when reset has been handled. So odd values (lowest bit set)
1384 * means that reset is in progress and even values that
1385 * (reset_counter >> 1):th reset was successfully completed.
1387 * If reset is not completed succesfully, the I915_WEDGE bit is
1388 * set meaning that hardware is terminally sour and there is no
1389 * recovery. All waiters on the reset_queue will be woken when
1392 * This counter is used by the wait_seqno code to notice that reset
1393 * event happened and it needs to restart the entire ioctl (since most
1394 * likely the seqno it waited for won't ever signal anytime soon).
1396 * This is important for lock-free wait paths, where no contended lock
1397 * naturally enforces the correct ordering between the bail-out of the
1398 * waiter and the gpu reset work code.
1400 atomic_t reset_counter
;
1402 #define I915_RESET_IN_PROGRESS_FLAG 1
1403 #define I915_WEDGED (1 << 31)
1406 * Waitqueue to signal when a hang is detected. Used to for waiters
1407 * to release the struct_mutex for the reset to procede.
1409 wait_queue_head_t wait_queue
;
1412 * Waitqueue to signal when the reset has completed. Used by clients
1413 * that wait for dev_priv->mm.wedged to settle.
1415 wait_queue_head_t reset_queue
;
1417 /* For missed irq/seqno simulation. */
1418 unsigned long test_irq_rings
;
1421 enum modeset_restore
{
1422 MODESET_ON_LID_OPEN
,
1427 #define DP_AUX_A 0x40
1428 #define DP_AUX_B 0x10
1429 #define DP_AUX_C 0x20
1430 #define DP_AUX_D 0x30
1432 #define DDC_PIN_B 0x05
1433 #define DDC_PIN_C 0x04
1434 #define DDC_PIN_D 0x06
1436 struct ddi_vbt_port_info
{
1438 * This is an index in the HDMI/DVI DDI buffer translation table.
1439 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1440 * populate this field.
1442 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1443 uint8_t hdmi_level_shift
;
1445 uint8_t supports_dvi
:1;
1446 uint8_t supports_hdmi
:1;
1447 uint8_t supports_dp
:1;
1449 uint8_t alternate_aux_channel
;
1450 uint8_t alternate_ddc_pin
;
1452 uint8_t dp_boost_level
;
1453 uint8_t hdmi_boost_level
;
1456 enum psr_lines_to_wait
{
1457 PSR_0_LINES_TO_WAIT
= 0,
1459 PSR_4_LINES_TO_WAIT
,
1463 struct intel_vbt_data
{
1464 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1465 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1468 unsigned int int_tv_support
:1;
1469 unsigned int lvds_dither
:1;
1470 unsigned int lvds_vbt
:1;
1471 unsigned int int_crt_support
:1;
1472 unsigned int lvds_use_ssc
:1;
1473 unsigned int display_clock_mode
:1;
1474 unsigned int fdi_rx_polarity_inverted
:1;
1475 unsigned int panel_type
:4;
1477 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1479 enum drrs_support_type drrs_type
;
1490 struct edp_power_seq pps
;
1495 bool require_aux_wakeup
;
1497 enum psr_lines_to_wait lines_to_wait
;
1498 int tp1_wakeup_time
;
1499 int tp2_tp3_wakeup_time
;
1505 bool active_low_pwm
;
1506 u8 min_brightness
; /* min_brightness/255 of max */
1507 enum intel_backlight_type type
;
1513 struct mipi_config
*config
;
1514 struct mipi_pps_data
*pps
;
1518 const u8
*sequence
[MIPI_SEQ_MAX
];
1524 union child_device_config
*child_dev
;
1526 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1527 struct sdvo_device_mapping sdvo_mappings
[2];
1530 enum intel_ddb_partitioning
{
1532 INTEL_DDB_PART_5_6
, /* IVB+ */
1535 struct intel_wm_level
{
1543 struct ilk_wm_values
{
1544 uint32_t wm_pipe
[3];
1546 uint32_t wm_lp_spr
[3];
1547 uint32_t wm_linetime
[3];
1549 enum intel_ddb_partitioning partitioning
;
1552 struct vlv_pipe_wm
{
1563 struct vlv_wm_values
{
1564 struct vlv_pipe_wm pipe
[3];
1565 struct vlv_sr_wm sr
;
1575 struct skl_ddb_entry
{
1576 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1579 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1581 return entry
->end
- entry
->start
;
1584 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1585 const struct skl_ddb_entry
*e2
)
1587 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1593 struct skl_ddb_allocation
{
1594 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1595 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1596 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1599 struct skl_wm_values
{
1600 unsigned dirty_pipes
;
1601 struct skl_ddb_allocation ddb
;
1602 uint32_t wm_linetime
[I915_MAX_PIPES
];
1603 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1604 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1607 struct skl_wm_level
{
1608 bool plane_en
[I915_MAX_PLANES
];
1609 uint16_t plane_res_b
[I915_MAX_PLANES
];
1610 uint8_t plane_res_l
[I915_MAX_PLANES
];
1614 * This struct helps tracking the state needed for runtime PM, which puts the
1615 * device in PCI D3 state. Notice that when this happens, nothing on the
1616 * graphics device works, even register access, so we don't get interrupts nor
1619 * Every piece of our code that needs to actually touch the hardware needs to
1620 * either call intel_runtime_pm_get or call intel_display_power_get with the
1621 * appropriate power domain.
1623 * Our driver uses the autosuspend delay feature, which means we'll only really
1624 * suspend if we stay with zero refcount for a certain amount of time. The
1625 * default value is currently very conservative (see intel_runtime_pm_enable), but
1626 * it can be changed with the standard runtime PM files from sysfs.
1628 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1629 * goes back to false exactly before we reenable the IRQs. We use this variable
1630 * to check if someone is trying to enable/disable IRQs while they're supposed
1631 * to be disabled. This shouldn't happen and we'll print some error messages in
1634 * For more, read the Documentation/power/runtime_pm.txt.
1636 struct i915_runtime_pm
{
1637 atomic_t wakeref_count
;
1638 atomic_t atomic_seq
;
1643 enum intel_pipe_crc_source
{
1644 INTEL_PIPE_CRC_SOURCE_NONE
,
1645 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1646 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1647 INTEL_PIPE_CRC_SOURCE_PF
,
1648 INTEL_PIPE_CRC_SOURCE_PIPE
,
1649 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1650 INTEL_PIPE_CRC_SOURCE_TV
,
1651 INTEL_PIPE_CRC_SOURCE_DP_B
,
1652 INTEL_PIPE_CRC_SOURCE_DP_C
,
1653 INTEL_PIPE_CRC_SOURCE_DP_D
,
1654 INTEL_PIPE_CRC_SOURCE_AUTO
,
1655 INTEL_PIPE_CRC_SOURCE_MAX
,
1658 struct intel_pipe_crc_entry
{
1663 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1664 struct intel_pipe_crc
{
1666 bool opened
; /* exclusive access to the result file */
1667 struct intel_pipe_crc_entry
*entries
;
1668 enum intel_pipe_crc_source source
;
1670 wait_queue_head_t wq
;
1673 struct i915_frontbuffer_tracking
{
1677 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1684 struct i915_wa_reg
{
1687 /* bitmask representing WA bits */
1692 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1693 * allowing it for RCS as we don't foresee any requirement of having
1694 * a whitelist for other engines. When it is really required for
1695 * other engines then the limit need to be increased.
1697 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1699 struct i915_workarounds
{
1700 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1702 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1705 struct i915_virtual_gpu
{
1709 struct i915_execbuffer_params
{
1710 struct drm_device
*dev
;
1711 struct drm_file
*file
;
1712 uint32_t dispatch_flags
;
1713 uint32_t args_batch_start_offset
;
1714 uint64_t batch_obj_vm_offset
;
1715 struct intel_engine_cs
*engine
;
1716 struct drm_i915_gem_object
*batch_obj
;
1717 struct i915_gem_context
*ctx
;
1718 struct drm_i915_gem_request
*request
;
1721 /* used in computing the new watermarks state */
1722 struct intel_wm_config
{
1723 unsigned int num_pipes_active
;
1724 bool sprites_enabled
;
1725 bool sprites_scaled
;
1728 struct drm_i915_private
{
1729 struct drm_device drm
;
1731 struct kmem_cache
*objects
;
1732 struct kmem_cache
*vmas
;
1733 struct kmem_cache
*requests
;
1735 const struct intel_device_info info
;
1737 int relative_constants_mode
;
1741 struct intel_uncore uncore
;
1743 struct i915_virtual_gpu vgpu
;
1745 struct intel_gvt gvt
;
1747 struct intel_guc guc
;
1749 struct intel_csr csr
;
1751 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1753 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1754 * controller on different i2c buses. */
1755 struct mutex gmbus_mutex
;
1758 * Base address of the gmbus and gpio block.
1760 uint32_t gpio_mmio_base
;
1762 /* MMIO base address for MIPI regs */
1763 uint32_t mipi_mmio_base
;
1765 uint32_t psr_mmio_base
;
1767 wait_queue_head_t gmbus_wait_queue
;
1769 struct pci_dev
*bridge_dev
;
1770 struct i915_gem_context
*kernel_context
;
1771 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1772 struct drm_i915_gem_object
*semaphore_obj
;
1773 uint32_t last_seqno
, next_seqno
;
1775 struct drm_dma_handle
*status_page_dmah
;
1776 struct resource mch_res
;
1778 /* protects the irq masks */
1779 spinlock_t irq_lock
;
1781 /* protects the mmio flip data */
1782 spinlock_t mmio_flip_lock
;
1784 bool display_irqs_enabled
;
1786 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1787 struct pm_qos_request pm_qos
;
1789 /* Sideband mailbox protection */
1790 struct mutex sb_lock
;
1792 /** Cached value of IMR to avoid reads in updating the bitfield */
1795 u32 de_irq_mask
[I915_MAX_PIPES
];
1800 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1802 struct i915_hotplug hotplug
;
1803 struct intel_fbc fbc
;
1804 struct i915_drrs drrs
;
1805 struct intel_opregion opregion
;
1806 struct intel_vbt_data vbt
;
1808 bool preserve_bios_swizzle
;
1811 struct intel_overlay
*overlay
;
1813 /* backlight registers and fields in struct intel_panel */
1814 struct mutex backlight_lock
;
1817 bool no_aux_handshake
;
1819 /* protects panel power sequencer state */
1820 struct mutex pps_mutex
;
1822 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1823 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1825 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1826 unsigned int skl_preferred_vco_freq
;
1827 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1828 unsigned int max_dotclk_freq
;
1829 unsigned int rawclk_freq
;
1830 unsigned int hpll_freq
;
1831 unsigned int czclk_freq
;
1834 unsigned int vco
, ref
;
1838 * wq - Driver workqueue for GEM.
1840 * NOTE: Work items scheduled here are not allowed to grab any modeset
1841 * locks, for otherwise the flushing done in the pageflip code will
1842 * result in deadlocks.
1844 struct workqueue_struct
*wq
;
1846 /* Display functions */
1847 struct drm_i915_display_funcs display
;
1849 /* PCH chipset type */
1850 enum intel_pch pch_type
;
1851 unsigned short pch_id
;
1853 unsigned long quirks
;
1855 enum modeset_restore modeset_restore
;
1856 struct mutex modeset_restore_lock
;
1857 struct drm_atomic_state
*modeset_restore_state
;
1859 struct list_head vm_list
; /* Global list of all address spaces */
1860 struct i915_ggtt ggtt
; /* VM representing the global address space */
1862 struct i915_gem_mm mm
;
1863 DECLARE_HASHTABLE(mm_structs
, 7);
1864 struct mutex mm_lock
;
1866 /* The hw wants to have a stable context identifier for the lifetime
1867 * of the context (for OA, PASID, faults, etc). This is limited
1868 * in execlists to 21 bits.
1870 struct ida context_hw_ida
;
1871 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1873 /* Kernel Modesetting */
1875 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1876 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1877 wait_queue_head_t pending_flip_queue
;
1879 #ifdef CONFIG_DEBUG_FS
1880 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1883 /* dpll and cdclk state is protected by connection_mutex */
1884 int num_shared_dpll
;
1885 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1886 const struct intel_dpll_mgr
*dpll_mgr
;
1889 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1890 * Must be global rather than per dpll, because on some platforms
1891 * plls share registers.
1893 struct mutex dpll_lock
;
1895 unsigned int active_crtcs
;
1896 unsigned int min_pixclk
[I915_MAX_PIPES
];
1898 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1900 struct i915_workarounds workarounds
;
1902 struct i915_frontbuffer_tracking fb_tracking
;
1906 bool mchbar_need_disable
;
1908 struct intel_l3_parity l3_parity
;
1910 /* Cannot be determined by PCIID. You must always read a register. */
1913 /* gen6+ rps state */
1914 struct intel_gen6_power_mgmt rps
;
1916 /* ilk-only ips/rps state. Everything in here is protected by the global
1917 * mchdev_lock in intel_pm.c */
1918 struct intel_ilk_power_mgmt ips
;
1920 struct i915_power_domains power_domains
;
1922 struct i915_psr psr
;
1924 struct i915_gpu_error gpu_error
;
1926 struct drm_i915_gem_object
*vlv_pctx
;
1928 #ifdef CONFIG_DRM_FBDEV_EMULATION
1929 /* list of fbdev register on this device */
1930 struct intel_fbdev
*fbdev
;
1931 struct work_struct fbdev_suspend_work
;
1934 struct drm_property
*broadcast_rgb_property
;
1935 struct drm_property
*force_audio_property
;
1937 /* hda/i915 audio component */
1938 struct i915_audio_component
*audio_component
;
1939 bool audio_component_registered
;
1941 * av_mutex - mutex for audio/video sync
1944 struct mutex av_mutex
;
1946 uint32_t hw_context_size
;
1947 struct list_head context_list
;
1951 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1952 u32 chv_phy_control
;
1954 * Shadows for CHV DPLL_MD regs to keep the state
1955 * checker somewhat working in the presence hardware
1956 * crappiness (can't read out DPLL_MD for pipes B & C).
1958 u32 chv_dpll_md
[I915_MAX_PIPES
];
1962 bool suspended_to_idle
;
1963 struct i915_suspend_saved_registers regfile
;
1964 struct vlv_s0ix_state vlv_s0ix_state
;
1968 * Raw watermark latency values:
1969 * in 0.1us units for WM0,
1970 * in 0.5us units for WM1+.
1973 uint16_t pri_latency
[5];
1975 uint16_t spr_latency
[5];
1977 uint16_t cur_latency
[5];
1979 * Raw watermark memory latency values
1980 * for SKL for all 8 levels
1983 uint16_t skl_latency
[8];
1986 * The skl_wm_values structure is a bit too big for stack
1987 * allocation, so we keep the staging struct where we store
1988 * intermediate results here instead.
1990 struct skl_wm_values skl_results
;
1992 /* current hardware state */
1994 struct ilk_wm_values hw
;
1995 struct skl_wm_values skl_hw
;
1996 struct vlv_wm_values vlv
;
2002 * Should be held around atomic WM register writing; also
2003 * protects * intel_crtc->wm.active and
2004 * cstate->wm.need_postvbl_update.
2006 struct mutex wm_mutex
;
2009 * Set during HW readout of watermarks/DDB. Some platforms
2010 * need to know when we're still using BIOS-provided values
2011 * (which we don't fully trust).
2013 bool distrust_bios_wm
;
2016 struct i915_runtime_pm pm
;
2018 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2020 int (*execbuf_submit
)(struct i915_execbuffer_params
*params
,
2021 struct drm_i915_gem_execbuffer2
*args
,
2022 struct list_head
*vmas
);
2023 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2024 void (*stop_engine
)(struct intel_engine_cs
*engine
);
2027 * Is the GPU currently considered idle, or busy executing
2028 * userspace requests? Whilst idle, we allow runtime power
2029 * management to power down the hardware and display clocks.
2030 * In order to reduce the effect on performance, there
2031 * is a slight delay before we do so.
2033 unsigned int active_engines
;
2037 * We leave the user IRQ off as much as possible,
2038 * but this means that requests will finish and never
2039 * be retired once the system goes idle. Set a timer to
2040 * fire periodically while the ring is running. When it
2041 * fires, go retire requests.
2043 struct delayed_work retire_work
;
2046 * When we detect an idle GPU, we want to turn on
2047 * powersaving features. So once we see that there
2048 * are no more requests outstanding and no more
2049 * arrive within a small period of time, we fire
2050 * off the idle_work.
2052 struct delayed_work idle_work
;
2055 /* perform PHY state sanity checks? */
2056 bool chv_phy_assert
[2];
2058 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2061 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2062 * will be rejected. Instead look for a better place.
2066 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2068 return container_of(dev
, struct drm_i915_private
, drm
);
2071 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2073 return to_i915(dev_get_drvdata(dev
));
2076 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2078 return container_of(guc
, struct drm_i915_private
, guc
);
2081 /* Simple iterator over all initialised engines */
2082 #define for_each_engine(engine__, dev_priv__) \
2083 for ((engine__) = &(dev_priv__)->engine[0]; \
2084 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2086 for_each_if (intel_engine_initialized(engine__))
2088 /* Iterator with engine_id */
2089 #define for_each_engine_id(engine__, dev_priv__, id__) \
2090 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2091 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2093 for_each_if (((id__) = (engine__)->id, \
2094 intel_engine_initialized(engine__)))
2096 /* Iterator over subset of engines selected by mask */
2097 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2098 for ((engine__) = &(dev_priv__)->engine[0]; \
2099 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2101 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2102 intel_engine_initialized(engine__))
2104 enum hdmi_force_audio
{
2105 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2106 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2107 HDMI_AUDIO_AUTO
, /* trust EDID */
2108 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2111 #define I915_GTT_OFFSET_NONE ((u32)-1)
2113 struct drm_i915_gem_object_ops
{
2115 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2117 /* Interface between the GEM object and its backing storage.
2118 * get_pages() is called once prior to the use of the associated set
2119 * of pages before to binding them into the GTT, and put_pages() is
2120 * called after we no longer need them. As we expect there to be
2121 * associated cost with migrating pages between the backing storage
2122 * and making them available for the GPU (e.g. clflush), we may hold
2123 * onto the pages after they are no longer referenced by the GPU
2124 * in case they may be used again shortly (for example migrating the
2125 * pages to a different memory domain within the GTT). put_pages()
2126 * will therefore most likely be called when the object itself is
2127 * being released or under memory pressure (where we attempt to
2128 * reap pages for the shrinker).
2130 int (*get_pages
)(struct drm_i915_gem_object
*);
2131 void (*put_pages
)(struct drm_i915_gem_object
*);
2133 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2134 void (*release
)(struct drm_i915_gem_object
*);
2138 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2139 * considered to be the frontbuffer for the given plane interface-wise. This
2140 * doesn't mean that the hw necessarily already scans it out, but that any
2141 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2143 * We have one bit per pipe and per scanout plane type.
2145 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2146 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2147 #define INTEL_FRONTBUFFER_BITS \
2148 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
2149 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2150 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2151 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2152 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2153 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2154 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2155 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2156 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2157 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2158 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2160 struct drm_i915_gem_object
{
2161 struct drm_gem_object base
;
2163 const struct drm_i915_gem_object_ops
*ops
;
2165 /** List of VMAs backed by this object */
2166 struct list_head vma_list
;
2168 /** Stolen memory for this object, instead of being backed by shmem. */
2169 struct drm_mm_node
*stolen
;
2170 struct list_head global_list
;
2172 struct list_head engine_list
[I915_NUM_ENGINES
];
2173 /** Used in execbuf to temporarily hold a ref */
2174 struct list_head obj_exec_link
;
2176 struct list_head batch_pool_link
;
2179 * This is set if the object is on the active lists (has pending
2180 * rendering and so a non-zero seqno), and is not set if it i s on
2181 * inactive (ready to be unbound) list.
2183 unsigned int active
:I915_NUM_ENGINES
;
2186 * This is set if the object has been written to since last bound
2189 unsigned int dirty
:1;
2192 * Fence register bits (if any) for this object. Will be set
2193 * as needed when mapped into the GTT.
2194 * Protected by dev->struct_mutex.
2196 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2199 * Advice: are the backing pages purgeable?
2201 unsigned int madv
:2;
2204 * Current tiling mode for the object.
2206 unsigned int tiling_mode
:2;
2208 * Whether the tiling parameters for the currently associated fence
2209 * register have changed. Note that for the purposes of tracking
2210 * tiling changes we also treat the unfenced register, the register
2211 * slot that the object occupies whilst it executes a fenced
2212 * command (such as BLT on gen2/3), as a "fence".
2214 unsigned int fence_dirty
:1;
2217 * Is the object at the current location in the gtt mappable and
2218 * fenceable? Used to avoid costly recalculations.
2220 unsigned int map_and_fenceable
:1;
2223 * Whether the current gtt mapping needs to be mappable (and isn't just
2224 * mappable by accident). Track pin and fault separate for a more
2225 * accurate mappable working set.
2227 unsigned int fault_mappable
:1;
2230 * Is the object to be mapped as read-only to the GPU
2231 * Only honoured if hardware has relevant pte bit
2233 unsigned long gt_ro
:1;
2234 unsigned int cache_level
:3;
2235 unsigned int cache_dirty
:1;
2237 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2239 unsigned int has_wc_mmap
;
2240 unsigned int pin_display
;
2242 struct sg_table
*pages
;
2243 int pages_pin_count
;
2245 struct scatterlist
*sg
;
2250 /** Breadcrumb of last rendering to the buffer.
2251 * There can only be one writer, but we allow for multiple readers.
2252 * If there is a writer that necessarily implies that all other
2253 * read requests are complete - but we may only be lazily clearing
2254 * the read requests. A read request is naturally the most recent
2255 * request on a ring, so we may have two different write and read
2256 * requests on one ring where the write request is older than the
2257 * read request. This allows for the CPU to read from an active
2258 * buffer by only waiting for the write to complete.
2260 struct drm_i915_gem_request
*last_read_req
[I915_NUM_ENGINES
];
2261 struct drm_i915_gem_request
*last_write_req
;
2262 /** Breadcrumb of last fenced GPU access to the buffer. */
2263 struct drm_i915_gem_request
*last_fenced_req
;
2265 /** Current tiling stride for the object, if it's tiled. */
2268 /** References from framebuffers, locks out tiling changes. */
2269 unsigned long framebuffer_references
;
2271 /** Record of address bit 17 of each page at last unbind. */
2272 unsigned long *bit_17
;
2275 /** for phy allocated objects */
2276 struct drm_dma_handle
*phys_handle
;
2278 struct i915_gem_userptr
{
2280 unsigned read_only
:1;
2281 unsigned workers
:4;
2282 #define I915_GEM_USERPTR_MAX_WORKERS 15
2284 struct i915_mm_struct
*mm
;
2285 struct i915_mmu_object
*mmu_object
;
2286 struct work_struct
*work
;
2290 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2293 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2295 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2299 * Optimised SGL iterator for GEM objects
2301 static __always_inline
struct sgt_iter
{
2302 struct scatterlist
*sgp
;
2309 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2310 struct sgt_iter s
= { .sgp
= sgl
};
2313 s
.max
= s
.curr
= s
.sgp
->offset
;
2314 s
.max
+= s
.sgp
->length
;
2316 s
.dma
= sg_dma_address(s
.sgp
);
2318 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2325 * __sg_next - return the next scatterlist entry in a list
2326 * @sg: The current sg entry
2329 * If the entry is the last, return NULL; otherwise, step to the next
2330 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2331 * otherwise just return the pointer to the current element.
2333 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2335 #ifdef CONFIG_DEBUG_SG
2336 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2338 return sg_is_last(sg
) ? NULL
:
2339 likely(!sg_is_chain(++sg
)) ? sg
:
2344 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2345 * @__dmap: DMA address (output)
2346 * @__iter: 'struct sgt_iter' (iterator state, internal)
2347 * @__sgt: sg_table to iterate over (input)
2349 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2350 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2351 ((__dmap) = (__iter).dma + (__iter).curr); \
2352 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2353 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2356 * for_each_sgt_page - iterate over the pages of the given sg_table
2357 * @__pp: page pointer (output)
2358 * @__iter: 'struct sgt_iter' (iterator state, internal)
2359 * @__sgt: sg_table to iterate over (input)
2361 #define for_each_sgt_page(__pp, __iter, __sgt) \
2362 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2363 ((__pp) = (__iter).pfn == 0 ? NULL : \
2364 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2365 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2366 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2369 * Request queue structure.
2371 * The request queue allows us to note sequence numbers that have been emitted
2372 * and may be associated with active buffers to be retired.
2374 * By keeping this list, we can avoid having to do questionable sequence
2375 * number comparisons on buffer last_read|write_seqno. It also allows an
2376 * emission time to be associated with the request for tracking how far ahead
2377 * of the GPU the submission is.
2379 * The requests are reference counted, so upon creation they should have an
2380 * initial reference taken using kref_init
2382 struct drm_i915_gem_request
{
2385 /** On Which ring this request was generated */
2386 struct drm_i915_private
*i915
;
2387 struct intel_engine_cs
*engine
;
2388 struct intel_signal_node signaling
;
2390 /** GEM sequence number associated with the previous request,
2391 * when the HWS breadcrumb is equal to this the GPU is processing
2396 /** GEM sequence number associated with this request,
2397 * when the HWS breadcrumb is equal or greater than this the GPU
2398 * has finished processing this request.
2402 /** Position in the ringbuffer of the start of the request */
2406 * Position in the ringbuffer of the start of the postfix.
2407 * This is required to calculate the maximum available ringbuffer
2408 * space without overwriting the postfix.
2412 /** Position in the ringbuffer of the end of the whole request */
2415 /** Preallocate space in the ringbuffer for the emitting the request */
2419 * Context and ring buffer related to this request
2420 * Contexts are refcounted, so when this request is associated with a
2421 * context, we must increment the context's refcount, to guarantee that
2422 * it persists while any request is linked to it. Requests themselves
2423 * are also refcounted, so the request will only be freed when the last
2424 * reference to it is dismissed, and the code in
2425 * i915_gem_request_free() will then decrement the refcount on the
2428 struct i915_gem_context
*ctx
;
2429 struct intel_ringbuffer
*ringbuf
;
2432 * Context related to the previous request.
2433 * As the contexts are accessed by the hardware until the switch is
2434 * completed to a new context, the hardware may still be writing
2435 * to the context object after the breadcrumb is visible. We must
2436 * not unpin/unbind/prune that object whilst still active and so
2437 * we keep the previous context pinned until the following (this)
2438 * request is retired.
2440 struct i915_gem_context
*previous_context
;
2442 /** Batch buffer related to this request if any (used for
2443 error state dump only) */
2444 struct drm_i915_gem_object
*batch_obj
;
2446 /** Time at which this request was emitted, in jiffies. */
2447 unsigned long emitted_jiffies
;
2449 /** global list entry for this request */
2450 struct list_head list
;
2452 struct drm_i915_file_private
*file_priv
;
2453 /** file_priv list entry for this request */
2454 struct list_head client_list
;
2456 /** process identifier submitting this request */
2460 * The ELSP only accepts two elements at a time, so we queue
2461 * context/tail pairs on a given queue (ring->execlist_queue) until the
2462 * hardware is available. The queue serves a double purpose: we also use
2463 * it to keep track of the up to 2 contexts currently in the hardware
2464 * (usually one in execution and the other queued up by the GPU): We
2465 * only remove elements from the head of the queue when the hardware
2466 * informs us that an element has been completed.
2468 * All accesses to the queue are mediated by a spinlock
2469 * (ring->execlist_lock).
2472 /** Execlist link in the submission queue.*/
2473 struct list_head execlist_link
;
2475 /** Execlists no. of times this request has been sent to the ELSP */
2478 /** Execlists context hardware id. */
2482 struct drm_i915_gem_request
* __must_check
2483 i915_gem_request_alloc(struct intel_engine_cs
*engine
,
2484 struct i915_gem_context
*ctx
);
2485 void i915_gem_request_free(struct kref
*req_ref
);
2486 int i915_gem_request_add_to_client(struct drm_i915_gem_request
*req
,
2487 struct drm_file
*file
);
2489 static inline uint32_t
2490 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2492 return req
? req
->seqno
: 0;
2495 static inline struct intel_engine_cs
*
2496 i915_gem_request_get_engine(struct drm_i915_gem_request
*req
)
2498 return req
? req
->engine
: NULL
;
2501 static inline struct drm_i915_gem_request
*
2502 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2505 kref_get(&req
->ref
);
2510 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2512 kref_put(&req
->ref
, i915_gem_request_free
);
2515 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2516 struct drm_i915_gem_request
*src
)
2519 i915_gem_request_reference(src
);
2522 i915_gem_request_unreference(*pdst
);
2528 * XXX: i915_gem_request_completed should be here but currently needs the
2529 * definition of i915_seqno_passed() which is below. It will be moved in
2530 * a later patch when the call to i915_seqno_passed() is obsoleted...
2534 * A command that requires special handling by the command parser.
2536 struct drm_i915_cmd_descriptor
{
2538 * Flags describing how the command parser processes the command.
2540 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2541 * a length mask if not set
2542 * CMD_DESC_SKIP: The command is allowed but does not follow the
2543 * standard length encoding for the opcode range in
2545 * CMD_DESC_REJECT: The command is never allowed
2546 * CMD_DESC_REGISTER: The command should be checked against the
2547 * register whitelist for the appropriate ring
2548 * CMD_DESC_MASTER: The command is allowed if the submitting process
2552 #define CMD_DESC_FIXED (1<<0)
2553 #define CMD_DESC_SKIP (1<<1)
2554 #define CMD_DESC_REJECT (1<<2)
2555 #define CMD_DESC_REGISTER (1<<3)
2556 #define CMD_DESC_BITMASK (1<<4)
2557 #define CMD_DESC_MASTER (1<<5)
2560 * The command's unique identification bits and the bitmask to get them.
2561 * This isn't strictly the opcode field as defined in the spec and may
2562 * also include type, subtype, and/or subop fields.
2570 * The command's length. The command is either fixed length (i.e. does
2571 * not include a length field) or has a length field mask. The flag
2572 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2573 * a length mask. All command entries in a command table must include
2574 * length information.
2582 * Describes where to find a register address in the command to check
2583 * against the ring's register whitelist. Only valid if flags has the
2584 * CMD_DESC_REGISTER bit set.
2586 * A non-zero step value implies that the command may access multiple
2587 * registers in sequence (e.g. LRI), in that case step gives the
2588 * distance in dwords between individual offset fields.
2596 #define MAX_CMD_DESC_BITMASKS 3
2598 * Describes command checks where a particular dword is masked and
2599 * compared against an expected value. If the command does not match
2600 * the expected value, the parser rejects it. Only valid if flags has
2601 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2604 * If the check specifies a non-zero condition_mask then the parser
2605 * only performs the check when the bits specified by condition_mask
2612 u32 condition_offset
;
2614 } bits
[MAX_CMD_DESC_BITMASKS
];
2618 * A table of commands requiring special handling by the command parser.
2620 * Each ring has an array of tables. Each table consists of an array of command
2621 * descriptors, which must be sorted with command opcodes in ascending order.
2623 struct drm_i915_cmd_table
{
2624 const struct drm_i915_cmd_descriptor
*table
;
2628 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2629 #define __I915__(p) ({ \
2630 struct drm_i915_private *__p; \
2631 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2632 __p = (struct drm_i915_private *)p; \
2633 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2634 __p = to_i915((struct drm_device *)p); \
2639 #define INTEL_INFO(p) (&__I915__(p)->info)
2640 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2641 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2643 #define REVID_FOREVER 0xff
2644 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2646 #define GEN_FOREVER (0)
2648 * Returns true if Gen is in inclusive range [Start, End].
2650 * Use GEN_FOREVER for unbound start and or end.
2652 #define IS_GEN(p, s, e) ({ \
2653 unsigned int __s = (s), __e = (e); \
2654 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2655 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2656 if ((__s) != GEN_FOREVER) \
2658 if ((__e) == GEN_FOREVER) \
2659 __e = BITS_PER_LONG - 1; \
2662 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2666 * Return true if revision is in range [since,until] inclusive.
2668 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2670 #define IS_REVID(p, since, until) \
2671 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2673 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2674 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2675 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2676 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2677 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2678 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2679 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2680 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2681 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2682 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2683 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2684 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2685 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2686 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2687 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2688 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2689 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2690 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2691 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2692 INTEL_DEVID(dev) == 0x0152 || \
2693 INTEL_DEVID(dev) == 0x015a)
2694 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2695 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2696 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2697 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2698 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2699 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2700 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2701 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2702 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2703 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2704 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2705 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2706 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2707 (INTEL_DEVID(dev) & 0xf) == 0xe))
2708 /* ULX machines are also considered ULT. */
2709 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2710 (INTEL_DEVID(dev) & 0xf) == 0xe)
2711 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2712 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2713 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2714 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2715 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2716 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2717 /* ULX machines are also considered ULT. */
2718 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2719 INTEL_DEVID(dev) == 0x0A1E)
2720 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2721 INTEL_DEVID(dev) == 0x1913 || \
2722 INTEL_DEVID(dev) == 0x1916 || \
2723 INTEL_DEVID(dev) == 0x1921 || \
2724 INTEL_DEVID(dev) == 0x1926)
2725 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2726 INTEL_DEVID(dev) == 0x1915 || \
2727 INTEL_DEVID(dev) == 0x191E)
2728 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2729 INTEL_DEVID(dev) == 0x5913 || \
2730 INTEL_DEVID(dev) == 0x5916 || \
2731 INTEL_DEVID(dev) == 0x5921 || \
2732 INTEL_DEVID(dev) == 0x5926)
2733 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2734 INTEL_DEVID(dev) == 0x5915 || \
2735 INTEL_DEVID(dev) == 0x591E)
2736 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2737 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2738 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2739 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2741 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2743 #define SKL_REVID_A0 0x0
2744 #define SKL_REVID_B0 0x1
2745 #define SKL_REVID_C0 0x2
2746 #define SKL_REVID_D0 0x3
2747 #define SKL_REVID_E0 0x4
2748 #define SKL_REVID_F0 0x5
2750 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2752 #define BXT_REVID_A0 0x0
2753 #define BXT_REVID_A1 0x1
2754 #define BXT_REVID_B0 0x3
2755 #define BXT_REVID_C0 0x9
2757 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2759 #define KBL_REVID_A0 0x0
2760 #define KBL_REVID_B0 0x1
2761 #define KBL_REVID_C0 0x2
2762 #define KBL_REVID_D0 0x3
2763 #define KBL_REVID_E0 0x4
2765 #define IS_KBL_REVID(p, since, until) \
2766 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2769 * The genX designation typically refers to the render engine, so render
2770 * capability related checks should use IS_GEN, while display and other checks
2771 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2774 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2775 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2776 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2777 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2778 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2779 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2780 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2781 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2783 #define ENGINE_MASK(id) BIT(id)
2784 #define RENDER_RING ENGINE_MASK(RCS)
2785 #define BSD_RING ENGINE_MASK(VCS)
2786 #define BLT_RING ENGINE_MASK(BCS)
2787 #define VEBOX_RING ENGINE_MASK(VECS)
2788 #define BSD2_RING ENGINE_MASK(VCS2)
2789 #define ALL_ENGINES (~0)
2791 #define HAS_ENGINE(dev_priv, id) \
2792 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2794 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2795 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2796 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2797 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2799 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2800 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2801 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2802 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2804 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2806 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2807 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2808 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2809 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2810 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2812 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2813 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2815 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2816 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2818 /* WaRsDisableCoarsePowerGating:skl,bxt */
2819 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2820 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2821 IS_SKL_GT3(dev_priv) || \
2822 IS_SKL_GT4(dev_priv))
2825 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2826 * even when in MSI mode. This results in spurious interrupt warnings if the
2827 * legacy irq no. is shared with another device. The kernel then disables that
2828 * interrupt source and so prevents the other device from working properly.
2830 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2831 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2833 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2834 * rows, which changed the alignment requirements and fence programming.
2836 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2838 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2839 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2841 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2842 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2843 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2845 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2847 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2848 INTEL_INFO(dev)->gen >= 9)
2850 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2851 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2852 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2853 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2854 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2855 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2856 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2857 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2858 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2859 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2860 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2862 #define HAS_CSR(dev) (IS_GEN9(dev))
2865 * For now, anything with a GuC requires uCode loading, and then supports
2866 * command submission once loaded. But these are logically independent
2867 * properties, so we have separate macros to test them.
2869 #define HAS_GUC(dev) (IS_GEN9(dev))
2870 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2871 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2873 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2874 INTEL_INFO(dev)->gen >= 8)
2876 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2877 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2880 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2882 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2883 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2884 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2885 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2886 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2887 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2888 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2889 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2890 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2891 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2892 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2893 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2895 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2896 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2897 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2898 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2899 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2900 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2901 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2902 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2903 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2904 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2906 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2907 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2909 /* DPF == dynamic parity feature */
2910 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2911 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2913 #define GT_FREQUENCY_MULTIPLIER 50
2914 #define GEN9_FREQ_SCALER 3
2916 #include "i915_trace.h"
2918 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2920 #ifdef CONFIG_INTEL_IOMMU
2921 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2927 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2928 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2930 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2935 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2936 const char *fmt
, ...);
2938 #define i915_report_error(dev_priv, fmt, ...) \
2939 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2941 #ifdef CONFIG_COMPAT
2942 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2945 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2946 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2947 extern int i915_reset(struct drm_i915_private
*dev_priv
);
2948 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2949 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2950 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2951 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2952 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2953 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2954 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2956 /* intel_hotplug.c */
2957 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2958 u32 pin_mask
, u32 long_mask
);
2959 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2960 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2961 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2962 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2963 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2964 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2967 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2969 unsigned long delay
;
2971 if (unlikely(!i915
.enable_hangcheck
))
2974 /* Don't continually defer the hangcheck so that it is always run at
2975 * least once after work has been scheduled on any ring. Otherwise,
2976 * we will ignore a hung ring if a second ring is kept busy.
2979 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2980 queue_delayed_work(system_long_wq
,
2981 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2985 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2987 const char *fmt
, ...);
2989 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2990 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2991 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2993 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2994 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2995 bool restore_forcewake
);
2996 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2997 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2998 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2999 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
3000 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
3002 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
3003 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
3004 enum forcewake_domains domains
);
3005 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
3006 enum forcewake_domains domains
);
3007 /* Like above but the caller must manage the uncore.lock itself.
3008 * Must be used with I915_READ_FW and friends.
3010 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
3011 enum forcewake_domains domains
);
3012 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
3013 enum forcewake_domains domains
);
3014 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
3016 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
3018 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
3022 const unsigned long timeout_ms
);
3023 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
3027 const unsigned long timeout_ms
);
3029 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
3031 return dev_priv
->gvt
.initialized
;
3034 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
3036 return dev_priv
->vgpu
.active
;
3040 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3044 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
3047 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
3048 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
3049 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
3052 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
3053 uint32_t interrupt_mask
,
3054 uint32_t enabled_irq_mask
);
3056 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3058 ilk_update_display_irq(dev_priv
, bits
, bits
);
3061 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3063 ilk_update_display_irq(dev_priv
, bits
, 0);
3065 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
3067 uint32_t interrupt_mask
,
3068 uint32_t enabled_irq_mask
);
3069 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
3070 enum pipe pipe
, uint32_t bits
)
3072 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3074 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3075 enum pipe pipe
, uint32_t bits
)
3077 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3079 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3080 uint32_t interrupt_mask
,
3081 uint32_t enabled_irq_mask
);
3083 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3085 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3088 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3090 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3094 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3095 struct drm_file
*file_priv
);
3096 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3097 struct drm_file
*file_priv
);
3098 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3099 struct drm_file
*file_priv
);
3100 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3101 struct drm_file
*file_priv
);
3102 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3103 struct drm_file
*file_priv
);
3104 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3105 struct drm_file
*file_priv
);
3106 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3107 struct drm_file
*file_priv
);
3108 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
3109 struct drm_i915_gem_request
*req
);
3110 int i915_gem_ringbuffer_submission(struct i915_execbuffer_params
*params
,
3111 struct drm_i915_gem_execbuffer2
*args
,
3112 struct list_head
*vmas
);
3113 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3114 struct drm_file
*file_priv
);
3115 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3116 struct drm_file
*file_priv
);
3117 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3118 struct drm_file
*file_priv
);
3119 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3120 struct drm_file
*file
);
3121 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3122 struct drm_file
*file
);
3123 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3124 struct drm_file
*file_priv
);
3125 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3126 struct drm_file
*file_priv
);
3127 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3128 struct drm_file
*file_priv
);
3129 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3130 struct drm_file
*file_priv
);
3131 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3132 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3133 struct drm_file
*file
);
3134 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3135 struct drm_file
*file_priv
);
3136 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3137 struct drm_file
*file_priv
);
3138 void i915_gem_load_init(struct drm_device
*dev
);
3139 void i915_gem_load_cleanup(struct drm_device
*dev
);
3140 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3141 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3143 void *i915_gem_object_alloc(struct drm_device
*dev
);
3144 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3145 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3146 const struct drm_i915_gem_object_ops
*ops
);
3147 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3149 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3150 struct drm_device
*dev
, const void *data
, size_t size
);
3151 void i915_gem_free_object(struct drm_gem_object
*obj
);
3152 void i915_gem_vma_destroy(struct i915_vma
*vma
);
3154 /* Flags used by pin/bind&friends. */
3155 #define PIN_MAPPABLE (1<<0)
3156 #define PIN_NONBLOCK (1<<1)
3157 #define PIN_GLOBAL (1<<2)
3158 #define PIN_OFFSET_BIAS (1<<3)
3159 #define PIN_USER (1<<4)
3160 #define PIN_UPDATE (1<<5)
3161 #define PIN_ZONE_4G (1<<6)
3162 #define PIN_HIGH (1<<7)
3163 #define PIN_OFFSET_FIXED (1<<8)
3164 #define PIN_OFFSET_MASK (~4095)
3166 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
3167 struct i915_address_space
*vm
,
3171 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3172 const struct i915_ggtt_view
*view
,
3176 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3178 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3179 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3181 * BEWARE: Do not use the function below unless you can _absolutely_
3182 * _guarantee_ VMA in question is _not in use_ anywhere.
3184 int __must_check
__i915_vma_unbind_no_wait(struct i915_vma
*vma
);
3185 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
3186 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
3187 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3189 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3190 int *needs_clflush
);
3192 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3194 static inline int __sg_page_count(struct scatterlist
*sg
)
3196 return sg
->length
>> PAGE_SHIFT
;
3200 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3202 static inline dma_addr_t
3203 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
, int n
)
3205 if (n
< obj
->get_page
.last
) {
3206 obj
->get_page
.sg
= obj
->pages
->sgl
;
3207 obj
->get_page
.last
= 0;
3210 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3211 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3212 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3213 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3216 return sg_dma_address(obj
->get_page
.sg
) + ((n
- obj
->get_page
.last
) << PAGE_SHIFT
);
3219 static inline struct page
*
3220 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3222 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3225 if (n
< obj
->get_page
.last
) {
3226 obj
->get_page
.sg
= obj
->pages
->sgl
;
3227 obj
->get_page
.last
= 0;
3230 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3231 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3232 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3233 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3236 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3239 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3241 BUG_ON(obj
->pages
== NULL
);
3242 obj
->pages_pin_count
++;
3245 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3247 BUG_ON(obj
->pages_pin_count
== 0);
3248 obj
->pages_pin_count
--;
3252 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3253 * @obj - the object to map into kernel address space
3255 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3256 * pages and then returns a contiguous mapping of the backing storage into
3257 * the kernel address space.
3259 * The caller must hold the struct_mutex, and is responsible for calling
3260 * i915_gem_object_unpin_map() when the mapping is no longer required.
3262 * Returns the pointer through which to access the mapped object, or an
3263 * ERR_PTR() on error.
3265 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
);
3268 * i915_gem_object_unpin_map - releases an earlier mapping
3269 * @obj - the object to unmap
3271 * After pinning the object and mapping its pages, once you are finished
3272 * with your access, call i915_gem_object_unpin_map() to release the pin
3273 * upon the mapping. Once the pin count reaches zero, that mapping may be
3276 * The caller must hold the struct_mutex.
3278 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3280 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3281 i915_gem_object_unpin_pages(obj
);
3284 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3285 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3286 struct intel_engine_cs
*to
,
3287 struct drm_i915_gem_request
**to_req
);
3288 void i915_vma_move_to_active(struct i915_vma
*vma
,
3289 struct drm_i915_gem_request
*req
);
3290 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3291 struct drm_device
*dev
,
3292 struct drm_mode_create_dumb
*args
);
3293 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3294 uint32_t handle
, uint64_t *offset
);
3296 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3297 struct drm_i915_gem_object
*new,
3298 unsigned frontbuffer_bits
);
3301 * Returns true if seq1 is later than seq2.
3304 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
3306 return (int32_t)(seq1
- seq2
) >= 0;
3309 static inline bool i915_gem_request_started(const struct drm_i915_gem_request
*req
)
3311 return i915_seqno_passed(intel_engine_get_seqno(req
->engine
),
3312 req
->previous_seqno
);
3315 static inline bool i915_gem_request_completed(const struct drm_i915_gem_request
*req
)
3317 return i915_seqno_passed(intel_engine_get_seqno(req
->engine
),
3321 bool __i915_spin_request(const struct drm_i915_gem_request
*request
,
3322 int state
, unsigned long timeout_us
);
3323 static inline bool i915_spin_request(const struct drm_i915_gem_request
*request
,
3324 int state
, unsigned long timeout_us
)
3326 return (i915_gem_request_started(request
) &&
3327 __i915_spin_request(request
, state
, timeout_us
));
3330 int __must_check
i915_gem_get_seqno(struct drm_i915_private
*dev_priv
, u32
*seqno
);
3331 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3333 struct drm_i915_gem_request
*
3334 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3336 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3337 void i915_gem_retire_requests_ring(struct intel_engine_cs
*engine
);
3339 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3341 return atomic_read(&error
->reset_counter
);
3344 static inline bool __i915_reset_in_progress(u32 reset
)
3346 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3349 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3351 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3354 static inline bool __i915_terminally_wedged(u32 reset
)
3356 return unlikely(reset
& I915_WEDGED
);
3359 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3361 return __i915_reset_in_progress(i915_reset_counter(error
));
3364 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3366 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3369 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3371 return __i915_terminally_wedged(i915_reset_counter(error
));
3374 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3376 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3379 void i915_gem_reset(struct drm_device
*dev
);
3380 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3381 int __must_check
i915_gem_init(struct drm_device
*dev
);
3382 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3383 void i915_gem_init_swizzling(struct drm_device
*dev
);
3384 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3385 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
);
3386 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3387 void __i915_add_request(struct drm_i915_gem_request
*req
,
3388 struct drm_i915_gem_object
*batch_obj
,
3390 #define i915_add_request(req) \
3391 __i915_add_request(req, NULL, true)
3392 #define i915_add_request_no_flush(req) \
3393 __i915_add_request(req, NULL, false)
3394 int __i915_wait_request(struct drm_i915_gem_request
*req
,
3397 struct intel_rps_client
*rps
);
3398 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
3399 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3401 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3404 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3407 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3409 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3411 const struct i915_ggtt_view
*view
);
3412 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
3413 const struct i915_ggtt_view
*view
);
3414 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3416 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3417 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3420 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
3422 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
3423 int tiling_mode
, bool fenced
);
3425 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3426 enum i915_cache_level cache_level
);
3428 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3429 struct dma_buf
*dma_buf
);
3431 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3432 struct drm_gem_object
*gem_obj
, int flags
);
3434 u64
i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
3435 const struct i915_ggtt_view
*view
);
3436 u64
i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
3437 struct i915_address_space
*vm
);
3439 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
3441 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
3444 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
3445 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
3446 const struct i915_ggtt_view
*view
);
3447 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
3448 struct i915_address_space
*vm
);
3451 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3452 struct i915_address_space
*vm
);
3454 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
3455 const struct i915_ggtt_view
*view
);
3458 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3459 struct i915_address_space
*vm
);
3461 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
3462 const struct i915_ggtt_view
*view
);
3464 static inline struct i915_vma
*
3465 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
3467 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
3469 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
3471 /* Some GGTT VM helpers */
3472 static inline struct i915_hw_ppgtt
*
3473 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3475 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3479 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
3481 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
3485 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
);
3487 static inline int __must_check
3488 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
3492 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3493 struct i915_ggtt
*ggtt
= &dev_priv
->ggtt
;
3495 return i915_gem_object_pin(obj
, &ggtt
->base
,
3496 alignment
, flags
| PIN_GLOBAL
);
3499 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
3500 const struct i915_ggtt_view
*view
);
3502 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
3504 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
3507 /* i915_gem_fence.c */
3508 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3509 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3511 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3512 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3514 void i915_gem_restore_fences(struct drm_device
*dev
);
3516 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3517 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3518 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3520 /* i915_gem_context.c */
3521 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3522 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3523 void i915_gem_context_fini(struct drm_device
*dev
);
3524 void i915_gem_context_reset(struct drm_device
*dev
);
3525 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3526 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3527 int i915_switch_context(struct drm_i915_gem_request
*req
);
3528 void i915_gem_context_free(struct kref
*ctx_ref
);
3529 struct drm_i915_gem_object
*
3530 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3531 struct i915_gem_context
*
3532 i915_gem_context_create_gvt(struct drm_device
*dev
);
3534 static inline struct i915_gem_context
*
3535 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3537 struct i915_gem_context
*ctx
;
3539 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3541 ctx
= idr_find(&file_priv
->context_idr
, id
);
3543 return ERR_PTR(-ENOENT
);
3548 static inline void i915_gem_context_reference(struct i915_gem_context
*ctx
)
3550 kref_get(&ctx
->ref
);
3553 static inline void i915_gem_context_unreference(struct i915_gem_context
*ctx
)
3555 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3556 kref_put(&ctx
->ref
, i915_gem_context_free
);
3559 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3561 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3564 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3565 struct drm_file
*file
);
3566 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3567 struct drm_file
*file
);
3568 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3569 struct drm_file
*file_priv
);
3570 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3571 struct drm_file
*file_priv
);
3572 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3573 struct drm_file
*file
);
3575 /* i915_gem_evict.c */
3576 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3577 struct i915_address_space
*vm
,
3580 unsigned cache_level
,
3581 unsigned long start
,
3584 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3585 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3587 /* belongs in i915_gem_gtt.h */
3588 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3590 if (INTEL_GEN(dev_priv
) < 6)
3591 intel_gtt_chipset_flush();
3594 /* i915_gem_stolen.c */
3595 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3596 struct drm_mm_node
*node
, u64 size
,
3597 unsigned alignment
);
3598 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3599 struct drm_mm_node
*node
, u64 size
,
3600 unsigned alignment
, u64 start
,
3602 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3603 struct drm_mm_node
*node
);
3604 int i915_gem_init_stolen(struct drm_device
*dev
);
3605 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3606 struct drm_i915_gem_object
*
3607 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3608 struct drm_i915_gem_object
*
3609 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3614 /* i915_gem_shrinker.c */
3615 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3616 unsigned long target
,
3618 #define I915_SHRINK_PURGEABLE 0x1
3619 #define I915_SHRINK_UNBOUND 0x2
3620 #define I915_SHRINK_BOUND 0x4
3621 #define I915_SHRINK_ACTIVE 0x8
3622 #define I915_SHRINK_VMAPS 0x10
3623 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3624 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3625 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3628 /* i915_gem_tiling.c */
3629 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3631 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3633 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3634 obj
->tiling_mode
!= I915_TILING_NONE
;
3637 /* i915_gem_debug.c */
3639 int i915_verify_lists(struct drm_device
*dev
);
3641 #define i915_verify_lists(dev) 0
3644 /* i915_debugfs.c */
3645 #ifdef CONFIG_DEBUG_FS
3646 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3647 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3648 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3649 void intel_display_crc_init(struct drm_device
*dev
);
3651 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3652 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3653 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3655 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3658 /* i915_gpu_error.c */
3660 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3661 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3662 const struct i915_error_state_file_priv
*error
);
3663 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3664 struct drm_i915_private
*i915
,
3665 size_t count
, loff_t pos
);
3666 static inline void i915_error_state_buf_release(
3667 struct drm_i915_error_state_buf
*eb
)
3671 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3673 const char *error_msg
);
3674 void i915_error_state_get(struct drm_device
*dev
,
3675 struct i915_error_state_file_priv
*error_priv
);
3676 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3677 void i915_destroy_error_state(struct drm_device
*dev
);
3679 void i915_get_extra_instdone(struct drm_i915_private
*dev_priv
, uint32_t *instdone
);
3680 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3682 /* i915_cmd_parser.c */
3683 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3684 int i915_cmd_parser_init_ring(struct intel_engine_cs
*engine
);
3685 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*engine
);
3686 bool i915_needs_cmd_parser(struct intel_engine_cs
*engine
);
3687 int i915_parse_cmds(struct intel_engine_cs
*engine
,
3688 struct drm_i915_gem_object
*batch_obj
,
3689 struct drm_i915_gem_object
*shadow_batch_obj
,
3690 u32 batch_start_offset
,
3694 /* i915_suspend.c */
3695 extern int i915_save_state(struct drm_device
*dev
);
3696 extern int i915_restore_state(struct drm_device
*dev
);
3699 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3700 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3703 extern int intel_setup_gmbus(struct drm_device
*dev
);
3704 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3705 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3708 extern struct i2c_adapter
*
3709 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3710 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3711 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3712 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3714 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3716 extern void intel_i2c_reset(struct drm_device
*dev
);
3719 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3720 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3721 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3722 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3723 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3724 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3725 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3726 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3727 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3730 /* intel_opregion.c */
3732 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3733 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3734 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3735 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3736 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3738 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3740 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3742 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3743 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3744 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3745 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3749 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3754 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3758 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3766 extern void intel_register_dsm_handler(void);
3767 extern void intel_unregister_dsm_handler(void);
3769 static inline void intel_register_dsm_handler(void) { return; }
3770 static inline void intel_unregister_dsm_handler(void) { return; }
3771 #endif /* CONFIG_ACPI */
3773 /* intel_device_info.c */
3774 static inline struct intel_device_info
*
3775 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3777 return (struct intel_device_info
*)&dev_priv
->info
;
3780 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3781 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3784 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3785 extern void intel_modeset_init(struct drm_device
*dev
);
3786 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3787 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3788 extern int intel_connector_register(struct drm_connector
*);
3789 extern void intel_connector_unregister(struct drm_connector
*);
3790 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3791 extern void intel_display_resume(struct drm_device
*dev
);
3792 extern void i915_redisable_vga(struct drm_device
*dev
);
3793 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3794 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3795 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3796 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3797 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3800 extern bool i915_semaphore_is_enabled(struct drm_i915_private
*dev_priv
);
3801 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3802 struct drm_file
*file
);
3805 extern struct intel_overlay_error_state
*
3806 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3807 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3808 struct intel_overlay_error_state
*error
);
3810 extern struct intel_display_error_state
*
3811 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3812 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3813 struct drm_device
*dev
,
3814 struct intel_display_error_state
*error
);
3816 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3817 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3819 /* intel_sideband.c */
3820 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3821 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3822 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3823 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3824 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3825 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3826 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3827 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3828 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3829 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3830 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3831 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3832 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3833 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3834 enum intel_sbi_destination destination
);
3835 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3836 enum intel_sbi_destination destination
);
3837 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3838 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3840 /* intel_dpio_phy.c */
3841 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3842 u32 deemph_reg_value
, u32 margin_reg_value
,
3843 bool uniq_trans_scale
);
3844 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3846 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3847 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3848 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3849 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3851 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3852 u32 demph_reg_value
, u32 preemph_reg_value
,
3853 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3854 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3855 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3856 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3858 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3859 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3861 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3862 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3864 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3865 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3866 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3867 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3869 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3870 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3871 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3872 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3874 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3875 * will be implemented using 2 32-bit writes in an arbitrary order with
3876 * an arbitrary delay between them. This can cause the hardware to
3877 * act upon the intermediate value, possibly leading to corruption and
3878 * machine death. You have been warned.
3880 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3881 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3883 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3884 u32 upper, lower, old_upper, loop = 0; \
3885 upper = I915_READ(upper_reg); \
3887 old_upper = upper; \
3888 lower = I915_READ(lower_reg); \
3889 upper = I915_READ(upper_reg); \
3890 } while (upper != old_upper && loop++ < 2); \
3891 (u64)upper << 32 | lower; })
3893 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3894 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3896 #define __raw_read(x, s) \
3897 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3900 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3903 #define __raw_write(x, s) \
3904 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3905 i915_reg_t reg, uint##x##_t val) \
3907 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3922 /* These are untraced mmio-accessors that are only valid to be used inside
3923 * criticial sections inside IRQ handlers where forcewake is explicitly
3925 * Think twice, and think again, before using these.
3926 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3927 * intel_uncore_forcewake_irqunlock().
3929 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3930 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3931 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3932 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3934 /* "Broadcast RGB" property */
3935 #define INTEL_BROADCAST_RGB_AUTO 0
3936 #define INTEL_BROADCAST_RGB_FULL 1
3937 #define INTEL_BROADCAST_RGB_LIMITED 2
3939 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3941 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3942 return VLV_VGACNTRL
;
3943 else if (INTEL_INFO(dev
)->gen
>= 5)
3944 return CPU_VGACNTRL
;
3949 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3951 unsigned long j
= msecs_to_jiffies(m
);
3953 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3956 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3958 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3961 static inline unsigned long
3962 timespec_to_jiffies_timeout(const struct timespec
*value
)
3964 unsigned long j
= timespec_to_jiffies(value
);
3966 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3970 * If you need to wait X milliseconds between events A and B, but event B
3971 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3972 * when event A happened, then just before event B you call this function and
3973 * pass the timestamp as the first argument, and X as the second argument.
3976 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3978 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3981 * Don't re-read the value of "jiffies" every time since it may change
3982 * behind our back and break the math.
3984 tmp_jiffies
= jiffies
;
3985 target_jiffies
= timestamp_jiffies
+
3986 msecs_to_jiffies_timeout(to_wait_ms
);
3988 if (time_after(target_jiffies
, tmp_jiffies
)) {
3989 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3990 while (remaining_jiffies
)
3992 schedule_timeout_uninterruptible(remaining_jiffies
);
3995 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3997 struct intel_engine_cs
*engine
= req
->engine
;
3999 /* Before we do the heavier coherent read of the seqno,
4000 * check the value (hopefully) in the CPU cacheline.
4002 if (i915_gem_request_completed(req
))
4005 /* Ensure our read of the seqno is coherent so that we
4006 * do not "miss an interrupt" (i.e. if this is the last
4007 * request and the seqno write from the GPU is not visible
4008 * by the time the interrupt fires, we will see that the
4009 * request is incomplete and go back to sleep awaiting
4010 * another interrupt that will never come.)
4012 * Strictly, we only need to do this once after an interrupt,
4013 * but it is easier and safer to do it every time the waiter
4016 if (engine
->irq_seqno_barrier
&&
4017 READ_ONCE(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
4018 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
4019 struct task_struct
*tsk
;
4021 /* The ordering of irq_posted versus applying the barrier
4022 * is crucial. The clearing of the current irq_posted must
4023 * be visible before we perform the barrier operation,
4024 * such that if a subsequent interrupt arrives, irq_posted
4025 * is reasserted and our task rewoken (which causes us to
4026 * do another __i915_request_irq_complete() immediately
4027 * and reapply the barrier). Conversely, if the clear
4028 * occurs after the barrier, then an interrupt that arrived
4029 * whilst we waited on the barrier would not trigger a
4030 * barrier on the next pass, and the read may not see the
4033 engine
->irq_seqno_barrier(engine
);
4035 /* If we consume the irq, but we are no longer the bottom-half,
4036 * the real bottom-half may not have serialised their own
4037 * seqno check with the irq-barrier (i.e. may have inspected
4038 * the seqno before we believe it coherent since they see
4039 * irq_posted == false but we are still running).
4042 tsk
= READ_ONCE(engine
->breadcrumbs
.irq_seqno_bh
);
4043 if (tsk
&& tsk
!= current
)
4044 /* Note that if the bottom-half is changed as we
4045 * are sending the wake-up, the new bottom-half will
4046 * be woken by whomever made the change. We only have
4047 * to worry about when we steal the irq-posted for
4050 wake_up_process(tsk
);
4053 if (i915_gem_request_completed(req
))
4057 /* We need to check whether any gpu reset happened in between
4058 * the request being submitted and now. If a reset has occurred,
4059 * the seqno will have been advance past ours and our request
4060 * is complete. If we are in the process of handling a reset,
4061 * the request is effectively complete as the rendering will
4062 * be discarded, but we need to return in order to drop the
4065 if (i915_reset_in_progress(&req
->i915
->gpu_error
))