drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include "i915_reg.h"
  36 #include "intel_bios.h"
  37 #include "intel_ringbuffer.h"
  38 #include "i915_gem_gtt.h"
  39 #include <linux/io-mapping.h>
  40 #include <linux/i2c.h>
  41 #include <linux/i2c-algo-bit.h>
  42 #include <drm/intel-gtt.h>
  43 #include <linux/backlight.h>
  44 #include <linux/hashtable.h>
  45 #include <linux/intel-iommu.h>
  46 #include <linux/kref.h>
  47 #include <linux/pm_qos.h>
  48
  49 /* General customization:
  50  */
  51
  52 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  53
  54 #define DRIVER_NAME             "i915"
  55 #define DRIVER_DESC             "Intel Graphics"
  56 #define DRIVER_DATE             "20140620"
  57
  58 enum pipe {
  59         INVALID_PIPE = -1,
  60         PIPE_A = 0,
  61         PIPE_B,
  62         PIPE_C,
  63         _PIPE_EDP,
  64         I915_MAX_PIPES = _PIPE_EDP
  65 };
  66 #define pipe_name(p) ((p) + 'A')
  67
  68 enum transcoder {
  69         TRANSCODER_A = 0,
  70         TRANSCODER_B,
  71         TRANSCODER_C,
  72         TRANSCODER_EDP,
  73         I915_MAX_TRANSCODERS
  74 };
  75 #define transcoder_name(t) ((t) + 'A')
  76
  77 enum plane {
  78         PLANE_A = 0,
  79         PLANE_B,
  80         PLANE_C,
  81 };
  82 #define plane_name(p) ((p) + 'A')
  83
  84 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
  85
  86 enum port {
  87         PORT_A = 0,
  88         PORT_B,
  89         PORT_C,
  90         PORT_D,
  91         PORT_E,
  92         I915_MAX_PORTS
  93 };
  94 #define port_name(p) ((p) + 'A')
  95
  96 #define I915_NUM_PHYS_VLV 2
  97
  98 enum dpio_channel {
  99         DPIO_CH0,
 100         DPIO_CH1
 101 };
 102
 103 enum dpio_phy {
 104         DPIO_PHY0,
 105         DPIO_PHY1
 106 };
 107
 108 enum intel_display_power_domain {
 109         POWER_DOMAIN_PIPE_A,
 110         POWER_DOMAIN_PIPE_B,
 111         POWER_DOMAIN_PIPE_C,
 112         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 113         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 114         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 115         POWER_DOMAIN_TRANSCODER_A,
 116         POWER_DOMAIN_TRANSCODER_B,
 117         POWER_DOMAIN_TRANSCODER_C,
 118         POWER_DOMAIN_TRANSCODER_EDP,
 119         POWER_DOMAIN_PORT_DDI_A_2_LANES,
 120         POWER_DOMAIN_PORT_DDI_A_4_LANES,
 121         POWER_DOMAIN_PORT_DDI_B_2_LANES,
 122         POWER_DOMAIN_PORT_DDI_B_4_LANES,
 123         POWER_DOMAIN_PORT_DDI_C_2_LANES,
 124         POWER_DOMAIN_PORT_DDI_C_4_LANES,
 125         POWER_DOMAIN_PORT_DDI_D_2_LANES,
 126         POWER_DOMAIN_PORT_DDI_D_4_LANES,
 127         POWER_DOMAIN_PORT_DSI,
 128         POWER_DOMAIN_PORT_CRT,
 129         POWER_DOMAIN_PORT_OTHER,
 130         POWER_DOMAIN_VGA,
 131         POWER_DOMAIN_AUDIO,
 132         POWER_DOMAIN_INIT,
 133
 134         POWER_DOMAIN_NUM,
 135 };
 136
 137 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 138 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 139                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 140 #define POWER_DOMAIN_TRANSCODER(tran) \
 141         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 142          (tran) + POWER_DOMAIN_TRANSCODER_A)
 143
 144 enum hpd_pin {
 145         HPD_NONE = 0,
 146         HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
 147         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 148         HPD_CRT,
 149         HPD_SDVO_B,
 150         HPD_SDVO_C,
 151         HPD_PORT_B,
 152         HPD_PORT_C,
 153         HPD_PORT_D,
 154         HPD_NUM_PINS
 155 };
 156
 157 #define I915_GEM_GPU_DOMAINS \
 158         (I915_GEM_DOMAIN_RENDER | \
 159          I915_GEM_DOMAIN_SAMPLER | \
 160          I915_GEM_DOMAIN_COMMAND | \
 161          I915_GEM_DOMAIN_INSTRUCTION | \
 162          I915_GEM_DOMAIN_VERTEX)
 163
 164 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
 165 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
 166
 167 #define for_each_crtc(dev, crtc) \
 168         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 169
 170 #define for_each_intel_crtc(dev, intel_crtc) \
 171         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
 172
 173 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 174         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 175                 if ((intel_encoder)->base.crtc == (__crtc))
 176
 177 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 178         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 179                 if ((intel_connector)->base.encoder == (__encoder))
 180
 181 struct drm_i915_private;
 182 struct i915_mmu_object;
 183
 184 enum intel_dpll_id {
 185         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 186         /* real shared dpll ids must be >= 0 */
 187         DPLL_ID_PCH_PLL_A,
 188         DPLL_ID_PCH_PLL_B,
 189 };
 190 #define I915_NUM_PLLS 2
 191
 192 struct intel_dpll_hw_state {
 193         uint32_t dpll;
 194         uint32_t dpll_md;
 195         uint32_t fp0;
 196         uint32_t fp1;
 197 };
 198
 199 struct intel_shared_dpll {
 200         int refcount; /* count of number of CRTCs sharing this PLL */
 201         int active; /* count of number of active CRTCs (i.e. DPMS on) */
 202         bool on; /* is the PLL actually active? Disabled during modeset */
 203         const char *name;
 204         /* should match the index in the dev_priv->shared_dplls array */
 205         enum intel_dpll_id id;
 206         struct intel_dpll_hw_state hw_state;
 207         void (*mode_set)(struct drm_i915_private *dev_priv,
 208                          struct intel_shared_dpll *pll);
 209         void (*enable)(struct drm_i915_private *dev_priv,
 210                        struct intel_shared_dpll *pll);
 211         void (*disable)(struct drm_i915_private *dev_priv,
 212                         struct intel_shared_dpll *pll);
 213         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 214                              struct intel_shared_dpll *pll,
 215                              struct intel_dpll_hw_state *hw_state);
 216 };
 217
 218 /* Used by dp and fdi links */
 219 struct intel_link_m_n {
 220         uint32_t        tu;
 221         uint32_t        gmch_m;
 222         uint32_t        gmch_n;
 223         uint32_t        link_m;
 224         uint32_t        link_n;
 225 };
 226
 227 void intel_link_compute_m_n(int bpp, int nlanes,
 228                             int pixel_clock, int link_clock,
 229                             struct intel_link_m_n *m_n);
 230
 231 struct intel_ddi_plls {
 232         int spll_refcount;
 233         int wrpll1_refcount;
 234         int wrpll2_refcount;
 235 };
 236
 237 /* Interface history:
 238  *
 239  * 1.1: Original.
 240  * 1.2: Add Power Management
 241  * 1.3: Add vblank support
 242  * 1.4: Fix cmdbuffer path, add heap destroy
 243  * 1.5: Add vblank pipe configuration
 244  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 245  *      - Support vertical blank on secondary display pipe
 246  */
 247 #define DRIVER_MAJOR            1
 248 #define DRIVER_MINOR            6
 249 #define DRIVER_PATCHLEVEL       0
 250
 251 #define WATCH_LISTS     0
 252 #define WATCH_GTT       0
 253
 254 struct opregion_header;
 255 struct opregion_acpi;
 256 struct opregion_swsci;
 257 struct opregion_asle;
 258
 259 struct intel_opregion {
 260         struct opregion_header __iomem *header;
 261         struct opregion_acpi __iomem *acpi;
 262         struct opregion_swsci __iomem *swsci;
 263         u32 swsci_gbda_sub_functions;
 264         u32 swsci_sbcb_sub_functions;
 265         struct opregion_asle __iomem *asle;
 266         void __iomem *vbt;
 267         u32 __iomem *lid_state;
 268         struct work_struct asle_work;
 269 };
 270 #define OPREGION_SIZE            (8*1024)
 271
 272 struct intel_overlay;
 273 struct intel_overlay_error_state;
 274
 275 struct drm_i915_master_private {
 276         drm_local_map_t *sarea;
 277         struct _drm_i915_sarea *sarea_priv;
 278 };
 279 #define I915_FENCE_REG_NONE -1
 280 #define I915_MAX_NUM_FENCES 32
 281 /* 32 fences + sign bit for FENCE_REG_NONE */
 282 #define I915_MAX_NUM_FENCE_BITS 6
 283
 284 struct drm_i915_fence_reg {
 285         struct list_head lru_list;
 286         struct drm_i915_gem_object *obj;
 287         int pin_count;
 288 };
 289
 290 struct sdvo_device_mapping {
 291         u8 initialized;
 292         u8 dvo_port;
 293         u8 slave_addr;
 294         u8 dvo_wiring;
 295         u8 i2c_pin;
 296         u8 ddc_pin;
 297 };
 298
 299 struct intel_display_error_state;
 300
 301 struct drm_i915_error_state {
 302         struct kref ref;
 303         struct timeval time;
 304
 305         char error_msg[128];
 306         u32 reset_count;
 307         u32 suspend_count;
 308
 309         /* Generic register state */
 310         u32 eir;
 311         u32 pgtbl_er;
 312         u32 ier;
 313         u32 ccid;
 314         u32 derrmr;
 315         u32 forcewake;
 316         u32 error; /* gen6+ */
 317         u32 err_int; /* gen7 */
 318         u32 done_reg;
 319         u32 gac_eco;
 320         u32 gam_ecochk;
 321         u32 gab_ctl;
 322         u32 gfx_mode;
 323         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 324         u64 fence[I915_MAX_NUM_FENCES];
 325         struct intel_overlay_error_state *overlay;
 326         struct intel_display_error_state *display;
 327
 328         struct drm_i915_error_ring {
 329                 bool valid;
 330                 /* Software tracked state */
 331                 bool waiting;
 332                 int hangcheck_score;
 333                 enum intel_ring_hangcheck_action hangcheck_action;
 334                 int num_requests;
 335
 336                 /* our own tracking of ring head and tail */
 337                 u32 cpu_ring_head;
 338                 u32 cpu_ring_tail;
 339
 340                 u32 semaphore_seqno[I915_NUM_RINGS - 1];
 341
 342                 /* Register state */
 343                 u32 tail;
 344                 u32 head;
 345                 u32 ctl;
 346                 u32 hws;
 347                 u32 ipeir;
 348                 u32 ipehr;
 349                 u32 instdone;
 350                 u32 bbstate;
 351                 u32 instpm;
 352                 u32 instps;
 353                 u32 seqno;
 354                 u64 bbaddr;
 355                 u64 acthd;
 356                 u32 fault_reg;
 357                 u64 faddr;
 358                 u32 rc_psmi; /* sleep state */
 359                 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
 360
 361                 struct drm_i915_error_object {
 362                         int page_count;
 363                         u32 gtt_offset;
 364                         u32 *pages[0];
 365                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 366
 367                 struct drm_i915_error_request {
 368                         long jiffies;
 369                         u32 seqno;
 370                         u32 tail;
 371                 } *requests;
 372
 373                 struct {
 374                         u32 gfx_mode;
 375                         union {
 376                                 u64 pdp[4];
 377                                 u32 pp_dir_base;
 378                         };
 379                 } vm_info;
 380
 381                 pid_t pid;
 382                 char comm[TASK_COMM_LEN];
 383         } ring[I915_NUM_RINGS];
 384         struct drm_i915_error_buffer {
 385                 u32 size;
 386                 u32 name;
 387                 u32 rseqno, wseqno;
 388                 u32 gtt_offset;
 389                 u32 read_domains;
 390                 u32 write_domain;
 391                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 392                 s32 pinned:2;
 393                 u32 tiling:2;
 394                 u32 dirty:1;
 395                 u32 purgeable:1;
 396                 u32 userptr:1;
 397                 s32 ring:4;
 398                 u32 cache_level:3;
 399         } **active_bo, **pinned_bo;
 400
 401         u32 *active_bo_count, *pinned_bo_count;
 402 };
 403
 404 struct intel_connector;
 405 struct intel_crtc_config;
 406 struct intel_plane_config;
 407 struct intel_crtc;
 408 struct intel_limit;
 409 struct dpll;
 410
 411 struct drm_i915_display_funcs {
 412         bool (*fbc_enabled)(struct drm_device *dev);
 413         void (*enable_fbc)(struct drm_crtc *crtc);
 414         void (*disable_fbc)(struct drm_device *dev);
 415         int (*get_display_clock_speed)(struct drm_device *dev);
 416         int (*get_fifo_size)(struct drm_device *dev, int plane);
 417         /**
 418          * find_dpll() - Find the best values for the PLL
 419          * @limit: limits for the PLL
 420          * @crtc: current CRTC
 421          * @target: target frequency in kHz
 422          * @refclk: reference clock frequency in kHz
 423          * @match_clock: if provided, @best_clock P divider must
 424          *               match the P divider from @match_clock
 425          *               used for LVDS downclocking
 426          * @best_clock: best PLL values found
 427          *
 428          * Returns true on success, false on failure.
 429          */
 430         bool (*find_dpll)(const struct intel_limit *limit,
 431                           struct drm_crtc *crtc,
 432                           int target, int refclk,
 433                           struct dpll *match_clock,
 434                           struct dpll *best_clock);
 435         void (*update_wm)(struct drm_crtc *crtc);
 436         void (*update_sprite_wm)(struct drm_plane *plane,
 437                                  struct drm_crtc *crtc,
 438                                  uint32_t sprite_width, int pixel_size,
 439                                  bool enable, bool scaled);
 440         void (*modeset_global_resources)(struct drm_device *dev);
 441         /* Returns the active state of the crtc, and if the crtc is active,
 442          * fills out the pipe-config with the hw state. */
 443         bool (*get_pipe_config)(struct intel_crtc *,
 444                                 struct intel_crtc_config *);
 445         void (*get_plane_config)(struct intel_crtc *,
 446                                  struct intel_plane_config *);
 447         int (*crtc_mode_set)(struct drm_crtc *crtc,
 448                              int x, int y,
 449                              struct drm_framebuffer *old_fb);
 450         void (*crtc_enable)(struct drm_crtc *crtc);
 451         void (*crtc_disable)(struct drm_crtc *crtc);
 452         void (*off)(struct drm_crtc *crtc);
 453         void (*write_eld)(struct drm_connector *connector,
 454                           struct drm_crtc *crtc,
 455                           struct drm_display_mode *mode);
 456         void (*fdi_link_train)(struct drm_crtc *crtc);
 457         void (*init_clock_gating)(struct drm_device *dev);
 458         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 459                           struct drm_framebuffer *fb,
 460                           struct drm_i915_gem_object *obj,
 461                           struct intel_engine_cs *ring,
 462                           uint32_t flags);
 463         void (*update_primary_plane)(struct drm_crtc *crtc,
 464                                      struct drm_framebuffer *fb,
 465                                      int x, int y);
 466         void (*hpd_irq_setup)(struct drm_device *dev);
 467         /* clock updates for mode set */
 468         /* cursor updates */
 469         /* render clock increase/decrease */
 470         /* display clock increase/decrease */
 471         /* pll clock increase/decrease */
 472
 473         int (*setup_backlight)(struct intel_connector *connector);
 474         uint32_t (*get_backlight)(struct intel_connector *connector);
 475         void (*set_backlight)(struct intel_connector *connector,
 476                               uint32_t level);
 477         void (*disable_backlight)(struct intel_connector *connector);
 478         void (*enable_backlight)(struct intel_connector *connector);
 479 };
 480
 481 struct intel_uncore_funcs {
 482         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 483                                                         int fw_engine);
 484         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 485                                                         int fw_engine);
 486
 487         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 488         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 489         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 490         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 491
 492         void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
 493                                 uint8_t val, bool trace);
 494         void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
 495                                 uint16_t val, bool trace);
 496         void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
 497                                 uint32_t val, bool trace);
 498         void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
 499                                 uint64_t val, bool trace);
 500 };
 501
 502 struct intel_uncore {
 503         spinlock_t lock; /** lock is also taken in irq contexts. */
 504
 505         struct intel_uncore_funcs funcs;
 506
 507         unsigned fifo_count;
 508         unsigned forcewake_count;
 509
 510         unsigned fw_rendercount;
 511         unsigned fw_mediacount;
 512
 513         struct timer_list force_wake_timer;
 514 };
 515
 516 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
 517         func(is_mobile) sep \
 518         func(is_i85x) sep \
 519         func(is_i915g) sep \
 520         func(is_i945gm) sep \
 521         func(is_g33) sep \
 522         func(need_gfx_hws) sep \
 523         func(is_g4x) sep \
 524         func(is_pineview) sep \
 525         func(is_broadwater) sep \
 526         func(is_crestline) sep \
 527         func(is_ivybridge) sep \
 528         func(is_valleyview) sep \
 529         func(is_haswell) sep \
 530         func(is_preliminary) sep \
 531         func(has_fbc) sep \
 532         func(has_pipe_cxsr) sep \
 533         func(has_hotplug) sep \
 534         func(cursor_needs_physical) sep \
 535         func(has_overlay) sep \
 536         func(overlay_needs_physical) sep \
 537         func(supports_tv) sep \
 538         func(has_llc) sep \
 539         func(has_ddi) sep \
 540         func(has_fpga_dbg)
 541
 542 #define DEFINE_FLAG(name) u8 name:1
 543 #define SEP_SEMICOLON ;
 544
 545 struct intel_device_info {
 546         u32 display_mmio_offset;
 547         u8 num_pipes:3;
 548         u8 num_sprites[I915_MAX_PIPES];
 549         u8 gen;
 550         u8 ring_mask; /* Rings supported by the HW */
 551         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 552         /* Register offsets for the various display pipes and transcoders */
 553         int pipe_offsets[I915_MAX_TRANSCODERS];
 554         int trans_offsets[I915_MAX_TRANSCODERS];
 555         int palette_offsets[I915_MAX_PIPES];
 556         int cursor_offsets[I915_MAX_PIPES];
 557 };
 558
 559 #undef DEFINE_FLAG
 560 #undef SEP_SEMICOLON
 561
 562 enum i915_cache_level {
 563         I915_CACHE_NONE = 0,
 564         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 565         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 566                               caches, eg sampler/render caches, and the
 567                               large Last-Level-Cache. LLC is coherent with
 568                               the CPU, but L3 is only visible to the GPU. */
 569         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 570 };
 571
 572 struct i915_ctx_hang_stats {
 573         /* This context had batch pending when hang was declared */
 574         unsigned batch_pending;
 575
 576         /* This context had batch active when hang was declared */
 577         unsigned batch_active;
 578
 579         /* Time when this context was last blamed for a GPU reset */
 580         unsigned long guilty_ts;
 581
 582         /* This context is banned to submit more work */
 583         bool banned;
 584 };
 585
 586 /* This must match up with the value previously used for execbuf2.rsvd1. */
 587 #define DEFAULT_CONTEXT_ID 0
 588 struct intel_context {
 589         struct kref ref;
 590         int id;
 591         bool is_initialized;
 592         uint8_t remap_slice;
 593         struct drm_i915_file_private *file_priv;
 594         struct drm_i915_gem_object *obj;
 595         struct i915_ctx_hang_stats hang_stats;
 596         struct i915_address_space *vm;
 597
 598         struct list_head link;
 599 };
 600
 601 struct i915_fbc {
 602         unsigned long size;
 603         unsigned threshold;
 604         unsigned int fb_id;
 605         enum plane plane;
 606         int y;
 607
 608         struct drm_mm_node compressed_fb;
 609         struct drm_mm_node *compressed_llb;
 610
 611         struct intel_fbc_work {
 612                 struct delayed_work work;
 613                 struct drm_crtc *crtc;
 614                 struct drm_framebuffer *fb;
 615         } *fbc_work;
 616
 617         enum no_fbc_reason {
 618                 FBC_OK, /* FBC is enabled */
 619                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
 620                 FBC_NO_OUTPUT, /* no outputs enabled to compress */
 621                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
 622                 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 623                 FBC_MODE_TOO_LARGE, /* mode too large for compression */
 624                 FBC_BAD_PLANE, /* fbc not supported on plane */
 625                 FBC_NOT_TILED, /* buffer not tiled */
 626                 FBC_MULTIPLE_PIPES, /* more than one pipe active */
 627                 FBC_MODULE_PARAM,
 628                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
 629         } no_fbc_reason;
 630 };
 631
 632 struct i915_drrs {
 633         struct intel_connector *connector;
 634 };
 635
 636 struct i915_psr {
 637         bool sink_support;
 638         bool source_ok;
 639         bool setup_done;
 640         bool enabled;
 641         bool active;
 642         struct delayed_work work;
 643 };
 644
 645 enum intel_pch {
 646         PCH_NONE = 0,   /* No PCH present */
 647         PCH_IBX,        /* Ibexpeak PCH */
 648         PCH_CPT,        /* Cougarpoint PCH */
 649         PCH_LPT,        /* Lynxpoint PCH */
 650         PCH_NOP,
 651 };
 652
 653 enum intel_sbi_destination {
 654         SBI_ICLK,
 655         SBI_MPHY,
 656 };
 657
 658 #define QUIRK_PIPEA_FORCE (1<<0)
 659 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 660 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 661
 662 struct intel_fbdev;
 663 struct intel_fbc_work;
 664
 665 struct intel_gmbus {
 666         struct i2c_adapter adapter;
 667         u32 force_bit;
 668         u32 reg0;
 669         u32 gpio_reg;
 670         struct i2c_algo_bit_data bit_algo;
 671         struct drm_i915_private *dev_priv;
 672 };
 673
 674 struct i915_suspend_saved_registers {
 675         u8 saveLBB;
 676         u32 saveDSPACNTR;
 677         u32 saveDSPBCNTR;
 678         u32 saveDSPARB;
 679         u32 savePIPEACONF;
 680         u32 savePIPEBCONF;
 681         u32 savePIPEASRC;
 682         u32 savePIPEBSRC;
 683         u32 saveFPA0;
 684         u32 saveFPA1;
 685         u32 saveDPLL_A;
 686         u32 saveDPLL_A_MD;
 687         u32 saveHTOTAL_A;
 688         u32 saveHBLANK_A;
 689         u32 saveHSYNC_A;
 690         u32 saveVTOTAL_A;
 691         u32 saveVBLANK_A;
 692         u32 saveVSYNC_A;
 693         u32 saveBCLRPAT_A;
 694         u32 saveTRANSACONF;
 695         u32 saveTRANS_HTOTAL_A;
 696         u32 saveTRANS_HBLANK_A;
 697         u32 saveTRANS_HSYNC_A;
 698         u32 saveTRANS_VTOTAL_A;
 699         u32 saveTRANS_VBLANK_A;
 700         u32 saveTRANS_VSYNC_A;
 701         u32 savePIPEASTAT;
 702         u32 saveDSPASTRIDE;
 703         u32 saveDSPASIZE;
 704         u32 saveDSPAPOS;
 705         u32 saveDSPAADDR;
 706         u32 saveDSPASURF;
 707         u32 saveDSPATILEOFF;
 708         u32 savePFIT_PGM_RATIOS;
 709         u32 saveBLC_HIST_CTL;
 710         u32 saveBLC_PWM_CTL;
 711         u32 saveBLC_PWM_CTL2;
 712         u32 saveBLC_HIST_CTL_B;
 713         u32 saveBLC_CPU_PWM_CTL;
 714         u32 saveBLC_CPU_PWM_CTL2;
 715         u32 saveFPB0;
 716         u32 saveFPB1;
 717         u32 saveDPLL_B;
 718         u32 saveDPLL_B_MD;
 719         u32 saveHTOTAL_B;
 720         u32 saveHBLANK_B;
 721         u32 saveHSYNC_B;
 722         u32 saveVTOTAL_B;
 723         u32 saveVBLANK_B;
 724         u32 saveVSYNC_B;
 725         u32 saveBCLRPAT_B;
 726         u32 saveTRANSBCONF;
 727         u32 saveTRANS_HTOTAL_B;
 728         u32 saveTRANS_HBLANK_B;
 729         u32 saveTRANS_HSYNC_B;
 730         u32 saveTRANS_VTOTAL_B;
 731         u32 saveTRANS_VBLANK_B;
 732         u32 saveTRANS_VSYNC_B;
 733         u32 savePIPEBSTAT;
 734         u32 saveDSPBSTRIDE;
 735         u32 saveDSPBSIZE;
 736         u32 saveDSPBPOS;
 737         u32 saveDSPBADDR;
 738         u32 saveDSPBSURF;
 739         u32 saveDSPBTILEOFF;
 740         u32 saveVGA0;
 741         u32 saveVGA1;
 742         u32 saveVGA_PD;
 743         u32 saveVGACNTRL;
 744         u32 saveADPA;
 745         u32 saveLVDS;
 746         u32 savePP_ON_DELAYS;
 747         u32 savePP_OFF_DELAYS;
 748         u32 saveDVOA;
 749         u32 saveDVOB;
 750         u32 saveDVOC;
 751         u32 savePP_ON;
 752         u32 savePP_OFF;
 753         u32 savePP_CONTROL;
 754         u32 savePP_DIVISOR;
 755         u32 savePFIT_CONTROL;
 756         u32 save_palette_a[256];
 757         u32 save_palette_b[256];
 758         u32 saveFBC_CONTROL;
 759         u32 saveIER;
 760         u32 saveIIR;
 761         u32 saveIMR;
 762         u32 saveDEIER;
 763         u32 saveDEIMR;
 764         u32 saveGTIER;
 765         u32 saveGTIMR;
 766         u32 saveFDI_RXA_IMR;
 767         u32 saveFDI_RXB_IMR;
 768         u32 saveCACHE_MODE_0;
 769         u32 saveMI_ARB_STATE;
 770         u32 saveSWF0[16];
 771         u32 saveSWF1[16];
 772         u32 saveSWF2[3];
 773         u8 saveMSR;
 774         u8 saveSR[8];
 775         u8 saveGR[25];
 776         u8 saveAR_INDEX;
 777         u8 saveAR[21];
 778         u8 saveDACMASK;
 779         u8 saveCR[37];
 780         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 781         u32 saveCURACNTR;
 782         u32 saveCURAPOS;
 783         u32 saveCURABASE;
 784         u32 saveCURBCNTR;
 785         u32 saveCURBPOS;
 786         u32 saveCURBBASE;
 787         u32 saveCURSIZE;
 788         u32 saveDP_B;
 789         u32 saveDP_C;
 790         u32 saveDP_D;
 791         u32 savePIPEA_GMCH_DATA_M;
 792         u32 savePIPEB_GMCH_DATA_M;
 793         u32 savePIPEA_GMCH_DATA_N;
 794         u32 savePIPEB_GMCH_DATA_N;
 795         u32 savePIPEA_DP_LINK_M;
 796         u32 savePIPEB_DP_LINK_M;
 797         u32 savePIPEA_DP_LINK_N;
 798         u32 savePIPEB_DP_LINK_N;
 799         u32 saveFDI_RXA_CTL;
 800         u32 saveFDI_TXA_CTL;
 801         u32 saveFDI_RXB_CTL;
 802         u32 saveFDI_TXB_CTL;
 803         u32 savePFA_CTL_1;
 804         u32 savePFB_CTL_1;
 805         u32 savePFA_WIN_SZ;
 806         u32 savePFB_WIN_SZ;
 807         u32 savePFA_WIN_POS;
 808         u32 savePFB_WIN_POS;
 809         u32 savePCH_DREF_CONTROL;
 810         u32 saveDISP_ARB_CTL;
 811         u32 savePIPEA_DATA_M1;
 812         u32 savePIPEA_DATA_N1;
 813         u32 savePIPEA_LINK_M1;
 814         u32 savePIPEA_LINK_N1;
 815         u32 savePIPEB_DATA_M1;
 816         u32 savePIPEB_DATA_N1;
 817         u32 savePIPEB_LINK_M1;
 818         u32 savePIPEB_LINK_N1;
 819         u32 saveMCHBAR_RENDER_STANDBY;
 820         u32 savePCH_PORT_HOTPLUG;
 821 };
 822
 823 struct vlv_s0ix_state {
 824         /* GAM */
 825         u32 wr_watermark;
 826         u32 gfx_prio_ctrl;
 827         u32 arb_mode;
 828         u32 gfx_pend_tlb0;
 829         u32 gfx_pend_tlb1;
 830         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
 831         u32 media_max_req_count;
 832         u32 gfx_max_req_count;
 833         u32 render_hwsp;
 834         u32 ecochk;
 835         u32 bsd_hwsp;
 836         u32 blt_hwsp;
 837         u32 tlb_rd_addr;
 838
 839         /* MBC */
 840         u32 g3dctl;
 841         u32 gsckgctl;
 842         u32 mbctl;
 843
 844         /* GCP */
 845         u32 ucgctl1;
 846         u32 ucgctl3;
 847         u32 rcgctl1;
 848         u32 rcgctl2;
 849         u32 rstctl;
 850         u32 misccpctl;
 851
 852         /* GPM */
 853         u32 gfxpause;
 854         u32 rpdeuhwtc;
 855         u32 rpdeuc;
 856         u32 ecobus;
 857         u32 pwrdwnupctl;
 858         u32 rp_down_timeout;
 859         u32 rp_deucsw;
 860         u32 rcubmabdtmr;
 861         u32 rcedata;
 862         u32 spare2gh;
 863
 864         /* Display 1 CZ domain */
 865         u32 gt_imr;
 866         u32 gt_ier;
 867         u32 pm_imr;
 868         u32 pm_ier;
 869         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 870
 871         /* GT SA CZ domain */
 872         u32 tilectl;
 873         u32 gt_fifoctl;
 874         u32 gtlc_wake_ctrl;
 875         u32 gtlc_survive;
 876         u32 pmwgicz;
 877
 878         /* Display 2 CZ domain */
 879         u32 gu_ctl0;
 880         u32 gu_ctl1;
 881         u32 clock_gate_dis2;
 882 };
 883
 884 struct intel_gen6_power_mgmt {
 885         /* work and pm_iir are protected by dev_priv->irq_lock */
 886         struct work_struct work;
 887         u32 pm_iir;
 888
 889         /* Frequencies are stored in potentially platform dependent multiples.
 890          * In other words, *_freq needs to be multiplied by X to be interesting.
 891          * Soft limits are those which are used for the dynamic reclocking done
 892          * by the driver (raise frequencies under heavy loads, and lower for
 893          * lighter loads). Hard limits are those imposed by the hardware.
 894          *
 895          * A distinction is made for overclocking, which is never enabled by
 896          * default, and is considered to be above the hard limit if it's
 897          * possible at all.
 898          */
 899         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
 900         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
 901         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
 902         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
 903         u8 min_freq;            /* AKA RPn. Minimum frequency */
 904         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
 905         u8 rp1_freq;            /* "less than" RP0 power/freqency */
 906         u8 rp0_freq;            /* Non-overclocked max frequency. */
 907
 908         int last_adj;
 909         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
 910
 911         bool enabled;
 912         struct delayed_work delayed_resume_work;
 913
 914         /*
 915          * Protects RPS/RC6 register access and PCU communication.
 916          * Must be taken after struct_mutex if nested.
 917          */
 918         struct mutex hw_lock;
 919 };
 920
 921 /* defined intel_pm.c */
 922 extern spinlock_t mchdev_lock;
 923
 924 struct intel_ilk_power_mgmt {
 925         u8 cur_delay;
 926         u8 min_delay;
 927         u8 max_delay;
 928         u8 fmax;
 929         u8 fstart;
 930
 931         u64 last_count1;
 932         unsigned long last_time1;
 933         unsigned long chipset_power;
 934         u64 last_count2;
 935         struct timespec last_time2;
 936         unsigned long gfx_power;
 937         u8 corr;
 938
 939         int c_m;
 940         int r_t;
 941
 942         struct drm_i915_gem_object *pwrctx;
 943         struct drm_i915_gem_object *renderctx;
 944 };
 945
 946 struct drm_i915_private;
 947 struct i915_power_well;
 948
 949 struct i915_power_well_ops {
 950         /*
 951          * Synchronize the well's hw state to match the current sw state, for
 952          * example enable/disable it based on the current refcount. Called
 953          * during driver init and resume time, possibly after first calling
 954          * the enable/disable handlers.
 955          */
 956         void (*sync_hw)(struct drm_i915_private *dev_priv,
 957                         struct i915_power_well *power_well);
 958         /*
 959          * Enable the well and resources that depend on it (for example
 960          * interrupts located on the well). Called after the 0->1 refcount
 961          * transition.
 962          */
 963         void (*enable)(struct drm_i915_private *dev_priv,
 964                        struct i915_power_well *power_well);
 965         /*
 966          * Disable the well and resources that depend on it. Called after
 967          * the 1->0 refcount transition.
 968          */
 969         void (*disable)(struct drm_i915_private *dev_priv,
 970                         struct i915_power_well *power_well);
 971         /* Returns the hw enabled state. */
 972         bool (*is_enabled)(struct drm_i915_private *dev_priv,
 973                            struct i915_power_well *power_well);
 974 };
 975
 976 /* Power well structure for haswell */
 977 struct i915_power_well {
 978         const char *name;
 979         bool always_on;
 980         /* power well enable/disable usage count */
 981         int count;
 982         /* cached hw enabled state */
 983         bool hw_enabled;
 984         unsigned long domains;
 985         unsigned long data;
 986         const struct i915_power_well_ops *ops;
 987 };
 988
 989 struct i915_power_domains {
 990         /*
 991          * Power wells needed for initialization at driver init and suspend
 992          * time are on. They are kept on until after the first modeset.
 993          */
 994         bool init_power_on;
 995         bool initializing;
 996         int power_well_count;
 997
 998         struct mutex lock;
 999         int domain_use_count[POWER_DOMAIN_NUM];
1000         struct i915_power_well *power_wells;
1001 };
1002
1003 struct i915_dri1_state {
1004         unsigned allow_batchbuffer : 1;
1005         u32 __iomem *gfx_hws_cpu_addr;
1006
1007         unsigned int cpp;
1008         int back_offset;
1009         int front_offset;
1010         int current_page;
1011         int page_flipping;
1012
1013         uint32_t counter;
1014 };
1015
1016 struct i915_ums_state {
1017         /**
1018          * Flag if the X Server, and thus DRM, is not currently in
1019          * control of the device.
1020          *
1021          * This is set between LeaveVT and EnterVT.  It needs to be
1022          * replaced with a semaphore.  It also needs to be
1023          * transitioned away from for kernel modesetting.
1024          */
1025         int mm_suspended;
1026 };
1027
1028 #define MAX_L3_SLICES 2
1029 struct intel_l3_parity {
1030         u32 *remap_info[MAX_L3_SLICES];
1031         struct work_struct error_work;
1032         int which_slice;
1033 };
1034
1035 struct i915_gem_mm {
1036         /** Memory allocator for GTT stolen memory */
1037         struct drm_mm stolen;
1038         /** List of all objects in gtt_space. Used to restore gtt
1039          * mappings on resume */
1040         struct list_head bound_list;
1041         /**
1042          * List of objects which are not bound to the GTT (thus
1043          * are idle and not used by the GPU) but still have
1044          * (presumably uncached) pages still attached.
1045          */
1046         struct list_head unbound_list;
1047
1048         /** Usable portion of the GTT for GEM */
1049         unsigned long stolen_base; /* limited to low memory (32-bit) */
1050
1051         /** PPGTT used for aliasing the PPGTT with the GTT */
1052         struct i915_hw_ppgtt *aliasing_ppgtt;
1053
1054         struct notifier_block oom_notifier;
1055         struct shrinker shrinker;
1056         bool shrinker_no_lock_stealing;
1057
1058         /** LRU list of objects with fence regs on them. */
1059         struct list_head fence_list;
1060
1061         /**
1062          * We leave the user IRQ off as much as possible,
1063          * but this means that requests will finish and never
1064          * be retired once the system goes idle. Set a timer to
1065          * fire periodically while the ring is running. When it
1066          * fires, go retire requests.
1067          */
1068         struct delayed_work retire_work;
1069
1070         /**
1071          * When we detect an idle GPU, we want to turn on
1072          * powersaving features. So once we see that there
1073          * are no more requests outstanding and no more
1074          * arrive within a small period of time, we fire
1075          * off the idle_work.
1076          */
1077         struct delayed_work idle_work;
1078
1079         /**
1080          * Are we in a non-interruptible section of code like
1081          * modesetting?
1082          */
1083         bool interruptible;
1084
1085         /**
1086          * Is the GPU currently considered idle, or busy executing userspace
1087          * requests?  Whilst idle, we attempt to power down the hardware and
1088          * display clocks. In order to reduce the effect on performance, there
1089          * is a slight delay before we do so.
1090          */
1091         bool busy;
1092
1093         /* the indicator for dispatch video commands on two BSD rings */
1094         int bsd_ring_dispatch_index;
1095
1096         /** Bit 6 swizzling required for X tiling */
1097         uint32_t bit_6_swizzle_x;
1098         /** Bit 6 swizzling required for Y tiling */
1099         uint32_t bit_6_swizzle_y;
1100
1101         /* accounting, useful for userland debugging */
1102         spinlock_t object_stat_lock;
1103         size_t object_memory;
1104         u32 object_count;
1105 };
1106
1107 struct drm_i915_error_state_buf {
1108         unsigned bytes;
1109         unsigned size;
1110         int err;
1111         u8 *buf;
1112         loff_t start;
1113         loff_t pos;
1114 };
1115
1116 struct i915_error_state_file_priv {
1117         struct drm_device *dev;
1118         struct drm_i915_error_state *error;
1119 };
1120
1121 struct i915_gpu_error {
1122         /* For hangcheck timer */
1123 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1124 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1125         /* Hang gpu twice in this window and your context gets banned */
1126 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1127
1128         struct timer_list hangcheck_timer;
1129
1130         /* For reset and error_state handling. */
1131         spinlock_t lock;
1132         /* Protected by the above dev->gpu_error.lock. */
1133         struct drm_i915_error_state *first_error;
1134         struct work_struct work;
1135
1136
1137         unsigned long missed_irq_rings;
1138
1139         /**
1140          * State variable controlling the reset flow and count
1141          *
1142          * This is a counter which gets incremented when reset is triggered,
1143          * and again when reset has been handled. So odd values (lowest bit set)
1144          * means that reset is in progress and even values that
1145          * (reset_counter >> 1):th reset was successfully completed.
1146          *
1147          * If reset is not completed succesfully, the I915_WEDGE bit is
1148          * set meaning that hardware is terminally sour and there is no
1149          * recovery. All waiters on the reset_queue will be woken when
1150          * that happens.
1151          *
1152          * This counter is used by the wait_seqno code to notice that reset
1153          * event happened and it needs to restart the entire ioctl (since most
1154          * likely the seqno it waited for won't ever signal anytime soon).
1155          *
1156          * This is important for lock-free wait paths, where no contended lock
1157          * naturally enforces the correct ordering between the bail-out of the
1158          * waiter and the gpu reset work code.
1159          */
1160         atomic_t reset_counter;
1161
1162 #define I915_RESET_IN_PROGRESS_FLAG     1
1163 #define I915_WEDGED                     (1 << 31)
1164
1165         /**
1166          * Waitqueue to signal when the reset has completed. Used by clients
1167          * that wait for dev_priv->mm.wedged to settle.
1168          */
1169         wait_queue_head_t reset_queue;
1170
1171         /* Userspace knobs for gpu hang simulation;
1172          * combines both a ring mask, and extra flags
1173          */
1174         u32 stop_rings;
1175 #define I915_STOP_RING_ALLOW_BAN       (1 << 31)
1176 #define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1177
1178         /* For missed irq/seqno simulation. */
1179         unsigned int test_irq_rings;
1180 };
1181
1182 enum modeset_restore {
1183         MODESET_ON_LID_OPEN,
1184         MODESET_DONE,
1185         MODESET_SUSPENDED,
1186 };
1187
1188 struct ddi_vbt_port_info {
1189         uint8_t hdmi_level_shift;
1190
1191         uint8_t supports_dvi:1;
1192         uint8_t supports_hdmi:1;
1193         uint8_t supports_dp:1;
1194 };
1195
1196 enum drrs_support_type {
1197         DRRS_NOT_SUPPORTED = 0,
1198         STATIC_DRRS_SUPPORT = 1,
1199         SEAMLESS_DRRS_SUPPORT = 2
1200 };
1201
1202 struct intel_vbt_data {
1203         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1204         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1205
1206         /* Feature bits */
1207         unsigned int int_tv_support:1;
1208         unsigned int lvds_dither:1;
1209         unsigned int lvds_vbt:1;
1210         unsigned int int_crt_support:1;
1211         unsigned int lvds_use_ssc:1;
1212         unsigned int display_clock_mode:1;
1213         unsigned int fdi_rx_polarity_inverted:1;
1214         unsigned int has_mipi:1;
1215         int lvds_ssc_freq;
1216         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1217
1218         enum drrs_support_type drrs_type;
1219
1220         /* eDP */
1221         int edp_rate;
1222         int edp_lanes;
1223         int edp_preemphasis;
1224         int edp_vswing;
1225         bool edp_initialized;
1226         bool edp_support;
1227         int edp_bpp;
1228         struct edp_power_seq edp_pps;
1229
1230         struct {
1231                 u16 pwm_freq_hz;
1232                 bool present;
1233                 bool active_low_pwm;
1234         } backlight;
1235
1236         /* MIPI DSI */
1237         struct {
1238                 u16 port;
1239                 u16 panel_id;
1240                 struct mipi_config *config;
1241                 struct mipi_pps_data *pps;
1242                 u8 seq_version;
1243                 u32 size;
1244                 u8 *data;
1245                 u8 *sequence[MIPI_SEQ_MAX];
1246         } dsi;
1247
1248         int crt_ddc_pin;
1249
1250         int child_dev_num;
1251         union child_device_config *child_dev;
1252
1253         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1254 };
1255
1256 enum intel_ddb_partitioning {
1257         INTEL_DDB_PART_1_2,
1258         INTEL_DDB_PART_5_6, /* IVB+ */
1259 };
1260
1261 struct intel_wm_level {
1262         bool enable;
1263         uint32_t pri_val;
1264         uint32_t spr_val;
1265         uint32_t cur_val;
1266         uint32_t fbc_val;
1267 };
1268
1269 struct ilk_wm_values {
1270         uint32_t wm_pipe[3];
1271         uint32_t wm_lp[3];
1272         uint32_t wm_lp_spr[3];
1273         uint32_t wm_linetime[3];
1274         bool enable_fbc_wm;
1275         enum intel_ddb_partitioning partitioning;
1276 };
1277
1278 /*
1279  * This struct helps tracking the state needed for runtime PM, which puts the
1280  * device in PCI D3 state. Notice that when this happens, nothing on the
1281  * graphics device works, even register access, so we don't get interrupts nor
1282  * anything else.
1283  *
1284  * Every piece of our code that needs to actually touch the hardware needs to
1285  * either call intel_runtime_pm_get or call intel_display_power_get with the
1286  * appropriate power domain.
1287  *
1288  * Our driver uses the autosuspend delay feature, which means we'll only really
1289  * suspend if we stay with zero refcount for a certain amount of time. The
1290  * default value is currently very conservative (see intel_init_runtime_pm), but
1291  * it can be changed with the standard runtime PM files from sysfs.
1292  *
1293  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1294  * goes back to false exactly before we reenable the IRQs. We use this variable
1295  * to check if someone is trying to enable/disable IRQs while they're supposed
1296  * to be disabled. This shouldn't happen and we'll print some error messages in
1297  * case it happens.
1298  *
1299  * For more, read the Documentation/power/runtime_pm.txt.
1300  */
1301 struct i915_runtime_pm {
1302         bool suspended;
1303         bool irqs_disabled;
1304 };
1305
1306 enum intel_pipe_crc_source {
1307         INTEL_PIPE_CRC_SOURCE_NONE,
1308         INTEL_PIPE_CRC_SOURCE_PLANE1,
1309         INTEL_PIPE_CRC_SOURCE_PLANE2,
1310         INTEL_PIPE_CRC_SOURCE_PF,
1311         INTEL_PIPE_CRC_SOURCE_PIPE,
1312         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1313         INTEL_PIPE_CRC_SOURCE_TV,
1314         INTEL_PIPE_CRC_SOURCE_DP_B,
1315         INTEL_PIPE_CRC_SOURCE_DP_C,
1316         INTEL_PIPE_CRC_SOURCE_DP_D,
1317         INTEL_PIPE_CRC_SOURCE_AUTO,
1318         INTEL_PIPE_CRC_SOURCE_MAX,
1319 };
1320
1321 struct intel_pipe_crc_entry {
1322         uint32_t frame;
1323         uint32_t crc[5];
1324 };
1325
1326 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1327 struct intel_pipe_crc {
1328         spinlock_t lock;
1329         bool opened;            /* exclusive access to the result file */
1330         struct intel_pipe_crc_entry *entries;
1331         enum intel_pipe_crc_source source;
1332         int head, tail;
1333         wait_queue_head_t wq;
1334 };
1335
1336 struct i915_frontbuffer_tracking {
1337         struct mutex lock;
1338
1339         /*
1340          * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1341          * scheduled flips.
1342          */
1343         unsigned busy_bits;
1344         unsigned flip_bits;
1345 };
1346
1347 struct drm_i915_private {
1348         struct drm_device *dev;
1349         struct kmem_cache *slab;
1350
1351         const struct intel_device_info info;
1352
1353         int relative_constants_mode;
1354
1355         void __iomem *regs;
1356
1357         struct intel_uncore uncore;
1358
1359         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1360
1361
1362         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1363          * controller on different i2c buses. */
1364         struct mutex gmbus_mutex;
1365
1366         /**
1367          * Base address of the gmbus and gpio block.
1368          */
1369         uint32_t gpio_mmio_base;
1370
1371         /* MMIO base address for MIPI regs */
1372         uint32_t mipi_mmio_base;
1373
1374         wait_queue_head_t gmbus_wait_queue;
1375
1376         struct pci_dev *bridge_dev;
1377         struct intel_engine_cs ring[I915_NUM_RINGS];
1378         uint32_t last_seqno, next_seqno;
1379
1380         drm_dma_handle_t *status_page_dmah;
1381         struct resource mch_res;
1382
1383         /* protects the irq masks */
1384         spinlock_t irq_lock;
1385
1386         /* protects the mmio flip data */
1387         spinlock_t mmio_flip_lock;
1388
1389         bool display_irqs_enabled;
1390
1391         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1392         struct pm_qos_request pm_qos;
1393
1394         /* DPIO indirect register protection */
1395         struct mutex dpio_lock;
1396
1397         /** Cached value of IMR to avoid reads in updating the bitfield */
1398         union {
1399                 u32 irq_mask;
1400                 u32 de_irq_mask[I915_MAX_PIPES];
1401         };
1402         u32 gt_irq_mask;
1403         u32 pm_irq_mask;
1404         u32 pm_rps_events;
1405         u32 pipestat_irq_mask[I915_MAX_PIPES];
1406
1407         struct work_struct hotplug_work;
1408         bool enable_hotplug_processing;
1409         struct {
1410                 unsigned long hpd_last_jiffies;
1411                 int hpd_cnt;
1412                 enum {
1413                         HPD_ENABLED = 0,
1414                         HPD_DISABLED = 1,
1415                         HPD_MARK_DISABLED = 2
1416                 } hpd_mark;
1417         } hpd_stats[HPD_NUM_PINS];
1418         u32 hpd_event_bits;
1419         struct timer_list hotplug_reenable_timer;
1420
1421         struct i915_fbc fbc;
1422         struct i915_drrs drrs;
1423         struct intel_opregion opregion;
1424         struct intel_vbt_data vbt;
1425
1426         /* overlay */
1427         struct intel_overlay *overlay;
1428
1429         /* backlight registers and fields in struct intel_panel */
1430         spinlock_t backlight_lock;
1431
1432         /* LVDS info */
1433         bool no_aux_handshake;
1434
1435         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1436         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1437         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1438
1439         unsigned int fsb_freq, mem_freq, is_ddr3;
1440         unsigned int vlv_cdclk_freq;
1441
1442         /**
1443          * wq - Driver workqueue for GEM.
1444          *
1445          * NOTE: Work items scheduled here are not allowed to grab any modeset
1446          * locks, for otherwise the flushing done in the pageflip code will
1447          * result in deadlocks.
1448          */
1449         struct workqueue_struct *wq;
1450
1451         /* Display functions */
1452         struct drm_i915_display_funcs display;
1453
1454         /* PCH chipset type */
1455         enum intel_pch pch_type;
1456         unsigned short pch_id;
1457
1458         unsigned long quirks;
1459
1460         enum modeset_restore modeset_restore;
1461         struct mutex modeset_restore_lock;
1462
1463         struct list_head vm_list; /* Global list of all address spaces */
1464         struct i915_gtt gtt; /* VM representing the global address space */
1465
1466         struct i915_gem_mm mm;
1467 #if defined(CONFIG_MMU_NOTIFIER)
1468         DECLARE_HASHTABLE(mmu_notifiers, 7);
1469 #endif
1470
1471         /* Kernel Modesetting */
1472
1473         struct sdvo_device_mapping sdvo_mappings[2];
1474
1475         struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1476         struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1477         wait_queue_head_t pending_flip_queue;
1478
1479 #ifdef CONFIG_DEBUG_FS
1480         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1481 #endif
1482
1483         int num_shared_dpll;
1484         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1485         struct intel_ddi_plls ddi_plls;
1486         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1487
1488         /* Reclocking support */
1489         bool render_reclock_avail;
1490         bool lvds_downclock_avail;
1491         /* indicates the reduced downclock for LVDS*/
1492         int lvds_downclock;
1493
1494         struct i915_frontbuffer_tracking fb_tracking;
1495
1496         u16 orig_clock;
1497
1498         bool mchbar_need_disable;
1499
1500         struct intel_l3_parity l3_parity;
1501
1502         /* Cannot be determined by PCIID. You must always read a register. */
1503         size_t ellc_size;
1504
1505         /* gen6+ rps state */
1506         struct intel_gen6_power_mgmt rps;
1507
1508         /* ilk-only ips/rps state. Everything in here is protected by the global
1509          * mchdev_lock in intel_pm.c */
1510         struct intel_ilk_power_mgmt ips;
1511
1512         struct i915_power_domains power_domains;
1513
1514         struct i915_psr psr;
1515
1516         struct i915_gpu_error gpu_error;
1517
1518         struct drm_i915_gem_object *vlv_pctx;
1519
1520 #ifdef CONFIG_DRM_I915_FBDEV
1521         /* list of fbdev register on this device */
1522         struct intel_fbdev *fbdev;
1523 #endif
1524
1525         /*
1526          * The console may be contended at resume, but we don't
1527          * want it to block on it.
1528          */
1529         struct work_struct console_resume_work;
1530
1531         struct drm_property *broadcast_rgb_property;
1532         struct drm_property *force_audio_property;
1533
1534         uint32_t hw_context_size;
1535         struct list_head context_list;
1536
1537         u32 fdi_rx_config;
1538
1539         u32 suspend_count;
1540         struct i915_suspend_saved_registers regfile;
1541         struct vlv_s0ix_state vlv_s0ix_state;
1542
1543         struct {
1544                 /*
1545                  * Raw watermark latency values:
1546                  * in 0.1us units for WM0,
1547                  * in 0.5us units for WM1+.
1548                  */
1549                 /* primary */
1550                 uint16_t pri_latency[5];
1551                 /* sprite */
1552                 uint16_t spr_latency[5];
1553                 /* cursor */
1554                 uint16_t cur_latency[5];
1555
1556                 /* current hardware state */
1557                 struct ilk_wm_values hw;
1558         } wm;
1559
1560         struct i915_runtime_pm pm;
1561
1562         struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1563         u32 long_hpd_port_mask;
1564         u32 short_hpd_port_mask;
1565         struct work_struct dig_port_work;
1566
1567         /* Old dri1 support infrastructure, beware the dragons ya fools entering
1568          * here! */
1569         struct i915_dri1_state dri1;
1570         /* Old ums support infrastructure, same warning applies. */
1571         struct i915_ums_state ums;
1572
1573         /*
1574          * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1575          * will be rejected. Instead look for a better place.
1576          */
1577 };
1578
1579 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1580 {
1581         return dev->dev_private;
1582 }
1583
1584 /* Iterate over initialised rings */
1585 #define for_each_ring(ring__, dev_priv__, i__) \
1586         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1587                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1588
1589 enum hdmi_force_audio {
1590         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
1591         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
1592         HDMI_AUDIO_AUTO,                /* trust EDID */
1593         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
1594 };
1595
1596 #define I915_GTT_OFFSET_NONE ((u32)-1)
1597
1598 struct drm_i915_gem_object_ops {
1599         /* Interface between the GEM object and its backing storage.
1600          * get_pages() is called once prior to the use of the associated set
1601          * of pages before to binding them into the GTT, and put_pages() is
1602          * called after we no longer need them. As we expect there to be
1603          * associated cost with migrating pages between the backing storage
1604          * and making them available for the GPU (e.g. clflush), we may hold
1605          * onto the pages after they are no longer referenced by the GPU
1606          * in case they may be used again shortly (for example migrating the
1607          * pages to a different memory domain within the GTT). put_pages()
1608          * will therefore most likely be called when the object itself is
1609          * being released or under memory pressure (where we attempt to
1610          * reap pages for the shrinker).
1611          */
1612         int (*get_pages)(struct drm_i915_gem_object *);
1613         void (*put_pages)(struct drm_i915_gem_object *);
1614         int (*dmabuf_export)(struct drm_i915_gem_object *);
1615         void (*release)(struct drm_i915_gem_object *);
1616 };
1617
1618 /*
1619  * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1620  * considered to be the frontbuffer for the given plane interface-vise. This
1621  * doesn't mean that the hw necessarily already scans it out, but that any
1622  * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1623  *
1624  * We have one bit per pipe and per scanout plane type.
1625  */
1626 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1627 #define INTEL_FRONTBUFFER_BITS \
1628         (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1629 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1630         (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1631 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1632         (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1633 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1634         (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1635 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1636         (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1637 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1638         (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1639
1640 struct drm_i915_gem_object {
1641         struct drm_gem_object base;
1642
1643         const struct drm_i915_gem_object_ops *ops;
1644
1645         /** List of VMAs backed by this object */
1646         struct list_head vma_list;
1647
1648         /** Stolen memory for this object, instead of being backed by shmem. */
1649         struct drm_mm_node *stolen;
1650         struct list_head global_list;
1651
1652         struct list_head ring_list;
1653         /** Used in execbuf to temporarily hold a ref */
1654         struct list_head obj_exec_link;
1655
1656         /**
1657          * This is set if the object is on the active lists (has pending
1658          * rendering and so a non-zero seqno), and is not set if it i s on
1659          * inactive (ready to be unbound) list.
1660          */
1661         unsigned int active:1;
1662
1663         /**
1664          * This is set if the object has been written to since last bound
1665          * to the GTT
1666          */
1667         unsigned int dirty:1;
1668
1669         /**
1670          * Fence register bits (if any) for this object.  Will be set
1671          * as needed when mapped into the GTT.
1672          * Protected by dev->struct_mutex.
1673          */
1674         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1675
1676         /**
1677          * Advice: are the backing pages purgeable?
1678          */
1679         unsigned int madv:2;
1680
1681         /**
1682          * Current tiling mode for the object.
1683          */
1684         unsigned int tiling_mode:2;
1685         /**
1686          * Whether the tiling parameters for the currently associated fence
1687          * register have changed. Note that for the purposes of tracking
1688          * tiling changes we also treat the unfenced register, the register
1689          * slot that the object occupies whilst it executes a fenced
1690          * command (such as BLT on gen2/3), as a "fence".
1691          */
1692         unsigned int fence_dirty:1;
1693
1694         /**
1695          * Is the object at the current location in the gtt mappable and
1696          * fenceable? Used to avoid costly recalculations.
1697          */
1698         unsigned int map_and_fenceable:1;
1699
1700         /**
1701          * Whether the current gtt mapping needs to be mappable (and isn't just
1702          * mappable by accident). Track pin and fault separate for a more
1703          * accurate mappable working set.
1704          */
1705         unsigned int fault_mappable:1;
1706         unsigned int pin_mappable:1;
1707         unsigned int pin_display:1;
1708
1709         /*
1710          * Is the object to be mapped as read-only to the GPU
1711          * Only honoured if hardware has relevant pte bit
1712          */
1713         unsigned long gt_ro:1;
1714
1715         /*
1716          * Is the GPU currently using a fence to access this buffer,
1717          */
1718         unsigned int pending_fenced_gpu_access:1;
1719         unsigned int fenced_gpu_access:1;
1720
1721         unsigned int cache_level:3;
1722
1723         unsigned int has_aliasing_ppgtt_mapping:1;
1724         unsigned int has_global_gtt_mapping:1;
1725         unsigned int has_dma_mapping:1;
1726
1727         unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1728
1729         struct sg_table *pages;
1730         int pages_pin_count;
1731
1732         /* prime dma-buf support */
1733         void *dma_buf_vmapping;
1734         int vmapping_count;
1735
1736         struct intel_engine_cs *ring;
1737
1738         /** Breadcrumb of last rendering to the buffer. */
1739         uint32_t last_read_seqno;
1740         uint32_t last_write_seqno;
1741         /** Breadcrumb of last fenced GPU access to the buffer. */
1742         uint32_t last_fenced_seqno;
1743
1744         /** Current tiling stride for the object, if it's tiled. */
1745         uint32_t stride;
1746
1747         /** References from framebuffers, locks out tiling changes. */
1748         unsigned long framebuffer_references;
1749
1750         /** Record of address bit 17 of each page at last unbind. */
1751         unsigned long *bit_17;
1752
1753         /** User space pin count and filp owning the pin */
1754         unsigned long user_pin_count;
1755         struct drm_file *pin_filp;
1756
1757         /** for phy allocated objects */
1758         drm_dma_handle_t *phys_handle;
1759
1760         union {
1761                 struct i915_gem_userptr {
1762                         uintptr_t ptr;
1763                         unsigned read_only :1;
1764                         unsigned workers :4;
1765 #define I915_GEM_USERPTR_MAX_WORKERS 15
1766
1767                         struct mm_struct *mm;
1768                         struct i915_mmu_object *mn;
1769                         struct work_struct *work;
1770                 } userptr;
1771         };
1772 };
1773 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1774
1775 void i915_gem_track_fb(struct drm_i915_gem_object *old,
1776                        struct drm_i915_gem_object *new,
1777                        unsigned frontbuffer_bits);
1778
1779 /**
1780  * Request queue structure.
1781  *
1782  * The request queue allows us to note sequence numbers that have been emitted
1783  * and may be associated with active buffers to be retired.
1784  *
1785  * By keeping this list, we can avoid having to do questionable
1786  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1787  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1788  */
1789 struct drm_i915_gem_request {
1790         /** On Which ring this request was generated */
1791         struct intel_engine_cs *ring;
1792
1793         /** GEM sequence number associated with this request. */
1794         uint32_t seqno;
1795
1796         /** Position in the ringbuffer of the start of the request */
1797         u32 head;
1798
1799         /** Position in the ringbuffer of the end of the request */
1800         u32 tail;
1801
1802         /** Context related to this request */
1803         struct intel_context *ctx;
1804
1805         /** Batch buffer related to this request if any */
1806         struct drm_i915_gem_object *batch_obj;
1807
1808         /** Time at which this request was emitted, in jiffies. */
1809         unsigned long emitted_jiffies;
1810
1811         /** global list entry for this request */
1812         struct list_head list;
1813
1814         struct drm_i915_file_private *file_priv;
1815         /** file_priv list entry for this request */
1816         struct list_head client_list;
1817 };
1818
1819 struct drm_i915_file_private {
1820         struct drm_i915_private *dev_priv;
1821         struct drm_file *file;
1822
1823         struct {
1824                 spinlock_t lock;
1825                 struct list_head request_list;
1826                 struct delayed_work idle_work;
1827         } mm;
1828         struct idr context_idr;
1829
1830         atomic_t rps_wait_boost;
1831         struct  intel_engine_cs *bsd_ring;
1832 };
1833
1834 /*
1835  * A command that requires special handling by the command parser.
1836  */
1837 struct drm_i915_cmd_descriptor {
1838         /*
1839          * Flags describing how the command parser processes the command.
1840          *
1841          * CMD_DESC_FIXED: The command has a fixed length if this is set,
1842          *                 a length mask if not set
1843          * CMD_DESC_SKIP: The command is allowed but does not follow the
1844          *                standard length encoding for the opcode range in
1845          *                which it falls
1846          * CMD_DESC_REJECT: The command is never allowed
1847          * CMD_DESC_REGISTER: The command should be checked against the
1848          *                    register whitelist for the appropriate ring
1849          * CMD_DESC_MASTER: The command is allowed if the submitting process
1850          *                  is the DRM master
1851          */
1852         u32 flags;
1853 #define CMD_DESC_FIXED    (1<<0)
1854 #define CMD_DESC_SKIP     (1<<1)
1855 #define CMD_DESC_REJECT   (1<<2)
1856 #define CMD_DESC_REGISTER (1<<3)
1857 #define CMD_DESC_BITMASK  (1<<4)
1858 #define CMD_DESC_MASTER   (1<<5)
1859
1860         /*
1861          * The command's unique identification bits and the bitmask to get them.
1862          * This isn't strictly the opcode field as defined in the spec and may
1863          * also include type, subtype, and/or subop fields.
1864          */
1865         struct {
1866                 u32 value;
1867                 u32 mask;
1868         } cmd;
1869
1870         /*
1871          * The command's length. The command is either fixed length (i.e. does
1872          * not include a length field) or has a length field mask. The flag
1873          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1874          * a length mask. All command entries in a command table must include
1875          * length information.
1876          */
1877         union {
1878                 u32 fixed;
1879                 u32 mask;
1880         } length;
1881
1882         /*
1883          * Describes where to find a register address in the command to check
1884          * against the ring's register whitelist. Only valid if flags has the
1885          * CMD_DESC_REGISTER bit set.
1886          */
1887         struct {
1888                 u32 offset;
1889                 u32 mask;
1890         } reg;
1891
1892 #define MAX_CMD_DESC_BITMASKS 3
1893         /*
1894          * Describes command checks where a particular dword is masked and
1895          * compared against an expected value. If the command does not match
1896          * the expected value, the parser rejects it. Only valid if flags has
1897          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1898          * are valid.
1899          *
1900          * If the check specifies a non-zero condition_mask then the parser
1901          * only performs the check when the bits specified by condition_mask
1902          * are non-zero.
1903          */
1904         struct {
1905                 u32 offset;
1906                 u32 mask;
1907                 u32 expected;
1908                 u32 condition_offset;
1909                 u32 condition_mask;
1910         } bits[MAX_CMD_DESC_BITMASKS];
1911 };
1912
1913 /*
1914  * A table of commands requiring special handling by the command parser.
1915  *
1916  * Each ring has an array of tables. Each table consists of an array of command
1917  * descriptors, which must be sorted with command opcodes in ascending order.
1918  */
1919 struct drm_i915_cmd_table {
1920         const struct drm_i915_cmd_descriptor *table;
1921         int count;
1922 };
1923
1924 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1925
1926 #define IS_I830(dev)            ((dev)->pdev->device == 0x3577)
1927 #define IS_845G(dev)            ((dev)->pdev->device == 0x2562)
1928 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1929 #define IS_I865G(dev)           ((dev)->pdev->device == 0x2572)
1930 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1931 #define IS_I915GM(dev)          ((dev)->pdev->device == 0x2592)
1932 #define IS_I945G(dev)           ((dev)->pdev->device == 0x2772)
1933 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1934 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1935 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1936 #define IS_GM45(dev)            ((dev)->pdev->device == 0x2A42)
1937 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1938 #define IS_PINEVIEW_G(dev)      ((dev)->pdev->device == 0xa001)
1939 #define IS_PINEVIEW_M(dev)      ((dev)->pdev->device == 0xa011)
1940 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1941 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1942 #define IS_IRONLAKE_M(dev)      ((dev)->pdev->device == 0x0046)
1943 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1944 #define IS_IVB_GT1(dev)         ((dev)->pdev->device == 0x0156 || \
1945                                  (dev)->pdev->device == 0x0152 || \
1946                                  (dev)->pdev->device == 0x015a)
1947 #define IS_SNB_GT1(dev)         ((dev)->pdev->device == 0x0102 || \
1948                                  (dev)->pdev->device == 0x0106 || \
1949                                  (dev)->pdev->device == 0x010A)
1950 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1951 #define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1952 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1953 #define IS_BROADWELL(dev)       (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1954 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1955 #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
1956                                  ((dev)->pdev->device & 0xFF00) == 0x0C00)
1957 #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
1958                                  (((dev)->pdev->device & 0xf) == 0x2  || \
1959                                  ((dev)->pdev->device & 0xf) == 0x6 || \
1960                                  ((dev)->pdev->device & 0xf) == 0xe))
1961 #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
1962                                  ((dev)->pdev->device & 0xFF00) == 0x0A00)
1963 #define IS_ULT(dev)             (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1964 #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
1965                                  ((dev)->pdev->device & 0x00F0) == 0x0020)
1966 /* ULX machines are also considered ULT. */
1967 #define IS_HSW_ULX(dev)         ((dev)->pdev->device == 0x0A0E || \
1968                                  (dev)->pdev->device == 0x0A1E)
1969 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1970
1971 /*
1972  * The genX designation typically refers to the render engine, so render
1973  * capability related checks should use IS_GEN, while display and other checks
1974  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1975  * chips, etc.).
1976  */
1977 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1978 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1979 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1980 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1981 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1982 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1983 #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
1984
1985 #define RENDER_RING             (1<<RCS)
1986 #define BSD_RING                (1<<VCS)
1987 #define BLT_RING                (1<<BCS)
1988 #define VEBOX_RING              (1<<VECS)
1989 #define BSD2_RING               (1<<VCS2)
1990 #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
1991 #define HAS_BSD2(dev)           (INTEL_INFO(dev)->ring_mask & BSD2_RING)
1992 #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
1993 #define HAS_VEBOX(dev)          (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1994 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1995 #define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
1996                                  to_i915(dev)->ellc_size)
1997 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1998
1999 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
2000 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2001 #define HAS_PPGTT(dev)          (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2002 #define USES_PPGTT(dev)         intel_enable_ppgtt(dev, false)
2003 #define USES_FULL_PPGTT(dev)    intel_enable_ppgtt(dev, true)
2004
2005 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
2006 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
2007
2008 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2009 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
2010 /*
2011  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2012  * even when in MSI mode. This results in spurious interrupt warnings if the
2013  * legacy irq no. is shared with another device. The kernel then disables that
2014  * interrupt source and so prevents the other device from working properly.
2015  */
2016 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2017 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2018
2019 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2020  * rows, which changed the alignment requirements and fence programming.
2021  */
2022 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2023                                                       IS_I915GM(dev)))
2024 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2025 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
2026 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
2027 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
2028 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
2029
2030 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2031 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2032 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2033
2034 #define HAS_IPS(dev)            (IS_ULT(dev) || IS_BROADWELL(dev))
2035
2036 #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
2037 #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
2038 #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
2039 #define HAS_RUNTIME_PM(dev)     (IS_GEN6(dev) || IS_HASWELL(dev) || \
2040                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2041
2042 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
2043 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
2044 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
2045 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
2046 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
2047 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
2048
2049 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2050 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2051 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2052 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2053 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2054 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2055
2056 /* DPF == dynamic parity feature */
2057 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2058 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2059
2060 #define GT_FREQUENCY_MULTIPLIER 50
2061
2062 #include "i915_trace.h"
2063
2064 extern const struct drm_ioctl_desc i915_ioctls[];
2065 extern int i915_max_ioctl;
2066
2067 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2068 extern int i915_resume(struct drm_device *dev);
2069 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2070 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2071
2072 /* i915_params.c */
2073 struct i915_params {
2074         int modeset;
2075         int panel_ignore_lid;
2076         unsigned int powersave;
2077         int semaphores;
2078         unsigned int lvds_downclock;
2079         int lvds_channel_mode;
2080         int panel_use_ssc;
2081         int vbt_sdvo_panel_type;
2082         int enable_rc6;
2083         int enable_fbc;
2084         int enable_ppgtt;
2085         int enable_psr;
2086         unsigned int preliminary_hw_support;
2087         int disable_power_well;
2088         int enable_ips;
2089         int invert_brightness;
2090         int enable_cmd_parser;
2091         /* leave bools at the end to not create holes */
2092         bool enable_hangcheck;
2093         bool fastboot;
2094         bool prefault_disable;
2095         bool reset;
2096         bool disable_display;
2097         bool disable_vtd_wa;
2098         int use_mmio_flip;
2099 };
2100 extern struct i915_params i915 __read_mostly;
2101
2102                                 /* i915_dma.c */
2103 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2104 extern void i915_kernel_lost_context(struct drm_device * dev);
2105 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2106 extern int i915_driver_unload(struct drm_device *);
2107 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2108 extern void i915_driver_lastclose(struct drm_device * dev);
2109 extern void i915_driver_preclose(struct drm_device *dev,
2110                                  struct drm_file *file);
2111 extern void i915_driver_postclose(struct drm_device *dev,
2112                                   struct drm_file *file);
2113 extern int i915_driver_device_is_agp(struct drm_device * dev);
2114 #ifdef CONFIG_COMPAT
2115 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2116                               unsigned long arg);
2117 #endif
2118 extern int i915_emit_box(struct drm_device *dev,
2119                          struct drm_clip_rect *box,
2120                          int DR1, int DR4);
2121 extern int intel_gpu_reset(struct drm_device *dev);
2122 extern int i915_reset(struct drm_device *dev);
2123 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2124 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2125 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2126 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2127 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2128
2129 extern void intel_console_resume(struct work_struct *work);
2130
2131 /* i915_irq.c */
2132 void i915_queue_hangcheck(struct drm_device *dev);
2133 __printf(3, 4)
2134 void i915_handle_error(struct drm_device *dev, bool wedged,
2135                        const char *fmt, ...);
2136
2137 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2138                                                         int new_delay);
2139 extern void intel_irq_init(struct drm_device *dev);
2140 extern void intel_hpd_init(struct drm_device *dev);
2141
2142 extern void intel_uncore_sanitize(struct drm_device *dev);
2143 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2144                                         bool restore_forcewake);
2145 extern void intel_uncore_init(struct drm_device *dev);
2146 extern void intel_uncore_check_errors(struct drm_device *dev);
2147 extern void intel_uncore_fini(struct drm_device *dev);
2148 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2149
2150 void
2151 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2152                      u32 status_mask);
2153
2154 void
2155 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2156                       u32 status_mask);
2157
2158 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2159 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2160
2161 /* i915_gem.c */
2162 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2163                         struct drm_file *file_priv);
2164 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2165                           struct drm_file *file_priv);
2166 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2167                          struct drm_file *file_priv);
2168 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2169                           struct drm_file *file_priv);
2170 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2171                         struct drm_file *file_priv);
2172 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2173                         struct drm_file *file_priv);
2174 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2175                               struct drm_file *file_priv);
2176 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2177                              struct drm_file *file_priv);
2178 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2179                         struct drm_file *file_priv);
2180 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2181                          struct drm_file *file_priv);
2182 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2183                        struct drm_file *file_priv);
2184 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2185                          struct drm_file *file_priv);
2186 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2187                         struct drm_file *file_priv);
2188 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2189                                struct drm_file *file);
2190 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2191                                struct drm_file *file);
2192 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2193                             struct drm_file *file_priv);
2194 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2195                            struct drm_file *file_priv);
2196 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2197                            struct drm_file *file_priv);
2198 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2199                            struct drm_file *file_priv);
2200 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2201                         struct drm_file *file_priv);
2202 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2203                         struct drm_file *file_priv);
2204 int i915_gem_init_userptr(struct drm_device *dev);
2205 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2206                            struct drm_file *file);
2207 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2208                                 struct drm_file *file_priv);
2209 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2210                         struct drm_file *file_priv);
2211 void i915_gem_load(struct drm_device *dev);
2212 void *i915_gem_object_alloc(struct drm_device *dev);
2213 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2214 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2215                          const struct drm_i915_gem_object_ops *ops);
2216 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2217                                                   size_t size);
2218 void i915_init_vm(struct drm_i915_private *dev_priv,
2219                   struct i915_address_space *vm);
2220 void i915_gem_free_object(struct drm_gem_object *obj);
2221 void i915_gem_vma_destroy(struct i915_vma *vma);
2222
2223 #define PIN_MAPPABLE 0x1
2224 #define PIN_NONBLOCK 0x2
2225 #define PIN_GLOBAL 0x4
2226 #define PIN_OFFSET_BIAS 0x8
2227 #define PIN_OFFSET_MASK (~4095)
2228 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2229                                      struct i915_address_space *vm,
2230                                      uint32_t alignment,
2231                                      uint64_t flags);
2232 int __must_check i915_vma_unbind(struct i915_vma *vma);
2233 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2234 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2235 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2236 void i915_gem_lastclose(struct drm_device *dev);
2237
2238 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2239                                     int *needs_clflush);
2240
2241 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2242 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2243 {
2244         struct sg_page_iter sg_iter;
2245
2246         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2247                 return sg_page_iter_page(&sg_iter);
2248
2249         return NULL;
2250 }
2251 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2252 {
2253         BUG_ON(obj->pages == NULL);
2254         obj->pages_pin_count++;
2255 }
2256 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2257 {
2258         BUG_ON(obj->pages_pin_count == 0);
2259         obj->pages_pin_count--;
2260 }
2261
2262 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2263 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2264                          struct intel_engine_cs *to);
2265 void i915_vma_move_to_active(struct i915_vma *vma,
2266                              struct intel_engine_cs *ring);
2267 int i915_gem_dumb_create(struct drm_file *file_priv,
2268                          struct drm_device *dev,
2269                          struct drm_mode_create_dumb *args);
2270 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2271                       uint32_t handle, uint64_t *offset);
2272 /**
2273  * Returns true if seq1 is later than seq2.
2274  */
2275 static inline bool
2276 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2277 {
2278         return (int32_t)(seq1 - seq2) >= 0;
2279 }
2280
2281 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2282 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2283 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2284 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2285
2286 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2287 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2288
2289 struct drm_i915_gem_request *
2290 i915_gem_find_active_request(struct intel_engine_cs *ring);
2291
2292 bool i915_gem_retire_requests(struct drm_device *dev);
2293 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2294 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2295                                       bool interruptible);
2296 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2297
2298 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2299 {
2300         return unlikely(atomic_read(&error->reset_counter)
2301                         & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2302 }
2303
2304 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2305 {
2306         return atomic_read(&error->reset_counter) & I915_WEDGED;
2307 }
2308
2309 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2310 {
2311         return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2312 }
2313
2314 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2315 {
2316         return dev_priv->gpu_error.stop_rings == 0 ||
2317                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2318 }
2319
2320 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2321 {
2322         return dev_priv->gpu_error.stop_rings == 0 ||
2323                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2324 }
2325
2326 void i915_gem_reset(struct drm_device *dev);
2327 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2328 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2329 int __must_check i915_gem_init(struct drm_device *dev);
2330 int __must_check i915_gem_init_hw(struct drm_device *dev);
2331 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2332 void i915_gem_init_swizzling(struct drm_device *dev);
2333 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2334 int __must_check i915_gpu_idle(struct drm_device *dev);
2335 int __must_check i915_gem_suspend(struct drm_device *dev);
2336 int __i915_add_request(struct intel_engine_cs *ring,
2337                        struct drm_file *file,
2338                        struct drm_i915_gem_object *batch_obj,
2339                        u32 *seqno);
2340 #define i915_add_request(ring, seqno) \
2341         __i915_add_request(ring, NULL, NULL, seqno)
2342 int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2343                                  uint32_t seqno);
2344 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2345 int __must_check
2346 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2347                                   bool write);
2348 int __must_check
2349 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2350 int __must_check
2351 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2352                                      u32 alignment,
2353                                      struct intel_engine_cs *pipelined);
2354 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2355 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2356                                 int align);
2357 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2358 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2359
2360 uint32_t
2361 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2362 uint32_t
2363 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2364                             int tiling_mode, bool fenced);
2365
2366 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2367                                     enum i915_cache_level cache_level);
2368
2369 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2370                                 struct dma_buf *dma_buf);
2371
2372 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2373                                 struct drm_gem_object *gem_obj, int flags);
2374
2375 void i915_gem_restore_fences(struct drm_device *dev);
2376
2377 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2378                                   struct i915_address_space *vm);
2379 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2380 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2381                         struct i915_address_space *vm);
2382 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2383                                 struct i915_address_space *vm);
2384 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2385                                      struct i915_address_space *vm);
2386 struct i915_vma *
2387 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2388                                   struct i915_address_space *vm);
2389
2390 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2391 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2392         struct i915_vma *vma;
2393         list_for_each_entry(vma, &obj->vma_list, vma_link)
2394                 if (vma->pin_count > 0)
2395                         return true;
2396         return false;
2397 }
2398
2399 /* Some GGTT VM helpers */
2400 #define obj_to_ggtt(obj) \
2401         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2402 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2403 {
2404         struct i915_address_space *ggtt =
2405                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2406         return vm == ggtt;
2407 }
2408
2409 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2410 {
2411         return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2412 }
2413
2414 static inline unsigned long
2415 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2416 {
2417         return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2418 }
2419
2420 static inline unsigned long
2421 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2422 {
2423         return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2424 }
2425
2426 static inline int __must_check
2427 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2428                       uint32_t alignment,
2429                       unsigned flags)
2430 {
2431         return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2432 }
2433
2434 static inline int
2435 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2436 {
2437         return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2438 }
2439
2440 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2441
2442 /* i915_gem_context.c */
2443 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2444 int __must_check i915_gem_context_init(struct drm_device *dev);
2445 void i915_gem_context_fini(struct drm_device *dev);
2446 void i915_gem_context_reset(struct drm_device *dev);
2447 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2448 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2449 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2450 int i915_switch_context(struct intel_engine_cs *ring,
2451                         struct intel_context *to);
2452 struct intel_context *
2453 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2454 void i915_gem_context_free(struct kref *ctx_ref);
2455 static inline void i915_gem_context_reference(struct intel_context *ctx)
2456 {
2457         kref_get(&ctx->ref);
2458 }
2459
2460 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2461 {
2462         kref_put(&ctx->ref, i915_gem_context_free);
2463 }
2464
2465 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2466 {
2467         return c->id == DEFAULT_CONTEXT_ID;
2468 }
2469
2470 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2471                                   struct drm_file *file);
2472 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2473                                    struct drm_file *file);
2474
2475 /* i915_gem_render_state.c */
2476 int i915_gem_render_state_init(struct intel_engine_cs *ring);
2477 /* i915_gem_evict.c */
2478 int __must_check i915_gem_evict_something(struct drm_device *dev,
2479                                           struct i915_address_space *vm,
2480                                           int min_size,
2481                                           unsigned alignment,
2482                                           unsigned cache_level,
2483                                           unsigned long start,
2484                                           unsigned long end,
2485                                           unsigned flags);
2486 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2487 int i915_gem_evict_everything(struct drm_device *dev);
2488
2489 /* belongs in i915_gem_gtt.h */
2490 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2491 {
2492         if (INTEL_INFO(dev)->gen < 6)
2493                 intel_gtt_chipset_flush();
2494 }
2495
2496 /* i915_gem_stolen.c */
2497 int i915_gem_init_stolen(struct drm_device *dev);
2498 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2499 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2500 void i915_gem_cleanup_stolen(struct drm_device *dev);
2501 struct drm_i915_gem_object *
2502 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2503 struct drm_i915_gem_object *
2504 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2505                                                u32 stolen_offset,
2506                                                u32 gtt_offset,
2507                                                u32 size);
2508
2509 /* i915_gem_tiling.c */
2510 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2511 {
2512         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2513
2514         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2515                 obj->tiling_mode != I915_TILING_NONE;
2516 }
2517
2518 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2519 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2520 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2521
2522 /* i915_gem_debug.c */
2523 #if WATCH_LISTS
2524 int i915_verify_lists(struct drm_device *dev);
2525 #else
2526 #define i915_verify_lists(dev) 0
2527 #endif
2528
2529 /* i915_debugfs.c */
2530 int i915_debugfs_init(struct drm_minor *minor);
2531 void i915_debugfs_cleanup(struct drm_minor *minor);
2532 #ifdef CONFIG_DEBUG_FS
2533 void intel_display_crc_init(struct drm_device *dev);
2534 #else
2535 static inline void intel_display_crc_init(struct drm_device *dev) {}
2536 #endif
2537
2538 /* i915_gpu_error.c */
2539 __printf(2, 3)
2540 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2541 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2542                             const struct i915_error_state_file_priv *error);
2543 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2544                               size_t count, loff_t pos);
2545 static inline void i915_error_state_buf_release(
2546         struct drm_i915_error_state_buf *eb)
2547 {
2548         kfree(eb->buf);
2549 }
2550 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2551                               const char *error_msg);
2552 void i915_error_state_get(struct drm_device *dev,
2553                           struct i915_error_state_file_priv *error_priv);
2554 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2555 void i915_destroy_error_state(struct drm_device *dev);
2556
2557 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2558 const char *i915_cache_level_str(int type);
2559
2560 /* i915_cmd_parser.c */
2561 int i915_cmd_parser_get_version(void);
2562 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2563 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2564 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2565 int i915_parse_cmds(struct intel_engine_cs *ring,
2566                     struct drm_i915_gem_object *batch_obj,
2567                     u32 batch_start_offset,
2568                     bool is_master);
2569
2570 /* i915_suspend.c */
2571 extern int i915_save_state(struct drm_device *dev);
2572 extern int i915_restore_state(struct drm_device *dev);
2573
2574 /* i915_ums.c */
2575 void i915_save_display_reg(struct drm_device *dev);
2576 void i915_restore_display_reg(struct drm_device *dev);
2577
2578 /* i915_sysfs.c */
2579 void i915_setup_sysfs(struct drm_device *dev_priv);
2580 void i915_teardown_sysfs(struct drm_device *dev_priv);
2581
2582 /* intel_i2c.c */
2583 extern int intel_setup_gmbus(struct drm_device *dev);
2584 extern void intel_teardown_gmbus(struct drm_device *dev);
2585 static inline bool intel_gmbus_is_port_valid(unsigned port)
2586 {
2587         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2588 }
2589
2590 extern struct i2c_adapter *intel_gmbus_get_adapter(
2591                 struct drm_i915_private *dev_priv, unsigned port);
2592 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2593 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2594 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2595 {
2596         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2597 }
2598 extern void intel_i2c_reset(struct drm_device *dev);
2599
2600 /* intel_opregion.c */
2601 struct intel_encoder;
2602 #ifdef CONFIG_ACPI
2603 extern int intel_opregion_setup(struct drm_device *dev);
2604 extern void intel_opregion_init(struct drm_device *dev);
2605 extern void intel_opregion_fini(struct drm_device *dev);
2606 extern void intel_opregion_asle_intr(struct drm_device *dev);
2607 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2608                                          bool enable);
2609 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2610                                          pci_power_t state);
2611 #else
2612 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2613 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2614 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2615 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2616 static inline int
2617 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2618 {
2619         return 0;
2620 }
2621 static inline int
2622 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2623 {
2624         return 0;
2625 }
2626 #endif
2627
2628 /* intel_acpi.c */
2629 #ifdef CONFIG_ACPI
2630 extern void intel_register_dsm_handler(void);
2631 extern void intel_unregister_dsm_handler(void);
2632 #else
2633 static inline void intel_register_dsm_handler(void) { return; }
2634 static inline void intel_unregister_dsm_handler(void) { return; }
2635 #endif /* CONFIG_ACPI */
2636
2637 /* modesetting */
2638 extern void intel_modeset_init_hw(struct drm_device *dev);
2639 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2640 extern void intel_modeset_init(struct drm_device *dev);
2641 extern void intel_modeset_gem_init(struct drm_device *dev);
2642 extern void intel_modeset_cleanup(struct drm_device *dev);
2643 extern void intel_connector_unregister(struct intel_connector *);
2644 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2645 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2646                                          bool force_restore);
2647 extern void i915_redisable_vga(struct drm_device *dev);
2648 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2649 extern bool intel_fbc_enabled(struct drm_device *dev);
2650 extern void intel_disable_fbc(struct drm_device *dev);
2651 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2652 extern void intel_init_pch_refclk(struct drm_device *dev);
2653 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2654 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2655 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2656 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2657 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2658                                   bool enable);
2659 extern void intel_detect_pch(struct drm_device *dev);
2660 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2661 extern int intel_enable_rc6(const struct drm_device *dev);
2662
2663 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2664 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2665                         struct drm_file *file);
2666 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2667                                struct drm_file *file);
2668
2669 void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2670
2671 /* overlay */
2672 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2673 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2674                                             struct intel_overlay_error_state *error);
2675
2676 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2677 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2678                                             struct drm_device *dev,
2679                                             struct intel_display_error_state *error);
2680
2681 /* On SNB platform, before reading ring registers forcewake bit
2682  * must be set to prevent GT core from power down and stale values being
2683  * returned.
2684  */
2685 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2686 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2687 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2688
2689 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2690 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2691
2692 /* intel_sideband.c */
2693 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2694 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2695 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2696 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2697 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2698 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2699 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2700 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2701 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2702 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2703 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2704 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2705 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2706 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2707 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2708 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2709                    enum intel_sbi_destination destination);
2710 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2711                      enum intel_sbi_destination destination);
2712 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2713 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2714
2715 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2716 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2717
2718 #define FORCEWAKE_RENDER        (1 << 0)
2719 #define FORCEWAKE_MEDIA         (1 << 1)
2720 #define FORCEWAKE_ALL           (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2721
2722
2723 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2724 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2725
2726 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2727 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2728 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2729 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2730
2731 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2732 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2733 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2734 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2735
2736 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2737  * will be implemented using 2 32-bit writes in an arbitrary order with
2738  * an arbitrary delay between them. This can cause the hardware to
2739  * act upon the intermediate value, possibly leading to corruption and
2740  * machine death. You have been warned.
2741  */
2742 #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2743 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2744
2745 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
2746                 u32 upper = I915_READ(upper_reg);                       \
2747                 u32 lower = I915_READ(lower_reg);                       \
2748                 u32 tmp = I915_READ(upper_reg);                         \
2749                 if (upper != tmp) {                                     \
2750                         upper = tmp;                                    \
2751                         lower = I915_READ(lower_reg);                   \
2752                         WARN_ON(I915_READ(upper_reg) != upper);         \
2753                 }                                                       \
2754                 (u64)upper << 32 | lower; })
2755
2756 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
2757 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
2758
2759 /* "Broadcast RGB" property */
2760 #define INTEL_BROADCAST_RGB_AUTO 0
2761 #define INTEL_BROADCAST_RGB_FULL 1
2762 #define INTEL_BROADCAST_RGB_LIMITED 2
2763
2764 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2765 {
2766         if (HAS_PCH_SPLIT(dev))
2767                 return CPU_VGACNTRL;
2768         else if (IS_VALLEYVIEW(dev))
2769                 return VLV_VGACNTRL;
2770         else
2771                 return VGACNTRL;
2772 }
2773
2774 static inline void __user *to_user_ptr(u64 address)
2775 {
2776         return (void __user *)(uintptr_t)address;
2777 }
2778
2779 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2780 {
2781         unsigned long j = msecs_to_jiffies(m);
2782
2783         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2784 }
2785
2786 static inline unsigned long
2787 timespec_to_jiffies_timeout(const struct timespec *value)
2788 {
2789         unsigned long j = timespec_to_jiffies(value);
2790
2791         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2792 }
2793
2794 /*
2795  * If you need to wait X milliseconds between events A and B, but event B
2796  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2797  * when event A happened, then just before event B you call this function and
2798  * pass the timestamp as the first argument, and X as the second argument.
2799  */
2800 static inline void
2801 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2802 {
2803         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2804
2805         /*
2806          * Don't re-read the value of "jiffies" every time since it may change
2807          * behind our back and break the math.
2808          */
2809         tmp_jiffies = jiffies;
2810         target_jiffies = timestamp_jiffies +
2811                          msecs_to_jiffies_timeout(to_wait_ms);
2812
2813         if (time_after(target_jiffies, tmp_jiffies)) {
2814                 remaining_jiffies = target_jiffies - tmp_jiffies;
2815                 while (remaining_jiffies)
2816                         remaining_jiffies =
2817                             schedule_timeout_uninterruptible(remaining_jiffies);
2818         }
2819 }
2820
2821 #endif