drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <linux/i2c-algo-bit.h>
  39 #include <drm/intel-gtt.h>
  40 #include <linux/backlight.h>
  41 #include <linux/intel-iommu.h>
  42
  43 /* General customization:
  44  */
  45
  46 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  47
  48 #define DRIVER_NAME             "i915"
  49 #define DRIVER_DESC             "Intel Graphics"
  50 #define DRIVER_DATE             "20080730"
  51
  52 enum pipe {
  53         PIPE_A = 0,
  54         PIPE_B,
  55         PIPE_C,
  56         I915_MAX_PIPES
  57 };
  58 #define pipe_name(p) ((p) + 'A')
  59
  60 enum plane {
  61         PLANE_A = 0,
  62         PLANE_B,
  63         PLANE_C,
  64 };
  65 #define plane_name(p) ((p) + 'A')
  66
  67 enum port {
  68         PORT_A = 0,
  69         PORT_B,
  70         PORT_C,
  71         PORT_D,
  72         PORT_E,
  73         I915_MAX_PORTS
  74 };
  75 #define port_name(p) ((p) + 'A')
  76
  77 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  78
  79 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  80
  81 struct intel_pch_pll {
  82         int refcount; /* count of number of CRTCs sharing this PLL */
  83         int active; /* count of number of active CRTCs (i.e. DPMS on) */
  84         bool on; /* is the PLL actually active? Disabled during modeset */
  85         int pll_reg;
  86         int fp0_reg;
  87         int fp1_reg;
  88 };
  89 #define I915_NUM_PLLS 2
  90
  91 /* Interface history:
  92  *
  93  * 1.1: Original.
  94  * 1.2: Add Power Management
  95  * 1.3: Add vblank support
  96  * 1.4: Fix cmdbuffer path, add heap destroy
  97  * 1.5: Add vblank pipe configuration
  98  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  99  *      - Support vertical blank on secondary display pipe
 100  */
 101 #define DRIVER_MAJOR            1
 102 #define DRIVER_MINOR            6
 103 #define DRIVER_PATCHLEVEL       0
 104
 105 #define WATCH_COHERENCY 0
 106 #define WATCH_LISTS     0
 107
 108 #define I915_GEM_PHYS_CURSOR_0 1
 109 #define I915_GEM_PHYS_CURSOR_1 2
 110 #define I915_GEM_PHYS_OVERLAY_REGS 3
 111 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 112
 113 struct drm_i915_gem_phys_object {
 114         int id;
 115         struct page **page_list;
 116         drm_dma_handle_t *handle;
 117         struct drm_i915_gem_object *cur_obj;
 118 };
 119
 120 struct mem_block {
 121         struct mem_block *next;
 122         struct mem_block *prev;
 123         int start;
 124         int size;
 125         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 126 };
 127
 128 struct opregion_header;
 129 struct opregion_acpi;
 130 struct opregion_swsci;
 131 struct opregion_asle;
 132 struct drm_i915_private;
 133
 134 struct intel_opregion {
 135         struct opregion_header __iomem *header;
 136         struct opregion_acpi __iomem *acpi;
 137         struct opregion_swsci __iomem *swsci;
 138         struct opregion_asle __iomem *asle;
 139         void __iomem *vbt;
 140         u32 __iomem *lid_state;
 141 };
 142 #define OPREGION_SIZE            (8*1024)
 143
 144 struct intel_overlay;
 145 struct intel_overlay_error_state;
 146
 147 struct drm_i915_master_private {
 148         drm_local_map_t *sarea;
 149         struct _drm_i915_sarea *sarea_priv;
 150 };
 151 #define I915_FENCE_REG_NONE -1
 152 #define I915_MAX_NUM_FENCES 16
 153 /* 16 fences + sign bit for FENCE_REG_NONE */
 154 #define I915_MAX_NUM_FENCE_BITS 5
 155
 156 struct drm_i915_fence_reg {
 157         struct list_head lru_list;
 158         struct drm_i915_gem_object *obj;
 159         int pin_count;
 160 };
 161
 162 struct sdvo_device_mapping {
 163         u8 initialized;
 164         u8 dvo_port;
 165         u8 slave_addr;
 166         u8 dvo_wiring;
 167         u8 i2c_pin;
 168         u8 ddc_pin;
 169 };
 170
 171 struct intel_display_error_state;
 172
 173 struct drm_i915_error_state {
 174         u32 eir;
 175         u32 pgtbl_er;
 176         u32 pipestat[I915_MAX_PIPES];
 177         u32 tail[I915_NUM_RINGS];
 178         u32 head[I915_NUM_RINGS];
 179         u32 ipeir[I915_NUM_RINGS];
 180         u32 ipehr[I915_NUM_RINGS];
 181         u32 instdone[I915_NUM_RINGS];
 182         u32 acthd[I915_NUM_RINGS];
 183         u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
 184         /* our own tracking of ring head and tail */
 185         u32 cpu_ring_head[I915_NUM_RINGS];
 186         u32 cpu_ring_tail[I915_NUM_RINGS];
 187         u32 error; /* gen6+ */
 188         u32 instpm[I915_NUM_RINGS];
 189         u32 instps[I915_NUM_RINGS];
 190         u32 instdone1;
 191         u32 seqno[I915_NUM_RINGS];
 192         u64 bbaddr;
 193         u32 fault_reg[I915_NUM_RINGS];
 194         u32 done_reg;
 195         u32 faddr[I915_NUM_RINGS];
 196         u64 fence[I915_MAX_NUM_FENCES];
 197         struct timeval time;
 198         struct drm_i915_error_ring {
 199                 struct drm_i915_error_object {
 200                         int page_count;
 201                         u32 gtt_offset;
 202                         u32 *pages[0];
 203                 } *ringbuffer, *batchbuffer;
 204                 struct drm_i915_error_request {
 205                         long jiffies;
 206                         u32 seqno;
 207                         u32 tail;
 208                 } *requests;
 209                 int num_requests;
 210         } ring[I915_NUM_RINGS];
 211         struct drm_i915_error_buffer {
 212                 u32 size;
 213                 u32 name;
 214                 u32 seqno;
 215                 u32 gtt_offset;
 216                 u32 read_domains;
 217                 u32 write_domain;
 218                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 219                 s32 pinned:2;
 220                 u32 tiling:2;
 221                 u32 dirty:1;
 222                 u32 purgeable:1;
 223                 s32 ring:4;
 224                 u32 cache_level:2;
 225         } *active_bo, *pinned_bo;
 226         u32 active_bo_count, pinned_bo_count;
 227         struct intel_overlay_error_state *overlay;
 228         struct intel_display_error_state *display;
 229 };
 230
 231 struct drm_i915_display_funcs {
 232         void (*dpms)(struct drm_crtc *crtc, int mode);
 233         bool (*fbc_enabled)(struct drm_device *dev);
 234         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 235         void (*disable_fbc)(struct drm_device *dev);
 236         int (*get_display_clock_speed)(struct drm_device *dev);
 237         int (*get_fifo_size)(struct drm_device *dev, int plane);
 238         void (*update_wm)(struct drm_device *dev);
 239         void (*update_sprite_wm)(struct drm_device *dev, int pipe,
 240                                  uint32_t sprite_width, int pixel_size);
 241         int (*crtc_mode_set)(struct drm_crtc *crtc,
 242                              struct drm_display_mode *mode,
 243                              struct drm_display_mode *adjusted_mode,
 244                              int x, int y,
 245                              struct drm_framebuffer *old_fb);
 246         void (*off)(struct drm_crtc *crtc);
 247         void (*write_eld)(struct drm_connector *connector,
 248                           struct drm_crtc *crtc);
 249         void (*fdi_link_train)(struct drm_crtc *crtc);
 250         void (*init_clock_gating)(struct drm_device *dev);
 251         void (*init_pch_clock_gating)(struct drm_device *dev);
 252         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 253                           struct drm_framebuffer *fb,
 254                           struct drm_i915_gem_object *obj);
 255         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 256                             int x, int y);
 257         void (*force_wake_get)(struct drm_i915_private *dev_priv);
 258         void (*force_wake_put)(struct drm_i915_private *dev_priv);
 259         /* clock updates for mode set */
 260         /* cursor updates */
 261         /* render clock increase/decrease */
 262         /* display clock increase/decrease */
 263         /* pll clock increase/decrease */
 264 };
 265
 266 struct intel_device_info {
 267         u8 gen;
 268         u8 is_mobile:1;
 269         u8 is_i85x:1;
 270         u8 is_i915g:1;
 271         u8 is_i945gm:1;
 272         u8 is_g33:1;
 273         u8 need_gfx_hws:1;
 274         u8 is_g4x:1;
 275         u8 is_pineview:1;
 276         u8 is_broadwater:1;
 277         u8 is_crestline:1;
 278         u8 is_ivybridge:1;
 279         u8 is_valleyview:1;
 280         u8 has_pch_split:1;
 281         u8 is_haswell:1;
 282         u8 has_fbc:1;
 283         u8 has_pipe_cxsr:1;
 284         u8 has_hotplug:1;
 285         u8 cursor_needs_physical:1;
 286         u8 has_overlay:1;
 287         u8 overlay_needs_physical:1;
 288         u8 supports_tv:1;
 289         u8 has_bsd_ring:1;
 290         u8 has_blt_ring:1;
 291         u8 has_llc:1;
 292 };
 293
 294 #define I915_PPGTT_PD_ENTRIES 512
 295 #define I915_PPGTT_PT_ENTRIES 1024
 296 struct i915_hw_ppgtt {
 297         unsigned num_pd_entries;
 298         struct page **pt_pages;
 299         uint32_t pd_offset;
 300         dma_addr_t *pt_dma_addr;
 301         dma_addr_t scratch_page_dma_addr;
 302 };
 303
 304 enum no_fbc_reason {
 305         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 306         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 307         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 308         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 309         FBC_BAD_PLANE, /* fbc not supported on plane */
 310         FBC_NOT_TILED, /* buffer not tiled */
 311         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 312         FBC_MODULE_PARAM,
 313 };
 314
 315 enum intel_pch {
 316         PCH_IBX,        /* Ibexpeak PCH */
 317         PCH_CPT,        /* Cougarpoint PCH */
 318         PCH_LPT,        /* Lynxpoint PCH */
 319 };
 320
 321 #define QUIRK_PIPEA_FORCE (1<<0)
 322 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 323 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 324
 325 struct intel_fbdev;
 326 struct intel_fbc_work;
 327
 328 struct intel_gmbus {
 329         struct i2c_adapter adapter;
 330         bool force_bit;
 331         u32 reg0;
 332         u32 gpio_reg;
 333         struct i2c_algo_bit_data bit_algo;
 334         struct drm_i915_private *dev_priv;
 335 };
 336
 337 typedef struct drm_i915_private {
 338         struct drm_device *dev;
 339
 340         const struct intel_device_info *info;
 341
 342         int relative_constants_mode;
 343
 344         void __iomem *regs;
 345         /** gt_fifo_count and the subsequent register write are synchronized
 346          * with dev->struct_mutex. */
 347         unsigned gt_fifo_count;
 348         /** forcewake_count is protected by gt_lock */
 349         unsigned forcewake_count;
 350         /** gt_lock is also taken in irq contexts. */
 351         struct spinlock gt_lock;
 352
 353         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
 354
 355         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
 356          * controller on different i2c buses. */
 357         struct mutex gmbus_mutex;
 358
 359         /**
 360          * Base address of the gmbus and gpio block.
 361          */
 362         uint32_t gpio_mmio_base;
 363
 364         struct pci_dev *bridge_dev;
 365         struct intel_ring_buffer ring[I915_NUM_RINGS];
 366         uint32_t next_seqno;
 367
 368         drm_dma_handle_t *status_page_dmah;
 369         uint32_t counter;
 370         drm_local_map_t hws_map;
 371         struct drm_i915_gem_object *pwrctx;
 372         struct drm_i915_gem_object *renderctx;
 373
 374         struct resource mch_res;
 375
 376         unsigned int cpp;
 377         int back_offset;
 378         int front_offset;
 379         int current_page;
 380         int page_flipping;
 381
 382         atomic_t irq_received;
 383
 384         /* protects the irq masks */
 385         spinlock_t irq_lock;
 386
 387         /* DPIO indirect register protection */
 388         spinlock_t dpio_lock;
 389
 390         /** Cached value of IMR to avoid reads in updating the bitfield */
 391         u32 pipestat[2];
 392         u32 irq_mask;
 393         u32 gt_irq_mask;
 394         u32 pch_irq_mask;
 395
 396         u32 hotplug_supported_mask;
 397         struct work_struct hotplug_work;
 398
 399         int tex_lru_log_granularity;
 400         int allow_batchbuffer;
 401         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 402         int vblank_pipe;
 403         int num_pipe;
 404         int num_pch_pll;
 405
 406         /* For hangcheck timer */
 407 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 408         struct timer_list hangcheck_timer;
 409         int hangcheck_count;
 410         uint32_t last_acthd;
 411         uint32_t last_acthd_bsd;
 412         uint32_t last_acthd_blt;
 413         uint32_t last_instdone;
 414         uint32_t last_instdone1;
 415
 416         unsigned long cfb_size;
 417         unsigned int cfb_fb;
 418         enum plane cfb_plane;
 419         int cfb_y;
 420         struct intel_fbc_work *fbc_work;
 421
 422         struct intel_opregion opregion;
 423
 424         /* overlay */
 425         struct intel_overlay *overlay;
 426         bool sprite_scaling_enabled;
 427
 428         /* LVDS info */
 429         int backlight_level;  /* restore backlight to this value */
 430         bool backlight_enabled;
 431         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 432         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 433
 434         /* Feature bits from the VBIOS */
 435         unsigned int int_tv_support:1;
 436         unsigned int lvds_dither:1;
 437         unsigned int lvds_vbt:1;
 438         unsigned int int_crt_support:1;
 439         unsigned int lvds_use_ssc:1;
 440         unsigned int display_clock_mode:1;
 441         int lvds_ssc_freq;
 442         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
 443         unsigned int lvds_val; /* used for checking LVDS channel mode */
 444         struct {
 445                 int rate;
 446                 int lanes;
 447                 int preemphasis;
 448                 int vswing;
 449
 450                 bool initialized;
 451                 bool support;
 452                 int bpp;
 453                 struct edp_power_seq pps;
 454         } edp;
 455         bool no_aux_handshake;
 456
 457         struct notifier_block lid_notifier;
 458
 459         int crt_ddc_pin;
 460         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
 461         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 462         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 463
 464         unsigned int fsb_freq, mem_freq, is_ddr3;
 465
 466         spinlock_t error_lock;
 467         struct drm_i915_error_state *first_error;
 468         struct work_struct error_work;
 469         struct completion error_completion;
 470         struct workqueue_struct *wq;
 471
 472         /* Display functions */
 473         struct drm_i915_display_funcs display;
 474
 475         /* PCH chipset type */
 476         enum intel_pch pch_type;
 477
 478         unsigned long quirks;
 479
 480         /* Register state */
 481         bool modeset_on_lid;
 482         u8 saveLBB;
 483         u32 saveDSPACNTR;
 484         u32 saveDSPBCNTR;
 485         u32 saveDSPARB;
 486         u32 saveHWS;
 487         u32 savePIPEACONF;
 488         u32 savePIPEBCONF;
 489         u32 savePIPEASRC;
 490         u32 savePIPEBSRC;
 491         u32 saveFPA0;
 492         u32 saveFPA1;
 493         u32 saveDPLL_A;
 494         u32 saveDPLL_A_MD;
 495         u32 saveHTOTAL_A;
 496         u32 saveHBLANK_A;
 497         u32 saveHSYNC_A;
 498         u32 saveVTOTAL_A;
 499         u32 saveVBLANK_A;
 500         u32 saveVSYNC_A;
 501         u32 saveBCLRPAT_A;
 502         u32 saveTRANSACONF;
 503         u32 saveTRANS_HTOTAL_A;
 504         u32 saveTRANS_HBLANK_A;
 505         u32 saveTRANS_HSYNC_A;
 506         u32 saveTRANS_VTOTAL_A;
 507         u32 saveTRANS_VBLANK_A;
 508         u32 saveTRANS_VSYNC_A;
 509         u32 savePIPEASTAT;
 510         u32 saveDSPASTRIDE;
 511         u32 saveDSPASIZE;
 512         u32 saveDSPAPOS;
 513         u32 saveDSPAADDR;
 514         u32 saveDSPASURF;
 515         u32 saveDSPATILEOFF;
 516         u32 savePFIT_PGM_RATIOS;
 517         u32 saveBLC_HIST_CTL;
 518         u32 saveBLC_PWM_CTL;
 519         u32 saveBLC_PWM_CTL2;
 520         u32 saveBLC_CPU_PWM_CTL;
 521         u32 saveBLC_CPU_PWM_CTL2;
 522         u32 saveFPB0;
 523         u32 saveFPB1;
 524         u32 saveDPLL_B;
 525         u32 saveDPLL_B_MD;
 526         u32 saveHTOTAL_B;
 527         u32 saveHBLANK_B;
 528         u32 saveHSYNC_B;
 529         u32 saveVTOTAL_B;
 530         u32 saveVBLANK_B;
 531         u32 saveVSYNC_B;
 532         u32 saveBCLRPAT_B;
 533         u32 saveTRANSBCONF;
 534         u32 saveTRANS_HTOTAL_B;
 535         u32 saveTRANS_HBLANK_B;
 536         u32 saveTRANS_HSYNC_B;
 537         u32 saveTRANS_VTOTAL_B;
 538         u32 saveTRANS_VBLANK_B;
 539         u32 saveTRANS_VSYNC_B;
 540         u32 savePIPEBSTAT;
 541         u32 saveDSPBSTRIDE;
 542         u32 saveDSPBSIZE;
 543         u32 saveDSPBPOS;
 544         u32 saveDSPBADDR;
 545         u32 saveDSPBSURF;
 546         u32 saveDSPBTILEOFF;
 547         u32 saveVGA0;
 548         u32 saveVGA1;
 549         u32 saveVGA_PD;
 550         u32 saveVGACNTRL;
 551         u32 saveADPA;
 552         u32 saveLVDS;
 553         u32 savePP_ON_DELAYS;
 554         u32 savePP_OFF_DELAYS;
 555         u32 saveDVOA;
 556         u32 saveDVOB;
 557         u32 saveDVOC;
 558         u32 savePP_ON;
 559         u32 savePP_OFF;
 560         u32 savePP_CONTROL;
 561         u32 savePP_DIVISOR;
 562         u32 savePFIT_CONTROL;
 563         u32 save_palette_a[256];
 564         u32 save_palette_b[256];
 565         u32 saveDPFC_CB_BASE;
 566         u32 saveFBC_CFB_BASE;
 567         u32 saveFBC_LL_BASE;
 568         u32 saveFBC_CONTROL;
 569         u32 saveFBC_CONTROL2;
 570         u32 saveIER;
 571         u32 saveIIR;
 572         u32 saveIMR;
 573         u32 saveDEIER;
 574         u32 saveDEIMR;
 575         u32 saveGTIER;
 576         u32 saveGTIMR;
 577         u32 saveFDI_RXA_IMR;
 578         u32 saveFDI_RXB_IMR;
 579         u32 saveCACHE_MODE_0;
 580         u32 saveMI_ARB_STATE;
 581         u32 saveSWF0[16];
 582         u32 saveSWF1[16];
 583         u32 saveSWF2[3];
 584         u8 saveMSR;
 585         u8 saveSR[8];
 586         u8 saveGR[25];
 587         u8 saveAR_INDEX;
 588         u8 saveAR[21];
 589         u8 saveDACMASK;
 590         u8 saveCR[37];
 591         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 592         u32 saveCURACNTR;
 593         u32 saveCURAPOS;
 594         u32 saveCURABASE;
 595         u32 saveCURBCNTR;
 596         u32 saveCURBPOS;
 597         u32 saveCURBBASE;
 598         u32 saveCURSIZE;
 599         u32 saveDP_B;
 600         u32 saveDP_C;
 601         u32 saveDP_D;
 602         u32 savePIPEA_GMCH_DATA_M;
 603         u32 savePIPEB_GMCH_DATA_M;
 604         u32 savePIPEA_GMCH_DATA_N;
 605         u32 savePIPEB_GMCH_DATA_N;
 606         u32 savePIPEA_DP_LINK_M;
 607         u32 savePIPEB_DP_LINK_M;
 608         u32 savePIPEA_DP_LINK_N;
 609         u32 savePIPEB_DP_LINK_N;
 610         u32 saveFDI_RXA_CTL;
 611         u32 saveFDI_TXA_CTL;
 612         u32 saveFDI_RXB_CTL;
 613         u32 saveFDI_TXB_CTL;
 614         u32 savePFA_CTL_1;
 615         u32 savePFB_CTL_1;
 616         u32 savePFA_WIN_SZ;
 617         u32 savePFB_WIN_SZ;
 618         u32 savePFA_WIN_POS;
 619         u32 savePFB_WIN_POS;
 620         u32 savePCH_DREF_CONTROL;
 621         u32 saveDISP_ARB_CTL;
 622         u32 savePIPEA_DATA_M1;
 623         u32 savePIPEA_DATA_N1;
 624         u32 savePIPEA_LINK_M1;
 625         u32 savePIPEA_LINK_N1;
 626         u32 savePIPEB_DATA_M1;
 627         u32 savePIPEB_DATA_N1;
 628         u32 savePIPEB_LINK_M1;
 629         u32 savePIPEB_LINK_N1;
 630         u32 saveMCHBAR_RENDER_STANDBY;
 631         u32 savePCH_PORT_HOTPLUG;
 632
 633         struct {
 634                 /** Bridge to intel-gtt-ko */
 635                 const struct intel_gtt *gtt;
 636                 /** Memory allocator for GTT stolen memory */
 637                 struct drm_mm stolen;
 638                 /** Memory allocator for GTT */
 639                 struct drm_mm gtt_space;
 640                 /** List of all objects in gtt_space. Used to restore gtt
 641                  * mappings on resume */
 642                 struct list_head gtt_list;
 643
 644                 /** Usable portion of the GTT for GEM */
 645                 unsigned long gtt_start;
 646                 unsigned long gtt_mappable_end;
 647                 unsigned long gtt_end;
 648
 649                 struct io_mapping *gtt_mapping;
 650                 int gtt_mtrr;
 651
 652                 /** PPGTT used for aliasing the PPGTT with the GTT */
 653                 struct i915_hw_ppgtt *aliasing_ppgtt;
 654
 655                 struct shrinker inactive_shrinker;
 656
 657                 /**
 658                  * List of objects currently involved in rendering.
 659                  *
 660                  * Includes buffers having the contents of their GPU caches
 661                  * flushed, not necessarily primitives.  last_rendering_seqno
 662                  * represents when the rendering involved will be completed.
 663                  *
 664                  * A reference is held on the buffer while on this list.
 665                  */
 666                 struct list_head active_list;
 667
 668                 /**
 669                  * List of objects which are not in the ringbuffer but which
 670                  * still have a write_domain which needs to be flushed before
 671                  * unbinding.
 672                  *
 673                  * last_rendering_seqno is 0 while an object is in this list.
 674                  *
 675                  * A reference is held on the buffer while on this list.
 676                  */
 677                 struct list_head flushing_list;
 678
 679                 /**
 680                  * LRU list of objects which are not in the ringbuffer and
 681                  * are ready to unbind, but are still in the GTT.
 682                  *
 683                  * last_rendering_seqno is 0 while an object is in this list.
 684                  *
 685                  * A reference is not held on the buffer while on this list,
 686                  * as merely being GTT-bound shouldn't prevent its being
 687                  * freed, and we'll pull it off the list in the free path.
 688                  */
 689                 struct list_head inactive_list;
 690
 691                 /** LRU list of objects with fence regs on them. */
 692                 struct list_head fence_list;
 693
 694                 /**
 695                  * We leave the user IRQ off as much as possible,
 696                  * but this means that requests will finish and never
 697                  * be retired once the system goes idle. Set a timer to
 698                  * fire periodically while the ring is running. When it
 699                  * fires, go retire requests.
 700                  */
 701                 struct delayed_work retire_work;
 702
 703                 /**
 704                  * Are we in a non-interruptible section of code like
 705                  * modesetting?
 706                  */
 707                 bool interruptible;
 708
 709                 /**
 710                  * Flag if the X Server, and thus DRM, is not currently in
 711                  * control of the device.
 712                  *
 713                  * This is set between LeaveVT and EnterVT.  It needs to be
 714                  * replaced with a semaphore.  It also needs to be
 715                  * transitioned away from for kernel modesetting.
 716                  */
 717                 int suspended;
 718
 719                 /**
 720                  * Flag if the hardware appears to be wedged.
 721                  *
 722                  * This is set when attempts to idle the device timeout.
 723                  * It prevents command submission from occurring and makes
 724                  * every pending request fail
 725                  */
 726                 atomic_t wedged;
 727
 728                 /** Bit 6 swizzling required for X tiling */
 729                 uint32_t bit_6_swizzle_x;
 730                 /** Bit 6 swizzling required for Y tiling */
 731                 uint32_t bit_6_swizzle_y;
 732
 733                 /* storage for physical objects */
 734                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 735
 736                 /* accounting, useful for userland debugging */
 737                 size_t gtt_total;
 738                 size_t mappable_gtt_total;
 739                 size_t object_memory;
 740                 u32 object_count;
 741         } mm;
 742         struct sdvo_device_mapping sdvo_mappings[2];
 743         /* indicate whether the LVDS_BORDER should be enabled or not */
 744         unsigned int lvds_border_bits;
 745         /* Panel fitter placement and size for Ironlake+ */
 746         u32 pch_pf_pos, pch_pf_size;
 747
 748         struct drm_crtc *plane_to_crtc_mapping[3];
 749         struct drm_crtc *pipe_to_crtc_mapping[3];
 750         wait_queue_head_t pending_flip_queue;
 751
 752         struct intel_pch_pll pch_plls[I915_NUM_PLLS];
 753
 754         /* Reclocking support */
 755         bool render_reclock_avail;
 756         bool lvds_downclock_avail;
 757         /* indicates the reduced downclock for LVDS*/
 758         int lvds_downclock;
 759         struct work_struct idle_work;
 760         struct timer_list idle_timer;
 761         bool busy;
 762         u16 orig_clock;
 763         int child_dev_num;
 764         struct child_device_config *child_dev;
 765         struct drm_connector *int_lvds_connector;
 766         struct drm_connector *int_edp_connector;
 767
 768         bool mchbar_need_disable;
 769
 770         struct work_struct rps_work;
 771         spinlock_t rps_lock;
 772         u32 pm_iir;
 773
 774         u8 cur_delay;
 775         u8 min_delay;
 776         u8 max_delay;
 777         u8 fmax;
 778         u8 fstart;
 779
 780         u64 last_count1;
 781         unsigned long last_time1;
 782         unsigned long chipset_power;
 783         u64 last_count2;
 784         struct timespec last_time2;
 785         unsigned long gfx_power;
 786         int c_m;
 787         int r_t;
 788         u8 corr;
 789         spinlock_t *mchdev_lock;
 790
 791         enum no_fbc_reason no_fbc_reason;
 792
 793         struct drm_mm_node *compressed_fb;
 794         struct drm_mm_node *compressed_llb;
 795
 796         unsigned long last_gpu_reset;
 797
 798         /* list of fbdev register on this device */
 799         struct intel_fbdev *fbdev;
 800
 801         struct backlight_device *backlight;
 802
 803         struct drm_property *broadcast_rgb_property;
 804         struct drm_property *force_audio_property;
 805 } drm_i915_private_t;
 806
 807 enum hdmi_force_audio {
 808         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
 809         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
 810         HDMI_AUDIO_AUTO,                /* trust EDID */
 811         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 812 };
 813
 814 enum i915_cache_level {
 815         I915_CACHE_NONE,
 816         I915_CACHE_LLC,
 817         I915_CACHE_LLC_MLC, /* gen6+ */
 818 };
 819
 820 struct drm_i915_gem_object {
 821         struct drm_gem_object base;
 822
 823         /** Current space allocated to this object in the GTT, if any. */
 824         struct drm_mm_node *gtt_space;
 825         struct list_head gtt_list;
 826
 827         /** This object's place on the active/flushing/inactive lists */
 828         struct list_head ring_list;
 829         struct list_head mm_list;
 830         /** This object's place on GPU write list */
 831         struct list_head gpu_write_list;
 832         /** This object's place in the batchbuffer or on the eviction list */
 833         struct list_head exec_list;
 834
 835         /**
 836          * This is set if the object is on the active or flushing lists
 837          * (has pending rendering), and is not set if it's on inactive (ready
 838          * to be unbound).
 839          */
 840         unsigned int active:1;
 841
 842         /**
 843          * This is set if the object has been written to since last bound
 844          * to the GTT
 845          */
 846         unsigned int dirty:1;
 847
 848         /**
 849          * This is set if the object has been written to since the last
 850          * GPU flush.
 851          */
 852         unsigned int pending_gpu_write:1;
 853
 854         /**
 855          * Fence register bits (if any) for this object.  Will be set
 856          * as needed when mapped into the GTT.
 857          * Protected by dev->struct_mutex.
 858          */
 859         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
 860
 861         /**
 862          * Advice: are the backing pages purgeable?
 863          */
 864         unsigned int madv:2;
 865
 866         /**
 867          * Current tiling mode for the object.
 868          */
 869         unsigned int tiling_mode:2;
 870         /**
 871          * Whether the tiling parameters for the currently associated fence
 872          * register have changed. Note that for the purposes of tracking
 873          * tiling changes we also treat the unfenced register, the register
 874          * slot that the object occupies whilst it executes a fenced
 875          * command (such as BLT on gen2/3), as a "fence".
 876          */
 877         unsigned int fence_dirty:1;
 878
 879         /** How many users have pinned this object in GTT space. The following
 880          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 881          * (via user_pin_count), execbuffer (objects are not allowed multiple
 882          * times for the same batchbuffer), and the framebuffer code. When
 883          * switching/pageflipping, the framebuffer code has at most two buffers
 884          * pinned per crtc.
 885          *
 886          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 887          * bits with absolutely no headroom. So use 4 bits. */
 888         unsigned int pin_count:4;
 889 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 890
 891         /**
 892          * Is the object at the current location in the gtt mappable and
 893          * fenceable? Used to avoid costly recalculations.
 894          */
 895         unsigned int map_and_fenceable:1;
 896
 897         /**
 898          * Whether the current gtt mapping needs to be mappable (and isn't just
 899          * mappable by accident). Track pin and fault separate for a more
 900          * accurate mappable working set.
 901          */
 902         unsigned int fault_mappable:1;
 903         unsigned int pin_mappable:1;
 904
 905         /*
 906          * Is the GPU currently using a fence to access this buffer,
 907          */
 908         unsigned int pending_fenced_gpu_access:1;
 909         unsigned int fenced_gpu_access:1;
 910
 911         unsigned int cache_level:2;
 912
 913         unsigned int has_aliasing_ppgtt_mapping:1;
 914         unsigned int has_global_gtt_mapping:1;
 915
 916         struct page **pages;
 917
 918         /**
 919          * DMAR support
 920          */
 921         struct scatterlist *sg_list;
 922         int num_sg;
 923
 924         /**
 925          * Used for performing relocations during execbuffer insertion.
 926          */
 927         struct hlist_node exec_node;
 928         unsigned long exec_handle;
 929         struct drm_i915_gem_exec_object2 *exec_entry;
 930
 931         /**
 932          * Current offset of the object in GTT space.
 933          *
 934          * This is the same as gtt_space->start
 935          */
 936         uint32_t gtt_offset;
 937
 938         struct intel_ring_buffer *ring;
 939
 940         /** Breadcrumb of last rendering to the buffer. */
 941         uint32_t last_rendering_seqno;
 942         /** Breadcrumb of last fenced GPU access to the buffer. */
 943         uint32_t last_fenced_seqno;
 944
 945         /** Current tiling stride for the object, if it's tiled. */
 946         uint32_t stride;
 947
 948         /** Record of address bit 17 of each page at last unbind. */
 949         unsigned long *bit_17;
 950
 951         /** User space pin count and filp owning the pin */
 952         uint32_t user_pin_count;
 953         struct drm_file *pin_filp;
 954
 955         /** for phy allocated objects */
 956         struct drm_i915_gem_phys_object *phys_obj;
 957
 958         /**
 959          * Number of crtcs where this object is currently the fb, but
 960          * will be page flipped away on the next vblank.  When it
 961          * reaches 0, dev_priv->pending_flip_queue will be woken up.
 962          */
 963         atomic_t pending_flip;
 964 };
 965
 966 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 967
 968 /**
 969  * Request queue structure.
 970  *
 971  * The request queue allows us to note sequence numbers that have been emitted
 972  * and may be associated with active buffers to be retired.
 973  *
 974  * By keeping this list, we can avoid having to do questionable
 975  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 976  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 977  */
 978 struct drm_i915_gem_request {
 979         /** On Which ring this request was generated */
 980         struct intel_ring_buffer *ring;
 981
 982         /** GEM sequence number associated with this request. */
 983         uint32_t seqno;
 984
 985         /** Postion in the ringbuffer of the end of the request */
 986         u32 tail;
 987
 988         /** Time at which this request was emitted, in jiffies. */
 989         unsigned long emitted_jiffies;
 990
 991         /** global list entry for this request */
 992         struct list_head list;
 993
 994         struct drm_i915_file_private *file_priv;
 995         /** file_priv list entry for this request */
 996         struct list_head client_list;
 997 };
 998
 999 struct drm_i915_file_private {
1000         struct {
1001                 struct spinlock lock;
1002                 struct list_head request_list;
1003         } mm;
1004 };
1005
1006 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1007
1008 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1009 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1010 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1011 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1012 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1013 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1014 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1015 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1016 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1017 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1018 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1019 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1020 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1021 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1022 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1023 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1024 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1025 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1026 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1027 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1028 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1029 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1030
1031 /*
1032  * The genX designation typically refers to the render engine, so render
1033  * capability related checks should use IS_GEN, while display and other checks
1034  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1035  * chips, etc.).
1036  */
1037 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1038 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1039 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1040 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1041 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1042 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1043
1044 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
1045 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
1046 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1047 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1048
1049 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
1050
1051 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1052 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1053
1054 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1055  * rows, which changed the alignment requirements and fence programming.
1056  */
1057 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1058                                                       IS_I915GM(dev)))
1059 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1060 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1061 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1062 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1063 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1064 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1065 /* dsparb controlled by hw only */
1066 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1067
1068 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1069 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1070 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1071
1072 #define HAS_PCH_SPLIT(dev) (INTEL_INFO(dev)->has_pch_split)
1073 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1074
1075 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1076 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1077 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1078 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1079
1080 #include "i915_trace.h"
1081
1082 /**
1083  * RC6 is a special power stage which allows the GPU to enter an very
1084  * low-voltage mode when idle, using down to 0V while at this stage.  This
1085  * stage is entered automatically when the GPU is idle when RC6 support is
1086  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1087  *
1088  * There are different RC6 modes available in Intel GPU, which differentiate
1089  * among each other with the latency required to enter and leave RC6 and
1090  * voltage consumed by the GPU in different states.
1091  *
1092  * The combination of the following flags define which states GPU is allowed
1093  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1094  * RC6pp is deepest RC6. Their support by hardware varies according to the
1095  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1096  * which brings the most power savings; deeper states save more power, but
1097  * require higher latency to switch to and wake up.
1098  */
1099 #define INTEL_RC6_ENABLE                        (1<<0)
1100 #define INTEL_RC6p_ENABLE                       (1<<1)
1101 #define INTEL_RC6pp_ENABLE                      (1<<2)
1102
1103 extern struct drm_ioctl_desc i915_ioctls[];
1104 extern int i915_max_ioctl;
1105 extern unsigned int i915_fbpercrtc __always_unused;
1106 extern int i915_panel_ignore_lid __read_mostly;
1107 extern unsigned int i915_powersave __read_mostly;
1108 extern int i915_semaphores __read_mostly;
1109 extern unsigned int i915_lvds_downclock __read_mostly;
1110 extern int i915_lvds_channel_mode __read_mostly;
1111 extern int i915_panel_use_ssc __read_mostly;
1112 extern int i915_vbt_sdvo_panel_type __read_mostly;
1113 extern int i915_enable_rc6 __read_mostly;
1114 extern int i915_enable_fbc __read_mostly;
1115 extern bool i915_enable_hangcheck __read_mostly;
1116 extern int i915_enable_ppgtt __read_mostly;
1117
1118 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1119 extern int i915_resume(struct drm_device *dev);
1120 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1121 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1122
1123                                 /* i915_dma.c */
1124 extern void i915_kernel_lost_context(struct drm_device * dev);
1125 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1126 extern int i915_driver_unload(struct drm_device *);
1127 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1128 extern void i915_driver_lastclose(struct drm_device * dev);
1129 extern void i915_driver_preclose(struct drm_device *dev,
1130                                  struct drm_file *file_priv);
1131 extern void i915_driver_postclose(struct drm_device *dev,
1132                                   struct drm_file *file_priv);
1133 extern int i915_driver_device_is_agp(struct drm_device * dev);
1134 #ifdef CONFIG_COMPAT
1135 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1136                               unsigned long arg);
1137 #endif
1138 extern int i915_emit_box(struct drm_device *dev,
1139                          struct drm_clip_rect *box,
1140                          int DR1, int DR4);
1141 extern int i915_reset(struct drm_device *dev, u8 flags);
1142 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1143 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1144 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1145 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1146
1147
1148 /* i915_irq.c */
1149 void i915_hangcheck_elapsed(unsigned long data);
1150 void i915_handle_error(struct drm_device *dev, bool wedged);
1151 extern int i915_irq_emit(struct drm_device *dev, void *data,
1152                          struct drm_file *file_priv);
1153 extern int i915_irq_wait(struct drm_device *dev, void *data,
1154                          struct drm_file *file_priv);
1155
1156 extern void intel_irq_init(struct drm_device *dev);
1157
1158 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1159                                 struct drm_file *file_priv);
1160 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1161                                 struct drm_file *file_priv);
1162 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1163                             struct drm_file *file_priv);
1164
1165 void
1166 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1167
1168 void
1169 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1170
1171 void intel_enable_asle(struct drm_device *dev);
1172
1173 #ifdef CONFIG_DEBUG_FS
1174 extern void i915_destroy_error_state(struct drm_device *dev);
1175 #else
1176 #define i915_destroy_error_state(x)
1177 #endif
1178
1179
1180 /* i915_gem.c */
1181 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1182                         struct drm_file *file_priv);
1183 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1184                           struct drm_file *file_priv);
1185 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1186                          struct drm_file *file_priv);
1187 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1188                           struct drm_file *file_priv);
1189 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1190                         struct drm_file *file_priv);
1191 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1192                         struct drm_file *file_priv);
1193 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1194                               struct drm_file *file_priv);
1195 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1196                              struct drm_file *file_priv);
1197 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1198                         struct drm_file *file_priv);
1199 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1200                          struct drm_file *file_priv);
1201 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1202                        struct drm_file *file_priv);
1203 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1204                          struct drm_file *file_priv);
1205 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1206                         struct drm_file *file_priv);
1207 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1208                             struct drm_file *file_priv);
1209 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1210                            struct drm_file *file_priv);
1211 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1212                            struct drm_file *file_priv);
1213 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1214                            struct drm_file *file_priv);
1215 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1216                         struct drm_file *file_priv);
1217 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1218                         struct drm_file *file_priv);
1219 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1220                                 struct drm_file *file_priv);
1221 void i915_gem_load(struct drm_device *dev);
1222 int i915_gem_init_object(struct drm_gem_object *obj);
1223 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1224                                      uint32_t invalidate_domains,
1225                                      uint32_t flush_domains);
1226 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1227                                                   size_t size);
1228 void i915_gem_free_object(struct drm_gem_object *obj);
1229 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1230                                      uint32_t alignment,
1231                                      bool map_and_fenceable);
1232 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1233 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1234 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1235 void i915_gem_lastclose(struct drm_device *dev);
1236
1237 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1238 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1239 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1240                          struct intel_ring_buffer *to);
1241 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1242                                     struct intel_ring_buffer *ring,
1243                                     u32 seqno);
1244
1245 int i915_gem_dumb_create(struct drm_file *file_priv,
1246                          struct drm_device *dev,
1247                          struct drm_mode_create_dumb *args);
1248 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1249                       uint32_t handle, uint64_t *offset);
1250 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1251                           uint32_t handle);
1252 /**
1253  * Returns true if seq1 is later than seq2.
1254  */
1255 static inline bool
1256 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1257 {
1258         return (int32_t)(seq1 - seq2) >= 0;
1259 }
1260
1261 u32 i915_gem_next_request_seqno(struct intel_ring_buffer *ring);
1262
1263 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1264 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1265
1266 static inline bool
1267 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1268 {
1269         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1270                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1271                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1272                 return true;
1273         } else
1274                 return false;
1275 }
1276
1277 static inline void
1278 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1279 {
1280         if (obj->fence_reg != I915_FENCE_REG_NONE) {
1281                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1282                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1283         }
1284 }
1285
1286 void i915_gem_retire_requests(struct drm_device *dev);
1287 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1288
1289 void i915_gem_reset(struct drm_device *dev);
1290 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1291 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1292                                             uint32_t read_domains,
1293                                             uint32_t write_domain);
1294 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1295 int __must_check i915_gem_init(struct drm_device *dev);
1296 int __must_check i915_gem_init_hw(struct drm_device *dev);
1297 void i915_gem_init_swizzling(struct drm_device *dev);
1298 void i915_gem_init_ppgtt(struct drm_device *dev);
1299 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1300 int __must_check i915_gpu_idle(struct drm_device *dev);
1301 int __must_check i915_gem_idle(struct drm_device *dev);
1302 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1303                                   struct drm_file *file,
1304                                   struct drm_i915_gem_request *request);
1305 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1306                                    uint32_t seqno);
1307 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1308 int __must_check
1309 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1310                                   bool write);
1311 int __must_check
1312 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1313 int __must_check
1314 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1315                                      u32 alignment,
1316                                      struct intel_ring_buffer *pipelined);
1317 int i915_gem_attach_phys_object(struct drm_device *dev,
1318                                 struct drm_i915_gem_object *obj,
1319                                 int id,
1320                                 int align);
1321 void i915_gem_detach_phys_object(struct drm_device *dev,
1322                                  struct drm_i915_gem_object *obj);
1323 void i915_gem_free_all_phys_object(struct drm_device *dev);
1324 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1325
1326 uint32_t
1327 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1328                                     uint32_t size,
1329                                     int tiling_mode);
1330
1331 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1332                                     enum i915_cache_level cache_level);
1333
1334 /* i915_gem_gtt.c */
1335 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1336 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1337 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1338                             struct drm_i915_gem_object *obj,
1339                             enum i915_cache_level cache_level);
1340 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1341                               struct drm_i915_gem_object *obj);
1342
1343 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1344 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1345 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1346                                 enum i915_cache_level cache_level);
1347 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1348 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1349 void i915_gem_init_global_gtt(struct drm_device *dev,
1350                               unsigned long start,
1351                               unsigned long mappable_end,
1352                               unsigned long end);
1353
1354 /* i915_gem_evict.c */
1355 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1356                                           unsigned alignment, bool mappable);
1357 int i915_gem_evict_everything(struct drm_device *dev, bool purgeable_only);
1358
1359 /* i915_gem_stolen.c */
1360 int i915_gem_init_stolen(struct drm_device *dev);
1361 void i915_gem_cleanup_stolen(struct drm_device *dev);
1362
1363 /* i915_gem_tiling.c */
1364 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1365 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1366 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1367
1368 /* i915_gem_debug.c */
1369 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1370                           const char *where, uint32_t mark);
1371 #if WATCH_LISTS
1372 int i915_verify_lists(struct drm_device *dev);
1373 #else
1374 #define i915_verify_lists(dev) 0
1375 #endif
1376 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1377                                      int handle);
1378 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1379                           const char *where, uint32_t mark);
1380
1381 /* i915_debugfs.c */
1382 int i915_debugfs_init(struct drm_minor *minor);
1383 void i915_debugfs_cleanup(struct drm_minor *minor);
1384
1385 /* i915_suspend.c */
1386 extern int i915_save_state(struct drm_device *dev);
1387 extern int i915_restore_state(struct drm_device *dev);
1388
1389 /* i915_suspend.c */
1390 extern int i915_save_state(struct drm_device *dev);
1391 extern int i915_restore_state(struct drm_device *dev);
1392
1393 /* i915_sysfs.c */
1394 void i915_setup_sysfs(struct drm_device *dev_priv);
1395 void i915_teardown_sysfs(struct drm_device *dev_priv);
1396
1397 /* intel_i2c.c */
1398 extern int intel_setup_gmbus(struct drm_device *dev);
1399 extern void intel_teardown_gmbus(struct drm_device *dev);
1400 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1401 {
1402         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1403 }
1404
1405 extern struct i2c_adapter *intel_gmbus_get_adapter(
1406                 struct drm_i915_private *dev_priv, unsigned port);
1407 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1408 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1409 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1410 {
1411         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1412 }
1413 extern void intel_i2c_reset(struct drm_device *dev);
1414
1415 /* intel_opregion.c */
1416 extern int intel_opregion_setup(struct drm_device *dev);
1417 #ifdef CONFIG_ACPI
1418 extern void intel_opregion_init(struct drm_device *dev);
1419 extern void intel_opregion_fini(struct drm_device *dev);
1420 extern void intel_opregion_asle_intr(struct drm_device *dev);
1421 extern void intel_opregion_gse_intr(struct drm_device *dev);
1422 extern void intel_opregion_enable_asle(struct drm_device *dev);
1423 #else
1424 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1425 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1426 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1427 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1428 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1429 #endif
1430
1431 /* intel_acpi.c */
1432 #ifdef CONFIG_ACPI
1433 extern void intel_register_dsm_handler(void);
1434 extern void intel_unregister_dsm_handler(void);
1435 #else
1436 static inline void intel_register_dsm_handler(void) { return; }
1437 static inline void intel_unregister_dsm_handler(void) { return; }
1438 #endif /* CONFIG_ACPI */
1439
1440 /* modesetting */
1441 extern void intel_modeset_init_hw(struct drm_device *dev);
1442 extern void intel_modeset_init(struct drm_device *dev);
1443 extern void intel_modeset_gem_init(struct drm_device *dev);
1444 extern void intel_modeset_cleanup(struct drm_device *dev);
1445 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1446 extern bool intel_fbc_enabled(struct drm_device *dev);
1447 extern void intel_disable_fbc(struct drm_device *dev);
1448 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1449 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1450 extern void ironlake_enable_rc6(struct drm_device *dev);
1451 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1452 extern void intel_detect_pch(struct drm_device *dev);
1453 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1454 extern int intel_enable_rc6(const struct drm_device *dev);
1455
1456 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1457 extern void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1458 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv);
1459 extern void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1460 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv);
1461
1462 extern void vlv_force_wake_get(struct drm_i915_private *dev_priv);
1463 extern void vlv_force_wake_put(struct drm_i915_private *dev_priv);
1464
1465 /* overlay */
1466 #ifdef CONFIG_DEBUG_FS
1467 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1468 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1469
1470 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1471 extern void intel_display_print_error_state(struct seq_file *m,
1472                                             struct drm_device *dev,
1473                                             struct intel_display_error_state *error);
1474 #endif
1475
1476 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1477
1478 #define BEGIN_LP_RING(n) \
1479         intel_ring_begin(LP_RING(dev_priv), (n))
1480
1481 #define OUT_RING(x) \
1482         intel_ring_emit(LP_RING(dev_priv), x)
1483
1484 #define ADVANCE_LP_RING() \
1485         intel_ring_advance(LP_RING(dev_priv))
1486
1487 /**
1488  * Lock test for when it's just for synchronization of ring access.
1489  *
1490  * In that case, we don't need to do it when GEM is initialized as nobody else
1491  * has access to the ring.
1492  */
1493 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
1494         if (LP_RING(dev->dev_private)->obj == NULL)                     \
1495                 LOCK_TEST_WITH_RETURN(dev, file);                       \
1496 } while (0)
1497
1498 /* On SNB platform, before reading ring registers forcewake bit
1499  * must be set to prevent GT core from power down and stale values being
1500  * returned.
1501  */
1502 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1503 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1504 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1505
1506 #define __i915_read(x, y) \
1507         u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1508
1509 __i915_read(8, b)
1510 __i915_read(16, w)
1511 __i915_read(32, l)
1512 __i915_read(64, q)
1513 #undef __i915_read
1514
1515 #define __i915_write(x, y) \
1516         void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1517
1518 __i915_write(8, b)
1519 __i915_write(16, w)
1520 __i915_write(32, l)
1521 __i915_write(64, q)
1522 #undef __i915_write
1523
1524 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1525 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1526
1527 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1528 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1529 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1530 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1531
1532 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1533 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1534 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1535 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1536
1537 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1538 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1539
1540 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1541 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1542
1543
1544 #endif