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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
36
37 /* General customization:
38 */
39
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
41
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
45
46 enum pipe {
47 PIPE_A = 0,
48 PIPE_B,
49 };
50
51 enum plane {
52 PLANE_A = 0,
53 PLANE_B,
54 };
55
56 #define I915_NUM_PIPE 2
57
58 /* Interface history:
59 *
60 * 1.1: Original.
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
67 */
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
71
72 #define WATCH_COHERENCY 0
73 #define WATCH_BUF 0
74 #define WATCH_EXEC 0
75 #define WATCH_LRU 0
76 #define WATCH_RELOC 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
79
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
84
85 struct drm_i915_gem_phys_object {
86 int id;
87 struct page **page_list;
88 drm_dma_handle_t *handle;
89 struct drm_gem_object *cur_obj;
90 };
91
92 typedef struct _drm_i915_ring_buffer {
93 unsigned long Size;
94 u8 *virtual_start;
95 int head;
96 int tail;
97 int space;
98 drm_local_map_t map;
99 struct drm_gem_object *ring_obj;
100 } drm_i915_ring_buffer_t;
101
102 struct mem_block {
103 struct mem_block *next;
104 struct mem_block *prev;
105 int start;
106 int size;
107 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
108 };
109
110 struct opregion_header;
111 struct opregion_acpi;
112 struct opregion_swsci;
113 struct opregion_asle;
114
115 struct intel_opregion {
116 struct opregion_header *header;
117 struct opregion_acpi *acpi;
118 struct opregion_swsci *swsci;
119 struct opregion_asle *asle;
120 int enabled;
121 };
122
123 struct drm_i915_master_private {
124 drm_local_map_t *sarea;
125 struct _drm_i915_sarea *sarea_priv;
126 };
127 #define I915_FENCE_REG_NONE -1
128
129 struct drm_i915_fence_reg {
130 struct drm_gem_object *obj;
131 };
132
133 struct sdvo_device_mapping {
134 u8 dvo_port;
135 u8 slave_addr;
136 u8 dvo_wiring;
137 u8 initialized;
138 };
139
140 struct drm_i915_error_state {
141 u32 eir;
142 u32 pgtbl_er;
143 u32 pipeastat;
144 u32 pipebstat;
145 u32 ipeir;
146 u32 ipehr;
147 u32 instdone;
148 u32 acthd;
149 u32 instpm;
150 u32 instps;
151 u32 instdone1;
152 u32 seqno;
153 struct timeval time;
154 };
155
156 struct drm_i915_display_funcs {
157 void (*dpms)(struct drm_crtc *crtc, int mode);
158 bool (*fbc_enabled)(struct drm_crtc *crtc);
159 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
160 void (*disable_fbc)(struct drm_device *dev);
161 int (*get_display_clock_speed)(struct drm_device *dev);
162 int (*get_fifo_size)(struct drm_device *dev, int plane);
163 void (*update_wm)(struct drm_device *dev, int planea_clock,
164 int planeb_clock, int sr_hdisplay, int pixel_size);
165 /* clock updates for mode set */
166 /* cursor updates */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
171 };
172
173 struct intel_overlay;
174
175 typedef struct drm_i915_private {
176 struct drm_device *dev;
177
178 int has_gem;
179
180 void __iomem *regs;
181
182 struct pci_dev *bridge_dev;
183 drm_i915_ring_buffer_t ring;
184
185 drm_dma_handle_t *status_page_dmah;
186 void *hw_status_page;
187 dma_addr_t dma_status_page;
188 uint32_t counter;
189 unsigned int status_gfx_addr;
190 drm_local_map_t hws_map;
191 struct drm_gem_object *hws_obj;
192 struct drm_gem_object *pwrctx;
193
194 struct resource mch_res;
195
196 unsigned int cpp;
197 int back_offset;
198 int front_offset;
199 int current_page;
200 int page_flipping;
201
202 wait_queue_head_t irq_queue;
203 atomic_t irq_received;
204 /** Protects user_irq_refcount and irq_mask_reg */
205 spinlock_t user_irq_lock;
206 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
207 int user_irq_refcount;
208 u32 trace_irq_seqno;
209 /** Cached value of IMR to avoid reads in updating the bitfield */
210 u32 irq_mask_reg;
211 u32 pipestat[2];
212 /** splitted irq regs for graphics and display engine on Ironlake,
213 irq_mask_reg is still used for display irq. */
214 u32 gt_irq_mask_reg;
215 u32 gt_irq_enable_reg;
216 u32 de_irq_enable_reg;
217 u32 pch_irq_mask_reg;
218 u32 pch_irq_enable_reg;
219
220 u32 hotplug_supported_mask;
221 struct work_struct hotplug_work;
222
223 int tex_lru_log_granularity;
224 int allow_batchbuffer;
225 struct mem_block *agp_heap;
226 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
227 int vblank_pipe;
228
229 /* For hangcheck timer */
230 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
231 struct timer_list hangcheck_timer;
232 int hangcheck_count;
233 uint32_t last_acthd;
234
235 bool cursor_needs_physical;
236
237 struct drm_mm vram;
238
239 unsigned long cfb_size;
240 unsigned long cfb_pitch;
241 int cfb_fence;
242 int cfb_plane;
243
244 int irq_enabled;
245
246 struct intel_opregion opregion;
247
248 /* overlay */
249 struct intel_overlay *overlay;
250
251 /* LVDS info */
252 int backlight_duty_cycle; /* restore backlight to this value */
253 bool panel_wants_dither;
254 struct drm_display_mode *panel_fixed_mode;
255 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
256 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
257
258 /* Feature bits from the VBIOS */
259 unsigned int int_tv_support:1;
260 unsigned int lvds_dither:1;
261 unsigned int lvds_vbt:1;
262 unsigned int int_crt_support:1;
263 unsigned int lvds_use_ssc:1;
264 unsigned int edp_support:1;
265 int lvds_ssc_freq;
266
267 struct notifier_block lid_notifier;
268
269 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
270 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
271 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
272 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
273
274 unsigned int fsb_freq, mem_freq;
275
276 spinlock_t error_lock;
277 struct drm_i915_error_state *first_error;
278 struct work_struct error_work;
279 struct workqueue_struct *wq;
280
281 /* Display functions */
282 struct drm_i915_display_funcs display;
283
284 /* Register state */
285 bool modeset_on_lid;
286 u8 saveLBB;
287 u32 saveDSPACNTR;
288 u32 saveDSPBCNTR;
289 u32 saveDSPARB;
290 u32 saveRENDERSTANDBY;
291 u32 savePWRCTXA;
292 u32 saveHWS;
293 u32 savePIPEACONF;
294 u32 savePIPEBCONF;
295 u32 savePIPEASRC;
296 u32 savePIPEBSRC;
297 u32 saveFPA0;
298 u32 saveFPA1;
299 u32 saveDPLL_A;
300 u32 saveDPLL_A_MD;
301 u32 saveHTOTAL_A;
302 u32 saveHBLANK_A;
303 u32 saveHSYNC_A;
304 u32 saveVTOTAL_A;
305 u32 saveVBLANK_A;
306 u32 saveVSYNC_A;
307 u32 saveBCLRPAT_A;
308 u32 saveTRANSACONF;
309 u32 saveTRANS_HTOTAL_A;
310 u32 saveTRANS_HBLANK_A;
311 u32 saveTRANS_HSYNC_A;
312 u32 saveTRANS_VTOTAL_A;
313 u32 saveTRANS_VBLANK_A;
314 u32 saveTRANS_VSYNC_A;
315 u32 savePIPEASTAT;
316 u32 saveDSPASTRIDE;
317 u32 saveDSPASIZE;
318 u32 saveDSPAPOS;
319 u32 saveDSPAADDR;
320 u32 saveDSPASURF;
321 u32 saveDSPATILEOFF;
322 u32 savePFIT_PGM_RATIOS;
323 u32 saveBLC_HIST_CTL;
324 u32 saveBLC_PWM_CTL;
325 u32 saveBLC_PWM_CTL2;
326 u32 saveBLC_CPU_PWM_CTL;
327 u32 saveBLC_CPU_PWM_CTL2;
328 u32 saveFPB0;
329 u32 saveFPB1;
330 u32 saveDPLL_B;
331 u32 saveDPLL_B_MD;
332 u32 saveHTOTAL_B;
333 u32 saveHBLANK_B;
334 u32 saveHSYNC_B;
335 u32 saveVTOTAL_B;
336 u32 saveVBLANK_B;
337 u32 saveVSYNC_B;
338 u32 saveBCLRPAT_B;
339 u32 saveTRANSBCONF;
340 u32 saveTRANS_HTOTAL_B;
341 u32 saveTRANS_HBLANK_B;
342 u32 saveTRANS_HSYNC_B;
343 u32 saveTRANS_VTOTAL_B;
344 u32 saveTRANS_VBLANK_B;
345 u32 saveTRANS_VSYNC_B;
346 u32 savePIPEBSTAT;
347 u32 saveDSPBSTRIDE;
348 u32 saveDSPBSIZE;
349 u32 saveDSPBPOS;
350 u32 saveDSPBADDR;
351 u32 saveDSPBSURF;
352 u32 saveDSPBTILEOFF;
353 u32 saveVGA0;
354 u32 saveVGA1;
355 u32 saveVGA_PD;
356 u32 saveVGACNTRL;
357 u32 saveADPA;
358 u32 saveLVDS;
359 u32 savePP_ON_DELAYS;
360 u32 savePP_OFF_DELAYS;
361 u32 saveDVOA;
362 u32 saveDVOB;
363 u32 saveDVOC;
364 u32 savePP_ON;
365 u32 savePP_OFF;
366 u32 savePP_CONTROL;
367 u32 savePP_DIVISOR;
368 u32 savePFIT_CONTROL;
369 u32 save_palette_a[256];
370 u32 save_palette_b[256];
371 u32 saveDPFC_CB_BASE;
372 u32 saveFBC_CFB_BASE;
373 u32 saveFBC_LL_BASE;
374 u32 saveFBC_CONTROL;
375 u32 saveFBC_CONTROL2;
376 u32 saveIER;
377 u32 saveIIR;
378 u32 saveIMR;
379 u32 saveDEIER;
380 u32 saveDEIMR;
381 u32 saveGTIER;
382 u32 saveGTIMR;
383 u32 saveFDI_RXA_IMR;
384 u32 saveFDI_RXB_IMR;
385 u32 saveCACHE_MODE_0;
386 u32 saveMI_ARB_STATE;
387 u32 saveSWF0[16];
388 u32 saveSWF1[16];
389 u32 saveSWF2[3];
390 u8 saveMSR;
391 u8 saveSR[8];
392 u8 saveGR[25];
393 u8 saveAR_INDEX;
394 u8 saveAR[21];
395 u8 saveDACMASK;
396 u8 saveCR[37];
397 uint64_t saveFENCE[16];
398 u32 saveCURACNTR;
399 u32 saveCURAPOS;
400 u32 saveCURABASE;
401 u32 saveCURBCNTR;
402 u32 saveCURBPOS;
403 u32 saveCURBBASE;
404 u32 saveCURSIZE;
405 u32 saveDP_B;
406 u32 saveDP_C;
407 u32 saveDP_D;
408 u32 savePIPEA_GMCH_DATA_M;
409 u32 savePIPEB_GMCH_DATA_M;
410 u32 savePIPEA_GMCH_DATA_N;
411 u32 savePIPEB_GMCH_DATA_N;
412 u32 savePIPEA_DP_LINK_M;
413 u32 savePIPEB_DP_LINK_M;
414 u32 savePIPEA_DP_LINK_N;
415 u32 savePIPEB_DP_LINK_N;
416 u32 saveFDI_RXA_CTL;
417 u32 saveFDI_TXA_CTL;
418 u32 saveFDI_RXB_CTL;
419 u32 saveFDI_TXB_CTL;
420 u32 savePFA_CTL_1;
421 u32 savePFB_CTL_1;
422 u32 savePFA_WIN_SZ;
423 u32 savePFB_WIN_SZ;
424 u32 savePFA_WIN_POS;
425 u32 savePFB_WIN_POS;
426 u32 savePCH_DREF_CONTROL;
427 u32 saveDISP_ARB_CTL;
428 u32 savePIPEA_DATA_M1;
429 u32 savePIPEA_DATA_N1;
430 u32 savePIPEA_LINK_M1;
431 u32 savePIPEA_LINK_N1;
432 u32 savePIPEB_DATA_M1;
433 u32 savePIPEB_DATA_N1;
434 u32 savePIPEB_LINK_M1;
435 u32 savePIPEB_LINK_N1;
436
437 struct {
438 struct drm_mm gtt_space;
439
440 struct io_mapping *gtt_mapping;
441 int gtt_mtrr;
442
443 /**
444 * Membership on list of all loaded devices, used to evict
445 * inactive buffers under memory pressure.
446 *
447 * Modifications should only be done whilst holding the
448 * shrink_list_lock spinlock.
449 */
450 struct list_head shrink_list;
451
452 /**
453 * List of objects currently involved in rendering from the
454 * ringbuffer.
455 *
456 * Includes buffers having the contents of their GPU caches
457 * flushed, not necessarily primitives. last_rendering_seqno
458 * represents when the rendering involved will be completed.
459 *
460 * A reference is held on the buffer while on this list.
461 */
462 spinlock_t active_list_lock;
463 struct list_head active_list;
464
465 /**
466 * List of objects which are not in the ringbuffer but which
467 * still have a write_domain which needs to be flushed before
468 * unbinding.
469 *
470 * last_rendering_seqno is 0 while an object is in this list.
471 *
472 * A reference is held on the buffer while on this list.
473 */
474 struct list_head flushing_list;
475
476 /**
477 * LRU list of objects which are not in the ringbuffer and
478 * are ready to unbind, but are still in the GTT.
479 *
480 * last_rendering_seqno is 0 while an object is in this list.
481 *
482 * A reference is not held on the buffer while on this list,
483 * as merely being GTT-bound shouldn't prevent its being
484 * freed, and we'll pull it off the list in the free path.
485 */
486 struct list_head inactive_list;
487
488 /** LRU list of objects with fence regs on them. */
489 struct list_head fence_list;
490
491 /**
492 * List of breadcrumbs associated with GPU requests currently
493 * outstanding.
494 */
495 struct list_head request_list;
496
497 /**
498 * We leave the user IRQ off as much as possible,
499 * but this means that requests will finish and never
500 * be retired once the system goes idle. Set a timer to
501 * fire periodically while the ring is running. When it
502 * fires, go retire requests.
503 */
504 struct delayed_work retire_work;
505
506 uint32_t next_gem_seqno;
507
508 /**
509 * Waiting sequence number, if any
510 */
511 uint32_t waiting_gem_seqno;
512
513 /**
514 * Last seq seen at irq time
515 */
516 uint32_t irq_gem_seqno;
517
518 /**
519 * Flag if the X Server, and thus DRM, is not currently in
520 * control of the device.
521 *
522 * This is set between LeaveVT and EnterVT. It needs to be
523 * replaced with a semaphore. It also needs to be
524 * transitioned away from for kernel modesetting.
525 */
526 int suspended;
527
528 /**
529 * Flag if the hardware appears to be wedged.
530 *
531 * This is set when attempts to idle the device timeout.
532 * It prevents command submission from occuring and makes
533 * every pending request fail
534 */
535 atomic_t wedged;
536
537 /** Bit 6 swizzling required for X tiling */
538 uint32_t bit_6_swizzle_x;
539 /** Bit 6 swizzling required for Y tiling */
540 uint32_t bit_6_swizzle_y;
541
542 /* storage for physical objects */
543 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
544 } mm;
545 struct sdvo_device_mapping sdvo_mappings[2];
546 /* indicate whether the LVDS_BORDER should be enabled or not */
547 unsigned int lvds_border_bits;
548
549 struct drm_crtc *plane_to_crtc_mapping[2];
550 struct drm_crtc *pipe_to_crtc_mapping[2];
551 wait_queue_head_t pending_flip_queue;
552
553 /* Reclocking support */
554 bool render_reclock_avail;
555 bool lvds_downclock_avail;
556 /* indicates the reduced downclock for LVDS*/
557 int lvds_downclock;
558 struct work_struct idle_work;
559 struct timer_list idle_timer;
560 bool busy;
561 u16 orig_clock;
562 int child_dev_num;
563 struct child_device_config *child_dev;
564 struct drm_connector *int_lvds_connector;
565 } drm_i915_private_t;
566
567 /** driver private structure attached to each drm_gem_object */
568 struct drm_i915_gem_object {
569 struct drm_gem_object *obj;
570
571 /** Current space allocated to this object in the GTT, if any. */
572 struct drm_mm_node *gtt_space;
573
574 /** This object's place on the active/flushing/inactive lists */
575 struct list_head list;
576
577 /** This object's place on the fenced object LRU */
578 struct list_head fence_list;
579
580 /**
581 * This is set if the object is on the active or flushing lists
582 * (has pending rendering), and is not set if it's on inactive (ready
583 * to be unbound).
584 */
585 int active;
586
587 /**
588 * This is set if the object has been written to since last bound
589 * to the GTT
590 */
591 int dirty;
592
593 /** AGP memory structure for our GTT binding. */
594 DRM_AGP_MEM *agp_mem;
595
596 struct page **pages;
597 int pages_refcount;
598
599 /**
600 * Current offset of the object in GTT space.
601 *
602 * This is the same as gtt_space->start
603 */
604 uint32_t gtt_offset;
605
606 /**
607 * Fake offset for use by mmap(2)
608 */
609 uint64_t mmap_offset;
610
611 /**
612 * Fence register bits (if any) for this object. Will be set
613 * as needed when mapped into the GTT.
614 * Protected by dev->struct_mutex.
615 */
616 int fence_reg;
617
618 /** How many users have pinned this object in GTT space */
619 int pin_count;
620
621 /** Breadcrumb of last rendering to the buffer. */
622 uint32_t last_rendering_seqno;
623
624 /** Current tiling mode for the object. */
625 uint32_t tiling_mode;
626 uint32_t stride;
627
628 /** Record of address bit 17 of each page at last unbind. */
629 long *bit_17;
630
631 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
632 uint32_t agp_type;
633
634 /**
635 * If present, while GEM_DOMAIN_CPU is in the read domain this array
636 * flags which individual pages are valid.
637 */
638 uint8_t *page_cpu_valid;
639
640 /** User space pin count and filp owning the pin */
641 uint32_t user_pin_count;
642 struct drm_file *pin_filp;
643
644 /** for phy allocated objects */
645 struct drm_i915_gem_phys_object *phys_obj;
646
647 /**
648 * Used for checking the object doesn't appear more than once
649 * in an execbuffer object list.
650 */
651 int in_execbuffer;
652
653 /**
654 * Advice: are the backing pages purgeable?
655 */
656 int madv;
657
658 /**
659 * Number of crtcs where this object is currently the fb, but
660 * will be page flipped away on the next vblank. When it
661 * reaches 0, dev_priv->pending_flip_queue will be woken up.
662 */
663 atomic_t pending_flip;
664 };
665
666 /**
667 * Request queue structure.
668 *
669 * The request queue allows us to note sequence numbers that have been emitted
670 * and may be associated with active buffers to be retired.
671 *
672 * By keeping this list, we can avoid having to do questionable
673 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
674 * an emission time with seqnos for tracking how far ahead of the GPU we are.
675 */
676 struct drm_i915_gem_request {
677 /** GEM sequence number associated with this request. */
678 uint32_t seqno;
679
680 /** Time at which this request was emitted, in jiffies. */
681 unsigned long emitted_jiffies;
682
683 /** global list entry for this request */
684 struct list_head list;
685
686 /** file_priv list entry for this request */
687 struct list_head client_list;
688 };
689
690 struct drm_i915_file_private {
691 struct {
692 struct list_head request_list;
693 } mm;
694 };
695
696 enum intel_chip_family {
697 CHIP_I8XX = 0x01,
698 CHIP_I9XX = 0x02,
699 CHIP_I915 = 0x04,
700 CHIP_I965 = 0x08,
701 };
702
703 extern struct drm_ioctl_desc i915_ioctls[];
704 extern int i915_max_ioctl;
705 extern unsigned int i915_fbpercrtc;
706 extern unsigned int i915_powersave;
707
708 extern void i915_save_display(struct drm_device *dev);
709 extern void i915_restore_display(struct drm_device *dev);
710 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
711 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
712
713 /* i915_dma.c */
714 extern void i915_kernel_lost_context(struct drm_device * dev);
715 extern int i915_driver_load(struct drm_device *, unsigned long flags);
716 extern int i915_driver_unload(struct drm_device *);
717 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
718 extern void i915_driver_lastclose(struct drm_device * dev);
719 extern void i915_driver_preclose(struct drm_device *dev,
720 struct drm_file *file_priv);
721 extern void i915_driver_postclose(struct drm_device *dev,
722 struct drm_file *file_priv);
723 extern int i915_driver_device_is_agp(struct drm_device * dev);
724 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
725 unsigned long arg);
726 extern int i915_emit_box(struct drm_device *dev,
727 struct drm_clip_rect *boxes,
728 int i, int DR1, int DR4);
729 extern int i965_reset(struct drm_device *dev, u8 flags);
730
731 /* i915_irq.c */
732 void i915_hangcheck_elapsed(unsigned long data);
733 extern int i915_irq_emit(struct drm_device *dev, void *data,
734 struct drm_file *file_priv);
735 extern int i915_irq_wait(struct drm_device *dev, void *data,
736 struct drm_file *file_priv);
737 void i915_user_irq_get(struct drm_device *dev);
738 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
739 void i915_user_irq_put(struct drm_device *dev);
740 extern void i915_enable_interrupt (struct drm_device *dev);
741
742 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
743 extern void i915_driver_irq_preinstall(struct drm_device * dev);
744 extern int i915_driver_irq_postinstall(struct drm_device *dev);
745 extern void i915_driver_irq_uninstall(struct drm_device * dev);
746 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
747 struct drm_file *file_priv);
748 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
749 struct drm_file *file_priv);
750 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
751 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
752 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
753 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
754 extern int i915_vblank_swap(struct drm_device *dev, void *data,
755 struct drm_file *file_priv);
756 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
757
758 void
759 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
760
761 void
762 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
763
764 void intel_enable_asle (struct drm_device *dev);
765
766
767 /* i915_mem.c */
768 extern int i915_mem_alloc(struct drm_device *dev, void *data,
769 struct drm_file *file_priv);
770 extern int i915_mem_free(struct drm_device *dev, void *data,
771 struct drm_file *file_priv);
772 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
773 struct drm_file *file_priv);
774 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
775 struct drm_file *file_priv);
776 extern void i915_mem_takedown(struct mem_block **heap);
777 extern void i915_mem_release(struct drm_device * dev,
778 struct drm_file *file_priv, struct mem_block *heap);
779 /* i915_gem.c */
780 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
781 struct drm_file *file_priv);
782 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
783 struct drm_file *file_priv);
784 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
785 struct drm_file *file_priv);
786 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
787 struct drm_file *file_priv);
788 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
789 struct drm_file *file_priv);
790 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
791 struct drm_file *file_priv);
792 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
793 struct drm_file *file_priv);
794 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
795 struct drm_file *file_priv);
796 int i915_gem_execbuffer(struct drm_device *dev, void *data,
797 struct drm_file *file_priv);
798 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
799 struct drm_file *file_priv);
800 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
801 struct drm_file *file_priv);
802 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
803 struct drm_file *file_priv);
804 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
805 struct drm_file *file_priv);
806 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
807 struct drm_file *file_priv);
808 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
809 struct drm_file *file_priv);
810 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
811 struct drm_file *file_priv);
812 int i915_gem_set_tiling(struct drm_device *dev, void *data,
813 struct drm_file *file_priv);
814 int i915_gem_get_tiling(struct drm_device *dev, void *data,
815 struct drm_file *file_priv);
816 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
817 struct drm_file *file_priv);
818 void i915_gem_load(struct drm_device *dev);
819 int i915_gem_init_object(struct drm_gem_object *obj);
820 void i915_gem_free_object(struct drm_gem_object *obj);
821 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
822 void i915_gem_object_unpin(struct drm_gem_object *obj);
823 int i915_gem_object_unbind(struct drm_gem_object *obj);
824 void i915_gem_release_mmap(struct drm_gem_object *obj);
825 void i915_gem_lastclose(struct drm_device *dev);
826 uint32_t i915_get_gem_seqno(struct drm_device *dev);
827 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
828 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
829 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
830 void i915_gem_retire_requests(struct drm_device *dev);
831 void i915_gem_retire_work_handler(struct work_struct *work);
832 void i915_gem_clflush_object(struct drm_gem_object *obj);
833 int i915_gem_object_set_domain(struct drm_gem_object *obj,
834 uint32_t read_domains,
835 uint32_t write_domain);
836 int i915_gem_init_ringbuffer(struct drm_device *dev);
837 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
838 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
839 unsigned long end);
840 int i915_gem_idle(struct drm_device *dev);
841 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
842 uint32_t flush_domains);
843 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
844 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
845 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
846 int write);
847 int i915_gem_attach_phys_object(struct drm_device *dev,
848 struct drm_gem_object *obj, int id);
849 void i915_gem_detach_phys_object(struct drm_device *dev,
850 struct drm_gem_object *obj);
851 void i915_gem_free_all_phys_object(struct drm_device *dev);
852 int i915_gem_object_get_pages(struct drm_gem_object *obj);
853 void i915_gem_object_put_pages(struct drm_gem_object *obj);
854 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
855 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
856
857 void i915_gem_shrinker_init(void);
858 void i915_gem_shrinker_exit(void);
859
860 /* i915_gem_tiling.c */
861 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
862 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
863 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
864
865 /* i915_gem_debug.c */
866 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
867 const char *where, uint32_t mark);
868 #if WATCH_INACTIVE
869 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
870 #else
871 #define i915_verify_inactive(dev, file, line)
872 #endif
873 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
874 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
875 const char *where, uint32_t mark);
876 void i915_dump_lru(struct drm_device *dev, const char *where);
877
878 /* i915_debugfs.c */
879 int i915_debugfs_init(struct drm_minor *minor);
880 void i915_debugfs_cleanup(struct drm_minor *minor);
881
882 /* i915_suspend.c */
883 extern int i915_save_state(struct drm_device *dev);
884 extern int i915_restore_state(struct drm_device *dev);
885
886 /* i915_suspend.c */
887 extern int i915_save_state(struct drm_device *dev);
888 extern int i915_restore_state(struct drm_device *dev);
889
890 #ifdef CONFIG_ACPI
891 /* i915_opregion.c */
892 extern int intel_opregion_init(struct drm_device *dev, int resume);
893 extern void intel_opregion_free(struct drm_device *dev, int suspend);
894 extern void opregion_asle_intr(struct drm_device *dev);
895 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
896 extern void opregion_enable_asle(struct drm_device *dev);
897 #else
898 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
899 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
900 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
901 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
902 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
903 #endif
904
905 /* modesetting */
906 extern void intel_modeset_init(struct drm_device *dev);
907 extern void intel_modeset_cleanup(struct drm_device *dev);
908 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
909 extern void i8xx_disable_fbc(struct drm_device *dev);
910 extern void g4x_disable_fbc(struct drm_device *dev);
911
912 /**
913 * Lock test for when it's just for synchronization of ring access.
914 *
915 * In that case, we don't need to do it when GEM is initialized as nobody else
916 * has access to the ring.
917 */
918 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
919 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
920 LOCK_TEST_WITH_RETURN(dev, file_priv); \
921 } while (0)
922
923 #define I915_READ(reg) readl(dev_priv->regs + (reg))
924 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
925 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
926 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
927 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
928 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
929 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
930 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
931 #define POSTING_READ(reg) (void)I915_READ(reg)
932
933 #define I915_VERBOSE 0
934
935 #define RING_LOCALS volatile unsigned int *ring_virt__;
936
937 #define BEGIN_LP_RING(n) do { \
938 int bytes__ = 4*(n); \
939 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
940 /* a wrap must occur between instructions so pad beforehand */ \
941 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
942 i915_wrap_ring(dev); \
943 if (unlikely (dev_priv->ring.space < bytes__)) \
944 i915_wait_ring(dev, bytes__, __func__); \
945 ring_virt__ = (unsigned int *) \
946 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
947 dev_priv->ring.tail += bytes__; \
948 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
949 dev_priv->ring.space -= bytes__; \
950 } while (0)
951
952 #define OUT_RING(n) do { \
953 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
954 *ring_virt__++ = (n); \
955 } while (0)
956
957 #define ADVANCE_LP_RING() do { \
958 if (I915_VERBOSE) \
959 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
960 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
961 } while(0)
962
963 /**
964 * Reads a dword out of the status page, which is written to from the command
965 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
966 * MI_STORE_DATA_IMM.
967 *
968 * The following dwords have a reserved meaning:
969 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
970 * 0x04: ring 0 head pointer
971 * 0x05: ring 1 head pointer (915-class)
972 * 0x06: ring 2 head pointer (915-class)
973 * 0x10-0x1b: Context status DWords (GM45)
974 * 0x1f: Last written status offset. (GM45)
975 *
976 * The area from dword 0x20 to 0x3ff is available for driver usage.
977 */
978 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
979 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
980 #define I915_GEM_HWS_INDEX 0x20
981 #define I915_BREADCRUMB_INDEX 0x21
982
983 extern int i915_wrap_ring(struct drm_device * dev);
984 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
985
986 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
987 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
988 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
989 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
990 #define IS_I8XX(dev) (IS_I830(dev) || IS_845G(dev) || IS_I85X(dev) || IS_I865G(dev))
991
992 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
993 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
994 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
995 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
996 (dev)->pci_device == 0x27AE)
997 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
998 (dev)->pci_device == 0x2982 || \
999 (dev)->pci_device == 0x2992 || \
1000 (dev)->pci_device == 0x29A2 || \
1001 (dev)->pci_device == 0x2A02 || \
1002 (dev)->pci_device == 0x2A12 || \
1003 (dev)->pci_device == 0x2A42 || \
1004 (dev)->pci_device == 0x2E02 || \
1005 (dev)->pci_device == 0x2E12 || \
1006 (dev)->pci_device == 0x2E22 || \
1007 (dev)->pci_device == 0x2E32 || \
1008 (dev)->pci_device == 0x2E42 || \
1009 (dev)->pci_device == 0x0042 || \
1010 (dev)->pci_device == 0x0046)
1011
1012 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
1013 (dev)->pci_device == 0x2A12)
1014
1015 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1016
1017 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
1018 (dev)->pci_device == 0x2E12 || \
1019 (dev)->pci_device == 0x2E22 || \
1020 (dev)->pci_device == 0x2E32 || \
1021 (dev)->pci_device == 0x2E42 || \
1022 IS_GM45(dev))
1023
1024 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1025 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1026 #define IS_PINEVIEW(dev) (IS_PINEVIEW_G(dev) || IS_PINEVIEW_M(dev))
1027
1028 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
1029 (dev)->pci_device == 0x29B2 || \
1030 (dev)->pci_device == 0x29D2 || \
1031 (IS_PINEVIEW(dev)))
1032
1033 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1034 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1035 #define IS_IRONLAKE(dev) (IS_IRONLAKE_D(dev) || IS_IRONLAKE_M(dev))
1036
1037 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1038 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1039 IS_IRONLAKE(dev))
1040
1041 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1042 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
1043 IS_PINEVIEW(dev) || IS_IRONLAKE_M(dev))
1044
1045 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1046 IS_IRONLAKE(dev))
1047 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1048 * rows, which changed the alignment requirements and fence programming.
1049 */
1050 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1051 IS_I915GM(dev)))
1052 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1053 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1054 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1055 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1056 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1057 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
1058 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
1059 /* dsparb controlled by hw only */
1060 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1061
1062 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1063 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1064 #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1065 (IS_I9XX(dev) || IS_GM45(dev)) && \
1066 !IS_PINEVIEW(dev) && \
1067 !IS_IRONLAKE(dev))
1068 #define I915_HAS_RC6(dev) (IS_I965GM(dev) || IS_GM45(dev) || IS_IRONLAKE_M(dev))
1069
1070 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
1071
1072 #endif
Linux kernel - Deliverables
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