1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20150117"
61 /* Many gcc seem to no see through this and fall over :( */
63 #define WARN_ON(x) ({ \
64 bool __i915_warn_cond = (x); \
65 if (__builtin_constant_p(__i915_warn_cond)) \
66 BUILD_BUG_ON(__i915_warn_cond); \
67 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
69 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
72 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
73 (long) (x), __func__);
75 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
76 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
77 * which may not necessarily be a user visible problem. This will either
78 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
79 * enable distros and users to tailor their preferred amount of i915 abrt
82 #define I915_STATE_WARN(condition, format...) ({ \
83 int __ret_warn_on = !!(condition); \
84 if (unlikely(__ret_warn_on)) { \
85 if (i915.verbose_state_checks) \
90 unlikely(__ret_warn_on); \
93 #define I915_STATE_WARN_ON(condition) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) { \
96 if (i915.verbose_state_checks) \
97 WARN(1, "WARN_ON(" #condition ")\n"); \
99 DRM_ERROR("WARN_ON(" #condition ")\n"); \
101 unlikely(__ret_warn_on); \
110 I915_MAX_PIPES
= _PIPE_EDP
112 #define pipe_name(p) ((p) + 'A')
121 #define transcoder_name(t) ((t) + 'A')
124 * This is the maximum (across all platforms) number of planes (primary +
125 * sprites) that can be active at the same time on one pipe.
127 * This value doesn't count the cursor plane.
129 #define I915_MAX_PLANES 3
136 #define plane_name(p) ((p) + 'A')
138 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
148 #define port_name(p) ((p) + 'A')
150 #define I915_NUM_PHYS_VLV 2
162 enum intel_display_power_domain
{
166 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
167 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
168 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
169 POWER_DOMAIN_TRANSCODER_A
,
170 POWER_DOMAIN_TRANSCODER_B
,
171 POWER_DOMAIN_TRANSCODER_C
,
172 POWER_DOMAIN_TRANSCODER_EDP
,
173 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
174 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
175 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
176 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
177 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
178 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
179 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
180 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
181 POWER_DOMAIN_PORT_DSI
,
182 POWER_DOMAIN_PORT_CRT
,
183 POWER_DOMAIN_PORT_OTHER
,
192 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
193 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
194 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
195 #define POWER_DOMAIN_TRANSCODER(tran) \
196 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
197 (tran) + POWER_DOMAIN_TRANSCODER_A)
201 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
202 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
212 #define I915_GEM_GPU_DOMAINS \
213 (I915_GEM_DOMAIN_RENDER | \
214 I915_GEM_DOMAIN_SAMPLER | \
215 I915_GEM_DOMAIN_COMMAND | \
216 I915_GEM_DOMAIN_INSTRUCTION | \
217 I915_GEM_DOMAIN_VERTEX)
219 #define for_each_pipe(__dev_priv, __p) \
220 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
221 #define for_each_plane(pipe, p) \
222 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
223 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
225 #define for_each_crtc(dev, crtc) \
226 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
228 #define for_each_intel_crtc(dev, intel_crtc) \
229 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
231 #define for_each_intel_encoder(dev, intel_encoder) \
232 list_for_each_entry(intel_encoder, \
233 &(dev)->mode_config.encoder_list, \
236 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
237 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
238 if ((intel_encoder)->base.crtc == (__crtc))
240 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
241 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
242 if ((intel_connector)->base.encoder == (__encoder))
244 #define for_each_power_domain(domain, mask) \
245 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
246 if ((1 << (domain)) & (mask))
248 struct drm_i915_private
;
249 struct i915_mm_struct
;
250 struct i915_mmu_object
;
253 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
254 /* real shared dpll ids must be >= 0 */
255 DPLL_ID_PCH_PLL_A
= 0,
256 DPLL_ID_PCH_PLL_B
= 1,
261 DPLL_ID_SKL_DPLL1
= 0,
262 DPLL_ID_SKL_DPLL2
= 1,
263 DPLL_ID_SKL_DPLL3
= 2,
265 #define I915_NUM_PLLS 3
267 struct intel_dpll_hw_state
{
279 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
280 * lower part of crtl1 and they get shifted into position when writing
281 * the register. This allows us to easily compare the state to share
285 /* HDMI only, 0 when used for DP */
286 uint32_t cfgcr1
, cfgcr2
;
289 struct intel_shared_dpll_config
{
290 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
291 struct intel_dpll_hw_state hw_state
;
294 struct intel_shared_dpll
{
295 struct intel_shared_dpll_config config
;
296 struct intel_shared_dpll_config
*new_config
;
298 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
299 bool on
; /* is the PLL actually active? Disabled during modeset */
301 /* should match the index in the dev_priv->shared_dplls array */
302 enum intel_dpll_id id
;
303 /* The mode_set hook is optional and should be used together with the
304 * intel_prepare_shared_dpll function. */
305 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
306 struct intel_shared_dpll
*pll
);
307 void (*enable
)(struct drm_i915_private
*dev_priv
,
308 struct intel_shared_dpll
*pll
);
309 void (*disable
)(struct drm_i915_private
*dev_priv
,
310 struct intel_shared_dpll
*pll
);
311 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
312 struct intel_shared_dpll
*pll
,
313 struct intel_dpll_hw_state
*hw_state
);
321 /* Used by dp and fdi links */
322 struct intel_link_m_n
{
330 void intel_link_compute_m_n(int bpp
, int nlanes
,
331 int pixel_clock
, int link_clock
,
332 struct intel_link_m_n
*m_n
);
334 /* Interface history:
337 * 1.2: Add Power Management
338 * 1.3: Add vblank support
339 * 1.4: Fix cmdbuffer path, add heap destroy
340 * 1.5: Add vblank pipe configuration
341 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
342 * - Support vertical blank on secondary display pipe
344 #define DRIVER_MAJOR 1
345 #define DRIVER_MINOR 6
346 #define DRIVER_PATCHLEVEL 0
348 #define WATCH_LISTS 0
350 struct opregion_header
;
351 struct opregion_acpi
;
352 struct opregion_swsci
;
353 struct opregion_asle
;
355 struct intel_opregion
{
356 struct opregion_header __iomem
*header
;
357 struct opregion_acpi __iomem
*acpi
;
358 struct opregion_swsci __iomem
*swsci
;
359 u32 swsci_gbda_sub_functions
;
360 u32 swsci_sbcb_sub_functions
;
361 struct opregion_asle __iomem
*asle
;
363 u32 __iomem
*lid_state
;
364 struct work_struct asle_work
;
366 #define OPREGION_SIZE (8*1024)
368 struct intel_overlay
;
369 struct intel_overlay_error_state
;
371 #define I915_FENCE_REG_NONE -1
372 #define I915_MAX_NUM_FENCES 32
373 /* 32 fences + sign bit for FENCE_REG_NONE */
374 #define I915_MAX_NUM_FENCE_BITS 6
376 struct drm_i915_fence_reg
{
377 struct list_head lru_list
;
378 struct drm_i915_gem_object
*obj
;
382 struct sdvo_device_mapping
{
391 struct intel_display_error_state
;
393 struct drm_i915_error_state
{
401 /* Generic register state */
409 u32 error
; /* gen6+ */
410 u32 err_int
; /* gen7 */
416 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
417 u64 fence
[I915_MAX_NUM_FENCES
];
418 struct intel_overlay_error_state
*overlay
;
419 struct intel_display_error_state
*display
;
420 struct drm_i915_error_object
*semaphore_obj
;
422 struct drm_i915_error_ring
{
424 /* Software tracked state */
427 enum intel_ring_hangcheck_action hangcheck_action
;
430 /* our own tracking of ring head and tail */
434 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
452 u32 rc_psmi
; /* sleep state */
453 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
455 struct drm_i915_error_object
{
459 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
461 struct drm_i915_error_request
{
476 char comm
[TASK_COMM_LEN
];
477 } ring
[I915_NUM_RINGS
];
479 struct drm_i915_error_buffer
{
486 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
494 } **active_bo
, **pinned_bo
;
496 u32
*active_bo_count
, *pinned_bo_count
;
500 struct intel_connector
;
501 struct intel_encoder
;
502 struct intel_crtc_config
;
503 struct intel_plane_config
;
508 struct drm_i915_display_funcs
{
509 bool (*fbc_enabled
)(struct drm_device
*dev
);
510 void (*enable_fbc
)(struct drm_crtc
*crtc
);
511 void (*disable_fbc
)(struct drm_device
*dev
);
512 int (*get_display_clock_speed
)(struct drm_device
*dev
);
513 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
515 * find_dpll() - Find the best values for the PLL
516 * @limit: limits for the PLL
517 * @crtc: current CRTC
518 * @target: target frequency in kHz
519 * @refclk: reference clock frequency in kHz
520 * @match_clock: if provided, @best_clock P divider must
521 * match the P divider from @match_clock
522 * used for LVDS downclocking
523 * @best_clock: best PLL values found
525 * Returns true on success, false on failure.
527 bool (*find_dpll
)(const struct intel_limit
*limit
,
528 struct intel_crtc
*crtc
,
529 int target
, int refclk
,
530 struct dpll
*match_clock
,
531 struct dpll
*best_clock
);
532 void (*update_wm
)(struct drm_crtc
*crtc
);
533 void (*update_sprite_wm
)(struct drm_plane
*plane
,
534 struct drm_crtc
*crtc
,
535 uint32_t sprite_width
, uint32_t sprite_height
,
536 int pixel_size
, bool enable
, bool scaled
);
537 void (*modeset_global_resources
)(struct drm_device
*dev
);
538 /* Returns the active state of the crtc, and if the crtc is active,
539 * fills out the pipe-config with the hw state. */
540 bool (*get_pipe_config
)(struct intel_crtc
*,
541 struct intel_crtc_config
*);
542 void (*get_plane_config
)(struct intel_crtc
*,
543 struct intel_plane_config
*);
544 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
);
545 void (*crtc_enable
)(struct drm_crtc
*crtc
);
546 void (*crtc_disable
)(struct drm_crtc
*crtc
);
547 void (*off
)(struct drm_crtc
*crtc
);
548 void (*audio_codec_enable
)(struct drm_connector
*connector
,
549 struct intel_encoder
*encoder
,
550 struct drm_display_mode
*mode
);
551 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
552 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
553 void (*init_clock_gating
)(struct drm_device
*dev
);
554 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
555 struct drm_framebuffer
*fb
,
556 struct drm_i915_gem_object
*obj
,
557 struct intel_engine_cs
*ring
,
559 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
560 struct drm_framebuffer
*fb
,
562 void (*hpd_irq_setup
)(struct drm_device
*dev
);
563 /* clock updates for mode set */
565 /* render clock increase/decrease */
566 /* display clock increase/decrease */
567 /* pll clock increase/decrease */
569 int (*setup_backlight
)(struct intel_connector
*connector
, enum pipe pipe
);
570 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
571 void (*set_backlight
)(struct intel_connector
*connector
,
573 void (*disable_backlight
)(struct intel_connector
*connector
);
574 void (*enable_backlight
)(struct intel_connector
*connector
);
577 struct intel_uncore_funcs
{
578 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
580 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
583 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
584 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
585 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
586 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
588 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
589 uint8_t val
, bool trace
);
590 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
591 uint16_t val
, bool trace
);
592 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
593 uint32_t val
, bool trace
);
594 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
595 uint64_t val
, bool trace
);
598 struct intel_uncore
{
599 spinlock_t lock
; /** lock is also taken in irq contexts. */
601 struct intel_uncore_funcs funcs
;
604 unsigned forcewake_count
;
606 unsigned fw_rendercount
;
607 unsigned fw_mediacount
;
608 unsigned fw_blittercount
;
610 struct timer_list force_wake_timer
;
613 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
614 func(is_mobile) sep \
617 func(is_i945gm) sep \
619 func(need_gfx_hws) sep \
621 func(is_pineview) sep \
622 func(is_broadwater) sep \
623 func(is_crestline) sep \
624 func(is_ivybridge) sep \
625 func(is_valleyview) sep \
626 func(is_haswell) sep \
627 func(is_skylake) sep \
628 func(is_preliminary) sep \
630 func(has_pipe_cxsr) sep \
631 func(has_hotplug) sep \
632 func(cursor_needs_physical) sep \
633 func(has_overlay) sep \
634 func(overlay_needs_physical) sep \
635 func(supports_tv) sep \
640 #define DEFINE_FLAG(name) u8 name:1
641 #define SEP_SEMICOLON ;
643 struct intel_device_info
{
644 u32 display_mmio_offset
;
647 u8 num_sprites
[I915_MAX_PIPES
];
649 u8 ring_mask
; /* Rings supported by the HW */
650 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
651 /* Register offsets for the various display pipes and transcoders */
652 int pipe_offsets
[I915_MAX_TRANSCODERS
];
653 int trans_offsets
[I915_MAX_TRANSCODERS
];
654 int palette_offsets
[I915_MAX_PIPES
];
655 int cursor_offsets
[I915_MAX_PIPES
];
656 unsigned int eu_total
;
662 enum i915_cache_level
{
664 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
665 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
666 caches, eg sampler/render caches, and the
667 large Last-Level-Cache. LLC is coherent with
668 the CPU, but L3 is only visible to the GPU. */
669 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
672 struct i915_ctx_hang_stats
{
673 /* This context had batch pending when hang was declared */
674 unsigned batch_pending
;
676 /* This context had batch active when hang was declared */
677 unsigned batch_active
;
679 /* Time when this context was last blamed for a GPU reset */
680 unsigned long guilty_ts
;
682 /* If the contexts causes a second GPU hang within this time,
683 * it is permanently banned from submitting any more work.
685 unsigned long ban_period_seconds
;
687 /* This context is banned to submit more work */
691 /* This must match up with the value previously used for execbuf2.rsvd1. */
692 #define DEFAULT_CONTEXT_HANDLE 0
694 * struct intel_context - as the name implies, represents a context.
695 * @ref: reference count.
696 * @user_handle: userspace tracking identity for this context.
697 * @remap_slice: l3 row remapping information.
698 * @file_priv: filp associated with this context (NULL for global default
700 * @hang_stats: information about the role of this context in possible GPU
702 * @vm: virtual memory space used by this context.
703 * @legacy_hw_ctx: render context backing object and whether it is correctly
704 * initialized (legacy ring submission mechanism only).
705 * @link: link in the global list of contexts.
707 * Contexts are memory images used by the hardware to store copies of their
710 struct intel_context
{
714 struct drm_i915_file_private
*file_priv
;
715 struct i915_ctx_hang_stats hang_stats
;
716 struct i915_hw_ppgtt
*ppgtt
;
718 /* Legacy ring buffer submission */
720 struct drm_i915_gem_object
*rcs_state
;
725 bool rcs_initialized
;
727 struct drm_i915_gem_object
*state
;
728 struct intel_ringbuffer
*ringbuf
;
730 } engine
[I915_NUM_RINGS
];
732 struct list_head link
;
742 struct drm_mm_node compressed_fb
;
743 struct drm_mm_node
*compressed_llb
;
747 /* Tracks whether the HW is actually enabled, not whether the feature is
751 /* On gen8 some rings cannont perform fbc clean operation so for now
752 * we are doing this on SW with mmio.
753 * This variable works in the opposite information direction
754 * of ring->fbc_dirty telling software on frontbuffer tracking
755 * to perform the cache clean on sw side.
757 bool need_sw_cache_clean
;
759 struct intel_fbc_work
{
760 struct delayed_work work
;
761 struct drm_crtc
*crtc
;
762 struct drm_framebuffer
*fb
;
766 FBC_OK
, /* FBC is enabled */
767 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
768 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
769 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
770 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
771 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
772 FBC_BAD_PLANE
, /* fbc not supported on plane */
773 FBC_NOT_TILED
, /* buffer not tiled */
774 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
776 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
781 * HIGH_RR is the highest eDP panel refresh rate read from EDID
782 * LOW_RR is the lowest eDP panel refresh rate found from EDID
783 * parsing for same resolution.
785 enum drrs_refresh_rate_type
{
788 DRRS_MAX_RR
, /* RR count */
791 enum drrs_support_type
{
792 DRRS_NOT_SUPPORTED
= 0,
793 STATIC_DRRS_SUPPORT
= 1,
794 SEAMLESS_DRRS_SUPPORT
= 2
800 struct delayed_work work
;
802 unsigned busy_frontbuffer_bits
;
803 enum drrs_refresh_rate_type refresh_rate_type
;
804 enum drrs_support_type type
;
811 struct intel_dp
*enabled
;
813 struct delayed_work work
;
814 unsigned busy_frontbuffer_bits
;
819 PCH_NONE
= 0, /* No PCH present */
820 PCH_IBX
, /* Ibexpeak PCH */
821 PCH_CPT
, /* Cougarpoint PCH */
822 PCH_LPT
, /* Lynxpoint PCH */
823 PCH_SPT
, /* Sunrisepoint PCH */
827 enum intel_sbi_destination
{
832 #define QUIRK_PIPEA_FORCE (1<<0)
833 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
834 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
835 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
836 #define QUIRK_PIPEB_FORCE (1<<4)
837 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
840 struct intel_fbc_work
;
843 struct i2c_adapter adapter
;
847 struct i2c_algo_bit_data bit_algo
;
848 struct drm_i915_private
*dev_priv
;
851 struct i915_suspend_saved_registers
{
872 u32 saveTRANS_HTOTAL_A
;
873 u32 saveTRANS_HBLANK_A
;
874 u32 saveTRANS_HSYNC_A
;
875 u32 saveTRANS_VTOTAL_A
;
876 u32 saveTRANS_VBLANK_A
;
877 u32 saveTRANS_VSYNC_A
;
885 u32 savePFIT_PGM_RATIOS
;
886 u32 saveBLC_HIST_CTL
;
888 u32 saveBLC_PWM_CTL2
;
889 u32 saveBLC_CPU_PWM_CTL
;
890 u32 saveBLC_CPU_PWM_CTL2
;
903 u32 saveTRANS_HTOTAL_B
;
904 u32 saveTRANS_HBLANK_B
;
905 u32 saveTRANS_HSYNC_B
;
906 u32 saveTRANS_VTOTAL_B
;
907 u32 saveTRANS_VBLANK_B
;
908 u32 saveTRANS_VSYNC_B
;
922 u32 savePP_ON_DELAYS
;
923 u32 savePP_OFF_DELAYS
;
931 u32 savePFIT_CONTROL
;
932 u32 save_palette_a
[256];
933 u32 save_palette_b
[256];
944 u32 saveCACHE_MODE_0
;
945 u32 saveMI_ARB_STATE
;
956 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
967 u32 savePIPEA_GMCH_DATA_M
;
968 u32 savePIPEB_GMCH_DATA_M
;
969 u32 savePIPEA_GMCH_DATA_N
;
970 u32 savePIPEB_GMCH_DATA_N
;
971 u32 savePIPEA_DP_LINK_M
;
972 u32 savePIPEB_DP_LINK_M
;
973 u32 savePIPEA_DP_LINK_N
;
974 u32 savePIPEB_DP_LINK_N
;
985 u32 savePCH_DREF_CONTROL
;
986 u32 saveDISP_ARB_CTL
;
987 u32 savePIPEA_DATA_M1
;
988 u32 savePIPEA_DATA_N1
;
989 u32 savePIPEA_LINK_M1
;
990 u32 savePIPEA_LINK_N1
;
991 u32 savePIPEB_DATA_M1
;
992 u32 savePIPEB_DATA_N1
;
993 u32 savePIPEB_LINK_M1
;
994 u32 savePIPEB_LINK_N1
;
995 u32 saveMCHBAR_RENDER_STANDBY
;
996 u32 savePCH_PORT_HOTPLUG
;
1000 struct vlv_s0ix_state
{
1007 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1008 u32 media_max_req_count
;
1009 u32 gfx_max_req_count
;
1035 u32 rp_down_timeout
;
1041 /* Display 1 CZ domain */
1046 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1048 /* GT SA CZ domain */
1055 /* Display 2 CZ domain */
1058 u32 clock_gate_dis2
;
1061 struct intel_rps_ei
{
1067 struct intel_gen6_power_mgmt
{
1069 * work, interrupts_enabled and pm_iir are protected by
1070 * dev_priv->irq_lock
1072 struct work_struct work
;
1073 bool interrupts_enabled
;
1076 /* Frequencies are stored in potentially platform dependent multiples.
1077 * In other words, *_freq needs to be multiplied by X to be interesting.
1078 * Soft limits are those which are used for the dynamic reclocking done
1079 * by the driver (raise frequencies under heavy loads, and lower for
1080 * lighter loads). Hard limits are those imposed by the hardware.
1082 * A distinction is made for overclocking, which is never enabled by
1083 * default, and is considered to be above the hard limit if it's
1086 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1087 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1088 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1089 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1090 u8 min_freq
; /* AKA RPn. Minimum frequency */
1091 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1092 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1093 u8 rp0_freq
; /* Non-overclocked max frequency. */
1096 u32 ei_interrupt_count
;
1099 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1102 struct delayed_work delayed_resume_work
;
1104 /* manual wa residency calculations */
1105 struct intel_rps_ei up_ei
, down_ei
;
1108 * Protects RPS/RC6 register access and PCU communication.
1109 * Must be taken after struct_mutex if nested.
1111 struct mutex hw_lock
;
1114 /* defined intel_pm.c */
1115 extern spinlock_t mchdev_lock
;
1117 struct intel_ilk_power_mgmt
{
1125 unsigned long last_time1
;
1126 unsigned long chipset_power
;
1129 unsigned long gfx_power
;
1135 struct drm_i915_gem_object
*pwrctx
;
1136 struct drm_i915_gem_object
*renderctx
;
1139 struct drm_i915_private
;
1140 struct i915_power_well
;
1142 struct i915_power_well_ops
{
1144 * Synchronize the well's hw state to match the current sw state, for
1145 * example enable/disable it based on the current refcount. Called
1146 * during driver init and resume time, possibly after first calling
1147 * the enable/disable handlers.
1149 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1150 struct i915_power_well
*power_well
);
1152 * Enable the well and resources that depend on it (for example
1153 * interrupts located on the well). Called after the 0->1 refcount
1156 void (*enable
)(struct drm_i915_private
*dev_priv
,
1157 struct i915_power_well
*power_well
);
1159 * Disable the well and resources that depend on it. Called after
1160 * the 1->0 refcount transition.
1162 void (*disable
)(struct drm_i915_private
*dev_priv
,
1163 struct i915_power_well
*power_well
);
1164 /* Returns the hw enabled state. */
1165 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1166 struct i915_power_well
*power_well
);
1169 /* Power well structure for haswell */
1170 struct i915_power_well
{
1173 /* power well enable/disable usage count */
1175 /* cached hw enabled state */
1177 unsigned long domains
;
1179 const struct i915_power_well_ops
*ops
;
1182 struct i915_power_domains
{
1184 * Power wells needed for initialization at driver init and suspend
1185 * time are on. They are kept on until after the first modeset.
1189 int power_well_count
;
1192 int domain_use_count
[POWER_DOMAIN_NUM
];
1193 struct i915_power_well
*power_wells
;
1196 #define MAX_L3_SLICES 2
1197 struct intel_l3_parity
{
1198 u32
*remap_info
[MAX_L3_SLICES
];
1199 struct work_struct error_work
;
1203 struct i915_gem_batch_pool
{
1204 struct drm_device
*dev
;
1205 struct list_head cache_list
;
1208 struct i915_gem_mm
{
1209 /** Memory allocator for GTT stolen memory */
1210 struct drm_mm stolen
;
1211 /** List of all objects in gtt_space. Used to restore gtt
1212 * mappings on resume */
1213 struct list_head bound_list
;
1215 * List of objects which are not bound to the GTT (thus
1216 * are idle and not used by the GPU) but still have
1217 * (presumably uncached) pages still attached.
1219 struct list_head unbound_list
;
1222 * A pool of objects to use as shadow copies of client batch buffers
1223 * when the command parser is enabled. Prevents the client from
1224 * modifying the batch contents after software parsing.
1226 struct i915_gem_batch_pool batch_pool
;
1228 /** Usable portion of the GTT for GEM */
1229 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1231 /** PPGTT used for aliasing the PPGTT with the GTT */
1232 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1234 struct notifier_block oom_notifier
;
1235 struct shrinker shrinker
;
1236 bool shrinker_no_lock_stealing
;
1238 /** LRU list of objects with fence regs on them. */
1239 struct list_head fence_list
;
1242 * We leave the user IRQ off as much as possible,
1243 * but this means that requests will finish and never
1244 * be retired once the system goes idle. Set a timer to
1245 * fire periodically while the ring is running. When it
1246 * fires, go retire requests.
1248 struct delayed_work retire_work
;
1251 * When we detect an idle GPU, we want to turn on
1252 * powersaving features. So once we see that there
1253 * are no more requests outstanding and no more
1254 * arrive within a small period of time, we fire
1255 * off the idle_work.
1257 struct delayed_work idle_work
;
1260 * Are we in a non-interruptible section of code like
1266 * Is the GPU currently considered idle, or busy executing userspace
1267 * requests? Whilst idle, we attempt to power down the hardware and
1268 * display clocks. In order to reduce the effect on performance, there
1269 * is a slight delay before we do so.
1273 /* the indicator for dispatch video commands on two BSD rings */
1274 int bsd_ring_dispatch_index
;
1276 /** Bit 6 swizzling required for X tiling */
1277 uint32_t bit_6_swizzle_x
;
1278 /** Bit 6 swizzling required for Y tiling */
1279 uint32_t bit_6_swizzle_y
;
1281 /* accounting, useful for userland debugging */
1282 spinlock_t object_stat_lock
;
1283 size_t object_memory
;
1287 struct drm_i915_error_state_buf
{
1288 struct drm_i915_private
*i915
;
1297 struct i915_error_state_file_priv
{
1298 struct drm_device
*dev
;
1299 struct drm_i915_error_state
*error
;
1302 struct i915_gpu_error
{
1303 /* For hangcheck timer */
1304 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1305 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1306 /* Hang gpu twice in this window and your context gets banned */
1307 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1309 struct timer_list hangcheck_timer
;
1311 /* For reset and error_state handling. */
1313 /* Protected by the above dev->gpu_error.lock. */
1314 struct drm_i915_error_state
*first_error
;
1315 struct work_struct work
;
1318 unsigned long missed_irq_rings
;
1321 * State variable controlling the reset flow and count
1323 * This is a counter which gets incremented when reset is triggered,
1324 * and again when reset has been handled. So odd values (lowest bit set)
1325 * means that reset is in progress and even values that
1326 * (reset_counter >> 1):th reset was successfully completed.
1328 * If reset is not completed succesfully, the I915_WEDGE bit is
1329 * set meaning that hardware is terminally sour and there is no
1330 * recovery. All waiters on the reset_queue will be woken when
1333 * This counter is used by the wait_seqno code to notice that reset
1334 * event happened and it needs to restart the entire ioctl (since most
1335 * likely the seqno it waited for won't ever signal anytime soon).
1337 * This is important for lock-free wait paths, where no contended lock
1338 * naturally enforces the correct ordering between the bail-out of the
1339 * waiter and the gpu reset work code.
1341 atomic_t reset_counter
;
1343 #define I915_RESET_IN_PROGRESS_FLAG 1
1344 #define I915_WEDGED (1 << 31)
1347 * Waitqueue to signal when the reset has completed. Used by clients
1348 * that wait for dev_priv->mm.wedged to settle.
1350 wait_queue_head_t reset_queue
;
1352 /* Userspace knobs for gpu hang simulation;
1353 * combines both a ring mask, and extra flags
1356 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1357 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1359 /* For missed irq/seqno simulation. */
1360 unsigned int test_irq_rings
;
1362 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1363 bool reload_in_reset
;
1366 enum modeset_restore
{
1367 MODESET_ON_LID_OPEN
,
1372 struct ddi_vbt_port_info
{
1374 * This is an index in the HDMI/DVI DDI buffer translation table.
1375 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1376 * populate this field.
1378 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1379 uint8_t hdmi_level_shift
;
1381 uint8_t supports_dvi
:1;
1382 uint8_t supports_hdmi
:1;
1383 uint8_t supports_dp
:1;
1386 enum psr_lines_to_wait
{
1387 PSR_0_LINES_TO_WAIT
= 0,
1389 PSR_4_LINES_TO_WAIT
,
1393 struct intel_vbt_data
{
1394 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1395 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1398 unsigned int int_tv_support
:1;
1399 unsigned int lvds_dither
:1;
1400 unsigned int lvds_vbt
:1;
1401 unsigned int int_crt_support
:1;
1402 unsigned int lvds_use_ssc
:1;
1403 unsigned int display_clock_mode
:1;
1404 unsigned int fdi_rx_polarity_inverted
:1;
1405 unsigned int has_mipi
:1;
1407 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1409 enum drrs_support_type drrs_type
;
1414 int edp_preemphasis
;
1416 bool edp_initialized
;
1419 struct edp_power_seq edp_pps
;
1423 bool require_aux_wakeup
;
1425 enum psr_lines_to_wait lines_to_wait
;
1426 int tp1_wakeup_time
;
1427 int tp2_tp3_wakeup_time
;
1433 bool active_low_pwm
;
1434 u8 min_brightness
; /* min_brightness/255 of max */
1441 struct mipi_config
*config
;
1442 struct mipi_pps_data
*pps
;
1446 u8
*sequence
[MIPI_SEQ_MAX
];
1452 union child_device_config
*child_dev
;
1454 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1457 enum intel_ddb_partitioning
{
1459 INTEL_DDB_PART_5_6
, /* IVB+ */
1462 struct intel_wm_level
{
1470 struct ilk_wm_values
{
1471 uint32_t wm_pipe
[3];
1473 uint32_t wm_lp_spr
[3];
1474 uint32_t wm_linetime
[3];
1476 enum intel_ddb_partitioning partitioning
;
1479 struct skl_ddb_entry
{
1480 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1483 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1485 return entry
->end
- entry
->start
;
1488 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1489 const struct skl_ddb_entry
*e2
)
1491 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1497 struct skl_ddb_allocation
{
1498 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1499 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1500 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1503 struct skl_wm_values
{
1504 bool dirty
[I915_MAX_PIPES
];
1505 struct skl_ddb_allocation ddb
;
1506 uint32_t wm_linetime
[I915_MAX_PIPES
];
1507 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1508 uint32_t cursor
[I915_MAX_PIPES
][8];
1509 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1510 uint32_t cursor_trans
[I915_MAX_PIPES
];
1513 struct skl_wm_level
{
1514 bool plane_en
[I915_MAX_PLANES
];
1516 uint16_t plane_res_b
[I915_MAX_PLANES
];
1517 uint8_t plane_res_l
[I915_MAX_PLANES
];
1518 uint16_t cursor_res_b
;
1519 uint8_t cursor_res_l
;
1523 * This struct helps tracking the state needed for runtime PM, which puts the
1524 * device in PCI D3 state. Notice that when this happens, nothing on the
1525 * graphics device works, even register access, so we don't get interrupts nor
1528 * Every piece of our code that needs to actually touch the hardware needs to
1529 * either call intel_runtime_pm_get or call intel_display_power_get with the
1530 * appropriate power domain.
1532 * Our driver uses the autosuspend delay feature, which means we'll only really
1533 * suspend if we stay with zero refcount for a certain amount of time. The
1534 * default value is currently very conservative (see intel_runtime_pm_enable), but
1535 * it can be changed with the standard runtime PM files from sysfs.
1537 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1538 * goes back to false exactly before we reenable the IRQs. We use this variable
1539 * to check if someone is trying to enable/disable IRQs while they're supposed
1540 * to be disabled. This shouldn't happen and we'll print some error messages in
1543 * For more, read the Documentation/power/runtime_pm.txt.
1545 struct i915_runtime_pm
{
1550 enum intel_pipe_crc_source
{
1551 INTEL_PIPE_CRC_SOURCE_NONE
,
1552 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1553 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1554 INTEL_PIPE_CRC_SOURCE_PF
,
1555 INTEL_PIPE_CRC_SOURCE_PIPE
,
1556 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1557 INTEL_PIPE_CRC_SOURCE_TV
,
1558 INTEL_PIPE_CRC_SOURCE_DP_B
,
1559 INTEL_PIPE_CRC_SOURCE_DP_C
,
1560 INTEL_PIPE_CRC_SOURCE_DP_D
,
1561 INTEL_PIPE_CRC_SOURCE_AUTO
,
1562 INTEL_PIPE_CRC_SOURCE_MAX
,
1565 struct intel_pipe_crc_entry
{
1570 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1571 struct intel_pipe_crc
{
1573 bool opened
; /* exclusive access to the result file */
1574 struct intel_pipe_crc_entry
*entries
;
1575 enum intel_pipe_crc_source source
;
1577 wait_queue_head_t wq
;
1580 struct i915_frontbuffer_tracking
{
1584 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1591 struct i915_wa_reg
{
1594 /* bitmask representing WA bits */
1598 #define I915_MAX_WA_REGS 16
1600 struct i915_workarounds
{
1601 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1605 struct drm_i915_private
{
1606 struct drm_device
*dev
;
1607 struct kmem_cache
*slab
;
1609 const struct intel_device_info info
;
1611 int relative_constants_mode
;
1615 struct intel_uncore uncore
;
1617 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1620 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1621 * controller on different i2c buses. */
1622 struct mutex gmbus_mutex
;
1625 * Base address of the gmbus and gpio block.
1627 uint32_t gpio_mmio_base
;
1629 /* MMIO base address for MIPI regs */
1630 uint32_t mipi_mmio_base
;
1632 wait_queue_head_t gmbus_wait_queue
;
1634 struct pci_dev
*bridge_dev
;
1635 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1636 struct drm_i915_gem_object
*semaphore_obj
;
1637 uint32_t last_seqno
, next_seqno
;
1639 struct drm_dma_handle
*status_page_dmah
;
1640 struct resource mch_res
;
1642 /* protects the irq masks */
1643 spinlock_t irq_lock
;
1645 /* protects the mmio flip data */
1646 spinlock_t mmio_flip_lock
;
1648 bool display_irqs_enabled
;
1650 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1651 struct pm_qos_request pm_qos
;
1653 /* DPIO indirect register protection */
1654 struct mutex dpio_lock
;
1656 /** Cached value of IMR to avoid reads in updating the bitfield */
1659 u32 de_irq_mask
[I915_MAX_PIPES
];
1664 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1666 struct work_struct hotplug_work
;
1668 unsigned long hpd_last_jiffies
;
1673 HPD_MARK_DISABLED
= 2
1675 } hpd_stats
[HPD_NUM_PINS
];
1677 struct delayed_work hotplug_reenable_work
;
1679 struct i915_fbc fbc
;
1680 struct i915_drrs drrs
;
1681 struct intel_opregion opregion
;
1682 struct intel_vbt_data vbt
;
1684 bool preserve_bios_swizzle
;
1687 struct intel_overlay
*overlay
;
1689 /* backlight registers and fields in struct intel_panel */
1690 struct mutex backlight_lock
;
1693 bool no_aux_handshake
;
1695 /* protects panel power sequencer state */
1696 struct mutex pps_mutex
;
1698 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1699 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1700 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1702 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1703 unsigned int vlv_cdclk_freq
;
1704 unsigned int hpll_freq
;
1707 * wq - Driver workqueue for GEM.
1709 * NOTE: Work items scheduled here are not allowed to grab any modeset
1710 * locks, for otherwise the flushing done in the pageflip code will
1711 * result in deadlocks.
1713 struct workqueue_struct
*wq
;
1715 /* Display functions */
1716 struct drm_i915_display_funcs display
;
1718 /* PCH chipset type */
1719 enum intel_pch pch_type
;
1720 unsigned short pch_id
;
1722 unsigned long quirks
;
1724 enum modeset_restore modeset_restore
;
1725 struct mutex modeset_restore_lock
;
1727 struct list_head vm_list
; /* Global list of all address spaces */
1728 struct i915_gtt gtt
; /* VM representing the global address space */
1730 struct i915_gem_mm mm
;
1731 DECLARE_HASHTABLE(mm_structs
, 7);
1732 struct mutex mm_lock
;
1734 /* Kernel Modesetting */
1736 struct sdvo_device_mapping sdvo_mappings
[2];
1738 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1739 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1740 wait_queue_head_t pending_flip_queue
;
1742 #ifdef CONFIG_DEBUG_FS
1743 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1746 int num_shared_dpll
;
1747 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1748 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1750 struct i915_workarounds workarounds
;
1752 /* Reclocking support */
1753 bool render_reclock_avail
;
1754 bool lvds_downclock_avail
;
1755 /* indicates the reduced downclock for LVDS*/
1758 struct i915_frontbuffer_tracking fb_tracking
;
1762 bool mchbar_need_disable
;
1764 struct intel_l3_parity l3_parity
;
1766 /* Cannot be determined by PCIID. You must always read a register. */
1769 /* gen6+ rps state */
1770 struct intel_gen6_power_mgmt rps
;
1772 /* ilk-only ips/rps state. Everything in here is protected by the global
1773 * mchdev_lock in intel_pm.c */
1774 struct intel_ilk_power_mgmt ips
;
1776 struct i915_power_domains power_domains
;
1778 struct i915_psr psr
;
1780 struct i915_gpu_error gpu_error
;
1782 struct drm_i915_gem_object
*vlv_pctx
;
1784 #ifdef CONFIG_DRM_I915_FBDEV
1785 /* list of fbdev register on this device */
1786 struct intel_fbdev
*fbdev
;
1787 struct work_struct fbdev_suspend_work
;
1790 struct drm_property
*broadcast_rgb_property
;
1791 struct drm_property
*force_audio_property
;
1793 /* hda/i915 audio component */
1794 bool audio_component_registered
;
1796 uint32_t hw_context_size
;
1797 struct list_head context_list
;
1802 struct i915_suspend_saved_registers regfile
;
1803 struct vlv_s0ix_state vlv_s0ix_state
;
1807 * Raw watermark latency values:
1808 * in 0.1us units for WM0,
1809 * in 0.5us units for WM1+.
1812 uint16_t pri_latency
[5];
1814 uint16_t spr_latency
[5];
1816 uint16_t cur_latency
[5];
1818 * Raw watermark memory latency values
1819 * for SKL for all 8 levels
1822 uint16_t skl_latency
[8];
1825 * The skl_wm_values structure is a bit too big for stack
1826 * allocation, so we keep the staging struct where we store
1827 * intermediate results here instead.
1829 struct skl_wm_values skl_results
;
1831 /* current hardware state */
1833 struct ilk_wm_values hw
;
1834 struct skl_wm_values skl_hw
;
1838 struct i915_runtime_pm pm
;
1840 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1841 u32 long_hpd_port_mask
;
1842 u32 short_hpd_port_mask
;
1843 struct work_struct dig_port_work
;
1846 * if we get a HPD irq from DP and a HPD irq from non-DP
1847 * the non-DP HPD could block the workqueue on a mode config
1848 * mutex getting, that userspace may have taken. However
1849 * userspace is waiting on the DP workqueue to run which is
1850 * blocked behind the non-DP one.
1852 struct workqueue_struct
*dp_wq
;
1854 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1856 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1857 struct intel_engine_cs
*ring
,
1858 struct intel_context
*ctx
,
1859 struct drm_i915_gem_execbuffer2
*args
,
1860 struct list_head
*vmas
,
1861 struct drm_i915_gem_object
*batch_obj
,
1862 u64 exec_start
, u32 flags
);
1863 int (*init_rings
)(struct drm_device
*dev
);
1864 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1865 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1868 uint32_t request_uniq
;
1871 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1872 * will be rejected. Instead look for a better place.
1876 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1878 return dev
->dev_private
;
1881 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1883 return to_i915(dev_get_drvdata(dev
));
1886 /* Iterate over initialised rings */
1887 #define for_each_ring(ring__, dev_priv__, i__) \
1888 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1889 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1891 enum hdmi_force_audio
{
1892 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1893 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1894 HDMI_AUDIO_AUTO
, /* trust EDID */
1895 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1898 #define I915_GTT_OFFSET_NONE ((u32)-1)
1900 struct drm_i915_gem_object_ops
{
1901 /* Interface between the GEM object and its backing storage.
1902 * get_pages() is called once prior to the use of the associated set
1903 * of pages before to binding them into the GTT, and put_pages() is
1904 * called after we no longer need them. As we expect there to be
1905 * associated cost with migrating pages between the backing storage
1906 * and making them available for the GPU (e.g. clflush), we may hold
1907 * onto the pages after they are no longer referenced by the GPU
1908 * in case they may be used again shortly (for example migrating the
1909 * pages to a different memory domain within the GTT). put_pages()
1910 * will therefore most likely be called when the object itself is
1911 * being released or under memory pressure (where we attempt to
1912 * reap pages for the shrinker).
1914 int (*get_pages
)(struct drm_i915_gem_object
*);
1915 void (*put_pages
)(struct drm_i915_gem_object
*);
1916 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1917 void (*release
)(struct drm_i915_gem_object
*);
1921 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1922 * considered to be the frontbuffer for the given plane interface-vise. This
1923 * doesn't mean that the hw necessarily already scans it out, but that any
1924 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1926 * We have one bit per pipe and per scanout plane type.
1928 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1929 #define INTEL_FRONTBUFFER_BITS \
1930 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1931 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1932 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1933 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1934 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1935 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1936 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1937 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1938 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1939 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1940 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1942 struct drm_i915_gem_object
{
1943 struct drm_gem_object base
;
1945 const struct drm_i915_gem_object_ops
*ops
;
1947 /** List of VMAs backed by this object */
1948 struct list_head vma_list
;
1950 /** Stolen memory for this object, instead of being backed by shmem. */
1951 struct drm_mm_node
*stolen
;
1952 struct list_head global_list
;
1954 struct list_head ring_list
;
1955 /** Used in execbuf to temporarily hold a ref */
1956 struct list_head obj_exec_link
;
1958 struct list_head batch_pool_list
;
1961 * This is set if the object is on the active lists (has pending
1962 * rendering and so a non-zero seqno), and is not set if it i s on
1963 * inactive (ready to be unbound) list.
1965 unsigned int active
:1;
1968 * This is set if the object has been written to since last bound
1971 unsigned int dirty
:1;
1974 * Fence register bits (if any) for this object. Will be set
1975 * as needed when mapped into the GTT.
1976 * Protected by dev->struct_mutex.
1978 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1981 * Advice: are the backing pages purgeable?
1983 unsigned int madv
:2;
1986 * Current tiling mode for the object.
1988 unsigned int tiling_mode
:2;
1990 * Whether the tiling parameters for the currently associated fence
1991 * register have changed. Note that for the purposes of tracking
1992 * tiling changes we also treat the unfenced register, the register
1993 * slot that the object occupies whilst it executes a fenced
1994 * command (such as BLT on gen2/3), as a "fence".
1996 unsigned int fence_dirty
:1;
1999 * Is the object at the current location in the gtt mappable and
2000 * fenceable? Used to avoid costly recalculations.
2002 unsigned int map_and_fenceable
:1;
2005 * Whether the current gtt mapping needs to be mappable (and isn't just
2006 * mappable by accident). Track pin and fault separate for a more
2007 * accurate mappable working set.
2009 unsigned int fault_mappable
:1;
2010 unsigned int pin_mappable
:1;
2011 unsigned int pin_display
:1;
2014 * Is the object to be mapped as read-only to the GPU
2015 * Only honoured if hardware has relevant pte bit
2017 unsigned long gt_ro
:1;
2018 unsigned int cache_level
:3;
2020 unsigned int has_dma_mapping
:1;
2022 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2024 struct sg_table
*pages
;
2025 int pages_pin_count
;
2027 /* prime dma-buf support */
2028 void *dma_buf_vmapping
;
2031 /** Breadcrumb of last rendering to the buffer. */
2032 struct drm_i915_gem_request
*last_read_req
;
2033 struct drm_i915_gem_request
*last_write_req
;
2034 /** Breadcrumb of last fenced GPU access to the buffer. */
2035 struct drm_i915_gem_request
*last_fenced_req
;
2037 /** Current tiling stride for the object, if it's tiled. */
2040 /** References from framebuffers, locks out tiling changes. */
2041 unsigned long framebuffer_references
;
2043 /** Record of address bit 17 of each page at last unbind. */
2044 unsigned long *bit_17
;
2047 /** for phy allocated objects */
2048 struct drm_dma_handle
*phys_handle
;
2050 struct i915_gem_userptr
{
2052 unsigned read_only
:1;
2053 unsigned workers
:4;
2054 #define I915_GEM_USERPTR_MAX_WORKERS 15
2056 struct i915_mm_struct
*mm
;
2057 struct i915_mmu_object
*mmu_object
;
2058 struct work_struct
*work
;
2062 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2064 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2065 struct drm_i915_gem_object
*new,
2066 unsigned frontbuffer_bits
);
2069 * Request queue structure.
2071 * The request queue allows us to note sequence numbers that have been emitted
2072 * and may be associated with active buffers to be retired.
2074 * By keeping this list, we can avoid having to do questionable sequence
2075 * number comparisons on buffer last_read|write_seqno. It also allows an
2076 * emission time to be associated with the request for tracking how far ahead
2077 * of the GPU the submission is.
2079 struct drm_i915_gem_request
{
2082 /** On Which ring this request was generated */
2083 struct intel_engine_cs
*ring
;
2085 /** GEM sequence number associated with this request. */
2088 /** Position in the ringbuffer of the start of the request */
2091 /** Position in the ringbuffer of the end of the request */
2094 /** Context related to this request */
2095 struct intel_context
*ctx
;
2097 /** Batch buffer related to this request if any */
2098 struct drm_i915_gem_object
*batch_obj
;
2100 /** Time at which this request was emitted, in jiffies. */
2101 unsigned long emitted_jiffies
;
2103 /** global list entry for this request */
2104 struct list_head list
;
2106 struct drm_i915_file_private
*file_priv
;
2107 /** file_priv list entry for this request */
2108 struct list_head client_list
;
2113 void i915_gem_request_free(struct kref
*req_ref
);
2115 static inline uint32_t
2116 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2118 return req
? req
->seqno
: 0;
2121 static inline struct intel_engine_cs
*
2122 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2124 return req
? req
->ring
: NULL
;
2128 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2130 kref_get(&req
->ref
);
2134 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2136 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2137 kref_put(&req
->ref
, i915_gem_request_free
);
2140 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2141 struct drm_i915_gem_request
*src
)
2144 i915_gem_request_reference(src
);
2147 i915_gem_request_unreference(*pdst
);
2153 * XXX: i915_gem_request_completed should be here but currently needs the
2154 * definition of i915_seqno_passed() which is below. It will be moved in
2155 * a later patch when the call to i915_seqno_passed() is obsoleted...
2158 struct drm_i915_file_private
{
2159 struct drm_i915_private
*dev_priv
;
2160 struct drm_file
*file
;
2164 struct list_head request_list
;
2165 struct delayed_work idle_work
;
2167 struct idr context_idr
;
2169 atomic_t rps_wait_boost
;
2170 struct intel_engine_cs
*bsd_ring
;
2174 * A command that requires special handling by the command parser.
2176 struct drm_i915_cmd_descriptor
{
2178 * Flags describing how the command parser processes the command.
2180 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2181 * a length mask if not set
2182 * CMD_DESC_SKIP: The command is allowed but does not follow the
2183 * standard length encoding for the opcode range in
2185 * CMD_DESC_REJECT: The command is never allowed
2186 * CMD_DESC_REGISTER: The command should be checked against the
2187 * register whitelist for the appropriate ring
2188 * CMD_DESC_MASTER: The command is allowed if the submitting process
2192 #define CMD_DESC_FIXED (1<<0)
2193 #define CMD_DESC_SKIP (1<<1)
2194 #define CMD_DESC_REJECT (1<<2)
2195 #define CMD_DESC_REGISTER (1<<3)
2196 #define CMD_DESC_BITMASK (1<<4)
2197 #define CMD_DESC_MASTER (1<<5)
2200 * The command's unique identification bits and the bitmask to get them.
2201 * This isn't strictly the opcode field as defined in the spec and may
2202 * also include type, subtype, and/or subop fields.
2210 * The command's length. The command is either fixed length (i.e. does
2211 * not include a length field) or has a length field mask. The flag
2212 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2213 * a length mask. All command entries in a command table must include
2214 * length information.
2222 * Describes where to find a register address in the command to check
2223 * against the ring's register whitelist. Only valid if flags has the
2224 * CMD_DESC_REGISTER bit set.
2231 #define MAX_CMD_DESC_BITMASKS 3
2233 * Describes command checks where a particular dword is masked and
2234 * compared against an expected value. If the command does not match
2235 * the expected value, the parser rejects it. Only valid if flags has
2236 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2239 * If the check specifies a non-zero condition_mask then the parser
2240 * only performs the check when the bits specified by condition_mask
2247 u32 condition_offset
;
2249 } bits
[MAX_CMD_DESC_BITMASKS
];
2253 * A table of commands requiring special handling by the command parser.
2255 * Each ring has an array of tables. Each table consists of an array of command
2256 * descriptors, which must be sorted with command opcodes in ascending order.
2258 struct drm_i915_cmd_table
{
2259 const struct drm_i915_cmd_descriptor
*table
;
2263 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2264 #define __I915__(p) ({ \
2265 struct drm_i915_private *__p; \
2266 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2267 __p = (struct drm_i915_private *)p; \
2268 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2269 __p = to_i915((struct drm_device *)p); \
2274 #define INTEL_INFO(p) (&__I915__(p)->info)
2275 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2277 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2278 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2279 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2280 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2281 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2282 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2283 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2284 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2285 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2286 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2287 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2288 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2289 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2290 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2291 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2292 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2293 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2294 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2295 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2296 INTEL_DEVID(dev) == 0x0152 || \
2297 INTEL_DEVID(dev) == 0x015a)
2298 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2299 INTEL_DEVID(dev) == 0x0106 || \
2300 INTEL_DEVID(dev) == 0x010A)
2301 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2302 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2303 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2304 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2305 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2306 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2307 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2308 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2309 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2310 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2311 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2312 (INTEL_DEVID(dev) & 0xf) == 0xe))
2313 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2314 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2315 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2316 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2317 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2318 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2319 /* ULX machines are also considered ULT. */
2320 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2321 INTEL_DEVID(dev) == 0x0A1E)
2322 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2325 * The genX designation typically refers to the render engine, so render
2326 * capability related checks should use IS_GEN, while display and other checks
2327 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2330 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2331 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2332 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2333 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2334 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2335 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2336 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2337 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2339 #define RENDER_RING (1<<RCS)
2340 #define BSD_RING (1<<VCS)
2341 #define BLT_RING (1<<BCS)
2342 #define VEBOX_RING (1<<VECS)
2343 #define BSD2_RING (1<<VCS2)
2344 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2345 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2346 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2347 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2348 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2349 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2350 __I915__(dev)->ellc_size)
2351 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2353 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2354 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2355 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2356 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2358 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2359 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2361 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2362 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2364 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2365 * even when in MSI mode. This results in spurious interrupt warnings if the
2366 * legacy irq no. is shared with another device. The kernel then disables that
2367 * interrupt source and so prevents the other device from working properly.
2369 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2370 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2372 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2373 * rows, which changed the alignment requirements and fence programming.
2375 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2377 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2378 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2379 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2380 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2381 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2383 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2384 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2385 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2387 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2389 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2390 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2391 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2392 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2393 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2394 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2395 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2396 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2398 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2399 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2400 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2401 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2402 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2403 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2404 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2405 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2407 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2408 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2409 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2410 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2411 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2412 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2413 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2415 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2417 /* DPF == dynamic parity feature */
2418 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2419 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2421 #define GT_FREQUENCY_MULTIPLIER 50
2423 #include "i915_trace.h"
2425 extern const struct drm_ioctl_desc i915_ioctls
[];
2426 extern int i915_max_ioctl
;
2428 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2429 extern int i915_resume_legacy(struct drm_device
*dev
);
2430 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2431 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2434 struct i915_params
{
2436 int panel_ignore_lid
;
2437 unsigned int powersave
;
2439 unsigned int lvds_downclock
;
2440 int lvds_channel_mode
;
2442 int vbt_sdvo_panel_type
;
2446 int enable_execlists
;
2448 unsigned int preliminary_hw_support
;
2449 int disable_power_well
;
2451 int invert_brightness
;
2452 int enable_cmd_parser
;
2453 /* leave bools at the end to not create holes */
2454 bool enable_hangcheck
;
2456 bool prefault_disable
;
2458 bool disable_display
;
2459 bool disable_vtd_wa
;
2462 bool verbose_state_checks
;
2464 extern struct i915_params i915 __read_mostly
;
2467 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2468 extern int i915_driver_unload(struct drm_device
*);
2469 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2470 extern void i915_driver_lastclose(struct drm_device
* dev
);
2471 extern void i915_driver_preclose(struct drm_device
*dev
,
2472 struct drm_file
*file
);
2473 extern void i915_driver_postclose(struct drm_device
*dev
,
2474 struct drm_file
*file
);
2475 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2476 #ifdef CONFIG_COMPAT
2477 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2480 extern int intel_gpu_reset(struct drm_device
*dev
);
2481 extern int i915_reset(struct drm_device
*dev
);
2482 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2483 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2484 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2485 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2486 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2487 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2490 void i915_queue_hangcheck(struct drm_device
*dev
);
2492 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2493 const char *fmt
, ...);
2495 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2496 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2497 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2498 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2500 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2501 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2502 bool restore_forcewake
);
2503 extern void intel_uncore_init(struct drm_device
*dev
);
2504 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2505 extern void intel_uncore_fini(struct drm_device
*dev
);
2506 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2509 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2513 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2516 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2517 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2519 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2521 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2522 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2523 uint32_t interrupt_mask
,
2524 uint32_t enabled_irq_mask
);
2525 #define ibx_enable_display_interrupt(dev_priv, bits) \
2526 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2527 #define ibx_disable_display_interrupt(dev_priv, bits) \
2528 ibx_display_interrupt_update((dev_priv), (bits), 0)
2531 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2532 struct drm_file
*file_priv
);
2533 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2534 struct drm_file
*file_priv
);
2535 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2536 struct drm_file
*file_priv
);
2537 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2538 struct drm_file
*file_priv
);
2539 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2540 struct drm_file
*file_priv
);
2541 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2542 struct drm_file
*file_priv
);
2543 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2544 struct drm_file
*file_priv
);
2545 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2546 struct intel_engine_cs
*ring
);
2547 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2548 struct drm_file
*file
,
2549 struct intel_engine_cs
*ring
,
2550 struct drm_i915_gem_object
*obj
);
2551 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2552 struct drm_file
*file
,
2553 struct intel_engine_cs
*ring
,
2554 struct intel_context
*ctx
,
2555 struct drm_i915_gem_execbuffer2
*args
,
2556 struct list_head
*vmas
,
2557 struct drm_i915_gem_object
*batch_obj
,
2558 u64 exec_start
, u32 flags
);
2559 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2560 struct drm_file
*file_priv
);
2561 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2562 struct drm_file
*file_priv
);
2563 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2564 struct drm_file
*file_priv
);
2565 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2566 struct drm_file
*file
);
2567 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2568 struct drm_file
*file
);
2569 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2570 struct drm_file
*file_priv
);
2571 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2572 struct drm_file
*file_priv
);
2573 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2574 struct drm_file
*file_priv
);
2575 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2576 struct drm_file
*file_priv
);
2577 int i915_gem_init_userptr(struct drm_device
*dev
);
2578 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2579 struct drm_file
*file
);
2580 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2581 struct drm_file
*file_priv
);
2582 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2583 struct drm_file
*file_priv
);
2584 void i915_gem_load(struct drm_device
*dev
);
2585 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2588 #define I915_SHRINK_PURGEABLE 0x1
2589 #define I915_SHRINK_UNBOUND 0x2
2590 #define I915_SHRINK_BOUND 0x4
2591 void *i915_gem_object_alloc(struct drm_device
*dev
);
2592 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2593 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2594 const struct drm_i915_gem_object_ops
*ops
);
2595 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2597 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2598 struct i915_address_space
*vm
);
2599 void i915_gem_free_object(struct drm_gem_object
*obj
);
2600 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2602 #define PIN_MAPPABLE 0x1
2603 #define PIN_NONBLOCK 0x2
2604 #define PIN_GLOBAL 0x4
2605 #define PIN_OFFSET_BIAS 0x8
2606 #define PIN_OFFSET_MASK (~4095)
2607 int __must_check
i915_gem_object_pin_view(struct drm_i915_gem_object
*obj
,
2608 struct i915_address_space
*vm
,
2611 const struct i915_ggtt_view
*view
);
2613 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2614 struct i915_address_space
*vm
,
2618 return i915_gem_object_pin_view(obj
, vm
, alignment
, flags
,
2619 &i915_ggtt_view_normal
);
2622 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2624 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2625 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2626 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2627 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2629 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2630 int *needs_clflush
);
2632 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2633 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2635 struct sg_page_iter sg_iter
;
2637 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2638 return sg_page_iter_page(&sg_iter
);
2642 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2644 BUG_ON(obj
->pages
== NULL
);
2645 obj
->pages_pin_count
++;
2647 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2649 BUG_ON(obj
->pages_pin_count
== 0);
2650 obj
->pages_pin_count
--;
2653 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2654 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2655 struct intel_engine_cs
*to
);
2656 void i915_vma_move_to_active(struct i915_vma
*vma
,
2657 struct intel_engine_cs
*ring
);
2658 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2659 struct drm_device
*dev
,
2660 struct drm_mode_create_dumb
*args
);
2661 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2662 uint32_t handle
, uint64_t *offset
);
2664 * Returns true if seq1 is later than seq2.
2667 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2669 return (int32_t)(seq1
- seq2
) >= 0;
2672 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2673 bool lazy_coherency
)
2677 BUG_ON(req
== NULL
);
2679 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2681 return i915_seqno_passed(seqno
, req
->seqno
);
2684 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2685 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2686 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2687 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2689 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2690 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2692 struct drm_i915_gem_request
*
2693 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2695 bool i915_gem_retire_requests(struct drm_device
*dev
);
2696 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2697 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2698 bool interruptible
);
2699 int __must_check
i915_gem_check_olr(struct drm_i915_gem_request
*req
);
2701 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2703 return unlikely(atomic_read(&error
->reset_counter
)
2704 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2707 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2709 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2712 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2714 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2717 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2719 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2720 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2723 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2725 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2726 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2729 void i915_gem_reset(struct drm_device
*dev
);
2730 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2731 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2732 int __must_check
i915_gem_init(struct drm_device
*dev
);
2733 int i915_gem_init_rings(struct drm_device
*dev
);
2734 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2735 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2736 void i915_gem_init_swizzling(struct drm_device
*dev
);
2737 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2738 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2739 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2740 int __i915_add_request(struct intel_engine_cs
*ring
,
2741 struct drm_file
*file
,
2742 struct drm_i915_gem_object
*batch_obj
);
2743 #define i915_add_request(ring) \
2744 __i915_add_request(ring, NULL, NULL)
2745 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2746 unsigned reset_counter
,
2749 struct drm_i915_file_private
*file_priv
);
2750 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2751 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2753 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2756 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2758 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2760 struct intel_engine_cs
*pipelined
);
2761 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2762 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2764 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2765 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2768 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2770 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2771 int tiling_mode
, bool fenced
);
2773 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2774 enum i915_cache_level cache_level
);
2776 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2777 struct dma_buf
*dma_buf
);
2779 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2780 struct drm_gem_object
*gem_obj
, int flags
);
2782 void i915_gem_restore_fences(struct drm_device
*dev
);
2784 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object
*o
,
2785 struct i915_address_space
*vm
,
2786 enum i915_ggtt_view_type view
);
2788 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2789 struct i915_address_space
*vm
)
2791 return i915_gem_obj_offset_view(o
, vm
, I915_GGTT_VIEW_NORMAL
);
2793 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2794 bool i915_gem_obj_bound_view(struct drm_i915_gem_object
*o
,
2795 struct i915_address_space
*vm
,
2796 enum i915_ggtt_view_type view
);
2798 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2799 struct i915_address_space
*vm
)
2801 return i915_gem_obj_bound_view(o
, vm
, I915_GGTT_VIEW_NORMAL
);
2804 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2805 struct i915_address_space
*vm
);
2806 struct i915_vma
*i915_gem_obj_to_vma_view(struct drm_i915_gem_object
*obj
,
2807 struct i915_address_space
*vm
,
2808 const struct i915_ggtt_view
*view
);
2810 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2811 struct i915_address_space
*vm
)
2813 return i915_gem_obj_to_vma_view(obj
, vm
, &i915_ggtt_view_normal
);
2817 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object
*obj
,
2818 struct i915_address_space
*vm
,
2819 const struct i915_ggtt_view
*view
);
2823 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2824 struct i915_address_space
*vm
)
2826 return i915_gem_obj_lookup_or_create_vma_view(obj
, vm
,
2827 &i915_ggtt_view_normal
);
2830 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2831 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2832 struct i915_vma
*vma
;
2833 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2834 if (vma
->pin_count
> 0)
2839 /* Some GGTT VM helpers */
2840 #define i915_obj_to_ggtt(obj) \
2841 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2842 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2844 struct i915_address_space
*ggtt
=
2845 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2849 static inline struct i915_hw_ppgtt
*
2850 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2852 WARN_ON(i915_is_ggtt(vm
));
2854 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2858 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2860 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2863 static inline unsigned long
2864 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2866 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2869 static inline unsigned long
2870 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2872 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2875 static inline int __must_check
2876 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2880 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2881 alignment
, flags
| PIN_GLOBAL
);
2885 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2887 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2890 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2892 /* i915_gem_context.c */
2893 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2894 void i915_gem_context_fini(struct drm_device
*dev
);
2895 void i915_gem_context_reset(struct drm_device
*dev
);
2896 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2897 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2898 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2899 int i915_switch_context(struct intel_engine_cs
*ring
,
2900 struct intel_context
*to
);
2901 struct intel_context
*
2902 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2903 void i915_gem_context_free(struct kref
*ctx_ref
);
2904 struct drm_i915_gem_object
*
2905 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2906 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2908 kref_get(&ctx
->ref
);
2911 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2913 kref_put(&ctx
->ref
, i915_gem_context_free
);
2916 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2918 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2921 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2922 struct drm_file
*file
);
2923 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2924 struct drm_file
*file
);
2925 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
2926 struct drm_file
*file_priv
);
2927 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
2928 struct drm_file
*file_priv
);
2930 /* i915_gem_evict.c */
2931 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2932 struct i915_address_space
*vm
,
2935 unsigned cache_level
,
2936 unsigned long start
,
2939 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2940 int i915_gem_evict_everything(struct drm_device
*dev
);
2942 /* belongs in i915_gem_gtt.h */
2943 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2945 if (INTEL_INFO(dev
)->gen
< 6)
2946 intel_gtt_chipset_flush();
2949 /* i915_gem_stolen.c */
2950 int i915_gem_init_stolen(struct drm_device
*dev
);
2951 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2952 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2953 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2954 struct drm_i915_gem_object
*
2955 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2956 struct drm_i915_gem_object
*
2957 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2962 /* i915_gem_tiling.c */
2963 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2965 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2967 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2968 obj
->tiling_mode
!= I915_TILING_NONE
;
2971 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2972 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2973 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2975 /* i915_gem_debug.c */
2977 int i915_verify_lists(struct drm_device
*dev
);
2979 #define i915_verify_lists(dev) 0
2982 /* i915_debugfs.c */
2983 int i915_debugfs_init(struct drm_minor
*minor
);
2984 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2985 #ifdef CONFIG_DEBUG_FS
2986 void intel_display_crc_init(struct drm_device
*dev
);
2988 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2991 /* i915_gpu_error.c */
2993 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2994 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2995 const struct i915_error_state_file_priv
*error
);
2996 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2997 struct drm_i915_private
*i915
,
2998 size_t count
, loff_t pos
);
2999 static inline void i915_error_state_buf_release(
3000 struct drm_i915_error_state_buf
*eb
)
3004 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3005 const char *error_msg
);
3006 void i915_error_state_get(struct drm_device
*dev
,
3007 struct i915_error_state_file_priv
*error_priv
);
3008 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3009 void i915_destroy_error_state(struct drm_device
*dev
);
3011 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3012 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3014 /* i915_gem_batch_pool.c */
3015 void i915_gem_batch_pool_init(struct drm_device
*dev
,
3016 struct i915_gem_batch_pool
*pool
);
3017 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool
*pool
);
3018 struct drm_i915_gem_object
*
3019 i915_gem_batch_pool_get(struct i915_gem_batch_pool
*pool
, size_t size
);
3021 /* i915_cmd_parser.c */
3022 int i915_cmd_parser_get_version(void);
3023 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3024 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3025 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3026 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3027 struct drm_i915_gem_object
*batch_obj
,
3028 struct drm_i915_gem_object
*shadow_batch_obj
,
3029 u32 batch_start_offset
,
3033 /* i915_suspend.c */
3034 extern int i915_save_state(struct drm_device
*dev
);
3035 extern int i915_restore_state(struct drm_device
*dev
);
3038 void i915_save_display_reg(struct drm_device
*dev
);
3039 void i915_restore_display_reg(struct drm_device
*dev
);
3042 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3043 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3046 extern int intel_setup_gmbus(struct drm_device
*dev
);
3047 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3048 static inline bool intel_gmbus_is_port_valid(unsigned port
)
3050 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
3053 extern struct i2c_adapter
*intel_gmbus_get_adapter(
3054 struct drm_i915_private
*dev_priv
, unsigned port
);
3055 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3056 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3057 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3059 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3061 extern void intel_i2c_reset(struct drm_device
*dev
);
3063 /* intel_opregion.c */
3065 extern int intel_opregion_setup(struct drm_device
*dev
);
3066 extern void intel_opregion_init(struct drm_device
*dev
);
3067 extern void intel_opregion_fini(struct drm_device
*dev
);
3068 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3069 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3071 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3074 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3075 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3076 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3077 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3079 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3084 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3092 extern void intel_register_dsm_handler(void);
3093 extern void intel_unregister_dsm_handler(void);
3095 static inline void intel_register_dsm_handler(void) { return; }
3096 static inline void intel_unregister_dsm_handler(void) { return; }
3097 #endif /* CONFIG_ACPI */
3100 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3101 extern void intel_modeset_init(struct drm_device
*dev
);
3102 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3103 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3104 extern void intel_connector_unregister(struct intel_connector
*);
3105 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3106 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
3107 bool force_restore
);
3108 extern void i915_redisable_vga(struct drm_device
*dev
);
3109 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3110 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3111 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3112 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
3113 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
3114 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3116 extern void intel_detect_pch(struct drm_device
*dev
);
3117 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3118 extern int intel_enable_rc6(const struct drm_device
*dev
);
3120 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3121 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3122 struct drm_file
*file
);
3123 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3124 struct drm_file
*file
);
3126 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
3129 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3130 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3131 struct intel_overlay_error_state
*error
);
3133 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3134 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3135 struct drm_device
*dev
,
3136 struct intel_display_error_state
*error
);
3138 /* On SNB platform, before reading ring registers forcewake bit
3139 * must be set to prevent GT core from power down and stale values being
3142 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
3143 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
3144 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
3146 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3147 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3149 /* intel_sideband.c */
3150 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3151 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3152 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3153 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3154 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3155 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3156 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3157 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3158 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3159 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3160 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3161 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3162 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3163 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3164 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3165 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3166 enum intel_sbi_destination destination
);
3167 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3168 enum intel_sbi_destination destination
);
3169 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3170 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3172 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3173 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3175 #define FORCEWAKE_RENDER (1 << 0)
3176 #define FORCEWAKE_MEDIA (1 << 1)
3177 #define FORCEWAKE_BLITTER (1 << 2)
3178 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
3182 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3183 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3185 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3186 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3187 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3188 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3190 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3191 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3192 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3193 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3195 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3196 * will be implemented using 2 32-bit writes in an arbitrary order with
3197 * an arbitrary delay between them. This can cause the hardware to
3198 * act upon the intermediate value, possibly leading to corruption and
3199 * machine death. You have been warned.
3201 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3202 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3204 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3205 u32 upper = I915_READ(upper_reg); \
3206 u32 lower = I915_READ(lower_reg); \
3207 u32 tmp = I915_READ(upper_reg); \
3208 if (upper != tmp) { \
3210 lower = I915_READ(lower_reg); \
3211 WARN_ON(I915_READ(upper_reg) != upper); \
3213 (u64)upper << 32 | lower; })
3215 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3216 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3218 /* "Broadcast RGB" property */
3219 #define INTEL_BROADCAST_RGB_AUTO 0
3220 #define INTEL_BROADCAST_RGB_FULL 1
3221 #define INTEL_BROADCAST_RGB_LIMITED 2
3223 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3225 if (IS_VALLEYVIEW(dev
))
3226 return VLV_VGACNTRL
;
3227 else if (INTEL_INFO(dev
)->gen
>= 5)
3228 return CPU_VGACNTRL
;
3233 static inline void __user
*to_user_ptr(u64 address
)
3235 return (void __user
*)(uintptr_t)address
;
3238 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3240 unsigned long j
= msecs_to_jiffies(m
);
3242 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3245 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3247 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3250 static inline unsigned long
3251 timespec_to_jiffies_timeout(const struct timespec
*value
)
3253 unsigned long j
= timespec_to_jiffies(value
);
3255 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3259 * If you need to wait X milliseconds between events A and B, but event B
3260 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3261 * when event A happened, then just before event B you call this function and
3262 * pass the timestamp as the first argument, and X as the second argument.
3265 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3267 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3270 * Don't re-read the value of "jiffies" every time since it may change
3271 * behind our back and break the math.
3273 tmp_jiffies
= jiffies
;
3274 target_jiffies
= timestamp_jiffies
+
3275 msecs_to_jiffies_timeout(to_wait_ms
);
3277 if (time_after(target_jiffies
, tmp_jiffies
)) {
3278 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3279 while (remaining_jiffies
)
3281 schedule_timeout_uninterruptible(remaining_jiffies
);
3285 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3286 struct drm_i915_gem_request
*req
)
3288 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3289 i915_gem_request_assign(&ring
->trace_irq_req
, req
);