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[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include "i915_reg.h"
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
46
47 /* General customization:
48 */
49
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
51
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
55
56 enum pipe {
57 PIPE_A = 0,
58 PIPE_B,
59 PIPE_C,
60 I915_MAX_PIPES
61 };
62 #define pipe_name(p) ((p) + 'A')
63
64 enum transcoder {
65 TRANSCODER_A = 0,
66 TRANSCODER_B,
67 TRANSCODER_C,
68 TRANSCODER_EDP = 0xF,
69 };
70 #define transcoder_name(t) ((t) + 'A')
71
72 enum plane {
73 PLANE_A = 0,
74 PLANE_B,
75 PLANE_C,
76 };
77 #define plane_name(p) ((p) + 'A')
78
79 enum port {
80 PORT_A = 0,
81 PORT_B,
82 PORT_C,
83 PORT_D,
84 PORT_E,
85 I915_MAX_PORTS
86 };
87 #define port_name(p) ((p) + 'A')
88
89 #define I915_GEM_GPU_DOMAINS \
90 (I915_GEM_DOMAIN_RENDER | \
91 I915_GEM_DOMAIN_SAMPLER | \
92 I915_GEM_DOMAIN_COMMAND | \
93 I915_GEM_DOMAIN_INSTRUCTION | \
94 I915_GEM_DOMAIN_VERTEX)
95
96 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
97
98 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
99 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
100 if ((intel_encoder)->base.crtc == (__crtc))
101
102 struct intel_pch_pll {
103 int refcount; /* count of number of CRTCs sharing this PLL */
104 int active; /* count of number of active CRTCs (i.e. DPMS on) */
105 bool on; /* is the PLL actually active? Disabled during modeset */
106 int pll_reg;
107 int fp0_reg;
108 int fp1_reg;
109 };
110 #define I915_NUM_PLLS 2
111
112 /* Used by dp and fdi links */
113 struct intel_link_m_n {
114 uint32_t tu;
115 uint32_t gmch_m;
116 uint32_t gmch_n;
117 uint32_t link_m;
118 uint32_t link_n;
119 };
120
121 void intel_link_compute_m_n(int bpp, int nlanes,
122 int pixel_clock, int link_clock,
123 struct intel_link_m_n *m_n);
124
125 struct intel_ddi_plls {
126 int spll_refcount;
127 int wrpll1_refcount;
128 int wrpll2_refcount;
129 };
130
131 /* Interface history:
132 *
133 * 1.1: Original.
134 * 1.2: Add Power Management
135 * 1.3: Add vblank support
136 * 1.4: Fix cmdbuffer path, add heap destroy
137 * 1.5: Add vblank pipe configuration
138 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
139 * - Support vertical blank on secondary display pipe
140 */
141 #define DRIVER_MAJOR 1
142 #define DRIVER_MINOR 6
143 #define DRIVER_PATCHLEVEL 0
144
145 #define WATCH_COHERENCY 0
146 #define WATCH_LISTS 0
147 #define WATCH_GTT 0
148
149 #define I915_GEM_PHYS_CURSOR_0 1
150 #define I915_GEM_PHYS_CURSOR_1 2
151 #define I915_GEM_PHYS_OVERLAY_REGS 3
152 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
153
154 struct drm_i915_gem_phys_object {
155 int id;
156 struct page **page_list;
157 drm_dma_handle_t *handle;
158 struct drm_i915_gem_object *cur_obj;
159 };
160
161 struct opregion_header;
162 struct opregion_acpi;
163 struct opregion_swsci;
164 struct opregion_asle;
165 struct drm_i915_private;
166
167 struct intel_opregion {
168 struct opregion_header __iomem *header;
169 struct opregion_acpi __iomem *acpi;
170 struct opregion_swsci __iomem *swsci;
171 struct opregion_asle __iomem *asle;
172 void __iomem *vbt;
173 u32 __iomem *lid_state;
174 };
175 #define OPREGION_SIZE (8*1024)
176
177 struct intel_overlay;
178 struct intel_overlay_error_state;
179
180 struct drm_i915_master_private {
181 drm_local_map_t *sarea;
182 struct _drm_i915_sarea *sarea_priv;
183 };
184 #define I915_FENCE_REG_NONE -1
185 #define I915_MAX_NUM_FENCES 16
186 /* 16 fences + sign bit for FENCE_REG_NONE */
187 #define I915_MAX_NUM_FENCE_BITS 5
188
189 struct drm_i915_fence_reg {
190 struct list_head lru_list;
191 struct drm_i915_gem_object *obj;
192 int pin_count;
193 };
194
195 struct sdvo_device_mapping {
196 u8 initialized;
197 u8 dvo_port;
198 u8 slave_addr;
199 u8 dvo_wiring;
200 u8 i2c_pin;
201 u8 ddc_pin;
202 };
203
204 struct intel_display_error_state;
205
206 struct drm_i915_error_state {
207 struct kref ref;
208 u32 eir;
209 u32 pgtbl_er;
210 u32 ier;
211 u32 ccid;
212 bool waiting[I915_NUM_RINGS];
213 u32 pipestat[I915_MAX_PIPES];
214 u32 tail[I915_NUM_RINGS];
215 u32 head[I915_NUM_RINGS];
216 u32 ipeir[I915_NUM_RINGS];
217 u32 ipehr[I915_NUM_RINGS];
218 u32 instdone[I915_NUM_RINGS];
219 u32 acthd[I915_NUM_RINGS];
220 u32 semaphore_mboxes[I915_NUM_RINGS][I915_NUM_RINGS - 1];
221 u32 semaphore_seqno[I915_NUM_RINGS][I915_NUM_RINGS - 1];
222 u32 rc_psmi[I915_NUM_RINGS]; /* sleep state */
223 /* our own tracking of ring head and tail */
224 u32 cpu_ring_head[I915_NUM_RINGS];
225 u32 cpu_ring_tail[I915_NUM_RINGS];
226 u32 error; /* gen6+ */
227 u32 err_int; /* gen7 */
228 u32 instpm[I915_NUM_RINGS];
229 u32 instps[I915_NUM_RINGS];
230 u32 extra_instdone[I915_NUM_INSTDONE_REG];
231 u32 seqno[I915_NUM_RINGS];
232 u64 bbaddr;
233 u32 fault_reg[I915_NUM_RINGS];
234 u32 done_reg;
235 u32 faddr[I915_NUM_RINGS];
236 u64 fence[I915_MAX_NUM_FENCES];
237 struct timeval time;
238 struct drm_i915_error_ring {
239 struct drm_i915_error_object {
240 int page_count;
241 u32 gtt_offset;
242 u32 *pages[0];
243 } *ringbuffer, *batchbuffer;
244 struct drm_i915_error_request {
245 long jiffies;
246 u32 seqno;
247 u32 tail;
248 } *requests;
249 int num_requests;
250 } ring[I915_NUM_RINGS];
251 struct drm_i915_error_buffer {
252 u32 size;
253 u32 name;
254 u32 rseqno, wseqno;
255 u32 gtt_offset;
256 u32 read_domains;
257 u32 write_domain;
258 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
259 s32 pinned:2;
260 u32 tiling:2;
261 u32 dirty:1;
262 u32 purgeable:1;
263 s32 ring:4;
264 u32 cache_level:2;
265 } *active_bo, *pinned_bo;
266 u32 active_bo_count, pinned_bo_count;
267 struct intel_overlay_error_state *overlay;
268 struct intel_display_error_state *display;
269 };
270
271 struct drm_i915_display_funcs {
272 bool (*fbc_enabled)(struct drm_device *dev);
273 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
274 void (*disable_fbc)(struct drm_device *dev);
275 int (*get_display_clock_speed)(struct drm_device *dev);
276 int (*get_fifo_size)(struct drm_device *dev, int plane);
277 void (*update_wm)(struct drm_device *dev);
278 void (*update_sprite_wm)(struct drm_device *dev, int pipe,
279 uint32_t sprite_width, int pixel_size);
280 void (*update_linetime_wm)(struct drm_device *dev, int pipe,
281 struct drm_display_mode *mode);
282 void (*modeset_global_resources)(struct drm_device *dev);
283 int (*crtc_mode_set)(struct drm_crtc *crtc,
284 struct drm_display_mode *mode,
285 struct drm_display_mode *adjusted_mode,
286 int x, int y,
287 struct drm_framebuffer *old_fb);
288 void (*crtc_enable)(struct drm_crtc *crtc);
289 void (*crtc_disable)(struct drm_crtc *crtc);
290 void (*off)(struct drm_crtc *crtc);
291 void (*write_eld)(struct drm_connector *connector,
292 struct drm_crtc *crtc);
293 void (*fdi_link_train)(struct drm_crtc *crtc);
294 void (*init_clock_gating)(struct drm_device *dev);
295 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
296 struct drm_framebuffer *fb,
297 struct drm_i915_gem_object *obj);
298 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
299 int x, int y);
300 void (*hpd_irq_setup)(struct drm_device *dev);
301 /* clock updates for mode set */
302 /* cursor updates */
303 /* render clock increase/decrease */
304 /* display clock increase/decrease */
305 /* pll clock increase/decrease */
306 };
307
308 struct drm_i915_gt_funcs {
309 void (*force_wake_get)(struct drm_i915_private *dev_priv);
310 void (*force_wake_put)(struct drm_i915_private *dev_priv);
311 };
312
313 #define DEV_INFO_FLAGS \
314 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
315 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
316 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
317 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
318 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
319 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
320 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
321 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
322 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
323 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
324 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
325 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
326 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
327 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
328 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
329 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
330 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
331 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
332 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
333 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
334 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
335 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
336 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
337 DEV_INFO_FLAG(has_llc)
338
339 struct intel_device_info {
340 u8 gen;
341 u8 is_mobile:1;
342 u8 is_i85x:1;
343 u8 is_i915g:1;
344 u8 is_i945gm:1;
345 u8 is_g33:1;
346 u8 need_gfx_hws:1;
347 u8 is_g4x:1;
348 u8 is_pineview:1;
349 u8 is_broadwater:1;
350 u8 is_crestline:1;
351 u8 is_ivybridge:1;
352 u8 is_valleyview:1;
353 u8 has_force_wake:1;
354 u8 is_haswell:1;
355 u8 has_fbc:1;
356 u8 has_pipe_cxsr:1;
357 u8 has_hotplug:1;
358 u8 cursor_needs_physical:1;
359 u8 has_overlay:1;
360 u8 overlay_needs_physical:1;
361 u8 supports_tv:1;
362 u8 has_bsd_ring:1;
363 u8 has_blt_ring:1;
364 u8 has_llc:1;
365 };
366
367 /* The Graphics Translation Table is the way in which GEN hardware translates a
368 * Graphics Virtual Address into a Physical Address. In addition to the normal
369 * collateral associated with any va->pa translations GEN hardware also has a
370 * portion of the GTT which can be mapped by the CPU and remain both coherent
371 * and correct (in cases like swizzling). That region is referred to as GMADR in
372 * the spec.
373 */
374 struct i915_gtt {
375 unsigned long start; /* Start offset of used GTT */
376 size_t total; /* Total size GTT can map */
377
378 unsigned long mappable_end; /* End offset that we can CPU map */
379 struct io_mapping *mappable; /* Mapping to our CPU mappable region */
380 phys_addr_t mappable_base; /* PA of our GMADR */
381
382 /** "Graphics Stolen Memory" holds the global PTEs */
383 void __iomem *gsm;
384
385 bool do_idle_maps;
386 dma_addr_t scratch_page_dma;
387 struct page *scratch_page;
388 };
389
390 #define I915_PPGTT_PD_ENTRIES 512
391 #define I915_PPGTT_PT_ENTRIES 1024
392 struct i915_hw_ppgtt {
393 struct drm_device *dev;
394 unsigned num_pd_entries;
395 struct page **pt_pages;
396 uint32_t pd_offset;
397 dma_addr_t *pt_dma_addr;
398 dma_addr_t scratch_page_dma_addr;
399 };
400
401
402 /* This must match up with the value previously used for execbuf2.rsvd1. */
403 #define DEFAULT_CONTEXT_ID 0
404 struct i915_hw_context {
405 int id;
406 bool is_initialized;
407 struct drm_i915_file_private *file_priv;
408 struct intel_ring_buffer *ring;
409 struct drm_i915_gem_object *obj;
410 };
411
412 enum no_fbc_reason {
413 FBC_NO_OUTPUT, /* no outputs enabled to compress */
414 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
415 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
416 FBC_MODE_TOO_LARGE, /* mode too large for compression */
417 FBC_BAD_PLANE, /* fbc not supported on plane */
418 FBC_NOT_TILED, /* buffer not tiled */
419 FBC_MULTIPLE_PIPES, /* more than one pipe active */
420 FBC_MODULE_PARAM,
421 };
422
423 enum intel_pch {
424 PCH_NONE = 0, /* No PCH present */
425 PCH_IBX, /* Ibexpeak PCH */
426 PCH_CPT, /* Cougarpoint PCH */
427 PCH_LPT, /* Lynxpoint PCH */
428 };
429
430 enum intel_sbi_destination {
431 SBI_ICLK,
432 SBI_MPHY,
433 };
434
435 #define QUIRK_PIPEA_FORCE (1<<0)
436 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
437 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
438
439 struct intel_fbdev;
440 struct intel_fbc_work;
441
442 struct intel_gmbus {
443 struct i2c_adapter adapter;
444 u32 force_bit;
445 u32 reg0;
446 u32 gpio_reg;
447 struct i2c_algo_bit_data bit_algo;
448 struct drm_i915_private *dev_priv;
449 };
450
451 struct i915_suspend_saved_registers {
452 u8 saveLBB;
453 u32 saveDSPACNTR;
454 u32 saveDSPBCNTR;
455 u32 saveDSPARB;
456 u32 savePIPEACONF;
457 u32 savePIPEBCONF;
458 u32 savePIPEASRC;
459 u32 savePIPEBSRC;
460 u32 saveFPA0;
461 u32 saveFPA1;
462 u32 saveDPLL_A;
463 u32 saveDPLL_A_MD;
464 u32 saveHTOTAL_A;
465 u32 saveHBLANK_A;
466 u32 saveHSYNC_A;
467 u32 saveVTOTAL_A;
468 u32 saveVBLANK_A;
469 u32 saveVSYNC_A;
470 u32 saveBCLRPAT_A;
471 u32 saveTRANSACONF;
472 u32 saveTRANS_HTOTAL_A;
473 u32 saveTRANS_HBLANK_A;
474 u32 saveTRANS_HSYNC_A;
475 u32 saveTRANS_VTOTAL_A;
476 u32 saveTRANS_VBLANK_A;
477 u32 saveTRANS_VSYNC_A;
478 u32 savePIPEASTAT;
479 u32 saveDSPASTRIDE;
480 u32 saveDSPASIZE;
481 u32 saveDSPAPOS;
482 u32 saveDSPAADDR;
483 u32 saveDSPASURF;
484 u32 saveDSPATILEOFF;
485 u32 savePFIT_PGM_RATIOS;
486 u32 saveBLC_HIST_CTL;
487 u32 saveBLC_PWM_CTL;
488 u32 saveBLC_PWM_CTL2;
489 u32 saveBLC_CPU_PWM_CTL;
490 u32 saveBLC_CPU_PWM_CTL2;
491 u32 saveFPB0;
492 u32 saveFPB1;
493 u32 saveDPLL_B;
494 u32 saveDPLL_B_MD;
495 u32 saveHTOTAL_B;
496 u32 saveHBLANK_B;
497 u32 saveHSYNC_B;
498 u32 saveVTOTAL_B;
499 u32 saveVBLANK_B;
500 u32 saveVSYNC_B;
501 u32 saveBCLRPAT_B;
502 u32 saveTRANSBCONF;
503 u32 saveTRANS_HTOTAL_B;
504 u32 saveTRANS_HBLANK_B;
505 u32 saveTRANS_HSYNC_B;
506 u32 saveTRANS_VTOTAL_B;
507 u32 saveTRANS_VBLANK_B;
508 u32 saveTRANS_VSYNC_B;
509 u32 savePIPEBSTAT;
510 u32 saveDSPBSTRIDE;
511 u32 saveDSPBSIZE;
512 u32 saveDSPBPOS;
513 u32 saveDSPBADDR;
514 u32 saveDSPBSURF;
515 u32 saveDSPBTILEOFF;
516 u32 saveVGA0;
517 u32 saveVGA1;
518 u32 saveVGA_PD;
519 u32 saveVGACNTRL;
520 u32 saveADPA;
521 u32 saveLVDS;
522 u32 savePP_ON_DELAYS;
523 u32 savePP_OFF_DELAYS;
524 u32 saveDVOA;
525 u32 saveDVOB;
526 u32 saveDVOC;
527 u32 savePP_ON;
528 u32 savePP_OFF;
529 u32 savePP_CONTROL;
530 u32 savePP_DIVISOR;
531 u32 savePFIT_CONTROL;
532 u32 save_palette_a[256];
533 u32 save_palette_b[256];
534 u32 saveDPFC_CB_BASE;
535 u32 saveFBC_CFB_BASE;
536 u32 saveFBC_LL_BASE;
537 u32 saveFBC_CONTROL;
538 u32 saveFBC_CONTROL2;
539 u32 saveIER;
540 u32 saveIIR;
541 u32 saveIMR;
542 u32 saveDEIER;
543 u32 saveDEIMR;
544 u32 saveGTIER;
545 u32 saveGTIMR;
546 u32 saveFDI_RXA_IMR;
547 u32 saveFDI_RXB_IMR;
548 u32 saveCACHE_MODE_0;
549 u32 saveMI_ARB_STATE;
550 u32 saveSWF0[16];
551 u32 saveSWF1[16];
552 u32 saveSWF2[3];
553 u8 saveMSR;
554 u8 saveSR[8];
555 u8 saveGR[25];
556 u8 saveAR_INDEX;
557 u8 saveAR[21];
558 u8 saveDACMASK;
559 u8 saveCR[37];
560 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
561 u32 saveCURACNTR;
562 u32 saveCURAPOS;
563 u32 saveCURABASE;
564 u32 saveCURBCNTR;
565 u32 saveCURBPOS;
566 u32 saveCURBBASE;
567 u32 saveCURSIZE;
568 u32 saveDP_B;
569 u32 saveDP_C;
570 u32 saveDP_D;
571 u32 savePIPEA_GMCH_DATA_M;
572 u32 savePIPEB_GMCH_DATA_M;
573 u32 savePIPEA_GMCH_DATA_N;
574 u32 savePIPEB_GMCH_DATA_N;
575 u32 savePIPEA_DP_LINK_M;
576 u32 savePIPEB_DP_LINK_M;
577 u32 savePIPEA_DP_LINK_N;
578 u32 savePIPEB_DP_LINK_N;
579 u32 saveFDI_RXA_CTL;
580 u32 saveFDI_TXA_CTL;
581 u32 saveFDI_RXB_CTL;
582 u32 saveFDI_TXB_CTL;
583 u32 savePFA_CTL_1;
584 u32 savePFB_CTL_1;
585 u32 savePFA_WIN_SZ;
586 u32 savePFB_WIN_SZ;
587 u32 savePFA_WIN_POS;
588 u32 savePFB_WIN_POS;
589 u32 savePCH_DREF_CONTROL;
590 u32 saveDISP_ARB_CTL;
591 u32 savePIPEA_DATA_M1;
592 u32 savePIPEA_DATA_N1;
593 u32 savePIPEA_LINK_M1;
594 u32 savePIPEA_LINK_N1;
595 u32 savePIPEB_DATA_M1;
596 u32 savePIPEB_DATA_N1;
597 u32 savePIPEB_LINK_M1;
598 u32 savePIPEB_LINK_N1;
599 u32 saveMCHBAR_RENDER_STANDBY;
600 u32 savePCH_PORT_HOTPLUG;
601 };
602
603 struct intel_gen6_power_mgmt {
604 struct work_struct work;
605 u32 pm_iir;
606 /* lock - irqsave spinlock that protectects the work_struct and
607 * pm_iir. */
608 spinlock_t lock;
609
610 /* The below variables an all the rps hw state are protected by
611 * dev->struct mutext. */
612 u8 cur_delay;
613 u8 min_delay;
614 u8 max_delay;
615
616 struct delayed_work delayed_resume_work;
617
618 /*
619 * Protects RPS/RC6 register access and PCU communication.
620 * Must be taken after struct_mutex if nested.
621 */
622 struct mutex hw_lock;
623 };
624
625 /* defined intel_pm.c */
626 extern spinlock_t mchdev_lock;
627
628 struct intel_ilk_power_mgmt {
629 u8 cur_delay;
630 u8 min_delay;
631 u8 max_delay;
632 u8 fmax;
633 u8 fstart;
634
635 u64 last_count1;
636 unsigned long last_time1;
637 unsigned long chipset_power;
638 u64 last_count2;
639 struct timespec last_time2;
640 unsigned long gfx_power;
641 u8 corr;
642
643 int c_m;
644 int r_t;
645
646 struct drm_i915_gem_object *pwrctx;
647 struct drm_i915_gem_object *renderctx;
648 };
649
650 struct i915_dri1_state {
651 unsigned allow_batchbuffer : 1;
652 u32 __iomem *gfx_hws_cpu_addr;
653
654 unsigned int cpp;
655 int back_offset;
656 int front_offset;
657 int current_page;
658 int page_flipping;
659
660 uint32_t counter;
661 };
662
663 struct intel_l3_parity {
664 u32 *remap_info;
665 struct work_struct error_work;
666 };
667
668 typedef struct drm_i915_private {
669 struct drm_device *dev;
670 struct kmem_cache *slab;
671
672 const struct intel_device_info *info;
673
674 int relative_constants_mode;
675
676 void __iomem *regs;
677
678 struct drm_i915_gt_funcs gt;
679 /** gt_fifo_count and the subsequent register write are synchronized
680 * with dev->struct_mutex. */
681 unsigned gt_fifo_count;
682 /** forcewake_count is protected by gt_lock */
683 unsigned forcewake_count;
684 /** gt_lock is also taken in irq contexts. */
685 spinlock_t gt_lock;
686
687 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
688
689
690 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
691 * controller on different i2c buses. */
692 struct mutex gmbus_mutex;
693
694 /**
695 * Base address of the gmbus and gpio block.
696 */
697 uint32_t gpio_mmio_base;
698
699 wait_queue_head_t gmbus_wait_queue;
700
701 struct pci_dev *bridge_dev;
702 struct intel_ring_buffer ring[I915_NUM_RINGS];
703 uint32_t last_seqno, next_seqno;
704
705 drm_dma_handle_t *status_page_dmah;
706 struct resource mch_res;
707
708 atomic_t irq_received;
709
710 /* protects the irq masks */
711 spinlock_t irq_lock;
712
713 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
714 struct pm_qos_request pm_qos;
715
716 /* DPIO indirect register protection */
717 struct mutex dpio_lock;
718
719 /** Cached value of IMR to avoid reads in updating the bitfield */
720 u32 pipestat[2];
721 u32 irq_mask;
722 u32 gt_irq_mask;
723
724 u32 hotplug_supported_mask;
725 struct work_struct hotplug_work;
726 bool enable_hotplug_processing;
727
728 int num_pipe;
729 int num_pch_pll;
730
731 /* For hangcheck timer */
732 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
733 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
734 struct timer_list hangcheck_timer;
735 int hangcheck_count;
736 uint32_t last_acthd[I915_NUM_RINGS];
737 uint32_t prev_instdone[I915_NUM_INSTDONE_REG];
738
739 unsigned int stop_rings;
740
741 unsigned long cfb_size;
742 unsigned int cfb_fb;
743 enum plane cfb_plane;
744 int cfb_y;
745 struct intel_fbc_work *fbc_work;
746
747 struct intel_opregion opregion;
748
749 /* overlay */
750 struct intel_overlay *overlay;
751 bool sprite_scaling_enabled;
752
753 /* LVDS info */
754 int backlight_level; /* restore backlight to this value */
755 bool backlight_enabled;
756 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
757 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
758
759 /* Feature bits from the VBIOS */
760 unsigned int int_tv_support:1;
761 unsigned int lvds_dither:1;
762 unsigned int lvds_vbt:1;
763 unsigned int int_crt_support:1;
764 unsigned int lvds_use_ssc:1;
765 unsigned int display_clock_mode:1;
766 int lvds_ssc_freq;
767 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
768 struct {
769 int rate;
770 int lanes;
771 int preemphasis;
772 int vswing;
773
774 bool initialized;
775 bool support;
776 int bpp;
777 struct edp_power_seq pps;
778 } edp;
779 bool no_aux_handshake;
780
781 int crt_ddc_pin;
782 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
783 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
784 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
785
786 unsigned int fsb_freq, mem_freq, is_ddr3;
787
788 spinlock_t error_lock;
789 /* Protected by dev->error_lock. */
790 struct drm_i915_error_state *first_error;
791 struct work_struct error_work;
792 struct completion error_completion;
793 struct workqueue_struct *wq;
794
795 /* Display functions */
796 struct drm_i915_display_funcs display;
797
798 /* PCH chipset type */
799 enum intel_pch pch_type;
800 unsigned short pch_id;
801
802 unsigned long quirks;
803
804 /* Register state */
805 bool modeset_on_lid;
806
807 struct i915_gtt gtt;
808
809 struct {
810 /** Bridge to intel-gtt-ko */
811 struct intel_gtt *gtt;
812 /** Memory allocator for GTT stolen memory */
813 struct drm_mm stolen;
814 /** Memory allocator for GTT */
815 struct drm_mm gtt_space;
816 /** List of all objects in gtt_space. Used to restore gtt
817 * mappings on resume */
818 struct list_head bound_list;
819 /**
820 * List of objects which are not bound to the GTT (thus
821 * are idle and not used by the GPU) but still have
822 * (presumably uncached) pages still attached.
823 */
824 struct list_head unbound_list;
825
826 /** Usable portion of the GTT for GEM */
827 unsigned long stolen_base; /* limited to low memory (32-bit) */
828
829 int gtt_mtrr;
830
831 /** PPGTT used for aliasing the PPGTT with the GTT */
832 struct i915_hw_ppgtt *aliasing_ppgtt;
833
834 struct shrinker inactive_shrinker;
835 bool shrinker_no_lock_stealing;
836
837 /**
838 * List of objects currently involved in rendering.
839 *
840 * Includes buffers having the contents of their GPU caches
841 * flushed, not necessarily primitives. last_rendering_seqno
842 * represents when the rendering involved will be completed.
843 *
844 * A reference is held on the buffer while on this list.
845 */
846 struct list_head active_list;
847
848 /**
849 * LRU list of objects which are not in the ringbuffer and
850 * are ready to unbind, but are still in the GTT.
851 *
852 * last_rendering_seqno is 0 while an object is in this list.
853 *
854 * A reference is not held on the buffer while on this list,
855 * as merely being GTT-bound shouldn't prevent its being
856 * freed, and we'll pull it off the list in the free path.
857 */
858 struct list_head inactive_list;
859
860 /** LRU list of objects with fence regs on them. */
861 struct list_head fence_list;
862
863 /**
864 * We leave the user IRQ off as much as possible,
865 * but this means that requests will finish and never
866 * be retired once the system goes idle. Set a timer to
867 * fire periodically while the ring is running. When it
868 * fires, go retire requests.
869 */
870 struct delayed_work retire_work;
871
872 /**
873 * Are we in a non-interruptible section of code like
874 * modesetting?
875 */
876 bool interruptible;
877
878 /**
879 * Flag if the X Server, and thus DRM, is not currently in
880 * control of the device.
881 *
882 * This is set between LeaveVT and EnterVT. It needs to be
883 * replaced with a semaphore. It also needs to be
884 * transitioned away from for kernel modesetting.
885 */
886 int suspended;
887
888 /**
889 * Flag if the hardware appears to be wedged.
890 *
891 * This is set when attempts to idle the device timeout.
892 * It prevents command submission from occurring and makes
893 * every pending request fail
894 */
895 atomic_t wedged;
896
897 /** Bit 6 swizzling required for X tiling */
898 uint32_t bit_6_swizzle_x;
899 /** Bit 6 swizzling required for Y tiling */
900 uint32_t bit_6_swizzle_y;
901
902 /* storage for physical objects */
903 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
904
905 /* accounting, useful for userland debugging */
906 size_t object_memory;
907 u32 object_count;
908 } mm;
909
910 /* Kernel Modesetting */
911
912 struct sdvo_device_mapping sdvo_mappings[2];
913 /* indicate whether the LVDS_BORDER should be enabled or not */
914 unsigned int lvds_border_bits;
915 /* Panel fitter placement and size for Ironlake+ */
916 u32 pch_pf_pos, pch_pf_size;
917
918 struct drm_crtc *plane_to_crtc_mapping[3];
919 struct drm_crtc *pipe_to_crtc_mapping[3];
920 wait_queue_head_t pending_flip_queue;
921
922 struct intel_pch_pll pch_plls[I915_NUM_PLLS];
923 struct intel_ddi_plls ddi_plls;
924
925 /* Reclocking support */
926 bool render_reclock_avail;
927 bool lvds_downclock_avail;
928 /* indicates the reduced downclock for LVDS*/
929 int lvds_downclock;
930 u16 orig_clock;
931 int child_dev_num;
932 struct child_device_config *child_dev;
933
934 bool mchbar_need_disable;
935
936 struct intel_l3_parity l3_parity;
937
938 /* gen6+ rps state */
939 struct intel_gen6_power_mgmt rps;
940
941 /* ilk-only ips/rps state. Everything in here is protected by the global
942 * mchdev_lock in intel_pm.c */
943 struct intel_ilk_power_mgmt ips;
944
945 enum no_fbc_reason no_fbc_reason;
946
947 struct drm_mm_node *compressed_fb;
948 struct drm_mm_node *compressed_llb;
949
950 unsigned long last_gpu_reset;
951
952 /* list of fbdev register on this device */
953 struct intel_fbdev *fbdev;
954
955 /*
956 * The console may be contended at resume, but we don't
957 * want it to block on it.
958 */
959 struct work_struct console_resume_work;
960
961 struct backlight_device *backlight;
962
963 struct drm_property *broadcast_rgb_property;
964 struct drm_property *force_audio_property;
965
966 bool hw_contexts_disabled;
967 uint32_t hw_context_size;
968
969 bool fdi_rx_polarity_reversed;
970
971 struct i915_suspend_saved_registers regfile;
972
973 /* Old dri1 support infrastructure, beware the dragons ya fools entering
974 * here! */
975 struct i915_dri1_state dri1;
976 } drm_i915_private_t;
977
978 /* Iterate over initialised rings */
979 #define for_each_ring(ring__, dev_priv__, i__) \
980 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
981 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
982
983 enum hdmi_force_audio {
984 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
985 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
986 HDMI_AUDIO_AUTO, /* trust EDID */
987 HDMI_AUDIO_ON, /* force turn on HDMI audio */
988 };
989
990 enum i915_cache_level {
991 I915_CACHE_NONE = 0,
992 I915_CACHE_LLC,
993 I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
994 };
995
996 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
997
998 struct drm_i915_gem_object_ops {
999 /* Interface between the GEM object and its backing storage.
1000 * get_pages() is called once prior to the use of the associated set
1001 * of pages before to binding them into the GTT, and put_pages() is
1002 * called after we no longer need them. As we expect there to be
1003 * associated cost with migrating pages between the backing storage
1004 * and making them available for the GPU (e.g. clflush), we may hold
1005 * onto the pages after they are no longer referenced by the GPU
1006 * in case they may be used again shortly (for example migrating the
1007 * pages to a different memory domain within the GTT). put_pages()
1008 * will therefore most likely be called when the object itself is
1009 * being released or under memory pressure (where we attempt to
1010 * reap pages for the shrinker).
1011 */
1012 int (*get_pages)(struct drm_i915_gem_object *);
1013 void (*put_pages)(struct drm_i915_gem_object *);
1014 };
1015
1016 struct drm_i915_gem_object {
1017 struct drm_gem_object base;
1018
1019 const struct drm_i915_gem_object_ops *ops;
1020
1021 /** Current space allocated to this object in the GTT, if any. */
1022 struct drm_mm_node *gtt_space;
1023 /** Stolen memory for this object, instead of being backed by shmem. */
1024 struct drm_mm_node *stolen;
1025 struct list_head gtt_list;
1026
1027 /** This object's place on the active/inactive lists */
1028 struct list_head ring_list;
1029 struct list_head mm_list;
1030 /** This object's place in the batchbuffer or on the eviction list */
1031 struct list_head exec_list;
1032
1033 /**
1034 * This is set if the object is on the active lists (has pending
1035 * rendering and so a non-zero seqno), and is not set if it i s on
1036 * inactive (ready to be unbound) list.
1037 */
1038 unsigned int active:1;
1039
1040 /**
1041 * This is set if the object has been written to since last bound
1042 * to the GTT
1043 */
1044 unsigned int dirty:1;
1045
1046 /**
1047 * Fence register bits (if any) for this object. Will be set
1048 * as needed when mapped into the GTT.
1049 * Protected by dev->struct_mutex.
1050 */
1051 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1052
1053 /**
1054 * Advice: are the backing pages purgeable?
1055 */
1056 unsigned int madv:2;
1057
1058 /**
1059 * Current tiling mode for the object.
1060 */
1061 unsigned int tiling_mode:2;
1062 /**
1063 * Whether the tiling parameters for the currently associated fence
1064 * register have changed. Note that for the purposes of tracking
1065 * tiling changes we also treat the unfenced register, the register
1066 * slot that the object occupies whilst it executes a fenced
1067 * command (such as BLT on gen2/3), as a "fence".
1068 */
1069 unsigned int fence_dirty:1;
1070
1071 /** How many users have pinned this object in GTT space. The following
1072 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1073 * (via user_pin_count), execbuffer (objects are not allowed multiple
1074 * times for the same batchbuffer), and the framebuffer code. When
1075 * switching/pageflipping, the framebuffer code has at most two buffers
1076 * pinned per crtc.
1077 *
1078 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1079 * bits with absolutely no headroom. So use 4 bits. */
1080 unsigned int pin_count:4;
1081 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1082
1083 /**
1084 * Is the object at the current location in the gtt mappable and
1085 * fenceable? Used to avoid costly recalculations.
1086 */
1087 unsigned int map_and_fenceable:1;
1088
1089 /**
1090 * Whether the current gtt mapping needs to be mappable (and isn't just
1091 * mappable by accident). Track pin and fault separate for a more
1092 * accurate mappable working set.
1093 */
1094 unsigned int fault_mappable:1;
1095 unsigned int pin_mappable:1;
1096
1097 /*
1098 * Is the GPU currently using a fence to access this buffer,
1099 */
1100 unsigned int pending_fenced_gpu_access:1;
1101 unsigned int fenced_gpu_access:1;
1102
1103 unsigned int cache_level:2;
1104
1105 unsigned int has_aliasing_ppgtt_mapping:1;
1106 unsigned int has_global_gtt_mapping:1;
1107 unsigned int has_dma_mapping:1;
1108
1109 struct sg_table *pages;
1110 int pages_pin_count;
1111
1112 /* prime dma-buf support */
1113 void *dma_buf_vmapping;
1114 int vmapping_count;
1115
1116 /**
1117 * Used for performing relocations during execbuffer insertion.
1118 */
1119 struct hlist_node exec_node;
1120 unsigned long exec_handle;
1121 struct drm_i915_gem_exec_object2 *exec_entry;
1122
1123 /**
1124 * Current offset of the object in GTT space.
1125 *
1126 * This is the same as gtt_space->start
1127 */
1128 uint32_t gtt_offset;
1129
1130 struct intel_ring_buffer *ring;
1131
1132 /** Breadcrumb of last rendering to the buffer. */
1133 uint32_t last_read_seqno;
1134 uint32_t last_write_seqno;
1135 /** Breadcrumb of last fenced GPU access to the buffer. */
1136 uint32_t last_fenced_seqno;
1137
1138 /** Current tiling stride for the object, if it's tiled. */
1139 uint32_t stride;
1140
1141 /** Record of address bit 17 of each page at last unbind. */
1142 unsigned long *bit_17;
1143
1144 /** User space pin count and filp owning the pin */
1145 uint32_t user_pin_count;
1146 struct drm_file *pin_filp;
1147
1148 /** for phy allocated objects */
1149 struct drm_i915_gem_phys_object *phys_obj;
1150
1151 /**
1152 * Number of crtcs where this object is currently the fb, but
1153 * will be page flipped away on the next vblank. When it
1154 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1155 */
1156 atomic_t pending_flip;
1157 };
1158 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1159
1160 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1161
1162 /**
1163 * Request queue structure.
1164 *
1165 * The request queue allows us to note sequence numbers that have been emitted
1166 * and may be associated with active buffers to be retired.
1167 *
1168 * By keeping this list, we can avoid having to do questionable
1169 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1170 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1171 */
1172 struct drm_i915_gem_request {
1173 /** On Which ring this request was generated */
1174 struct intel_ring_buffer *ring;
1175
1176 /** GEM sequence number associated with this request. */
1177 uint32_t seqno;
1178
1179 /** Postion in the ringbuffer of the end of the request */
1180 u32 tail;
1181
1182 /** Time at which this request was emitted, in jiffies. */
1183 unsigned long emitted_jiffies;
1184
1185 /** global list entry for this request */
1186 struct list_head list;
1187
1188 struct drm_i915_file_private *file_priv;
1189 /** file_priv list entry for this request */
1190 struct list_head client_list;
1191 };
1192
1193 struct drm_i915_file_private {
1194 struct {
1195 spinlock_t lock;
1196 struct list_head request_list;
1197 } mm;
1198 struct idr context_idr;
1199 };
1200
1201 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1202
1203 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1204 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1205 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1206 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1207 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1208 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1209 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1210 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1211 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1212 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1213 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1214 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1215 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1216 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1217 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1218 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1219 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1220 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1221 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1222 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1223 (dev)->pci_device == 0x0152 || \
1224 (dev)->pci_device == 0x015a)
1225 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1226 (dev)->pci_device == 0x0106 || \
1227 (dev)->pci_device == 0x010A)
1228 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1229 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1230 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1231 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1232 ((dev)->pci_device & 0xFF00) == 0x0A00)
1233
1234 /*
1235 * The genX designation typically refers to the render engine, so render
1236 * capability related checks should use IS_GEN, while display and other checks
1237 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1238 * chips, etc.).
1239 */
1240 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1241 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1242 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1243 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1244 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1245 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1246
1247 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1248 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1249 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1250 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1251
1252 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1253 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1254
1255 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1256 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1257
1258 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1259 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1260
1261 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1262 * rows, which changed the alignment requirements and fence programming.
1263 */
1264 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1265 IS_I915GM(dev)))
1266 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1267 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1268 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1269 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1270 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1271 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1272 /* dsparb controlled by hw only */
1273 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1274
1275 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1276 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1277 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1278
1279 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1280
1281 #define HAS_DDI(dev) (IS_HASWELL(dev))
1282
1283 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1284 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1285 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1286 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1287 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1288 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1289
1290 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1291 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1292 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1293 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1294 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1295
1296 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1297
1298 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1299
1300 #define GT_FREQUENCY_MULTIPLIER 50
1301
1302 #include "i915_trace.h"
1303
1304 /**
1305 * RC6 is a special power stage which allows the GPU to enter an very
1306 * low-voltage mode when idle, using down to 0V while at this stage. This
1307 * stage is entered automatically when the GPU is idle when RC6 support is
1308 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1309 *
1310 * There are different RC6 modes available in Intel GPU, which differentiate
1311 * among each other with the latency required to enter and leave RC6 and
1312 * voltage consumed by the GPU in different states.
1313 *
1314 * The combination of the following flags define which states GPU is allowed
1315 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1316 * RC6pp is deepest RC6. Their support by hardware varies according to the
1317 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1318 * which brings the most power savings; deeper states save more power, but
1319 * require higher latency to switch to and wake up.
1320 */
1321 #define INTEL_RC6_ENABLE (1<<0)
1322 #define INTEL_RC6p_ENABLE (1<<1)
1323 #define INTEL_RC6pp_ENABLE (1<<2)
1324
1325 extern struct drm_ioctl_desc i915_ioctls[];
1326 extern int i915_max_ioctl;
1327 extern unsigned int i915_fbpercrtc __always_unused;
1328 extern int i915_panel_ignore_lid __read_mostly;
1329 extern unsigned int i915_powersave __read_mostly;
1330 extern int i915_semaphores __read_mostly;
1331 extern unsigned int i915_lvds_downclock __read_mostly;
1332 extern int i915_lvds_channel_mode __read_mostly;
1333 extern int i915_panel_use_ssc __read_mostly;
1334 extern int i915_vbt_sdvo_panel_type __read_mostly;
1335 extern int i915_enable_rc6 __read_mostly;
1336 extern int i915_enable_fbc __read_mostly;
1337 extern bool i915_enable_hangcheck __read_mostly;
1338 extern int i915_enable_ppgtt __read_mostly;
1339 extern unsigned int i915_preliminary_hw_support __read_mostly;
1340
1341 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1342 extern int i915_resume(struct drm_device *dev);
1343 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1344 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1345
1346 /* i915_dma.c */
1347 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1348 extern void i915_kernel_lost_context(struct drm_device * dev);
1349 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1350 extern int i915_driver_unload(struct drm_device *);
1351 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1352 extern void i915_driver_lastclose(struct drm_device * dev);
1353 extern void i915_driver_preclose(struct drm_device *dev,
1354 struct drm_file *file_priv);
1355 extern void i915_driver_postclose(struct drm_device *dev,
1356 struct drm_file *file_priv);
1357 extern int i915_driver_device_is_agp(struct drm_device * dev);
1358 #ifdef CONFIG_COMPAT
1359 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1360 unsigned long arg);
1361 #endif
1362 extern int i915_emit_box(struct drm_device *dev,
1363 struct drm_clip_rect *box,
1364 int DR1, int DR4);
1365 extern int intel_gpu_reset(struct drm_device *dev);
1366 extern int i915_reset(struct drm_device *dev);
1367 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1368 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1369 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1370 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1371
1372 extern void intel_console_resume(struct work_struct *work);
1373
1374 /* i915_irq.c */
1375 void i915_hangcheck_elapsed(unsigned long data);
1376 void i915_handle_error(struct drm_device *dev, bool wedged);
1377
1378 extern void intel_irq_init(struct drm_device *dev);
1379 extern void intel_hpd_init(struct drm_device *dev);
1380 extern void intel_gt_init(struct drm_device *dev);
1381 extern void intel_gt_reset(struct drm_device *dev);
1382
1383 void i915_error_state_free(struct kref *error_ref);
1384
1385 void
1386 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1387
1388 void
1389 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1390
1391 void intel_enable_asle(struct drm_device *dev);
1392
1393 #ifdef CONFIG_DEBUG_FS
1394 extern void i915_destroy_error_state(struct drm_device *dev);
1395 #else
1396 #define i915_destroy_error_state(x)
1397 #endif
1398
1399
1400 /* i915_gem.c */
1401 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1402 struct drm_file *file_priv);
1403 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1404 struct drm_file *file_priv);
1405 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1406 struct drm_file *file_priv);
1407 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1408 struct drm_file *file_priv);
1409 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1410 struct drm_file *file_priv);
1411 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1412 struct drm_file *file_priv);
1413 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1414 struct drm_file *file_priv);
1415 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1416 struct drm_file *file_priv);
1417 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1418 struct drm_file *file_priv);
1419 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1420 struct drm_file *file_priv);
1421 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1422 struct drm_file *file_priv);
1423 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1424 struct drm_file *file_priv);
1425 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1426 struct drm_file *file_priv);
1427 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
1428 struct drm_file *file);
1429 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
1430 struct drm_file *file);
1431 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1432 struct drm_file *file_priv);
1433 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1434 struct drm_file *file_priv);
1435 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1436 struct drm_file *file_priv);
1437 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1438 struct drm_file *file_priv);
1439 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1440 struct drm_file *file_priv);
1441 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1442 struct drm_file *file_priv);
1443 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1444 struct drm_file *file_priv);
1445 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
1446 struct drm_file *file_priv);
1447 void i915_gem_load(struct drm_device *dev);
1448 void *i915_gem_object_alloc(struct drm_device *dev);
1449 void i915_gem_object_free(struct drm_i915_gem_object *obj);
1450 int i915_gem_init_object(struct drm_gem_object *obj);
1451 void i915_gem_object_init(struct drm_i915_gem_object *obj,
1452 const struct drm_i915_gem_object_ops *ops);
1453 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1454 size_t size);
1455 void i915_gem_free_object(struct drm_gem_object *obj);
1456
1457 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1458 uint32_t alignment,
1459 bool map_and_fenceable,
1460 bool nonblocking);
1461 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1462 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1463 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
1464 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1465 void i915_gem_lastclose(struct drm_device *dev);
1466
1467 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
1468 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
1469 {
1470 struct scatterlist *sg = obj->pages->sgl;
1471 int nents = obj->pages->nents;
1472 while (nents > SG_MAX_SINGLE_ALLOC) {
1473 if (n < SG_MAX_SINGLE_ALLOC - 1)
1474 break;
1475
1476 sg = sg_chain_ptr(sg + SG_MAX_SINGLE_ALLOC - 1);
1477 n -= SG_MAX_SINGLE_ALLOC - 1;
1478 nents -= SG_MAX_SINGLE_ALLOC - 1;
1479 }
1480 return sg_page(sg+n);
1481 }
1482 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
1483 {
1484 BUG_ON(obj->pages == NULL);
1485 obj->pages_pin_count++;
1486 }
1487 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
1488 {
1489 BUG_ON(obj->pages_pin_count == 0);
1490 obj->pages_pin_count--;
1491 }
1492
1493 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1494 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
1495 struct intel_ring_buffer *to);
1496 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1497 struct intel_ring_buffer *ring);
1498
1499 int i915_gem_dumb_create(struct drm_file *file_priv,
1500 struct drm_device *dev,
1501 struct drm_mode_create_dumb *args);
1502 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1503 uint32_t handle, uint64_t *offset);
1504 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1505 uint32_t handle);
1506 /**
1507 * Returns true if seq1 is later than seq2.
1508 */
1509 static inline bool
1510 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1511 {
1512 return (int32_t)(seq1 - seq2) >= 0;
1513 }
1514
1515 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
1516 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
1517 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
1518 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1519
1520 static inline bool
1521 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
1522 {
1523 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1524 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1525 dev_priv->fence_regs[obj->fence_reg].pin_count++;
1526 return true;
1527 } else
1528 return false;
1529 }
1530
1531 static inline void
1532 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
1533 {
1534 if (obj->fence_reg != I915_FENCE_REG_NONE) {
1535 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
1536 dev_priv->fence_regs[obj->fence_reg].pin_count--;
1537 }
1538 }
1539
1540 void i915_gem_retire_requests(struct drm_device *dev);
1541 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
1542 int __must_check i915_gem_check_wedge(struct drm_i915_private *dev_priv,
1543 bool interruptible);
1544
1545 void i915_gem_reset(struct drm_device *dev);
1546 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1547 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1548 uint32_t read_domains,
1549 uint32_t write_domain);
1550 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1551 int __must_check i915_gem_init(struct drm_device *dev);
1552 int __must_check i915_gem_init_hw(struct drm_device *dev);
1553 void i915_gem_l3_remap(struct drm_device *dev);
1554 void i915_gem_init_swizzling(struct drm_device *dev);
1555 void i915_gem_init_ppgtt(struct drm_device *dev);
1556 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1557 int __must_check i915_gpu_idle(struct drm_device *dev);
1558 int __must_check i915_gem_idle(struct drm_device *dev);
1559 int i915_add_request(struct intel_ring_buffer *ring,
1560 struct drm_file *file,
1561 u32 *seqno);
1562 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
1563 uint32_t seqno);
1564 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1565 int __must_check
1566 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1567 bool write);
1568 int __must_check
1569 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
1570 int __must_check
1571 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1572 u32 alignment,
1573 struct intel_ring_buffer *pipelined);
1574 int i915_gem_attach_phys_object(struct drm_device *dev,
1575 struct drm_i915_gem_object *obj,
1576 int id,
1577 int align);
1578 void i915_gem_detach_phys_object(struct drm_device *dev,
1579 struct drm_i915_gem_object *obj);
1580 void i915_gem_free_all_phys_object(struct drm_device *dev);
1581 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1582
1583 uint32_t
1584 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
1585 uint32_t
1586 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
1587 int tiling_mode, bool fenced);
1588
1589 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1590 enum i915_cache_level cache_level);
1591
1592 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
1593 struct dma_buf *dma_buf);
1594
1595 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
1596 struct drm_gem_object *gem_obj, int flags);
1597
1598 /* i915_gem_context.c */
1599 void i915_gem_context_init(struct drm_device *dev);
1600 void i915_gem_context_fini(struct drm_device *dev);
1601 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
1602 int i915_switch_context(struct intel_ring_buffer *ring,
1603 struct drm_file *file, int to_id);
1604 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
1605 struct drm_file *file);
1606 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
1607 struct drm_file *file);
1608
1609 /* i915_gem_gtt.c */
1610 int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
1611 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
1612 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
1613 struct drm_i915_gem_object *obj,
1614 enum i915_cache_level cache_level);
1615 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt *ppgtt,
1616 struct drm_i915_gem_object *obj);
1617
1618 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1619 int __must_check i915_gem_gtt_prepare_object(struct drm_i915_gem_object *obj);
1620 void i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj,
1621 enum i915_cache_level cache_level);
1622 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1623 void i915_gem_gtt_finish_object(struct drm_i915_gem_object *obj);
1624 void i915_gem_init_global_gtt(struct drm_device *dev);
1625 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
1626 unsigned long mappable_end, unsigned long end);
1627 int i915_gem_gtt_init(struct drm_device *dev);
1628 void i915_gem_gtt_fini(struct drm_device *dev);
1629 static inline void i915_gem_chipset_flush(struct drm_device *dev)
1630 {
1631 if (INTEL_INFO(dev)->gen < 6)
1632 intel_gtt_chipset_flush();
1633 }
1634
1635
1636 /* i915_gem_evict.c */
1637 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1638 unsigned alignment,
1639 unsigned cache_level,
1640 bool mappable,
1641 bool nonblock);
1642 int i915_gem_evict_everything(struct drm_device *dev);
1643
1644 /* i915_gem_stolen.c */
1645 int i915_gem_init_stolen(struct drm_device *dev);
1646 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
1647 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
1648 void i915_gem_cleanup_stolen(struct drm_device *dev);
1649 struct drm_i915_gem_object *
1650 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
1651 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
1652
1653 /* i915_gem_tiling.c */
1654 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
1655 {
1656 drm_i915_private_t *dev_priv = obj->base.dev->dev_private;
1657
1658 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
1659 obj->tiling_mode != I915_TILING_NONE;
1660 }
1661
1662 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1663 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1664 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1665
1666 /* i915_gem_debug.c */
1667 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1668 const char *where, uint32_t mark);
1669 #if WATCH_LISTS
1670 int i915_verify_lists(struct drm_device *dev);
1671 #else
1672 #define i915_verify_lists(dev) 0
1673 #endif
1674 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1675 int handle);
1676 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1677 const char *where, uint32_t mark);
1678
1679 /* i915_debugfs.c */
1680 int i915_debugfs_init(struct drm_minor *minor);
1681 void i915_debugfs_cleanup(struct drm_minor *minor);
1682
1683 /* i915_suspend.c */
1684 extern int i915_save_state(struct drm_device *dev);
1685 extern int i915_restore_state(struct drm_device *dev);
1686
1687 /* i915_suspend.c */
1688 extern int i915_save_state(struct drm_device *dev);
1689 extern int i915_restore_state(struct drm_device *dev);
1690
1691 /* i915_sysfs.c */
1692 void i915_setup_sysfs(struct drm_device *dev_priv);
1693 void i915_teardown_sysfs(struct drm_device *dev_priv);
1694
1695 /* intel_i2c.c */
1696 extern int intel_setup_gmbus(struct drm_device *dev);
1697 extern void intel_teardown_gmbus(struct drm_device *dev);
1698 extern inline bool intel_gmbus_is_port_valid(unsigned port)
1699 {
1700 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
1701 }
1702
1703 extern struct i2c_adapter *intel_gmbus_get_adapter(
1704 struct drm_i915_private *dev_priv, unsigned port);
1705 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1706 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1707 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1708 {
1709 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1710 }
1711 extern void intel_i2c_reset(struct drm_device *dev);
1712
1713 /* intel_opregion.c */
1714 extern int intel_opregion_setup(struct drm_device *dev);
1715 #ifdef CONFIG_ACPI
1716 extern void intel_opregion_init(struct drm_device *dev);
1717 extern void intel_opregion_fini(struct drm_device *dev);
1718 extern void intel_opregion_asle_intr(struct drm_device *dev);
1719 extern void intel_opregion_gse_intr(struct drm_device *dev);
1720 extern void intel_opregion_enable_asle(struct drm_device *dev);
1721 #else
1722 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1723 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1724 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1725 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1726 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1727 #endif
1728
1729 /* intel_acpi.c */
1730 #ifdef CONFIG_ACPI
1731 extern void intel_register_dsm_handler(void);
1732 extern void intel_unregister_dsm_handler(void);
1733 #else
1734 static inline void intel_register_dsm_handler(void) { return; }
1735 static inline void intel_unregister_dsm_handler(void) { return; }
1736 #endif /* CONFIG_ACPI */
1737
1738 /* modesetting */
1739 extern void intel_modeset_init_hw(struct drm_device *dev);
1740 extern void intel_modeset_init(struct drm_device *dev);
1741 extern void intel_modeset_gem_init(struct drm_device *dev);
1742 extern void intel_modeset_cleanup(struct drm_device *dev);
1743 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1744 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
1745 bool force_restore);
1746 extern bool intel_fbc_enabled(struct drm_device *dev);
1747 extern void intel_disable_fbc(struct drm_device *dev);
1748 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1749 extern void intel_init_pch_refclk(struct drm_device *dev);
1750 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1751 extern void intel_detect_pch(struct drm_device *dev);
1752 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1753 extern int intel_enable_rc6(const struct drm_device *dev);
1754
1755 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
1756 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
1757 struct drm_file *file);
1758
1759 /* overlay */
1760 #ifdef CONFIG_DEBUG_FS
1761 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1762 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1763
1764 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1765 extern void intel_display_print_error_state(struct seq_file *m,
1766 struct drm_device *dev,
1767 struct intel_display_error_state *error);
1768 #endif
1769
1770 /* On SNB platform, before reading ring registers forcewake bit
1771 * must be set to prevent GT core from power down and stale values being
1772 * returned.
1773 */
1774 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1775 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1776 int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1777
1778 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
1779 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
1780
1781 #define __i915_read(x, y) \
1782 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1783
1784 __i915_read(8, b)
1785 __i915_read(16, w)
1786 __i915_read(32, l)
1787 __i915_read(64, q)
1788 #undef __i915_read
1789
1790 #define __i915_write(x, y) \
1791 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1792
1793 __i915_write(8, b)
1794 __i915_write(16, w)
1795 __i915_write(32, l)
1796 __i915_write(64, q)
1797 #undef __i915_write
1798
1799 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1800 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1801
1802 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1803 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1804 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1805 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1806
1807 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1808 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1809 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1810 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1811
1812 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1813 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1814
1815 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1816 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1817
1818 /* "Broadcast RGB" property */
1819 #define INTEL_BROADCAST_RGB_AUTO 0
1820 #define INTEL_BROADCAST_RGB_FULL 1
1821 #define INTEL_BROADCAST_RGB_LIMITED 2
1822
1823 #endif
Linux kernel - Deliverables
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