1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 #include <linux/backlight.h>
41 /* General customization:
44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
46 #define DRIVER_NAME "i915"
47 #define DRIVER_DESC "Intel Graphics"
48 #define DRIVER_DATE "20080730"
56 #define pipe_name(p) ((p) + 'A')
63 #define plane_name(p) ((p) + 'A')
65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
79 #define DRIVER_MAJOR 1
80 #define DRIVER_MINOR 6
81 #define DRIVER_PATCHLEVEL 0
83 #define WATCH_COHERENCY 0
86 #define I915_GEM_PHYS_CURSOR_0 1
87 #define I915_GEM_PHYS_CURSOR_1 2
88 #define I915_GEM_PHYS_OVERLAY_REGS 3
89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
91 struct drm_i915_gem_phys_object
{
93 struct page
**page_list
;
94 drm_dma_handle_t
*handle
;
95 struct drm_i915_gem_object
*cur_obj
;
99 struct mem_block
*next
;
100 struct mem_block
*prev
;
103 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
106 struct opregion_header
;
107 struct opregion_acpi
;
108 struct opregion_swsci
;
109 struct opregion_asle
;
110 struct drm_i915_private
;
112 struct intel_opregion
{
113 struct opregion_header
*header
;
114 struct opregion_acpi
*acpi
;
115 struct opregion_swsci
*swsci
;
116 struct opregion_asle
*asle
;
118 u32 __iomem
*lid_state
;
120 #define OPREGION_SIZE (8*1024)
122 struct intel_overlay
;
123 struct intel_overlay_error_state
;
125 struct drm_i915_master_private
{
126 drm_local_map_t
*sarea
;
127 struct _drm_i915_sarea
*sarea_priv
;
129 #define I915_FENCE_REG_NONE -1
130 #define I915_MAX_NUM_FENCES 16
131 /* 16 fences + sign bit for FENCE_REG_NONE */
132 #define I915_MAX_NUM_FENCE_BITS 5
134 struct drm_i915_fence_reg
{
135 struct list_head lru_list
;
136 struct drm_i915_gem_object
*obj
;
137 uint32_t setup_seqno
;
141 struct sdvo_device_mapping
{
150 struct intel_display_error_state
;
152 struct drm_i915_error_state
{
155 u32 pipestat
[I915_MAX_PIPES
];
156 u32 tail
[I915_NUM_RINGS
];
157 u32 head
[I915_NUM_RINGS
];
158 u32 ipeir
[I915_NUM_RINGS
];
159 u32 ipehr
[I915_NUM_RINGS
];
160 u32 instdone
[I915_NUM_RINGS
];
161 u32 acthd
[I915_NUM_RINGS
];
162 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
163 /* our own tracking of ring head and tail */
164 u32 cpu_ring_head
[I915_NUM_RINGS
];
165 u32 cpu_ring_tail
[I915_NUM_RINGS
];
166 u32 error
; /* gen6+ */
167 u32 instpm
[I915_NUM_RINGS
];
168 u32 instps
[I915_NUM_RINGS
];
170 u32 seqno
[I915_NUM_RINGS
];
172 u32 fault_reg
[I915_NUM_RINGS
];
174 u32 faddr
[I915_NUM_RINGS
];
175 u64 fence
[I915_MAX_NUM_FENCES
];
177 struct drm_i915_error_object
{
181 } *ringbuffer
[I915_NUM_RINGS
], *batchbuffer
[I915_NUM_RINGS
];
182 struct drm_i915_error_buffer
{
189 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
196 } *active_bo
, *pinned_bo
;
197 u32 active_bo_count
, pinned_bo_count
;
198 struct intel_overlay_error_state
*overlay
;
199 struct intel_display_error_state
*display
;
202 struct drm_i915_display_funcs
{
203 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
204 bool (*fbc_enabled
)(struct drm_device
*dev
);
205 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
206 void (*disable_fbc
)(struct drm_device
*dev
);
207 int (*get_display_clock_speed
)(struct drm_device
*dev
);
208 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
209 void (*update_wm
)(struct drm_device
*dev
);
210 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
211 uint32_t sprite_width
, int pixel_size
);
212 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
213 struct drm_display_mode
*mode
,
214 struct drm_display_mode
*adjusted_mode
,
216 struct drm_framebuffer
*old_fb
);
217 void (*write_eld
)(struct drm_connector
*connector
,
218 struct drm_crtc
*crtc
);
219 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
220 void (*init_clock_gating
)(struct drm_device
*dev
);
221 void (*init_pch_clock_gating
)(struct drm_device
*dev
);
222 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
223 struct drm_framebuffer
*fb
,
224 struct drm_i915_gem_object
*obj
);
225 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
227 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
228 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
229 /* clock updates for mode set */
231 /* render clock increase/decrease */
232 /* display clock increase/decrease */
233 /* pll clock increase/decrease */
236 struct intel_device_info
{
252 u8 cursor_needs_physical
:1;
254 u8 overlay_needs_physical
:1;
261 #define I915_PPGTT_PD_ENTRIES 512
262 #define I915_PPGTT_PT_ENTRIES 1024
263 struct i915_hw_ppgtt
{
264 unsigned num_pd_entries
;
265 struct page
**pt_pages
;
267 dma_addr_t
*pt_dma_addr
;
268 dma_addr_t scratch_page_dma_addr
;
272 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
273 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
274 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
275 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
276 FBC_BAD_PLANE
, /* fbc not supported on plane */
277 FBC_NOT_TILED
, /* buffer not tiled */
278 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
283 PCH_IBX
, /* Ibexpeak PCH */
284 PCH_CPT
, /* Cougarpoint PCH */
287 #define QUIRK_PIPEA_FORCE (1<<0)
288 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
291 struct intel_fbc_work
;
293 typedef struct drm_i915_private
{
294 struct drm_device
*dev
;
296 const struct intel_device_info
*info
;
299 int relative_constants_mode
;
305 struct i2c_adapter adapter
;
306 struct i2c_adapter
*force_bit
;
310 struct pci_dev
*bridge_dev
;
311 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
314 drm_dma_handle_t
*status_page_dmah
;
316 drm_local_map_t hws_map
;
317 struct drm_i915_gem_object
*pwrctx
;
318 struct drm_i915_gem_object
*renderctx
;
320 struct resource mch_res
;
328 atomic_t irq_received
;
330 /* protects the irq masks */
332 /** Cached value of IMR to avoid reads in updating the bitfield */
338 u32 hotplug_supported_mask
;
339 struct work_struct hotplug_work
;
341 int tex_lru_log_granularity
;
342 int allow_batchbuffer
;
343 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
347 /* For hangcheck timer */
348 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
349 struct timer_list hangcheck_timer
;
352 uint32_t last_acthd_bsd
;
353 uint32_t last_acthd_blt
;
354 uint32_t last_instdone
;
355 uint32_t last_instdone1
;
357 unsigned long cfb_size
;
359 enum plane cfb_plane
;
361 struct intel_fbc_work
*fbc_work
;
363 struct intel_opregion opregion
;
366 struct intel_overlay
*overlay
;
367 bool sprite_scaling_enabled
;
370 int backlight_level
; /* restore backlight to this value */
371 bool backlight_enabled
;
372 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
373 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
375 /* Feature bits from the VBIOS */
376 unsigned int int_tv_support
:1;
377 unsigned int lvds_dither
:1;
378 unsigned int lvds_vbt
:1;
379 unsigned int int_crt_support
:1;
380 unsigned int lvds_use_ssc
:1;
381 unsigned int display_clock_mode
:1;
392 struct edp_power_seq pps
;
394 bool no_aux_handshake
;
396 struct notifier_block lid_notifier
;
399 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
400 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
401 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
403 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
405 spinlock_t error_lock
;
406 struct drm_i915_error_state
*first_error
;
407 struct work_struct error_work
;
408 struct completion error_completion
;
409 struct workqueue_struct
*wq
;
411 /* Display functions */
412 struct drm_i915_display_funcs display
;
414 /* PCH chipset type */
415 enum intel_pch pch_type
;
417 unsigned long quirks
;
442 u32 saveTRANS_HTOTAL_A
;
443 u32 saveTRANS_HBLANK_A
;
444 u32 saveTRANS_HSYNC_A
;
445 u32 saveTRANS_VTOTAL_A
;
446 u32 saveTRANS_VBLANK_A
;
447 u32 saveTRANS_VSYNC_A
;
455 u32 savePFIT_PGM_RATIOS
;
456 u32 saveBLC_HIST_CTL
;
458 u32 saveBLC_PWM_CTL2
;
459 u32 saveBLC_CPU_PWM_CTL
;
460 u32 saveBLC_CPU_PWM_CTL2
;
473 u32 saveTRANS_HTOTAL_B
;
474 u32 saveTRANS_HBLANK_B
;
475 u32 saveTRANS_HSYNC_B
;
476 u32 saveTRANS_VTOTAL_B
;
477 u32 saveTRANS_VBLANK_B
;
478 u32 saveTRANS_VSYNC_B
;
492 u32 savePP_ON_DELAYS
;
493 u32 savePP_OFF_DELAYS
;
501 u32 savePFIT_CONTROL
;
502 u32 save_palette_a
[256];
503 u32 save_palette_b
[256];
504 u32 saveDPFC_CB_BASE
;
505 u32 saveFBC_CFB_BASE
;
508 u32 saveFBC_CONTROL2
;
518 u32 saveCACHE_MODE_0
;
519 u32 saveMI_ARB_STATE
;
530 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
541 u32 savePIPEA_GMCH_DATA_M
;
542 u32 savePIPEB_GMCH_DATA_M
;
543 u32 savePIPEA_GMCH_DATA_N
;
544 u32 savePIPEB_GMCH_DATA_N
;
545 u32 savePIPEA_DP_LINK_M
;
546 u32 savePIPEB_DP_LINK_M
;
547 u32 savePIPEA_DP_LINK_N
;
548 u32 savePIPEB_DP_LINK_N
;
559 u32 savePCH_DREF_CONTROL
;
560 u32 saveDISP_ARB_CTL
;
561 u32 savePIPEA_DATA_M1
;
562 u32 savePIPEA_DATA_N1
;
563 u32 savePIPEA_LINK_M1
;
564 u32 savePIPEA_LINK_N1
;
565 u32 savePIPEB_DATA_M1
;
566 u32 savePIPEB_DATA_N1
;
567 u32 savePIPEB_LINK_M1
;
568 u32 savePIPEB_LINK_N1
;
569 u32 saveMCHBAR_RENDER_STANDBY
;
570 u32 savePCH_PORT_HOTPLUG
;
573 /** Bridge to intel-gtt-ko */
574 const struct intel_gtt
*gtt
;
575 /** Memory allocator for GTT stolen memory */
576 struct drm_mm stolen
;
577 /** Memory allocator for GTT */
578 struct drm_mm gtt_space
;
579 /** List of all objects in gtt_space. Used to restore gtt
580 * mappings on resume */
581 struct list_head gtt_list
;
583 /** Usable portion of the GTT for GEM */
584 unsigned long gtt_start
;
585 unsigned long gtt_mappable_end
;
586 unsigned long gtt_end
;
588 struct io_mapping
*gtt_mapping
;
591 /** PPGTT used for aliasing the PPGTT with the GTT */
592 struct i915_hw_ppgtt
*aliasing_ppgtt
;
594 struct shrinker inactive_shrinker
;
597 * List of objects currently involved in rendering.
599 * Includes buffers having the contents of their GPU caches
600 * flushed, not necessarily primitives. last_rendering_seqno
601 * represents when the rendering involved will be completed.
603 * A reference is held on the buffer while on this list.
605 struct list_head active_list
;
608 * List of objects which are not in the ringbuffer but which
609 * still have a write_domain which needs to be flushed before
612 * last_rendering_seqno is 0 while an object is in this list.
614 * A reference is held on the buffer while on this list.
616 struct list_head flushing_list
;
619 * LRU list of objects which are not in the ringbuffer and
620 * are ready to unbind, but are still in the GTT.
622 * last_rendering_seqno is 0 while an object is in this list.
624 * A reference is not held on the buffer while on this list,
625 * as merely being GTT-bound shouldn't prevent its being
626 * freed, and we'll pull it off the list in the free path.
628 struct list_head inactive_list
;
631 * LRU list of objects which are not in the ringbuffer but
632 * are still pinned in the GTT.
634 struct list_head pinned_list
;
636 /** LRU list of objects with fence regs on them. */
637 struct list_head fence_list
;
640 * List of objects currently pending being freed.
642 * These objects are no longer in use, but due to a signal
643 * we were prevented from freeing them at the appointed time.
645 struct list_head deferred_free_list
;
648 * We leave the user IRQ off as much as possible,
649 * but this means that requests will finish and never
650 * be retired once the system goes idle. Set a timer to
651 * fire periodically while the ring is running. When it
652 * fires, go retire requests.
654 struct delayed_work retire_work
;
657 * Are we in a non-interruptible section of code like
663 * Flag if the X Server, and thus DRM, is not currently in
664 * control of the device.
666 * This is set between LeaveVT and EnterVT. It needs to be
667 * replaced with a semaphore. It also needs to be
668 * transitioned away from for kernel modesetting.
673 * Flag if the hardware appears to be wedged.
675 * This is set when attempts to idle the device timeout.
676 * It prevents command submission from occurring and makes
677 * every pending request fail
681 /** Bit 6 swizzling required for X tiling */
682 uint32_t bit_6_swizzle_x
;
683 /** Bit 6 swizzling required for Y tiling */
684 uint32_t bit_6_swizzle_y
;
686 /* storage for physical objects */
687 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
689 /* accounting, useful for userland debugging */
691 size_t mappable_gtt_total
;
692 size_t object_memory
;
695 struct sdvo_device_mapping sdvo_mappings
[2];
696 /* indicate whether the LVDS_BORDER should be enabled or not */
697 unsigned int lvds_border_bits
;
698 /* Panel fitter placement and size for Ironlake+ */
699 u32 pch_pf_pos
, pch_pf_size
;
701 struct drm_crtc
*plane_to_crtc_mapping
[3];
702 struct drm_crtc
*pipe_to_crtc_mapping
[3];
703 wait_queue_head_t pending_flip_queue
;
704 bool flip_pending_is_done
;
706 /* Reclocking support */
707 bool render_reclock_avail
;
708 bool lvds_downclock_avail
;
709 /* indicates the reduced downclock for LVDS*/
711 struct work_struct idle_work
;
712 struct timer_list idle_timer
;
716 struct child_device_config
*child_dev
;
717 struct drm_connector
*int_lvds_connector
;
718 struct drm_connector
*int_edp_connector
;
720 bool mchbar_need_disable
;
722 struct work_struct rps_work
;
733 unsigned long last_time1
;
734 unsigned long chipset_power
;
736 struct timespec last_time2
;
737 unsigned long gfx_power
;
741 spinlock_t
*mchdev_lock
;
743 enum no_fbc_reason no_fbc_reason
;
745 struct drm_mm_node
*compressed_fb
;
746 struct drm_mm_node
*compressed_llb
;
748 unsigned long last_gpu_reset
;
750 /* list of fbdev register on this device */
751 struct intel_fbdev
*fbdev
;
753 struct backlight_device
*backlight
;
755 struct drm_property
*broadcast_rgb_property
;
756 struct drm_property
*force_audio_property
;
758 atomic_t forcewake_count
;
759 } drm_i915_private_t
;
761 enum i915_cache_level
{
764 I915_CACHE_LLC_MLC
, /* gen6+ */
767 struct drm_i915_gem_object
{
768 struct drm_gem_object base
;
770 /** Current space allocated to this object in the GTT, if any. */
771 struct drm_mm_node
*gtt_space
;
772 struct list_head gtt_list
;
774 /** This object's place on the active/flushing/inactive lists */
775 struct list_head ring_list
;
776 struct list_head mm_list
;
777 /** This object's place on GPU write list */
778 struct list_head gpu_write_list
;
779 /** This object's place in the batchbuffer or on the eviction list */
780 struct list_head exec_list
;
783 * This is set if the object is on the active or flushing lists
784 * (has pending rendering), and is not set if it's on inactive (ready
787 unsigned int active
:1;
790 * This is set if the object has been written to since last bound
793 unsigned int dirty
:1;
796 * This is set if the object has been written to since the last
799 unsigned int pending_gpu_write
:1;
802 * Fence register bits (if any) for this object. Will be set
803 * as needed when mapped into the GTT.
804 * Protected by dev->struct_mutex.
806 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
809 * Advice: are the backing pages purgeable?
814 * Current tiling mode for the object.
816 unsigned int tiling_mode
:2;
817 unsigned int tiling_changed
:1;
819 /** How many users have pinned this object in GTT space. The following
820 * users can each hold at most one reference: pwrite/pread, pin_ioctl
821 * (via user_pin_count), execbuffer (objects are not allowed multiple
822 * times for the same batchbuffer), and the framebuffer code. When
823 * switching/pageflipping, the framebuffer code has at most two buffers
826 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
827 * bits with absolutely no headroom. So use 4 bits. */
828 unsigned int pin_count
:4;
829 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
832 * Is the object at the current location in the gtt mappable and
833 * fenceable? Used to avoid costly recalculations.
835 unsigned int map_and_fenceable
:1;
838 * Whether the current gtt mapping needs to be mappable (and isn't just
839 * mappable by accident). Track pin and fault separate for a more
840 * accurate mappable working set.
842 unsigned int fault_mappable
:1;
843 unsigned int pin_mappable
:1;
846 * Is the GPU currently using a fence to access this buffer,
848 unsigned int pending_fenced_gpu_access
:1;
849 unsigned int fenced_gpu_access
:1;
851 unsigned int cache_level
:2;
853 unsigned int has_aliasing_ppgtt_mapping
:1;
860 struct scatterlist
*sg_list
;
864 * Used for performing relocations during execbuffer insertion.
866 struct hlist_node exec_node
;
867 unsigned long exec_handle
;
868 struct drm_i915_gem_exec_object2
*exec_entry
;
871 * Current offset of the object in GTT space.
873 * This is the same as gtt_space->start
877 /** Breadcrumb of last rendering to the buffer. */
878 uint32_t last_rendering_seqno
;
879 struct intel_ring_buffer
*ring
;
881 /** Breadcrumb of last fenced GPU access to the buffer. */
882 uint32_t last_fenced_seqno
;
883 struct intel_ring_buffer
*last_fenced_ring
;
885 /** Current tiling stride for the object, if it's tiled. */
888 /** Record of address bit 17 of each page at last unbind. */
889 unsigned long *bit_17
;
893 * If present, while GEM_DOMAIN_CPU is in the read domain this array
894 * flags which individual pages are valid.
896 uint8_t *page_cpu_valid
;
898 /** User space pin count and filp owning the pin */
899 uint32_t user_pin_count
;
900 struct drm_file
*pin_filp
;
902 /** for phy allocated objects */
903 struct drm_i915_gem_phys_object
*phys_obj
;
906 * Number of crtcs where this object is currently the fb, but
907 * will be page flipped away on the next vblank. When it
908 * reaches 0, dev_priv->pending_flip_queue will be woken up.
910 atomic_t pending_flip
;
913 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
916 * Request queue structure.
918 * The request queue allows us to note sequence numbers that have been emitted
919 * and may be associated with active buffers to be retired.
921 * By keeping this list, we can avoid having to do questionable
922 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
923 * an emission time with seqnos for tracking how far ahead of the GPU we are.
925 struct drm_i915_gem_request
{
926 /** On Which ring this request was generated */
927 struct intel_ring_buffer
*ring
;
929 /** GEM sequence number associated with this request. */
932 /** Time at which this request was emitted, in jiffies. */
933 unsigned long emitted_jiffies
;
935 /** global list entry for this request */
936 struct list_head list
;
938 struct drm_i915_file_private
*file_priv
;
939 /** file_priv list entry for this request */
940 struct list_head client_list
;
943 struct drm_i915_file_private
{
945 struct spinlock lock
;
946 struct list_head request_list
;
950 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
952 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
953 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
954 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
955 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
956 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
957 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
958 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
959 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
960 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
961 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
962 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
963 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
964 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
965 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
966 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
967 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
968 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
969 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
970 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
971 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
974 * The genX designation typically refers to the render engine, so render
975 * capability related checks should use IS_GEN, while display and other checks
976 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
979 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
980 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
981 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
982 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
983 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
984 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
986 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
987 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
988 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
989 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
991 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6)
993 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
994 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
996 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
997 * rows, which changed the alignment requirements and fence programming.
999 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1001 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1002 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1003 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1004 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1005 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1006 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1007 /* dsparb controlled by hw only */
1008 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1010 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1011 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1012 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1014 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
1015 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1017 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1018 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1019 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1021 #include "i915_trace.h"
1023 extern struct drm_ioctl_desc i915_ioctls
[];
1024 extern int i915_max_ioctl
;
1025 extern unsigned int i915_fbpercrtc __always_unused
;
1026 extern int i915_panel_ignore_lid __read_mostly
;
1027 extern unsigned int i915_powersave __read_mostly
;
1028 extern int i915_semaphores __read_mostly
;
1029 extern unsigned int i915_lvds_downclock __read_mostly
;
1030 extern int i915_panel_use_ssc __read_mostly
;
1031 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1032 extern int i915_enable_rc6 __read_mostly
;
1033 extern int i915_enable_fbc __read_mostly
;
1034 extern bool i915_enable_hangcheck __read_mostly
;
1036 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1037 extern int i915_resume(struct drm_device
*dev
);
1038 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1039 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1042 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1043 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1044 extern int i915_driver_unload(struct drm_device
*);
1045 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1046 extern void i915_driver_lastclose(struct drm_device
* dev
);
1047 extern void i915_driver_preclose(struct drm_device
*dev
,
1048 struct drm_file
*file_priv
);
1049 extern void i915_driver_postclose(struct drm_device
*dev
,
1050 struct drm_file
*file_priv
);
1051 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1052 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1054 extern int i915_emit_box(struct drm_device
*dev
,
1055 struct drm_clip_rect
*box
,
1057 extern int i915_reset(struct drm_device
*dev
, u8 flags
);
1058 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1059 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1060 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1061 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1065 void i915_hangcheck_elapsed(unsigned long data
);
1066 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1067 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
1068 struct drm_file
*file_priv
);
1069 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
1070 struct drm_file
*file_priv
);
1072 extern void intel_irq_init(struct drm_device
*dev
);
1074 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
1075 struct drm_file
*file_priv
);
1076 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
1077 struct drm_file
*file_priv
);
1078 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
1079 struct drm_file
*file_priv
);
1082 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1085 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1087 void intel_enable_asle(struct drm_device
*dev
);
1089 #ifdef CONFIG_DEBUG_FS
1090 extern void i915_destroy_error_state(struct drm_device
*dev
);
1092 #define i915_destroy_error_state(x)
1097 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1098 struct drm_file
*file_priv
);
1099 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1100 struct drm_file
*file_priv
);
1101 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1102 struct drm_file
*file_priv
);
1103 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1104 struct drm_file
*file_priv
);
1105 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1106 struct drm_file
*file_priv
);
1107 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1108 struct drm_file
*file_priv
);
1109 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1110 struct drm_file
*file_priv
);
1111 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1112 struct drm_file
*file_priv
);
1113 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1114 struct drm_file
*file_priv
);
1115 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1116 struct drm_file
*file_priv
);
1117 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1118 struct drm_file
*file_priv
);
1119 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1120 struct drm_file
*file_priv
);
1121 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1122 struct drm_file
*file_priv
);
1123 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1124 struct drm_file
*file_priv
);
1125 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1126 struct drm_file
*file_priv
);
1127 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1128 struct drm_file
*file_priv
);
1129 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1130 struct drm_file
*file_priv
);
1131 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1132 struct drm_file
*file_priv
);
1133 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1134 struct drm_file
*file_priv
);
1135 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1136 struct drm_file
*file_priv
);
1137 void i915_gem_load(struct drm_device
*dev
);
1138 int i915_gem_init_object(struct drm_gem_object
*obj
);
1139 int __must_check
i915_gem_flush_ring(struct intel_ring_buffer
*ring
,
1140 uint32_t invalidate_domains
,
1141 uint32_t flush_domains
);
1142 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1144 void i915_gem_free_object(struct drm_gem_object
*obj
);
1145 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1147 bool map_and_fenceable
);
1148 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1149 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1150 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1151 void i915_gem_lastclose(struct drm_device
*dev
);
1153 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1154 int __must_check
i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
);
1155 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1156 struct intel_ring_buffer
*ring
,
1159 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1160 struct drm_device
*dev
,
1161 struct drm_mode_create_dumb
*args
);
1162 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1163 uint32_t handle
, uint64_t *offset
);
1164 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1167 * Returns true if seq1 is later than seq2.
1170 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1172 return (int32_t)(seq1
- seq2
) >= 0;
1176 i915_gem_next_request_seqno(struct intel_ring_buffer
*ring
)
1178 drm_i915_private_t
*dev_priv
= ring
->dev
->dev_private
;
1179 return ring
->outstanding_lazy_request
= dev_priv
->next_seqno
;
1182 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
,
1183 struct intel_ring_buffer
*pipelined
);
1184 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1187 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1189 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1190 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1191 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1196 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1198 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1199 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1200 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1204 void i915_gem_retire_requests(struct drm_device
*dev
);
1205 void i915_gem_reset(struct drm_device
*dev
);
1206 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1207 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1208 uint32_t read_domains
,
1209 uint32_t write_domain
);
1210 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1211 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1212 void i915_gem_init_swizzling(struct drm_device
*dev
);
1213 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1214 void i915_gem_do_init(struct drm_device
*dev
,
1215 unsigned long start
,
1216 unsigned long mappable_end
,
1218 int __must_check
i915_gpu_idle(struct drm_device
*dev
, bool do_retire
);
1219 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1220 int __must_check
i915_add_request(struct intel_ring_buffer
*ring
,
1221 struct drm_file
*file
,
1222 struct drm_i915_gem_request
*request
);
1223 int __must_check
i915_wait_request(struct intel_ring_buffer
*ring
,
1226 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1228 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1231 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1233 struct intel_ring_buffer
*pipelined
);
1234 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1235 struct drm_i915_gem_object
*obj
,
1238 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1239 struct drm_i915_gem_object
*obj
);
1240 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1241 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1244 i915_gem_get_unfenced_gtt_alignment(struct drm_device
*dev
,
1248 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1249 enum i915_cache_level cache_level
);
1251 /* i915_gem_gtt.c */
1252 int __must_check
i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
);
1253 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1254 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1255 struct drm_i915_gem_object
*obj
,
1256 enum i915_cache_level cache_level
);
1257 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1258 struct drm_i915_gem_object
*obj
);
1260 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1261 int __must_check
i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
);
1262 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object
*obj
,
1263 enum i915_cache_level cache_level
);
1264 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1266 /* i915_gem_evict.c */
1267 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1268 unsigned alignment
, bool mappable
);
1269 int __must_check
i915_gem_evict_everything(struct drm_device
*dev
,
1270 bool purgeable_only
);
1271 int __must_check
i915_gem_evict_inactive(struct drm_device
*dev
,
1272 bool purgeable_only
);
1274 /* i915_gem_tiling.c */
1275 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1276 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1277 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1279 /* i915_gem_debug.c */
1280 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1281 const char *where
, uint32_t mark
);
1283 int i915_verify_lists(struct drm_device
*dev
);
1285 #define i915_verify_lists(dev) 0
1287 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1289 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1290 const char *where
, uint32_t mark
);
1292 /* i915_debugfs.c */
1293 int i915_debugfs_init(struct drm_minor
*minor
);
1294 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1296 /* i915_suspend.c */
1297 extern int i915_save_state(struct drm_device
*dev
);
1298 extern int i915_restore_state(struct drm_device
*dev
);
1300 /* i915_suspend.c */
1301 extern int i915_save_state(struct drm_device
*dev
);
1302 extern int i915_restore_state(struct drm_device
*dev
);
1305 extern int intel_setup_gmbus(struct drm_device
*dev
);
1306 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1307 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1308 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1309 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1311 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1313 extern void intel_i2c_reset(struct drm_device
*dev
);
1315 /* intel_opregion.c */
1316 extern int intel_opregion_setup(struct drm_device
*dev
);
1318 extern void intel_opregion_init(struct drm_device
*dev
);
1319 extern void intel_opregion_fini(struct drm_device
*dev
);
1320 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1321 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1322 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1324 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1325 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1326 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1327 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1328 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1333 extern void intel_register_dsm_handler(void);
1334 extern void intel_unregister_dsm_handler(void);
1336 static inline void intel_register_dsm_handler(void) { return; }
1337 static inline void intel_unregister_dsm_handler(void) { return; }
1338 #endif /* CONFIG_ACPI */
1341 extern void intel_modeset_init(struct drm_device
*dev
);
1342 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1343 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1344 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1345 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1346 extern void intel_disable_fbc(struct drm_device
*dev
);
1347 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1348 extern void ironlake_init_pch_refclk(struct drm_device
*dev
);
1349 extern void ironlake_enable_rc6(struct drm_device
*dev
);
1350 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1351 extern void intel_detect_pch(struct drm_device
*dev
);
1352 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1354 extern void __gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1355 extern void __gen6_gt_force_wake_mt_get(struct drm_i915_private
*dev_priv
);
1356 extern void __gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1357 extern void __gen6_gt_force_wake_mt_put(struct drm_i915_private
*dev_priv
);
1360 #ifdef CONFIG_DEBUG_FS
1361 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1362 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1364 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1365 extern void intel_display_print_error_state(struct seq_file
*m
,
1366 struct drm_device
*dev
,
1367 struct intel_display_error_state
*error
);
1370 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1372 #define BEGIN_LP_RING(n) \
1373 intel_ring_begin(LP_RING(dev_priv), (n))
1375 #define OUT_RING(x) \
1376 intel_ring_emit(LP_RING(dev_priv), x)
1378 #define ADVANCE_LP_RING() \
1379 intel_ring_advance(LP_RING(dev_priv))
1382 * Lock test for when it's just for synchronization of ring access.
1384 * In that case, we don't need to do it when GEM is initialized as nobody else
1385 * has access to the ring.
1387 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1388 if (LP_RING(dev->dev_private)->obj == NULL) \
1389 LOCK_TEST_WITH_RETURN(dev, file); \
1392 /* On SNB platform, before reading ring registers forcewake bit
1393 * must be set to prevent GT core from power down and stale values being
1396 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1397 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1398 void __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1400 /* We give fast paths for the really cool registers */
1401 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1402 (((dev_priv)->info->gen >= 6) && \
1403 ((reg) < 0x40000) && \
1404 ((reg) != FORCEWAKE))
1406 #define __i915_read(x, y) \
1407 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1415 #define __i915_write(x, y) \
1416 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1424 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1425 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1427 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1428 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1429 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1430 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1432 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1433 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1434 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1435 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1437 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1438 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1440 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1441 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)