1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20150117"
61 /* Many gcc seem to no see through this and fall over :( */
63 #define WARN_ON(x) ({ \
64 bool __i915_warn_cond = (x); \
65 if (__builtin_constant_p(__i915_warn_cond)) \
66 BUILD_BUG_ON(__i915_warn_cond); \
67 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
69 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
72 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
73 (long) (x), __func__);
75 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
76 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
77 * which may not necessarily be a user visible problem. This will either
78 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
79 * enable distros and users to tailor their preferred amount of i915 abrt
82 #define I915_STATE_WARN(condition, format...) ({ \
83 int __ret_warn_on = !!(condition); \
84 if (unlikely(__ret_warn_on)) { \
85 if (i915.verbose_state_checks) \
90 unlikely(__ret_warn_on); \
93 #define I915_STATE_WARN_ON(condition) ({ \
94 int __ret_warn_on = !!(condition); \
95 if (unlikely(__ret_warn_on)) { \
96 if (i915.verbose_state_checks) \
97 WARN(1, "WARN_ON(" #condition ")\n"); \
99 DRM_ERROR("WARN_ON(" #condition ")\n"); \
101 unlikely(__ret_warn_on); \
110 I915_MAX_PIPES
= _PIPE_EDP
112 #define pipe_name(p) ((p) + 'A')
121 #define transcoder_name(t) ((t) + 'A')
124 * This is the maximum (across all platforms) number of planes (primary +
125 * sprites) that can be active at the same time on one pipe.
127 * This value doesn't count the cursor plane.
129 #define I915_MAX_PLANES 3
136 #define plane_name(p) ((p) + 'A')
138 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
148 #define port_name(p) ((p) + 'A')
150 #define I915_NUM_PHYS_VLV 2
162 enum intel_display_power_domain
{
166 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
167 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
168 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
169 POWER_DOMAIN_TRANSCODER_A
,
170 POWER_DOMAIN_TRANSCODER_B
,
171 POWER_DOMAIN_TRANSCODER_C
,
172 POWER_DOMAIN_TRANSCODER_EDP
,
173 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
174 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
175 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
176 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
177 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
178 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
179 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
180 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
181 POWER_DOMAIN_PORT_DSI
,
182 POWER_DOMAIN_PORT_CRT
,
183 POWER_DOMAIN_PORT_OTHER
,
196 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
197 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
198 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
199 #define POWER_DOMAIN_TRANSCODER(tran) \
200 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
201 (tran) + POWER_DOMAIN_TRANSCODER_A)
205 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
206 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
216 #define I915_GEM_GPU_DOMAINS \
217 (I915_GEM_DOMAIN_RENDER | \
218 I915_GEM_DOMAIN_SAMPLER | \
219 I915_GEM_DOMAIN_COMMAND | \
220 I915_GEM_DOMAIN_INSTRUCTION | \
221 I915_GEM_DOMAIN_VERTEX)
223 #define for_each_pipe(__dev_priv, __p) \
224 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
225 #define for_each_plane(pipe, p) \
226 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
227 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
229 #define for_each_crtc(dev, crtc) \
230 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
232 #define for_each_intel_crtc(dev, intel_crtc) \
233 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
235 #define for_each_intel_encoder(dev, intel_encoder) \
236 list_for_each_entry(intel_encoder, \
237 &(dev)->mode_config.encoder_list, \
240 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
241 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
242 if ((intel_encoder)->base.crtc == (__crtc))
244 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
245 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
246 if ((intel_connector)->base.encoder == (__encoder))
248 #define for_each_power_domain(domain, mask) \
249 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
250 if ((1 << (domain)) & (mask))
252 struct drm_i915_private
;
253 struct i915_mm_struct
;
254 struct i915_mmu_object
;
257 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
258 /* real shared dpll ids must be >= 0 */
259 DPLL_ID_PCH_PLL_A
= 0,
260 DPLL_ID_PCH_PLL_B
= 1,
265 DPLL_ID_SKL_DPLL1
= 0,
266 DPLL_ID_SKL_DPLL2
= 1,
267 DPLL_ID_SKL_DPLL3
= 2,
269 #define I915_NUM_PLLS 3
271 struct intel_dpll_hw_state
{
283 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
284 * lower part of crtl1 and they get shifted into position when writing
285 * the register. This allows us to easily compare the state to share
289 /* HDMI only, 0 when used for DP */
290 uint32_t cfgcr1
, cfgcr2
;
293 struct intel_shared_dpll_config
{
294 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
295 struct intel_dpll_hw_state hw_state
;
298 struct intel_shared_dpll
{
299 struct intel_shared_dpll_config config
;
300 struct intel_shared_dpll_config
*new_config
;
302 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
303 bool on
; /* is the PLL actually active? Disabled during modeset */
305 /* should match the index in the dev_priv->shared_dplls array */
306 enum intel_dpll_id id
;
307 /* The mode_set hook is optional and should be used together with the
308 * intel_prepare_shared_dpll function. */
309 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
310 struct intel_shared_dpll
*pll
);
311 void (*enable
)(struct drm_i915_private
*dev_priv
,
312 struct intel_shared_dpll
*pll
);
313 void (*disable
)(struct drm_i915_private
*dev_priv
,
314 struct intel_shared_dpll
*pll
);
315 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
316 struct intel_shared_dpll
*pll
,
317 struct intel_dpll_hw_state
*hw_state
);
325 /* Used by dp and fdi links */
326 struct intel_link_m_n
{
334 void intel_link_compute_m_n(int bpp
, int nlanes
,
335 int pixel_clock
, int link_clock
,
336 struct intel_link_m_n
*m_n
);
338 /* Interface history:
341 * 1.2: Add Power Management
342 * 1.3: Add vblank support
343 * 1.4: Fix cmdbuffer path, add heap destroy
344 * 1.5: Add vblank pipe configuration
345 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
346 * - Support vertical blank on secondary display pipe
348 #define DRIVER_MAJOR 1
349 #define DRIVER_MINOR 6
350 #define DRIVER_PATCHLEVEL 0
352 #define WATCH_LISTS 0
354 struct opregion_header
;
355 struct opregion_acpi
;
356 struct opregion_swsci
;
357 struct opregion_asle
;
359 struct intel_opregion
{
360 struct opregion_header __iomem
*header
;
361 struct opregion_acpi __iomem
*acpi
;
362 struct opregion_swsci __iomem
*swsci
;
363 u32 swsci_gbda_sub_functions
;
364 u32 swsci_sbcb_sub_functions
;
365 struct opregion_asle __iomem
*asle
;
367 u32 __iomem
*lid_state
;
368 struct work_struct asle_work
;
370 #define OPREGION_SIZE (8*1024)
372 struct intel_overlay
;
373 struct intel_overlay_error_state
;
375 #define I915_FENCE_REG_NONE -1
376 #define I915_MAX_NUM_FENCES 32
377 /* 32 fences + sign bit for FENCE_REG_NONE */
378 #define I915_MAX_NUM_FENCE_BITS 6
380 struct drm_i915_fence_reg
{
381 struct list_head lru_list
;
382 struct drm_i915_gem_object
*obj
;
386 struct sdvo_device_mapping
{
395 struct intel_display_error_state
;
397 struct drm_i915_error_state
{
405 /* Generic register state */
413 u32 error
; /* gen6+ */
414 u32 err_int
; /* gen7 */
420 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
421 u64 fence
[I915_MAX_NUM_FENCES
];
422 struct intel_overlay_error_state
*overlay
;
423 struct intel_display_error_state
*display
;
424 struct drm_i915_error_object
*semaphore_obj
;
426 struct drm_i915_error_ring
{
428 /* Software tracked state */
431 enum intel_ring_hangcheck_action hangcheck_action
;
434 /* our own tracking of ring head and tail */
438 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
456 u32 rc_psmi
; /* sleep state */
457 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
459 struct drm_i915_error_object
{
463 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
465 struct drm_i915_error_request
{
480 char comm
[TASK_COMM_LEN
];
481 } ring
[I915_NUM_RINGS
];
483 struct drm_i915_error_buffer
{
490 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
498 } **active_bo
, **pinned_bo
;
500 u32
*active_bo_count
, *pinned_bo_count
;
504 struct intel_connector
;
505 struct intel_encoder
;
506 struct intel_crtc_state
;
507 struct intel_initial_plane_config
;
512 struct drm_i915_display_funcs
{
513 bool (*fbc_enabled
)(struct drm_device
*dev
);
514 void (*enable_fbc
)(struct drm_crtc
*crtc
);
515 void (*disable_fbc
)(struct drm_device
*dev
);
516 int (*get_display_clock_speed
)(struct drm_device
*dev
);
517 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
519 * find_dpll() - Find the best values for the PLL
520 * @limit: limits for the PLL
521 * @crtc: current CRTC
522 * @target: target frequency in kHz
523 * @refclk: reference clock frequency in kHz
524 * @match_clock: if provided, @best_clock P divider must
525 * match the P divider from @match_clock
526 * used for LVDS downclocking
527 * @best_clock: best PLL values found
529 * Returns true on success, false on failure.
531 bool (*find_dpll
)(const struct intel_limit
*limit
,
532 struct intel_crtc
*crtc
,
533 int target
, int refclk
,
534 struct dpll
*match_clock
,
535 struct dpll
*best_clock
);
536 void (*update_wm
)(struct drm_crtc
*crtc
);
537 void (*update_sprite_wm
)(struct drm_plane
*plane
,
538 struct drm_crtc
*crtc
,
539 uint32_t sprite_width
, uint32_t sprite_height
,
540 int pixel_size
, bool enable
, bool scaled
);
541 void (*modeset_global_resources
)(struct drm_device
*dev
);
542 /* Returns the active state of the crtc, and if the crtc is active,
543 * fills out the pipe-config with the hw state. */
544 bool (*get_pipe_config
)(struct intel_crtc
*,
545 struct intel_crtc_state
*);
546 void (*get_initial_plane_config
)(struct intel_crtc
*,
547 struct intel_initial_plane_config
*);
548 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
549 struct intel_crtc_state
*crtc_state
);
550 void (*crtc_enable
)(struct drm_crtc
*crtc
);
551 void (*crtc_disable
)(struct drm_crtc
*crtc
);
552 void (*off
)(struct drm_crtc
*crtc
);
553 void (*audio_codec_enable
)(struct drm_connector
*connector
,
554 struct intel_encoder
*encoder
,
555 struct drm_display_mode
*mode
);
556 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
557 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
558 void (*init_clock_gating
)(struct drm_device
*dev
);
559 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
560 struct drm_framebuffer
*fb
,
561 struct drm_i915_gem_object
*obj
,
562 struct intel_engine_cs
*ring
,
564 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
565 struct drm_framebuffer
*fb
,
567 void (*hpd_irq_setup
)(struct drm_device
*dev
);
568 /* clock updates for mode set */
570 /* render clock increase/decrease */
571 /* display clock increase/decrease */
572 /* pll clock increase/decrease */
574 int (*setup_backlight
)(struct intel_connector
*connector
, enum pipe pipe
);
575 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
576 void (*set_backlight
)(struct intel_connector
*connector
,
578 void (*disable_backlight
)(struct intel_connector
*connector
);
579 void (*enable_backlight
)(struct intel_connector
*connector
);
582 enum forcewake_domain_id
{
583 FW_DOMAIN_ID_RENDER
= 0,
584 FW_DOMAIN_ID_BLITTER
,
590 enum forcewake_domains
{
591 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
592 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
593 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
594 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
599 struct intel_uncore_funcs
{
600 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
601 enum forcewake_domains domains
);
602 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
603 enum forcewake_domains domains
);
605 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
606 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
607 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
608 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
610 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
611 uint8_t val
, bool trace
);
612 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
613 uint16_t val
, bool trace
);
614 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
615 uint32_t val
, bool trace
);
616 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
617 uint64_t val
, bool trace
);
620 struct intel_uncore
{
621 spinlock_t lock
; /** lock is also taken in irq contexts. */
623 struct intel_uncore_funcs funcs
;
626 enum forcewake_domains fw_domains
;
628 struct intel_uncore_forcewake_domain
{
629 struct drm_i915_private
*i915
;
630 enum forcewake_domain_id id
;
632 struct timer_list timer
;
639 } fw_domain
[FW_DOMAIN_ID_COUNT
];
642 /* Iterate over initialised fw domains */
643 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
644 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
645 (i__) < FW_DOMAIN_ID_COUNT; \
646 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
647 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
649 #define for_each_fw_domain(domain__, dev_priv__, i__) \
650 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
652 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
653 func(is_mobile) sep \
656 func(is_i945gm) sep \
658 func(need_gfx_hws) sep \
660 func(is_pineview) sep \
661 func(is_broadwater) sep \
662 func(is_crestline) sep \
663 func(is_ivybridge) sep \
664 func(is_valleyview) sep \
665 func(is_haswell) sep \
666 func(is_skylake) sep \
667 func(is_preliminary) sep \
669 func(has_pipe_cxsr) sep \
670 func(has_hotplug) sep \
671 func(cursor_needs_physical) sep \
672 func(has_overlay) sep \
673 func(overlay_needs_physical) sep \
674 func(supports_tv) sep \
679 #define DEFINE_FLAG(name) u8 name:1
680 #define SEP_SEMICOLON ;
682 struct intel_device_info
{
683 u32 display_mmio_offset
;
686 u8 num_sprites
[I915_MAX_PIPES
];
688 u8 ring_mask
; /* Rings supported by the HW */
689 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
690 /* Register offsets for the various display pipes and transcoders */
691 int pipe_offsets
[I915_MAX_TRANSCODERS
];
692 int trans_offsets
[I915_MAX_TRANSCODERS
];
693 int palette_offsets
[I915_MAX_PIPES
];
694 int cursor_offsets
[I915_MAX_PIPES
];
695 unsigned int eu_total
;
701 enum i915_cache_level
{
703 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
704 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
705 caches, eg sampler/render caches, and the
706 large Last-Level-Cache. LLC is coherent with
707 the CPU, but L3 is only visible to the GPU. */
708 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
711 struct i915_ctx_hang_stats
{
712 /* This context had batch pending when hang was declared */
713 unsigned batch_pending
;
715 /* This context had batch active when hang was declared */
716 unsigned batch_active
;
718 /* Time when this context was last blamed for a GPU reset */
719 unsigned long guilty_ts
;
721 /* If the contexts causes a second GPU hang within this time,
722 * it is permanently banned from submitting any more work.
724 unsigned long ban_period_seconds
;
726 /* This context is banned to submit more work */
730 /* This must match up with the value previously used for execbuf2.rsvd1. */
731 #define DEFAULT_CONTEXT_HANDLE 0
733 * struct intel_context - as the name implies, represents a context.
734 * @ref: reference count.
735 * @user_handle: userspace tracking identity for this context.
736 * @remap_slice: l3 row remapping information.
737 * @file_priv: filp associated with this context (NULL for global default
739 * @hang_stats: information about the role of this context in possible GPU
741 * @vm: virtual memory space used by this context.
742 * @legacy_hw_ctx: render context backing object and whether it is correctly
743 * initialized (legacy ring submission mechanism only).
744 * @link: link in the global list of contexts.
746 * Contexts are memory images used by the hardware to store copies of their
749 struct intel_context
{
753 struct drm_i915_file_private
*file_priv
;
754 struct i915_ctx_hang_stats hang_stats
;
755 struct i915_hw_ppgtt
*ppgtt
;
757 /* Legacy ring buffer submission */
759 struct drm_i915_gem_object
*rcs_state
;
764 bool rcs_initialized
;
766 struct drm_i915_gem_object
*state
;
767 struct intel_ringbuffer
*ringbuf
;
769 } engine
[I915_NUM_RINGS
];
771 struct list_head link
;
781 struct drm_mm_node compressed_fb
;
782 struct drm_mm_node
*compressed_llb
;
786 /* Tracks whether the HW is actually enabled, not whether the feature is
790 /* On gen8 some rings cannont perform fbc clean operation so for now
791 * we are doing this on SW with mmio.
792 * This variable works in the opposite information direction
793 * of ring->fbc_dirty telling software on frontbuffer tracking
794 * to perform the cache clean on sw side.
796 bool need_sw_cache_clean
;
798 struct intel_fbc_work
{
799 struct delayed_work work
;
800 struct drm_crtc
*crtc
;
801 struct drm_framebuffer
*fb
;
805 FBC_OK
, /* FBC is enabled */
806 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
807 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
808 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
809 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
810 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
811 FBC_BAD_PLANE
, /* fbc not supported on plane */
812 FBC_NOT_TILED
, /* buffer not tiled */
813 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
815 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
820 * HIGH_RR is the highest eDP panel refresh rate read from EDID
821 * LOW_RR is the lowest eDP panel refresh rate found from EDID
822 * parsing for same resolution.
824 enum drrs_refresh_rate_type
{
827 DRRS_MAX_RR
, /* RR count */
830 enum drrs_support_type
{
831 DRRS_NOT_SUPPORTED
= 0,
832 STATIC_DRRS_SUPPORT
= 1,
833 SEAMLESS_DRRS_SUPPORT
= 2
839 struct delayed_work work
;
841 unsigned busy_frontbuffer_bits
;
842 enum drrs_refresh_rate_type refresh_rate_type
;
843 enum drrs_support_type type
;
850 struct intel_dp
*enabled
;
852 struct delayed_work work
;
853 unsigned busy_frontbuffer_bits
;
858 PCH_NONE
= 0, /* No PCH present */
859 PCH_IBX
, /* Ibexpeak PCH */
860 PCH_CPT
, /* Cougarpoint PCH */
861 PCH_LPT
, /* Lynxpoint PCH */
862 PCH_SPT
, /* Sunrisepoint PCH */
866 enum intel_sbi_destination
{
871 #define QUIRK_PIPEA_FORCE (1<<0)
872 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
873 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
874 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
875 #define QUIRK_PIPEB_FORCE (1<<4)
876 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
879 struct intel_fbc_work
;
882 struct i2c_adapter adapter
;
886 struct i2c_algo_bit_data bit_algo
;
887 struct drm_i915_private
*dev_priv
;
890 struct i915_suspend_saved_registers
{
911 u32 saveTRANS_HTOTAL_A
;
912 u32 saveTRANS_HBLANK_A
;
913 u32 saveTRANS_HSYNC_A
;
914 u32 saveTRANS_VTOTAL_A
;
915 u32 saveTRANS_VBLANK_A
;
916 u32 saveTRANS_VSYNC_A
;
924 u32 savePFIT_PGM_RATIOS
;
925 u32 saveBLC_HIST_CTL
;
927 u32 saveBLC_PWM_CTL2
;
928 u32 saveBLC_CPU_PWM_CTL
;
929 u32 saveBLC_CPU_PWM_CTL2
;
942 u32 saveTRANS_HTOTAL_B
;
943 u32 saveTRANS_HBLANK_B
;
944 u32 saveTRANS_HSYNC_B
;
945 u32 saveTRANS_VTOTAL_B
;
946 u32 saveTRANS_VBLANK_B
;
947 u32 saveTRANS_VSYNC_B
;
961 u32 savePP_ON_DELAYS
;
962 u32 savePP_OFF_DELAYS
;
970 u32 savePFIT_CONTROL
;
971 u32 save_palette_a
[256];
972 u32 save_palette_b
[256];
983 u32 saveCACHE_MODE_0
;
984 u32 saveMI_ARB_STATE
;
995 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1006 u32 savePIPEA_GMCH_DATA_M
;
1007 u32 savePIPEB_GMCH_DATA_M
;
1008 u32 savePIPEA_GMCH_DATA_N
;
1009 u32 savePIPEB_GMCH_DATA_N
;
1010 u32 savePIPEA_DP_LINK_M
;
1011 u32 savePIPEB_DP_LINK_M
;
1012 u32 savePIPEA_DP_LINK_N
;
1013 u32 savePIPEB_DP_LINK_N
;
1014 u32 saveFDI_RXA_CTL
;
1015 u32 saveFDI_TXA_CTL
;
1016 u32 saveFDI_RXB_CTL
;
1017 u32 saveFDI_TXB_CTL
;
1022 u32 savePFA_WIN_POS
;
1023 u32 savePFB_WIN_POS
;
1024 u32 savePCH_DREF_CONTROL
;
1025 u32 saveDISP_ARB_CTL
;
1026 u32 savePIPEA_DATA_M1
;
1027 u32 savePIPEA_DATA_N1
;
1028 u32 savePIPEA_LINK_M1
;
1029 u32 savePIPEA_LINK_N1
;
1030 u32 savePIPEB_DATA_M1
;
1031 u32 savePIPEB_DATA_N1
;
1032 u32 savePIPEB_LINK_M1
;
1033 u32 savePIPEB_LINK_N1
;
1034 u32 saveMCHBAR_RENDER_STANDBY
;
1035 u32 savePCH_PORT_HOTPLUG
;
1039 struct vlv_s0ix_state
{
1046 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1047 u32 media_max_req_count
;
1048 u32 gfx_max_req_count
;
1074 u32 rp_down_timeout
;
1080 /* Display 1 CZ domain */
1085 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1087 /* GT SA CZ domain */
1094 /* Display 2 CZ domain */
1097 u32 clock_gate_dis2
;
1100 struct intel_rps_ei
{
1106 struct intel_gen6_power_mgmt
{
1108 * work, interrupts_enabled and pm_iir are protected by
1109 * dev_priv->irq_lock
1111 struct work_struct work
;
1112 bool interrupts_enabled
;
1115 /* Frequencies are stored in potentially platform dependent multiples.
1116 * In other words, *_freq needs to be multiplied by X to be interesting.
1117 * Soft limits are those which are used for the dynamic reclocking done
1118 * by the driver (raise frequencies under heavy loads, and lower for
1119 * lighter loads). Hard limits are those imposed by the hardware.
1121 * A distinction is made for overclocking, which is never enabled by
1122 * default, and is considered to be above the hard limit if it's
1125 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1126 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1127 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1128 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1129 u8 min_freq
; /* AKA RPn. Minimum frequency */
1130 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1131 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1132 u8 rp0_freq
; /* Non-overclocked max frequency. */
1135 u32 ei_interrupt_count
;
1138 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1141 struct delayed_work delayed_resume_work
;
1143 /* manual wa residency calculations */
1144 struct intel_rps_ei up_ei
, down_ei
;
1147 * Protects RPS/RC6 register access and PCU communication.
1148 * Must be taken after struct_mutex if nested.
1150 struct mutex hw_lock
;
1153 /* defined intel_pm.c */
1154 extern spinlock_t mchdev_lock
;
1156 struct intel_ilk_power_mgmt
{
1164 unsigned long last_time1
;
1165 unsigned long chipset_power
;
1168 unsigned long gfx_power
;
1174 struct drm_i915_gem_object
*pwrctx
;
1175 struct drm_i915_gem_object
*renderctx
;
1178 struct drm_i915_private
;
1179 struct i915_power_well
;
1181 struct i915_power_well_ops
{
1183 * Synchronize the well's hw state to match the current sw state, for
1184 * example enable/disable it based on the current refcount. Called
1185 * during driver init and resume time, possibly after first calling
1186 * the enable/disable handlers.
1188 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1189 struct i915_power_well
*power_well
);
1191 * Enable the well and resources that depend on it (for example
1192 * interrupts located on the well). Called after the 0->1 refcount
1195 void (*enable
)(struct drm_i915_private
*dev_priv
,
1196 struct i915_power_well
*power_well
);
1198 * Disable the well and resources that depend on it. Called after
1199 * the 1->0 refcount transition.
1201 void (*disable
)(struct drm_i915_private
*dev_priv
,
1202 struct i915_power_well
*power_well
);
1203 /* Returns the hw enabled state. */
1204 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1205 struct i915_power_well
*power_well
);
1208 /* Power well structure for haswell */
1209 struct i915_power_well
{
1212 /* power well enable/disable usage count */
1214 /* cached hw enabled state */
1216 unsigned long domains
;
1218 const struct i915_power_well_ops
*ops
;
1221 struct i915_power_domains
{
1223 * Power wells needed for initialization at driver init and suspend
1224 * time are on. They are kept on until after the first modeset.
1228 int power_well_count
;
1231 int domain_use_count
[POWER_DOMAIN_NUM
];
1232 struct i915_power_well
*power_wells
;
1235 #define MAX_L3_SLICES 2
1236 struct intel_l3_parity
{
1237 u32
*remap_info
[MAX_L3_SLICES
];
1238 struct work_struct error_work
;
1242 struct i915_gem_batch_pool
{
1243 struct drm_device
*dev
;
1244 struct list_head cache_list
;
1247 struct i915_gem_mm
{
1248 /** Memory allocator for GTT stolen memory */
1249 struct drm_mm stolen
;
1250 /** List of all objects in gtt_space. Used to restore gtt
1251 * mappings on resume */
1252 struct list_head bound_list
;
1254 * List of objects which are not bound to the GTT (thus
1255 * are idle and not used by the GPU) but still have
1256 * (presumably uncached) pages still attached.
1258 struct list_head unbound_list
;
1261 * A pool of objects to use as shadow copies of client batch buffers
1262 * when the command parser is enabled. Prevents the client from
1263 * modifying the batch contents after software parsing.
1265 struct i915_gem_batch_pool batch_pool
;
1267 /** Usable portion of the GTT for GEM */
1268 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1270 /** PPGTT used for aliasing the PPGTT with the GTT */
1271 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1273 struct notifier_block oom_notifier
;
1274 struct shrinker shrinker
;
1275 bool shrinker_no_lock_stealing
;
1277 /** LRU list of objects with fence regs on them. */
1278 struct list_head fence_list
;
1281 * We leave the user IRQ off as much as possible,
1282 * but this means that requests will finish and never
1283 * be retired once the system goes idle. Set a timer to
1284 * fire periodically while the ring is running. When it
1285 * fires, go retire requests.
1287 struct delayed_work retire_work
;
1290 * When we detect an idle GPU, we want to turn on
1291 * powersaving features. So once we see that there
1292 * are no more requests outstanding and no more
1293 * arrive within a small period of time, we fire
1294 * off the idle_work.
1296 struct delayed_work idle_work
;
1299 * Are we in a non-interruptible section of code like
1305 * Is the GPU currently considered idle, or busy executing userspace
1306 * requests? Whilst idle, we attempt to power down the hardware and
1307 * display clocks. In order to reduce the effect on performance, there
1308 * is a slight delay before we do so.
1312 /* the indicator for dispatch video commands on two BSD rings */
1313 int bsd_ring_dispatch_index
;
1315 /** Bit 6 swizzling required for X tiling */
1316 uint32_t bit_6_swizzle_x
;
1317 /** Bit 6 swizzling required for Y tiling */
1318 uint32_t bit_6_swizzle_y
;
1320 /* accounting, useful for userland debugging */
1321 spinlock_t object_stat_lock
;
1322 size_t object_memory
;
1326 struct drm_i915_error_state_buf
{
1327 struct drm_i915_private
*i915
;
1336 struct i915_error_state_file_priv
{
1337 struct drm_device
*dev
;
1338 struct drm_i915_error_state
*error
;
1341 struct i915_gpu_error
{
1342 /* For hangcheck timer */
1343 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1344 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1345 /* Hang gpu twice in this window and your context gets banned */
1346 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1348 struct timer_list hangcheck_timer
;
1350 /* For reset and error_state handling. */
1352 /* Protected by the above dev->gpu_error.lock. */
1353 struct drm_i915_error_state
*first_error
;
1354 struct work_struct work
;
1357 unsigned long missed_irq_rings
;
1360 * State variable controlling the reset flow and count
1362 * This is a counter which gets incremented when reset is triggered,
1363 * and again when reset has been handled. So odd values (lowest bit set)
1364 * means that reset is in progress and even values that
1365 * (reset_counter >> 1):th reset was successfully completed.
1367 * If reset is not completed succesfully, the I915_WEDGE bit is
1368 * set meaning that hardware is terminally sour and there is no
1369 * recovery. All waiters on the reset_queue will be woken when
1372 * This counter is used by the wait_seqno code to notice that reset
1373 * event happened and it needs to restart the entire ioctl (since most
1374 * likely the seqno it waited for won't ever signal anytime soon).
1376 * This is important for lock-free wait paths, where no contended lock
1377 * naturally enforces the correct ordering between the bail-out of the
1378 * waiter and the gpu reset work code.
1380 atomic_t reset_counter
;
1382 #define I915_RESET_IN_PROGRESS_FLAG 1
1383 #define I915_WEDGED (1 << 31)
1386 * Waitqueue to signal when the reset has completed. Used by clients
1387 * that wait for dev_priv->mm.wedged to settle.
1389 wait_queue_head_t reset_queue
;
1391 /* Userspace knobs for gpu hang simulation;
1392 * combines both a ring mask, and extra flags
1395 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1396 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1398 /* For missed irq/seqno simulation. */
1399 unsigned int test_irq_rings
;
1401 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1402 bool reload_in_reset
;
1405 enum modeset_restore
{
1406 MODESET_ON_LID_OPEN
,
1411 struct ddi_vbt_port_info
{
1413 * This is an index in the HDMI/DVI DDI buffer translation table.
1414 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1415 * populate this field.
1417 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1418 uint8_t hdmi_level_shift
;
1420 uint8_t supports_dvi
:1;
1421 uint8_t supports_hdmi
:1;
1422 uint8_t supports_dp
:1;
1425 enum psr_lines_to_wait
{
1426 PSR_0_LINES_TO_WAIT
= 0,
1428 PSR_4_LINES_TO_WAIT
,
1432 struct intel_vbt_data
{
1433 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1434 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1437 unsigned int int_tv_support
:1;
1438 unsigned int lvds_dither
:1;
1439 unsigned int lvds_vbt
:1;
1440 unsigned int int_crt_support
:1;
1441 unsigned int lvds_use_ssc
:1;
1442 unsigned int display_clock_mode
:1;
1443 unsigned int fdi_rx_polarity_inverted
:1;
1444 unsigned int has_mipi
:1;
1446 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1448 enum drrs_support_type drrs_type
;
1453 int edp_preemphasis
;
1455 bool edp_initialized
;
1458 struct edp_power_seq edp_pps
;
1462 bool require_aux_wakeup
;
1464 enum psr_lines_to_wait lines_to_wait
;
1465 int tp1_wakeup_time
;
1466 int tp2_tp3_wakeup_time
;
1472 bool active_low_pwm
;
1473 u8 min_brightness
; /* min_brightness/255 of max */
1480 struct mipi_config
*config
;
1481 struct mipi_pps_data
*pps
;
1485 u8
*sequence
[MIPI_SEQ_MAX
];
1491 union child_device_config
*child_dev
;
1493 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1496 enum intel_ddb_partitioning
{
1498 INTEL_DDB_PART_5_6
, /* IVB+ */
1501 struct intel_wm_level
{
1509 struct ilk_wm_values
{
1510 uint32_t wm_pipe
[3];
1512 uint32_t wm_lp_spr
[3];
1513 uint32_t wm_linetime
[3];
1515 enum intel_ddb_partitioning partitioning
;
1518 struct skl_ddb_entry
{
1519 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1522 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1524 return entry
->end
- entry
->start
;
1527 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1528 const struct skl_ddb_entry
*e2
)
1530 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1536 struct skl_ddb_allocation
{
1537 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1538 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1539 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1542 struct skl_wm_values
{
1543 bool dirty
[I915_MAX_PIPES
];
1544 struct skl_ddb_allocation ddb
;
1545 uint32_t wm_linetime
[I915_MAX_PIPES
];
1546 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1547 uint32_t cursor
[I915_MAX_PIPES
][8];
1548 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1549 uint32_t cursor_trans
[I915_MAX_PIPES
];
1552 struct skl_wm_level
{
1553 bool plane_en
[I915_MAX_PLANES
];
1555 uint16_t plane_res_b
[I915_MAX_PLANES
];
1556 uint8_t plane_res_l
[I915_MAX_PLANES
];
1557 uint16_t cursor_res_b
;
1558 uint8_t cursor_res_l
;
1562 * This struct helps tracking the state needed for runtime PM, which puts the
1563 * device in PCI D3 state. Notice that when this happens, nothing on the
1564 * graphics device works, even register access, so we don't get interrupts nor
1567 * Every piece of our code that needs to actually touch the hardware needs to
1568 * either call intel_runtime_pm_get or call intel_display_power_get with the
1569 * appropriate power domain.
1571 * Our driver uses the autosuspend delay feature, which means we'll only really
1572 * suspend if we stay with zero refcount for a certain amount of time. The
1573 * default value is currently very conservative (see intel_runtime_pm_enable), but
1574 * it can be changed with the standard runtime PM files from sysfs.
1576 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1577 * goes back to false exactly before we reenable the IRQs. We use this variable
1578 * to check if someone is trying to enable/disable IRQs while they're supposed
1579 * to be disabled. This shouldn't happen and we'll print some error messages in
1582 * For more, read the Documentation/power/runtime_pm.txt.
1584 struct i915_runtime_pm
{
1589 enum intel_pipe_crc_source
{
1590 INTEL_PIPE_CRC_SOURCE_NONE
,
1591 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1592 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1593 INTEL_PIPE_CRC_SOURCE_PF
,
1594 INTEL_PIPE_CRC_SOURCE_PIPE
,
1595 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1596 INTEL_PIPE_CRC_SOURCE_TV
,
1597 INTEL_PIPE_CRC_SOURCE_DP_B
,
1598 INTEL_PIPE_CRC_SOURCE_DP_C
,
1599 INTEL_PIPE_CRC_SOURCE_DP_D
,
1600 INTEL_PIPE_CRC_SOURCE_AUTO
,
1601 INTEL_PIPE_CRC_SOURCE_MAX
,
1604 struct intel_pipe_crc_entry
{
1609 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1610 struct intel_pipe_crc
{
1612 bool opened
; /* exclusive access to the result file */
1613 struct intel_pipe_crc_entry
*entries
;
1614 enum intel_pipe_crc_source source
;
1616 wait_queue_head_t wq
;
1619 struct i915_frontbuffer_tracking
{
1623 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1630 struct i915_wa_reg
{
1633 /* bitmask representing WA bits */
1637 #define I915_MAX_WA_REGS 16
1639 struct i915_workarounds
{
1640 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1644 struct drm_i915_private
{
1645 struct drm_device
*dev
;
1646 struct kmem_cache
*slab
;
1648 const struct intel_device_info info
;
1650 int relative_constants_mode
;
1654 struct intel_uncore uncore
;
1656 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1659 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1660 * controller on different i2c buses. */
1661 struct mutex gmbus_mutex
;
1664 * Base address of the gmbus and gpio block.
1666 uint32_t gpio_mmio_base
;
1668 /* MMIO base address for MIPI regs */
1669 uint32_t mipi_mmio_base
;
1671 wait_queue_head_t gmbus_wait_queue
;
1673 struct pci_dev
*bridge_dev
;
1674 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1675 struct drm_i915_gem_object
*semaphore_obj
;
1676 uint32_t last_seqno
, next_seqno
;
1678 struct drm_dma_handle
*status_page_dmah
;
1679 struct resource mch_res
;
1681 /* protects the irq masks */
1682 spinlock_t irq_lock
;
1684 /* protects the mmio flip data */
1685 spinlock_t mmio_flip_lock
;
1687 bool display_irqs_enabled
;
1689 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1690 struct pm_qos_request pm_qos
;
1692 /* DPIO indirect register protection */
1693 struct mutex dpio_lock
;
1695 /** Cached value of IMR to avoid reads in updating the bitfield */
1698 u32 de_irq_mask
[I915_MAX_PIPES
];
1703 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1705 struct work_struct hotplug_work
;
1707 unsigned long hpd_last_jiffies
;
1712 HPD_MARK_DISABLED
= 2
1714 } hpd_stats
[HPD_NUM_PINS
];
1716 struct delayed_work hotplug_reenable_work
;
1718 struct i915_fbc fbc
;
1719 struct i915_drrs drrs
;
1720 struct intel_opregion opregion
;
1721 struct intel_vbt_data vbt
;
1723 bool preserve_bios_swizzle
;
1726 struct intel_overlay
*overlay
;
1728 /* backlight registers and fields in struct intel_panel */
1729 struct mutex backlight_lock
;
1732 bool no_aux_handshake
;
1734 /* protects panel power sequencer state */
1735 struct mutex pps_mutex
;
1737 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1738 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1739 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1741 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1742 unsigned int vlv_cdclk_freq
;
1743 unsigned int hpll_freq
;
1746 * wq - Driver workqueue for GEM.
1748 * NOTE: Work items scheduled here are not allowed to grab any modeset
1749 * locks, for otherwise the flushing done in the pageflip code will
1750 * result in deadlocks.
1752 struct workqueue_struct
*wq
;
1754 /* Display functions */
1755 struct drm_i915_display_funcs display
;
1757 /* PCH chipset type */
1758 enum intel_pch pch_type
;
1759 unsigned short pch_id
;
1761 unsigned long quirks
;
1763 enum modeset_restore modeset_restore
;
1764 struct mutex modeset_restore_lock
;
1766 struct list_head vm_list
; /* Global list of all address spaces */
1767 struct i915_gtt gtt
; /* VM representing the global address space */
1769 struct i915_gem_mm mm
;
1770 DECLARE_HASHTABLE(mm_structs
, 7);
1771 struct mutex mm_lock
;
1773 /* Kernel Modesetting */
1775 struct sdvo_device_mapping sdvo_mappings
[2];
1777 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1778 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1779 wait_queue_head_t pending_flip_queue
;
1781 #ifdef CONFIG_DEBUG_FS
1782 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1785 int num_shared_dpll
;
1786 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1787 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1789 struct i915_workarounds workarounds
;
1791 /* Reclocking support */
1792 bool render_reclock_avail
;
1793 bool lvds_downclock_avail
;
1794 /* indicates the reduced downclock for LVDS*/
1797 struct i915_frontbuffer_tracking fb_tracking
;
1801 bool mchbar_need_disable
;
1803 struct intel_l3_parity l3_parity
;
1805 /* Cannot be determined by PCIID. You must always read a register. */
1808 /* gen6+ rps state */
1809 struct intel_gen6_power_mgmt rps
;
1811 /* ilk-only ips/rps state. Everything in here is protected by the global
1812 * mchdev_lock in intel_pm.c */
1813 struct intel_ilk_power_mgmt ips
;
1815 struct i915_power_domains power_domains
;
1817 struct i915_psr psr
;
1819 struct i915_gpu_error gpu_error
;
1821 struct drm_i915_gem_object
*vlv_pctx
;
1823 #ifdef CONFIG_DRM_I915_FBDEV
1824 /* list of fbdev register on this device */
1825 struct intel_fbdev
*fbdev
;
1826 struct work_struct fbdev_suspend_work
;
1829 struct drm_property
*broadcast_rgb_property
;
1830 struct drm_property
*force_audio_property
;
1832 /* hda/i915 audio component */
1833 bool audio_component_registered
;
1835 uint32_t hw_context_size
;
1836 struct list_head context_list
;
1841 struct i915_suspend_saved_registers regfile
;
1842 struct vlv_s0ix_state vlv_s0ix_state
;
1846 * Raw watermark latency values:
1847 * in 0.1us units for WM0,
1848 * in 0.5us units for WM1+.
1851 uint16_t pri_latency
[5];
1853 uint16_t spr_latency
[5];
1855 uint16_t cur_latency
[5];
1857 * Raw watermark memory latency values
1858 * for SKL for all 8 levels
1861 uint16_t skl_latency
[8];
1864 * The skl_wm_values structure is a bit too big for stack
1865 * allocation, so we keep the staging struct where we store
1866 * intermediate results here instead.
1868 struct skl_wm_values skl_results
;
1870 /* current hardware state */
1872 struct ilk_wm_values hw
;
1873 struct skl_wm_values skl_hw
;
1877 struct i915_runtime_pm pm
;
1879 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1880 u32 long_hpd_port_mask
;
1881 u32 short_hpd_port_mask
;
1882 struct work_struct dig_port_work
;
1885 * if we get a HPD irq from DP and a HPD irq from non-DP
1886 * the non-DP HPD could block the workqueue on a mode config
1887 * mutex getting, that userspace may have taken. However
1888 * userspace is waiting on the DP workqueue to run which is
1889 * blocked behind the non-DP one.
1891 struct workqueue_struct
*dp_wq
;
1893 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1895 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1896 struct intel_engine_cs
*ring
,
1897 struct intel_context
*ctx
,
1898 struct drm_i915_gem_execbuffer2
*args
,
1899 struct list_head
*vmas
,
1900 struct drm_i915_gem_object
*batch_obj
,
1901 u64 exec_start
, u32 flags
);
1902 int (*init_rings
)(struct drm_device
*dev
);
1903 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1904 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1907 uint32_t request_uniq
;
1910 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1911 * will be rejected. Instead look for a better place.
1915 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1917 return dev
->dev_private
;
1920 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1922 return to_i915(dev_get_drvdata(dev
));
1925 /* Iterate over initialised rings */
1926 #define for_each_ring(ring__, dev_priv__, i__) \
1927 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1928 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1930 enum hdmi_force_audio
{
1931 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1932 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1933 HDMI_AUDIO_AUTO
, /* trust EDID */
1934 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1937 #define I915_GTT_OFFSET_NONE ((u32)-1)
1939 struct drm_i915_gem_object_ops
{
1940 /* Interface between the GEM object and its backing storage.
1941 * get_pages() is called once prior to the use of the associated set
1942 * of pages before to binding them into the GTT, and put_pages() is
1943 * called after we no longer need them. As we expect there to be
1944 * associated cost with migrating pages between the backing storage
1945 * and making them available for the GPU (e.g. clflush), we may hold
1946 * onto the pages after they are no longer referenced by the GPU
1947 * in case they may be used again shortly (for example migrating the
1948 * pages to a different memory domain within the GTT). put_pages()
1949 * will therefore most likely be called when the object itself is
1950 * being released or under memory pressure (where we attempt to
1951 * reap pages for the shrinker).
1953 int (*get_pages
)(struct drm_i915_gem_object
*);
1954 void (*put_pages
)(struct drm_i915_gem_object
*);
1955 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1956 void (*release
)(struct drm_i915_gem_object
*);
1960 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1961 * considered to be the frontbuffer for the given plane interface-vise. This
1962 * doesn't mean that the hw necessarily already scans it out, but that any
1963 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1965 * We have one bit per pipe and per scanout plane type.
1967 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1968 #define INTEL_FRONTBUFFER_BITS \
1969 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1970 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1971 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1972 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1973 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1974 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1975 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1976 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1977 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1978 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1979 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1981 struct drm_i915_gem_object
{
1982 struct drm_gem_object base
;
1984 const struct drm_i915_gem_object_ops
*ops
;
1986 /** List of VMAs backed by this object */
1987 struct list_head vma_list
;
1989 /** Stolen memory for this object, instead of being backed by shmem. */
1990 struct drm_mm_node
*stolen
;
1991 struct list_head global_list
;
1993 struct list_head ring_list
;
1994 /** Used in execbuf to temporarily hold a ref */
1995 struct list_head obj_exec_link
;
1997 struct list_head batch_pool_list
;
2000 * This is set if the object is on the active lists (has pending
2001 * rendering and so a non-zero seqno), and is not set if it i s on
2002 * inactive (ready to be unbound) list.
2004 unsigned int active
:1;
2007 * This is set if the object has been written to since last bound
2010 unsigned int dirty
:1;
2013 * Fence register bits (if any) for this object. Will be set
2014 * as needed when mapped into the GTT.
2015 * Protected by dev->struct_mutex.
2017 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2020 * Advice: are the backing pages purgeable?
2022 unsigned int madv
:2;
2025 * Current tiling mode for the object.
2027 unsigned int tiling_mode
:2;
2029 * Whether the tiling parameters for the currently associated fence
2030 * register have changed. Note that for the purposes of tracking
2031 * tiling changes we also treat the unfenced register, the register
2032 * slot that the object occupies whilst it executes a fenced
2033 * command (such as BLT on gen2/3), as a "fence".
2035 unsigned int fence_dirty
:1;
2038 * Is the object at the current location in the gtt mappable and
2039 * fenceable? Used to avoid costly recalculations.
2041 unsigned int map_and_fenceable
:1;
2044 * Whether the current gtt mapping needs to be mappable (and isn't just
2045 * mappable by accident). Track pin and fault separate for a more
2046 * accurate mappable working set.
2048 unsigned int fault_mappable
:1;
2049 unsigned int pin_mappable
:1;
2050 unsigned int pin_display
:1;
2053 * Is the object to be mapped as read-only to the GPU
2054 * Only honoured if hardware has relevant pte bit
2056 unsigned long gt_ro
:1;
2057 unsigned int cache_level
:3;
2059 unsigned int has_dma_mapping
:1;
2061 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2063 struct sg_table
*pages
;
2064 int pages_pin_count
;
2066 /* prime dma-buf support */
2067 void *dma_buf_vmapping
;
2070 /** Breadcrumb of last rendering to the buffer. */
2071 struct drm_i915_gem_request
*last_read_req
;
2072 struct drm_i915_gem_request
*last_write_req
;
2073 /** Breadcrumb of last fenced GPU access to the buffer. */
2074 struct drm_i915_gem_request
*last_fenced_req
;
2076 /** Current tiling stride for the object, if it's tiled. */
2079 /** References from framebuffers, locks out tiling changes. */
2080 unsigned long framebuffer_references
;
2082 /** Record of address bit 17 of each page at last unbind. */
2083 unsigned long *bit_17
;
2086 /** for phy allocated objects */
2087 struct drm_dma_handle
*phys_handle
;
2089 struct i915_gem_userptr
{
2091 unsigned read_only
:1;
2092 unsigned workers
:4;
2093 #define I915_GEM_USERPTR_MAX_WORKERS 15
2095 struct i915_mm_struct
*mm
;
2096 struct i915_mmu_object
*mmu_object
;
2097 struct work_struct
*work
;
2101 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2103 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2104 struct drm_i915_gem_object
*new,
2105 unsigned frontbuffer_bits
);
2108 * Request queue structure.
2110 * The request queue allows us to note sequence numbers that have been emitted
2111 * and may be associated with active buffers to be retired.
2113 * By keeping this list, we can avoid having to do questionable sequence
2114 * number comparisons on buffer last_read|write_seqno. It also allows an
2115 * emission time to be associated with the request for tracking how far ahead
2116 * of the GPU the submission is.
2118 struct drm_i915_gem_request
{
2121 /** On Which ring this request was generated */
2122 struct intel_engine_cs
*ring
;
2124 /** GEM sequence number associated with this request. */
2127 /** Position in the ringbuffer of the start of the request */
2131 * Position in the ringbuffer of the start of the postfix.
2132 * This is required to calculate the maximum available ringbuffer
2133 * space without overwriting the postfix.
2137 /** Position in the ringbuffer of the end of the whole request */
2140 /** Context related to this request */
2141 struct intel_context
*ctx
;
2143 /** Batch buffer related to this request if any */
2144 struct drm_i915_gem_object
*batch_obj
;
2146 /** Time at which this request was emitted, in jiffies. */
2147 unsigned long emitted_jiffies
;
2149 /** global list entry for this request */
2150 struct list_head list
;
2152 struct drm_i915_file_private
*file_priv
;
2153 /** file_priv list entry for this request */
2154 struct list_head client_list
;
2159 * The ELSP only accepts two elements at a time, so we queue
2160 * context/tail pairs on a given queue (ring->execlist_queue) until the
2161 * hardware is available. The queue serves a double purpose: we also use
2162 * it to keep track of the up to 2 contexts currently in the hardware
2163 * (usually one in execution and the other queued up by the GPU): We
2164 * only remove elements from the head of the queue when the hardware
2165 * informs us that an element has been completed.
2167 * All accesses to the queue are mediated by a spinlock
2168 * (ring->execlist_lock).
2171 /** Execlist link in the submission queue.*/
2172 struct list_head execlist_link
;
2174 /** Execlists no. of times this request has been sent to the ELSP */
2179 void i915_gem_request_free(struct kref
*req_ref
);
2181 static inline uint32_t
2182 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2184 return req
? req
->seqno
: 0;
2187 static inline struct intel_engine_cs
*
2188 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2190 return req
? req
->ring
: NULL
;
2194 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2196 kref_get(&req
->ref
);
2200 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2202 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2203 kref_put(&req
->ref
, i915_gem_request_free
);
2206 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2207 struct drm_i915_gem_request
*src
)
2210 i915_gem_request_reference(src
);
2213 i915_gem_request_unreference(*pdst
);
2219 * XXX: i915_gem_request_completed should be here but currently needs the
2220 * definition of i915_seqno_passed() which is below. It will be moved in
2221 * a later patch when the call to i915_seqno_passed() is obsoleted...
2224 struct drm_i915_file_private
{
2225 struct drm_i915_private
*dev_priv
;
2226 struct drm_file
*file
;
2230 struct list_head request_list
;
2231 struct delayed_work idle_work
;
2233 struct idr context_idr
;
2235 atomic_t rps_wait_boost
;
2236 struct intel_engine_cs
*bsd_ring
;
2240 * A command that requires special handling by the command parser.
2242 struct drm_i915_cmd_descriptor
{
2244 * Flags describing how the command parser processes the command.
2246 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2247 * a length mask if not set
2248 * CMD_DESC_SKIP: The command is allowed but does not follow the
2249 * standard length encoding for the opcode range in
2251 * CMD_DESC_REJECT: The command is never allowed
2252 * CMD_DESC_REGISTER: The command should be checked against the
2253 * register whitelist for the appropriate ring
2254 * CMD_DESC_MASTER: The command is allowed if the submitting process
2258 #define CMD_DESC_FIXED (1<<0)
2259 #define CMD_DESC_SKIP (1<<1)
2260 #define CMD_DESC_REJECT (1<<2)
2261 #define CMD_DESC_REGISTER (1<<3)
2262 #define CMD_DESC_BITMASK (1<<4)
2263 #define CMD_DESC_MASTER (1<<5)
2266 * The command's unique identification bits and the bitmask to get them.
2267 * This isn't strictly the opcode field as defined in the spec and may
2268 * also include type, subtype, and/or subop fields.
2276 * The command's length. The command is either fixed length (i.e. does
2277 * not include a length field) or has a length field mask. The flag
2278 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2279 * a length mask. All command entries in a command table must include
2280 * length information.
2288 * Describes where to find a register address in the command to check
2289 * against the ring's register whitelist. Only valid if flags has the
2290 * CMD_DESC_REGISTER bit set.
2297 #define MAX_CMD_DESC_BITMASKS 3
2299 * Describes command checks where a particular dword is masked and
2300 * compared against an expected value. If the command does not match
2301 * the expected value, the parser rejects it. Only valid if flags has
2302 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2305 * If the check specifies a non-zero condition_mask then the parser
2306 * only performs the check when the bits specified by condition_mask
2313 u32 condition_offset
;
2315 } bits
[MAX_CMD_DESC_BITMASKS
];
2319 * A table of commands requiring special handling by the command parser.
2321 * Each ring has an array of tables. Each table consists of an array of command
2322 * descriptors, which must be sorted with command opcodes in ascending order.
2324 struct drm_i915_cmd_table
{
2325 const struct drm_i915_cmd_descriptor
*table
;
2329 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2330 #define __I915__(p) ({ \
2331 struct drm_i915_private *__p; \
2332 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2333 __p = (struct drm_i915_private *)p; \
2334 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2335 __p = to_i915((struct drm_device *)p); \
2340 #define INTEL_INFO(p) (&__I915__(p)->info)
2341 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2343 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2344 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2345 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2346 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2347 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2348 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2349 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2350 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2351 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2352 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2353 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2354 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2355 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2356 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2357 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2358 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2359 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2360 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2361 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2362 INTEL_DEVID(dev) == 0x0152 || \
2363 INTEL_DEVID(dev) == 0x015a)
2364 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2365 INTEL_DEVID(dev) == 0x0106 || \
2366 INTEL_DEVID(dev) == 0x010A)
2367 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2368 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2369 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2370 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2371 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2372 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2373 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2374 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2375 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2376 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2377 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2378 (INTEL_DEVID(dev) & 0xf) == 0xe))
2379 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2380 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2381 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2382 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2383 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2384 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2385 /* ULX machines are also considered ULT. */
2386 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2387 INTEL_DEVID(dev) == 0x0A1E)
2388 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2391 * The genX designation typically refers to the render engine, so render
2392 * capability related checks should use IS_GEN, while display and other checks
2393 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2396 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2397 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2398 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2399 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2400 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2401 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2402 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2403 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2405 #define RENDER_RING (1<<RCS)
2406 #define BSD_RING (1<<VCS)
2407 #define BLT_RING (1<<BCS)
2408 #define VEBOX_RING (1<<VECS)
2409 #define BSD2_RING (1<<VCS2)
2410 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2411 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2412 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2413 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2414 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2415 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2416 __I915__(dev)->ellc_size)
2417 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2419 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2420 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2421 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2422 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2424 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2425 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2427 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2428 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2430 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2431 * even when in MSI mode. This results in spurious interrupt warnings if the
2432 * legacy irq no. is shared with another device. The kernel then disables that
2433 * interrupt source and so prevents the other device from working properly.
2435 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2436 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2438 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2439 * rows, which changed the alignment requirements and fence programming.
2441 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2443 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2444 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2445 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2446 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2447 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2449 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2450 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2451 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2453 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2455 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2456 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2457 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2458 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2459 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2460 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2461 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2462 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2464 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2465 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2466 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2467 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2468 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2469 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2470 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2471 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2473 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2474 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2475 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2476 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2477 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2478 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2479 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2481 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2483 /* DPF == dynamic parity feature */
2484 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2485 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2487 #define GT_FREQUENCY_MULTIPLIER 50
2489 #include "i915_trace.h"
2491 extern const struct drm_ioctl_desc i915_ioctls
[];
2492 extern int i915_max_ioctl
;
2494 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2495 extern int i915_resume_legacy(struct drm_device
*dev
);
2496 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2497 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2500 struct i915_params
{
2502 int panel_ignore_lid
;
2503 unsigned int powersave
;
2505 unsigned int lvds_downclock
;
2506 int lvds_channel_mode
;
2508 int vbt_sdvo_panel_type
;
2512 int enable_execlists
;
2514 unsigned int preliminary_hw_support
;
2515 int disable_power_well
;
2517 int invert_brightness
;
2518 int enable_cmd_parser
;
2519 /* leave bools at the end to not create holes */
2520 bool enable_hangcheck
;
2522 bool prefault_disable
;
2524 bool disable_display
;
2525 bool disable_vtd_wa
;
2528 bool verbose_state_checks
;
2530 extern struct i915_params i915 __read_mostly
;
2533 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2534 extern int i915_driver_unload(struct drm_device
*);
2535 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2536 extern void i915_driver_lastclose(struct drm_device
* dev
);
2537 extern void i915_driver_preclose(struct drm_device
*dev
,
2538 struct drm_file
*file
);
2539 extern void i915_driver_postclose(struct drm_device
*dev
,
2540 struct drm_file
*file
);
2541 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2542 #ifdef CONFIG_COMPAT
2543 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2546 extern int intel_gpu_reset(struct drm_device
*dev
);
2547 extern int i915_reset(struct drm_device
*dev
);
2548 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2549 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2550 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2551 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2552 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2553 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2556 void i915_queue_hangcheck(struct drm_device
*dev
);
2558 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2559 const char *fmt
, ...);
2561 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2562 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2563 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2564 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2566 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2567 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2568 bool restore_forcewake
);
2569 extern void intel_uncore_init(struct drm_device
*dev
);
2570 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2571 extern void intel_uncore_fini(struct drm_device
*dev
);
2572 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2573 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2574 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2575 enum forcewake_domains domains
);
2576 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2577 enum forcewake_domains domains
);
2578 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2581 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2585 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2588 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2589 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2591 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2593 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2594 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2595 uint32_t interrupt_mask
,
2596 uint32_t enabled_irq_mask
);
2597 #define ibx_enable_display_interrupt(dev_priv, bits) \
2598 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2599 #define ibx_disable_display_interrupt(dev_priv, bits) \
2600 ibx_display_interrupt_update((dev_priv), (bits), 0)
2603 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2604 struct drm_file
*file_priv
);
2605 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2606 struct drm_file
*file_priv
);
2607 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2608 struct drm_file
*file_priv
);
2609 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2610 struct drm_file
*file_priv
);
2611 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2612 struct drm_file
*file_priv
);
2613 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2614 struct drm_file
*file_priv
);
2615 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2616 struct drm_file
*file_priv
);
2617 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2618 struct intel_engine_cs
*ring
);
2619 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2620 struct drm_file
*file
,
2621 struct intel_engine_cs
*ring
,
2622 struct drm_i915_gem_object
*obj
);
2623 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2624 struct drm_file
*file
,
2625 struct intel_engine_cs
*ring
,
2626 struct intel_context
*ctx
,
2627 struct drm_i915_gem_execbuffer2
*args
,
2628 struct list_head
*vmas
,
2629 struct drm_i915_gem_object
*batch_obj
,
2630 u64 exec_start
, u32 flags
);
2631 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2632 struct drm_file
*file_priv
);
2633 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2634 struct drm_file
*file_priv
);
2635 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2636 struct drm_file
*file_priv
);
2637 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2638 struct drm_file
*file
);
2639 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2640 struct drm_file
*file
);
2641 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2642 struct drm_file
*file_priv
);
2643 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2644 struct drm_file
*file_priv
);
2645 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2646 struct drm_file
*file_priv
);
2647 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2648 struct drm_file
*file_priv
);
2649 int i915_gem_init_userptr(struct drm_device
*dev
);
2650 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2651 struct drm_file
*file
);
2652 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2653 struct drm_file
*file_priv
);
2654 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2655 struct drm_file
*file_priv
);
2656 void i915_gem_load(struct drm_device
*dev
);
2657 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2660 #define I915_SHRINK_PURGEABLE 0x1
2661 #define I915_SHRINK_UNBOUND 0x2
2662 #define I915_SHRINK_BOUND 0x4
2663 void *i915_gem_object_alloc(struct drm_device
*dev
);
2664 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2665 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2666 const struct drm_i915_gem_object_ops
*ops
);
2667 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2669 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2670 struct i915_address_space
*vm
);
2671 void i915_gem_free_object(struct drm_gem_object
*obj
);
2672 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2674 #define PIN_MAPPABLE 0x1
2675 #define PIN_NONBLOCK 0x2
2676 #define PIN_GLOBAL 0x4
2677 #define PIN_OFFSET_BIAS 0x8
2678 #define PIN_OFFSET_MASK (~4095)
2679 int __must_check
i915_gem_object_pin_view(struct drm_i915_gem_object
*obj
,
2680 struct i915_address_space
*vm
,
2683 const struct i915_ggtt_view
*view
);
2685 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2686 struct i915_address_space
*vm
,
2690 return i915_gem_object_pin_view(obj
, vm
, alignment
, flags
,
2691 &i915_ggtt_view_normal
);
2694 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2696 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2697 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2698 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2699 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2701 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2702 int *needs_clflush
);
2704 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2705 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2707 struct sg_page_iter sg_iter
;
2709 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2710 return sg_page_iter_page(&sg_iter
);
2714 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2716 BUG_ON(obj
->pages
== NULL
);
2717 obj
->pages_pin_count
++;
2719 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2721 BUG_ON(obj
->pages_pin_count
== 0);
2722 obj
->pages_pin_count
--;
2725 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2726 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2727 struct intel_engine_cs
*to
);
2728 void i915_vma_move_to_active(struct i915_vma
*vma
,
2729 struct intel_engine_cs
*ring
);
2730 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2731 struct drm_device
*dev
,
2732 struct drm_mode_create_dumb
*args
);
2733 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2734 uint32_t handle
, uint64_t *offset
);
2736 * Returns true if seq1 is later than seq2.
2739 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2741 return (int32_t)(seq1
- seq2
) >= 0;
2744 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2745 bool lazy_coherency
)
2749 BUG_ON(req
== NULL
);
2751 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2753 return i915_seqno_passed(seqno
, req
->seqno
);
2756 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2757 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2758 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2759 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2761 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2762 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2764 struct drm_i915_gem_request
*
2765 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2767 bool i915_gem_retire_requests(struct drm_device
*dev
);
2768 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2769 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2770 bool interruptible
);
2771 int __must_check
i915_gem_check_olr(struct drm_i915_gem_request
*req
);
2773 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2775 return unlikely(atomic_read(&error
->reset_counter
)
2776 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2779 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2781 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2784 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2786 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2789 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2791 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2792 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2795 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2797 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2798 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2801 void i915_gem_reset(struct drm_device
*dev
);
2802 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2803 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2804 int __must_check
i915_gem_init(struct drm_device
*dev
);
2805 int i915_gem_init_rings(struct drm_device
*dev
);
2806 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2807 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2808 void i915_gem_init_swizzling(struct drm_device
*dev
);
2809 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2810 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2811 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2812 int __i915_add_request(struct intel_engine_cs
*ring
,
2813 struct drm_file
*file
,
2814 struct drm_i915_gem_object
*batch_obj
);
2815 #define i915_add_request(ring) \
2816 __i915_add_request(ring, NULL, NULL)
2817 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2818 unsigned reset_counter
,
2821 struct drm_i915_file_private
*file_priv
);
2822 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2823 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2825 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2828 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2830 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2832 struct intel_engine_cs
*pipelined
);
2833 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2834 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2836 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2837 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2840 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2842 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2843 int tiling_mode
, bool fenced
);
2845 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2846 enum i915_cache_level cache_level
);
2848 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2849 struct dma_buf
*dma_buf
);
2851 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2852 struct drm_gem_object
*gem_obj
, int flags
);
2854 void i915_gem_restore_fences(struct drm_device
*dev
);
2856 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object
*o
,
2857 struct i915_address_space
*vm
,
2858 enum i915_ggtt_view_type view
);
2860 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2861 struct i915_address_space
*vm
)
2863 return i915_gem_obj_offset_view(o
, vm
, I915_GGTT_VIEW_NORMAL
);
2865 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2866 bool i915_gem_obj_bound_view(struct drm_i915_gem_object
*o
,
2867 struct i915_address_space
*vm
,
2868 enum i915_ggtt_view_type view
);
2870 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2871 struct i915_address_space
*vm
)
2873 return i915_gem_obj_bound_view(o
, vm
, I915_GGTT_VIEW_NORMAL
);
2876 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2877 struct i915_address_space
*vm
);
2878 struct i915_vma
*i915_gem_obj_to_vma_view(struct drm_i915_gem_object
*obj
,
2879 struct i915_address_space
*vm
,
2880 const struct i915_ggtt_view
*view
);
2882 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2883 struct i915_address_space
*vm
)
2885 return i915_gem_obj_to_vma_view(obj
, vm
, &i915_ggtt_view_normal
);
2889 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object
*obj
,
2890 struct i915_address_space
*vm
,
2891 const struct i915_ggtt_view
*view
);
2895 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2896 struct i915_address_space
*vm
)
2898 return i915_gem_obj_lookup_or_create_vma_view(obj
, vm
,
2899 &i915_ggtt_view_normal
);
2902 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2903 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2904 struct i915_vma
*vma
;
2905 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2906 if (vma
->pin_count
> 0)
2911 /* Some GGTT VM helpers */
2912 #define i915_obj_to_ggtt(obj) \
2913 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2914 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2916 struct i915_address_space
*ggtt
=
2917 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2921 static inline struct i915_hw_ppgtt
*
2922 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2924 WARN_ON(i915_is_ggtt(vm
));
2926 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2930 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2932 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2935 static inline unsigned long
2936 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2938 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2941 static inline unsigned long
2942 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2944 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2947 static inline int __must_check
2948 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2952 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2953 alignment
, flags
| PIN_GLOBAL
);
2957 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2959 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2962 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2964 /* i915_gem_context.c */
2965 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2966 void i915_gem_context_fini(struct drm_device
*dev
);
2967 void i915_gem_context_reset(struct drm_device
*dev
);
2968 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2969 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2970 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2971 int i915_switch_context(struct intel_engine_cs
*ring
,
2972 struct intel_context
*to
);
2973 struct intel_context
*
2974 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2975 void i915_gem_context_free(struct kref
*ctx_ref
);
2976 struct drm_i915_gem_object
*
2977 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2978 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2980 kref_get(&ctx
->ref
);
2983 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2985 kref_put(&ctx
->ref
, i915_gem_context_free
);
2988 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2990 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2993 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2994 struct drm_file
*file
);
2995 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2996 struct drm_file
*file
);
2997 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
2998 struct drm_file
*file_priv
);
2999 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3000 struct drm_file
*file_priv
);
3002 /* i915_gem_evict.c */
3003 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3004 struct i915_address_space
*vm
,
3007 unsigned cache_level
,
3008 unsigned long start
,
3011 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3012 int i915_gem_evict_everything(struct drm_device
*dev
);
3014 /* belongs in i915_gem_gtt.h */
3015 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3017 if (INTEL_INFO(dev
)->gen
< 6)
3018 intel_gtt_chipset_flush();
3021 /* i915_gem_stolen.c */
3022 int i915_gem_init_stolen(struct drm_device
*dev
);
3023 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
3024 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
3025 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3026 struct drm_i915_gem_object
*
3027 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3028 struct drm_i915_gem_object
*
3029 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3034 /* i915_gem_tiling.c */
3035 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3037 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3039 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3040 obj
->tiling_mode
!= I915_TILING_NONE
;
3043 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3044 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3045 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3047 /* i915_gem_debug.c */
3049 int i915_verify_lists(struct drm_device
*dev
);
3051 #define i915_verify_lists(dev) 0
3054 /* i915_debugfs.c */
3055 int i915_debugfs_init(struct drm_minor
*minor
);
3056 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3057 #ifdef CONFIG_DEBUG_FS
3058 void intel_display_crc_init(struct drm_device
*dev
);
3060 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3063 /* i915_gpu_error.c */
3065 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3066 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3067 const struct i915_error_state_file_priv
*error
);
3068 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3069 struct drm_i915_private
*i915
,
3070 size_t count
, loff_t pos
);
3071 static inline void i915_error_state_buf_release(
3072 struct drm_i915_error_state_buf
*eb
)
3076 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3077 const char *error_msg
);
3078 void i915_error_state_get(struct drm_device
*dev
,
3079 struct i915_error_state_file_priv
*error_priv
);
3080 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3081 void i915_destroy_error_state(struct drm_device
*dev
);
3083 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3084 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3086 /* i915_gem_batch_pool.c */
3087 void i915_gem_batch_pool_init(struct drm_device
*dev
,
3088 struct i915_gem_batch_pool
*pool
);
3089 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool
*pool
);
3090 struct drm_i915_gem_object
*
3091 i915_gem_batch_pool_get(struct i915_gem_batch_pool
*pool
, size_t size
);
3093 /* i915_cmd_parser.c */
3094 int i915_cmd_parser_get_version(void);
3095 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3096 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3097 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3098 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3099 struct drm_i915_gem_object
*batch_obj
,
3100 struct drm_i915_gem_object
*shadow_batch_obj
,
3101 u32 batch_start_offset
,
3105 /* i915_suspend.c */
3106 extern int i915_save_state(struct drm_device
*dev
);
3107 extern int i915_restore_state(struct drm_device
*dev
);
3110 void i915_save_display_reg(struct drm_device
*dev
);
3111 void i915_restore_display_reg(struct drm_device
*dev
);
3114 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3115 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3118 extern int intel_setup_gmbus(struct drm_device
*dev
);
3119 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3120 static inline bool intel_gmbus_is_port_valid(unsigned port
)
3122 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
3125 extern struct i2c_adapter
*intel_gmbus_get_adapter(
3126 struct drm_i915_private
*dev_priv
, unsigned port
);
3127 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3128 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3129 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3131 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3133 extern void intel_i2c_reset(struct drm_device
*dev
);
3135 /* intel_opregion.c */
3137 extern int intel_opregion_setup(struct drm_device
*dev
);
3138 extern void intel_opregion_init(struct drm_device
*dev
);
3139 extern void intel_opregion_fini(struct drm_device
*dev
);
3140 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3141 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3143 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3146 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3147 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3148 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3149 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3151 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3156 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3164 extern void intel_register_dsm_handler(void);
3165 extern void intel_unregister_dsm_handler(void);
3167 static inline void intel_register_dsm_handler(void) { return; }
3168 static inline void intel_unregister_dsm_handler(void) { return; }
3169 #endif /* CONFIG_ACPI */
3172 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3173 extern void intel_modeset_init(struct drm_device
*dev
);
3174 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3175 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3176 extern void intel_connector_unregister(struct intel_connector
*);
3177 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3178 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
3179 bool force_restore
);
3180 extern void i915_redisable_vga(struct drm_device
*dev
);
3181 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3182 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3183 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3184 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
3185 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
3186 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3188 extern void intel_detect_pch(struct drm_device
*dev
);
3189 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3190 extern int intel_enable_rc6(const struct drm_device
*dev
);
3192 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3193 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3194 struct drm_file
*file
);
3195 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3196 struct drm_file
*file
);
3198 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
3201 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3202 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3203 struct intel_overlay_error_state
*error
);
3205 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3206 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3207 struct drm_device
*dev
,
3208 struct intel_display_error_state
*error
);
3210 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3211 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3213 /* intel_sideband.c */
3214 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3215 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3216 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3217 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3218 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3219 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3220 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3221 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3222 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3223 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3224 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3225 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3226 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3227 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3228 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3229 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3230 enum intel_sbi_destination destination
);
3231 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3232 enum intel_sbi_destination destination
);
3233 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3234 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3236 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3237 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3239 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3240 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3242 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3243 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3244 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3245 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3247 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3248 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3249 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3250 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3252 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3253 * will be implemented using 2 32-bit writes in an arbitrary order with
3254 * an arbitrary delay between them. This can cause the hardware to
3255 * act upon the intermediate value, possibly leading to corruption and
3256 * machine death. You have been warned.
3258 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3259 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3261 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3262 u32 upper = I915_READ(upper_reg); \
3263 u32 lower = I915_READ(lower_reg); \
3264 u32 tmp = I915_READ(upper_reg); \
3265 if (upper != tmp) { \
3267 lower = I915_READ(lower_reg); \
3268 WARN_ON(I915_READ(upper_reg) != upper); \
3270 (u64)upper << 32 | lower; })
3272 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3273 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3275 /* "Broadcast RGB" property */
3276 #define INTEL_BROADCAST_RGB_AUTO 0
3277 #define INTEL_BROADCAST_RGB_FULL 1
3278 #define INTEL_BROADCAST_RGB_LIMITED 2
3280 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3282 if (IS_VALLEYVIEW(dev
))
3283 return VLV_VGACNTRL
;
3284 else if (INTEL_INFO(dev
)->gen
>= 5)
3285 return CPU_VGACNTRL
;
3290 static inline void __user
*to_user_ptr(u64 address
)
3292 return (void __user
*)(uintptr_t)address
;
3295 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3297 unsigned long j
= msecs_to_jiffies(m
);
3299 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3302 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3304 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3307 static inline unsigned long
3308 timespec_to_jiffies_timeout(const struct timespec
*value
)
3310 unsigned long j
= timespec_to_jiffies(value
);
3312 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3316 * If you need to wait X milliseconds between events A and B, but event B
3317 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3318 * when event A happened, then just before event B you call this function and
3319 * pass the timestamp as the first argument, and X as the second argument.
3322 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3324 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3327 * Don't re-read the value of "jiffies" every time since it may change
3328 * behind our back and break the math.
3330 tmp_jiffies
= jiffies
;
3331 target_jiffies
= timestamp_jiffies
+
3332 msecs_to_jiffies_timeout(to_wait_ms
);
3334 if (time_after(target_jiffies
, tmp_jiffies
)) {
3335 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3336 while (remaining_jiffies
)
3338 schedule_timeout_uninterruptible(remaining_jiffies
);
3342 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3343 struct drm_i915_gem_request
*req
)
3345 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3346 i915_gem_request_assign(&ring
->trace_irq_req
, req
);