drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include "i915_reg.h"
  36 #include "intel_bios.h"
  37 #include "intel_ringbuffer.h"
  38 #include "i915_gem_gtt.h"
  39 #include <linux/io-mapping.h>
  40 #include <linux/i2c.h>
  41 #include <linux/i2c-algo-bit.h>
  42 #include <drm/intel-gtt.h>
  43 #include <linux/backlight.h>
  44 #include <linux/intel-iommu.h>
  45 #include <linux/kref.h>
  46 #include <linux/pm_qos.h>
  47
  48 /* General customization:
  49  */
  50
  51 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  52
  53 #define DRIVER_NAME             "i915"
  54 #define DRIVER_DESC             "Intel Graphics"
  55 #define DRIVER_DATE             "20080730"
  56
  57 enum pipe {
  58         INVALID_PIPE = -1,
  59         PIPE_A = 0,
  60         PIPE_B,
  61         PIPE_C,
  62         _PIPE_EDP,
  63         I915_MAX_PIPES = _PIPE_EDP
  64 };
  65 #define pipe_name(p) ((p) + 'A')
  66
  67 enum transcoder {
  68         TRANSCODER_A = 0,
  69         TRANSCODER_B,
  70         TRANSCODER_C,
  71         TRANSCODER_EDP,
  72         I915_MAX_TRANSCODERS
  73 };
  74 #define transcoder_name(t) ((t) + 'A')
  75
  76 enum plane {
  77         PLANE_A = 0,
  78         PLANE_B,
  79         PLANE_C,
  80 };
  81 #define plane_name(p) ((p) + 'A')
  82
  83 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
  84
  85 enum port {
  86         PORT_A = 0,
  87         PORT_B,
  88         PORT_C,
  89         PORT_D,
  90         PORT_E,
  91         I915_MAX_PORTS
  92 };
  93 #define port_name(p) ((p) + 'A')
  94
  95 #define I915_NUM_PHYS_VLV 1
  96
  97 enum dpio_channel {
  98         DPIO_CH0,
  99         DPIO_CH1
 100 };
 101
 102 enum dpio_phy {
 103         DPIO_PHY0,
 104         DPIO_PHY1
 105 };
 106
 107 enum intel_display_power_domain {
 108         POWER_DOMAIN_PIPE_A,
 109         POWER_DOMAIN_PIPE_B,
 110         POWER_DOMAIN_PIPE_C,
 111         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 112         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 113         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 114         POWER_DOMAIN_TRANSCODER_A,
 115         POWER_DOMAIN_TRANSCODER_B,
 116         POWER_DOMAIN_TRANSCODER_C,
 117         POWER_DOMAIN_TRANSCODER_EDP,
 118         POWER_DOMAIN_PORT_DDI_A_2_LANES,
 119         POWER_DOMAIN_PORT_DDI_A_4_LANES,
 120         POWER_DOMAIN_PORT_DDI_B_2_LANES,
 121         POWER_DOMAIN_PORT_DDI_B_4_LANES,
 122         POWER_DOMAIN_PORT_DDI_C_2_LANES,
 123         POWER_DOMAIN_PORT_DDI_C_4_LANES,
 124         POWER_DOMAIN_PORT_DDI_D_2_LANES,
 125         POWER_DOMAIN_PORT_DDI_D_4_LANES,
 126         POWER_DOMAIN_PORT_DSI,
 127         POWER_DOMAIN_PORT_CRT,
 128         POWER_DOMAIN_PORT_OTHER,
 129         POWER_DOMAIN_VGA,
 130         POWER_DOMAIN_AUDIO,
 131         POWER_DOMAIN_INIT,
 132
 133         POWER_DOMAIN_NUM,
 134 };
 135
 136 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 137 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 138                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 139 #define POWER_DOMAIN_TRANSCODER(tran) \
 140         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 141          (tran) + POWER_DOMAIN_TRANSCODER_A)
 142
 143 enum hpd_pin {
 144         HPD_NONE = 0,
 145         HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
 146         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 147         HPD_CRT,
 148         HPD_SDVO_B,
 149         HPD_SDVO_C,
 150         HPD_PORT_B,
 151         HPD_PORT_C,
 152         HPD_PORT_D,
 153         HPD_NUM_PINS
 154 };
 155
 156 #define I915_GEM_GPU_DOMAINS \
 157         (I915_GEM_DOMAIN_RENDER | \
 158          I915_GEM_DOMAIN_SAMPLER | \
 159          I915_GEM_DOMAIN_COMMAND | \
 160          I915_GEM_DOMAIN_INSTRUCTION | \
 161          I915_GEM_DOMAIN_VERTEX)
 162
 163 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
 164 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
 165
 166 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 167         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 168                 if ((intel_encoder)->base.crtc == (__crtc))
 169
 170 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 171         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 172                 if ((intel_connector)->base.encoder == (__encoder))
 173
 174 struct drm_i915_private;
 175
 176 enum intel_dpll_id {
 177         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 178         /* real shared dpll ids must be >= 0 */
 179         DPLL_ID_PCH_PLL_A,
 180         DPLL_ID_PCH_PLL_B,
 181 };
 182 #define I915_NUM_PLLS 2
 183
 184 struct intel_dpll_hw_state {
 185         uint32_t dpll;
 186         uint32_t dpll_md;
 187         uint32_t fp0;
 188         uint32_t fp1;
 189 };
 190
 191 struct intel_shared_dpll {
 192         int refcount; /* count of number of CRTCs sharing this PLL */
 193         int active; /* count of number of active CRTCs (i.e. DPMS on) */
 194         bool on; /* is the PLL actually active? Disabled during modeset */
 195         const char *name;
 196         /* should match the index in the dev_priv->shared_dplls array */
 197         enum intel_dpll_id id;
 198         struct intel_dpll_hw_state hw_state;
 199         void (*mode_set)(struct drm_i915_private *dev_priv,
 200                          struct intel_shared_dpll *pll);
 201         void (*enable)(struct drm_i915_private *dev_priv,
 202                        struct intel_shared_dpll *pll);
 203         void (*disable)(struct drm_i915_private *dev_priv,
 204                         struct intel_shared_dpll *pll);
 205         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 206                              struct intel_shared_dpll *pll,
 207                              struct intel_dpll_hw_state *hw_state);
 208 };
 209
 210 /* Used by dp and fdi links */
 211 struct intel_link_m_n {
 212         uint32_t        tu;
 213         uint32_t        gmch_m;
 214         uint32_t        gmch_n;
 215         uint32_t        link_m;
 216         uint32_t        link_n;
 217 };
 218
 219 void intel_link_compute_m_n(int bpp, int nlanes,
 220                             int pixel_clock, int link_clock,
 221                             struct intel_link_m_n *m_n);
 222
 223 struct intel_ddi_plls {
 224         int spll_refcount;
 225         int wrpll1_refcount;
 226         int wrpll2_refcount;
 227 };
 228
 229 /* Interface history:
 230  *
 231  * 1.1: Original.
 232  * 1.2: Add Power Management
 233  * 1.3: Add vblank support
 234  * 1.4: Fix cmdbuffer path, add heap destroy
 235  * 1.5: Add vblank pipe configuration
 236  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 237  *      - Support vertical blank on secondary display pipe
 238  */
 239 #define DRIVER_MAJOR            1
 240 #define DRIVER_MINOR            6
 241 #define DRIVER_PATCHLEVEL       0
 242
 243 #define WATCH_LISTS     0
 244 #define WATCH_GTT       0
 245
 246 #define I915_GEM_PHYS_CURSOR_0 1
 247 #define I915_GEM_PHYS_CURSOR_1 2
 248 #define I915_GEM_PHYS_OVERLAY_REGS 3
 249 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 250
 251 struct drm_i915_gem_phys_object {
 252         int id;
 253         struct page **page_list;
 254         drm_dma_handle_t *handle;
 255         struct drm_i915_gem_object *cur_obj;
 256 };
 257
 258 struct opregion_header;
 259 struct opregion_acpi;
 260 struct opregion_swsci;
 261 struct opregion_asle;
 262
 263 struct intel_opregion {
 264         struct opregion_header __iomem *header;
 265         struct opregion_acpi __iomem *acpi;
 266         struct opregion_swsci __iomem *swsci;
 267         u32 swsci_gbda_sub_functions;
 268         u32 swsci_sbcb_sub_functions;
 269         struct opregion_asle __iomem *asle;
 270         void __iomem *vbt;
 271         u32 __iomem *lid_state;
 272         struct work_struct asle_work;
 273 };
 274 #define OPREGION_SIZE            (8*1024)
 275
 276 struct intel_overlay;
 277 struct intel_overlay_error_state;
 278
 279 struct drm_i915_master_private {
 280         drm_local_map_t *sarea;
 281         struct _drm_i915_sarea *sarea_priv;
 282 };
 283 #define I915_FENCE_REG_NONE -1
 284 #define I915_MAX_NUM_FENCES 32
 285 /* 32 fences + sign bit for FENCE_REG_NONE */
 286 #define I915_MAX_NUM_FENCE_BITS 6
 287
 288 struct drm_i915_fence_reg {
 289         struct list_head lru_list;
 290         struct drm_i915_gem_object *obj;
 291         int pin_count;
 292 };
 293
 294 struct sdvo_device_mapping {
 295         u8 initialized;
 296         u8 dvo_port;
 297         u8 slave_addr;
 298         u8 dvo_wiring;
 299         u8 i2c_pin;
 300         u8 ddc_pin;
 301 };
 302
 303 struct intel_display_error_state;
 304
 305 struct drm_i915_error_state {
 306         struct kref ref;
 307         struct timeval time;
 308
 309         char error_msg[128];
 310         u32 reset_count;
 311         u32 suspend_count;
 312
 313         /* Generic register state */
 314         u32 eir;
 315         u32 pgtbl_er;
 316         u32 ier;
 317         u32 ccid;
 318         u32 derrmr;
 319         u32 forcewake;
 320         u32 error; /* gen6+ */
 321         u32 err_int; /* gen7 */
 322         u32 done_reg;
 323         u32 gac_eco;
 324         u32 gam_ecochk;
 325         u32 gab_ctl;
 326         u32 gfx_mode;
 327         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 328         u64 fence[I915_MAX_NUM_FENCES];
 329         struct intel_overlay_error_state *overlay;
 330         struct intel_display_error_state *display;
 331
 332         struct drm_i915_error_ring {
 333                 bool valid;
 334                 /* Software tracked state */
 335                 bool waiting;
 336                 int hangcheck_score;
 337                 enum intel_ring_hangcheck_action hangcheck_action;
 338                 int num_requests;
 339
 340                 /* our own tracking of ring head and tail */
 341                 u32 cpu_ring_head;
 342                 u32 cpu_ring_tail;
 343
 344                 u32 semaphore_seqno[I915_NUM_RINGS - 1];
 345
 346                 /* Register state */
 347                 u32 tail;
 348                 u32 head;
 349                 u32 ctl;
 350                 u32 hws;
 351                 u32 ipeir;
 352                 u32 ipehr;
 353                 u32 instdone;
 354                 u32 bbstate;
 355                 u32 instpm;
 356                 u32 instps;
 357                 u32 seqno;
 358                 u64 bbaddr;
 359                 u64 acthd;
 360                 u32 fault_reg;
 361                 u64 faddr;
 362                 u32 rc_psmi; /* sleep state */
 363                 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
 364
 365                 struct drm_i915_error_object {
 366                         int page_count;
 367                         u32 gtt_offset;
 368                         u32 *pages[0];
 369                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 370
 371                 struct drm_i915_error_request {
 372                         long jiffies;
 373                         u32 seqno;
 374                         u32 tail;
 375                 } *requests;
 376
 377                 struct {
 378                         u32 gfx_mode;
 379                         union {
 380                                 u64 pdp[4];
 381                                 u32 pp_dir_base;
 382                         };
 383                 } vm_info;
 384
 385                 pid_t pid;
 386                 char comm[TASK_COMM_LEN];
 387         } ring[I915_NUM_RINGS];
 388         struct drm_i915_error_buffer {
 389                 u32 size;
 390                 u32 name;
 391                 u32 rseqno, wseqno;
 392                 u32 gtt_offset;
 393                 u32 read_domains;
 394                 u32 write_domain;
 395                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 396                 s32 pinned:2;
 397                 u32 tiling:2;
 398                 u32 dirty:1;
 399                 u32 purgeable:1;
 400                 s32 ring:4;
 401                 u32 cache_level:3;
 402         } **active_bo, **pinned_bo;
 403
 404         u32 *active_bo_count, *pinned_bo_count;
 405 };
 406
 407 struct intel_connector;
 408 struct intel_crtc_config;
 409 struct intel_plane_config;
 410 struct intel_crtc;
 411 struct intel_limit;
 412 struct dpll;
 413
 414 struct drm_i915_display_funcs {
 415         bool (*fbc_enabled)(struct drm_device *dev);
 416         void (*enable_fbc)(struct drm_crtc *crtc);
 417         void (*disable_fbc)(struct drm_device *dev);
 418         int (*get_display_clock_speed)(struct drm_device *dev);
 419         int (*get_fifo_size)(struct drm_device *dev, int plane);
 420         /**
 421          * find_dpll() - Find the best values for the PLL
 422          * @limit: limits for the PLL
 423          * @crtc: current CRTC
 424          * @target: target frequency in kHz
 425          * @refclk: reference clock frequency in kHz
 426          * @match_clock: if provided, @best_clock P divider must
 427          *               match the P divider from @match_clock
 428          *               used for LVDS downclocking
 429          * @best_clock: best PLL values found
 430          *
 431          * Returns true on success, false on failure.
 432          */
 433         bool (*find_dpll)(const struct intel_limit *limit,
 434                           struct drm_crtc *crtc,
 435                           int target, int refclk,
 436                           struct dpll *match_clock,
 437                           struct dpll *best_clock);
 438         void (*update_wm)(struct drm_crtc *crtc);
 439         void (*update_sprite_wm)(struct drm_plane *plane,
 440                                  struct drm_crtc *crtc,
 441                                  uint32_t sprite_width, int pixel_size,
 442                                  bool enable, bool scaled);
 443         void (*modeset_global_resources)(struct drm_device *dev);
 444         /* Returns the active state of the crtc, and if the crtc is active,
 445          * fills out the pipe-config with the hw state. */
 446         bool (*get_pipe_config)(struct intel_crtc *,
 447                                 struct intel_crtc_config *);
 448         void (*get_plane_config)(struct intel_crtc *,
 449                                  struct intel_plane_config *);
 450         int (*crtc_mode_set)(struct drm_crtc *crtc,
 451                              int x, int y,
 452                              struct drm_framebuffer *old_fb);
 453         void (*crtc_enable)(struct drm_crtc *crtc);
 454         void (*crtc_disable)(struct drm_crtc *crtc);
 455         void (*off)(struct drm_crtc *crtc);
 456         void (*write_eld)(struct drm_connector *connector,
 457                           struct drm_crtc *crtc,
 458                           struct drm_display_mode *mode);
 459         void (*fdi_link_train)(struct drm_crtc *crtc);
 460         void (*init_clock_gating)(struct drm_device *dev);
 461         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 462                           struct drm_framebuffer *fb,
 463                           struct drm_i915_gem_object *obj,
 464                           uint32_t flags);
 465         int (*update_primary_plane)(struct drm_crtc *crtc,
 466                                     struct drm_framebuffer *fb,
 467                                     int x, int y);
 468         void (*hpd_irq_setup)(struct drm_device *dev);
 469         /* clock updates for mode set */
 470         /* cursor updates */
 471         /* render clock increase/decrease */
 472         /* display clock increase/decrease */
 473         /* pll clock increase/decrease */
 474
 475         int (*setup_backlight)(struct intel_connector *connector);
 476         uint32_t (*get_backlight)(struct intel_connector *connector);
 477         void (*set_backlight)(struct intel_connector *connector,
 478                               uint32_t level);
 479         void (*disable_backlight)(struct intel_connector *connector);
 480         void (*enable_backlight)(struct intel_connector *connector);
 481 };
 482
 483 struct intel_uncore_funcs {
 484         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 485                                                         int fw_engine);
 486         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 487                                                         int fw_engine);
 488
 489         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 490         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 491         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 492         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 493
 494         void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
 495                                 uint8_t val, bool trace);
 496         void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
 497                                 uint16_t val, bool trace);
 498         void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
 499                                 uint32_t val, bool trace);
 500         void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
 501                                 uint64_t val, bool trace);
 502 };
 503
 504 struct intel_uncore {
 505         spinlock_t lock; /** lock is also taken in irq contexts. */
 506
 507         struct intel_uncore_funcs funcs;
 508
 509         unsigned fifo_count;
 510         unsigned forcewake_count;
 511
 512         unsigned fw_rendercount;
 513         unsigned fw_mediacount;
 514
 515         struct timer_list force_wake_timer;
 516 };
 517
 518 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
 519         func(is_mobile) sep \
 520         func(is_i85x) sep \
 521         func(is_i915g) sep \
 522         func(is_i945gm) sep \
 523         func(is_g33) sep \
 524         func(need_gfx_hws) sep \
 525         func(is_g4x) sep \
 526         func(is_pineview) sep \
 527         func(is_broadwater) sep \
 528         func(is_crestline) sep \
 529         func(is_ivybridge) sep \
 530         func(is_valleyview) sep \
 531         func(is_haswell) sep \
 532         func(is_preliminary) sep \
 533         func(has_fbc) sep \
 534         func(has_pipe_cxsr) sep \
 535         func(has_hotplug) sep \
 536         func(cursor_needs_physical) sep \
 537         func(has_overlay) sep \
 538         func(overlay_needs_physical) sep \
 539         func(supports_tv) sep \
 540         func(has_llc) sep \
 541         func(has_ddi) sep \
 542         func(has_fpga_dbg)
 543
 544 #define DEFINE_FLAG(name) u8 name:1
 545 #define SEP_SEMICOLON ;
 546
 547 struct intel_device_info {
 548         u32 display_mmio_offset;
 549         u8 num_pipes:3;
 550         u8 num_sprites[I915_MAX_PIPES];
 551         u8 gen;
 552         u8 ring_mask; /* Rings supported by the HW */
 553         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 554         /* Register offsets for the various display pipes and transcoders */
 555         int pipe_offsets[I915_MAX_TRANSCODERS];
 556         int trans_offsets[I915_MAX_TRANSCODERS];
 557         int dpll_offsets[I915_MAX_PIPES];
 558         int dpll_md_offsets[I915_MAX_PIPES];
 559         int palette_offsets[I915_MAX_PIPES];
 560 };
 561
 562 #undef DEFINE_FLAG
 563 #undef SEP_SEMICOLON
 564
 565 enum i915_cache_level {
 566         I915_CACHE_NONE = 0,
 567         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 568         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 569                               caches, eg sampler/render caches, and the
 570                               large Last-Level-Cache. LLC is coherent with
 571                               the CPU, but L3 is only visible to the GPU. */
 572         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 573 };
 574
 575 struct i915_ctx_hang_stats {
 576         /* This context had batch pending when hang was declared */
 577         unsigned batch_pending;
 578
 579         /* This context had batch active when hang was declared */
 580         unsigned batch_active;
 581
 582         /* Time when this context was last blamed for a GPU reset */
 583         unsigned long guilty_ts;
 584
 585         /* This context is banned to submit more work */
 586         bool banned;
 587 };
 588
 589 /* This must match up with the value previously used for execbuf2.rsvd1. */
 590 #define DEFAULT_CONTEXT_ID 0
 591 struct i915_hw_context {
 592         struct kref ref;
 593         int id;
 594         bool is_initialized;
 595         uint8_t remap_slice;
 596         struct drm_i915_file_private *file_priv;
 597         struct intel_ring_buffer *last_ring;
 598         struct drm_i915_gem_object *obj;
 599         struct i915_ctx_hang_stats hang_stats;
 600         struct i915_address_space *vm;
 601
 602         struct list_head link;
 603 };
 604
 605 struct i915_fbc {
 606         unsigned long size;
 607         unsigned int fb_id;
 608         enum plane plane;
 609         int y;
 610
 611         struct drm_mm_node *compressed_fb;
 612         struct drm_mm_node *compressed_llb;
 613
 614         struct intel_fbc_work {
 615                 struct delayed_work work;
 616                 struct drm_crtc *crtc;
 617                 struct drm_framebuffer *fb;
 618         } *fbc_work;
 619
 620         enum no_fbc_reason {
 621                 FBC_OK, /* FBC is enabled */
 622                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
 623                 FBC_NO_OUTPUT, /* no outputs enabled to compress */
 624                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
 625                 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 626                 FBC_MODE_TOO_LARGE, /* mode too large for compression */
 627                 FBC_BAD_PLANE, /* fbc not supported on plane */
 628                 FBC_NOT_TILED, /* buffer not tiled */
 629                 FBC_MULTIPLE_PIPES, /* more than one pipe active */
 630                 FBC_MODULE_PARAM,
 631                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
 632         } no_fbc_reason;
 633 };
 634
 635 struct i915_drrs {
 636         struct intel_connector *connector;
 637 };
 638
 639 struct i915_psr {
 640         bool sink_support;
 641         bool source_ok;
 642 };
 643
 644 enum intel_pch {
 645         PCH_NONE = 0,   /* No PCH present */
 646         PCH_IBX,        /* Ibexpeak PCH */
 647         PCH_CPT,        /* Cougarpoint PCH */
 648         PCH_LPT,        /* Lynxpoint PCH */
 649         PCH_NOP,
 650 };
 651
 652 enum intel_sbi_destination {
 653         SBI_ICLK,
 654         SBI_MPHY,
 655 };
 656
 657 #define QUIRK_PIPEA_FORCE (1<<0)
 658 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 659 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 660
 661 struct intel_fbdev;
 662 struct intel_fbc_work;
 663
 664 struct intel_gmbus {
 665         struct i2c_adapter adapter;
 666         u32 force_bit;
 667         u32 reg0;
 668         u32 gpio_reg;
 669         struct i2c_algo_bit_data bit_algo;
 670         struct drm_i915_private *dev_priv;
 671 };
 672
 673 struct i915_suspend_saved_registers {
 674         u8 saveLBB;
 675         u32 saveDSPACNTR;
 676         u32 saveDSPBCNTR;
 677         u32 saveDSPARB;
 678         u32 savePIPEACONF;
 679         u32 savePIPEBCONF;
 680         u32 savePIPEASRC;
 681         u32 savePIPEBSRC;
 682         u32 saveFPA0;
 683         u32 saveFPA1;
 684         u32 saveDPLL_A;
 685         u32 saveDPLL_A_MD;
 686         u32 saveHTOTAL_A;
 687         u32 saveHBLANK_A;
 688         u32 saveHSYNC_A;
 689         u32 saveVTOTAL_A;
 690         u32 saveVBLANK_A;
 691         u32 saveVSYNC_A;
 692         u32 saveBCLRPAT_A;
 693         u32 saveTRANSACONF;
 694         u32 saveTRANS_HTOTAL_A;
 695         u32 saveTRANS_HBLANK_A;
 696         u32 saveTRANS_HSYNC_A;
 697         u32 saveTRANS_VTOTAL_A;
 698         u32 saveTRANS_VBLANK_A;
 699         u32 saveTRANS_VSYNC_A;
 700         u32 savePIPEASTAT;
 701         u32 saveDSPASTRIDE;
 702         u32 saveDSPASIZE;
 703         u32 saveDSPAPOS;
 704         u32 saveDSPAADDR;
 705         u32 saveDSPASURF;
 706         u32 saveDSPATILEOFF;
 707         u32 savePFIT_PGM_RATIOS;
 708         u32 saveBLC_HIST_CTL;
 709         u32 saveBLC_PWM_CTL;
 710         u32 saveBLC_PWM_CTL2;
 711         u32 saveBLC_HIST_CTL_B;
 712         u32 saveBLC_CPU_PWM_CTL;
 713         u32 saveBLC_CPU_PWM_CTL2;
 714         u32 saveFPB0;
 715         u32 saveFPB1;
 716         u32 saveDPLL_B;
 717         u32 saveDPLL_B_MD;
 718         u32 saveHTOTAL_B;
 719         u32 saveHBLANK_B;
 720         u32 saveHSYNC_B;
 721         u32 saveVTOTAL_B;
 722         u32 saveVBLANK_B;
 723         u32 saveVSYNC_B;
 724         u32 saveBCLRPAT_B;
 725         u32 saveTRANSBCONF;
 726         u32 saveTRANS_HTOTAL_B;
 727         u32 saveTRANS_HBLANK_B;
 728         u32 saveTRANS_HSYNC_B;
 729         u32 saveTRANS_VTOTAL_B;
 730         u32 saveTRANS_VBLANK_B;
 731         u32 saveTRANS_VSYNC_B;
 732         u32 savePIPEBSTAT;
 733         u32 saveDSPBSTRIDE;
 734         u32 saveDSPBSIZE;
 735         u32 saveDSPBPOS;
 736         u32 saveDSPBADDR;
 737         u32 saveDSPBSURF;
 738         u32 saveDSPBTILEOFF;
 739         u32 saveVGA0;
 740         u32 saveVGA1;
 741         u32 saveVGA_PD;
 742         u32 saveVGACNTRL;
 743         u32 saveADPA;
 744         u32 saveLVDS;
 745         u32 savePP_ON_DELAYS;
 746         u32 savePP_OFF_DELAYS;
 747         u32 saveDVOA;
 748         u32 saveDVOB;
 749         u32 saveDVOC;
 750         u32 savePP_ON;
 751         u32 savePP_OFF;
 752         u32 savePP_CONTROL;
 753         u32 savePP_DIVISOR;
 754         u32 savePFIT_CONTROL;
 755         u32 save_palette_a[256];
 756         u32 save_palette_b[256];
 757         u32 saveFBC_CONTROL;
 758         u32 saveIER;
 759         u32 saveIIR;
 760         u32 saveIMR;
 761         u32 saveDEIER;
 762         u32 saveDEIMR;
 763         u32 saveGTIER;
 764         u32 saveGTIMR;
 765         u32 saveFDI_RXA_IMR;
 766         u32 saveFDI_RXB_IMR;
 767         u32 saveCACHE_MODE_0;
 768         u32 saveMI_ARB_STATE;
 769         u32 saveSWF0[16];
 770         u32 saveSWF1[16];
 771         u32 saveSWF2[3];
 772         u8 saveMSR;
 773         u8 saveSR[8];
 774         u8 saveGR[25];
 775         u8 saveAR_INDEX;
 776         u8 saveAR[21];
 777         u8 saveDACMASK;
 778         u8 saveCR[37];
 779         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 780         u32 saveCURACNTR;
 781         u32 saveCURAPOS;
 782         u32 saveCURABASE;
 783         u32 saveCURBCNTR;
 784         u32 saveCURBPOS;
 785         u32 saveCURBBASE;
 786         u32 saveCURSIZE;
 787         u32 saveDP_B;
 788         u32 saveDP_C;
 789         u32 saveDP_D;
 790         u32 savePIPEA_GMCH_DATA_M;
 791         u32 savePIPEB_GMCH_DATA_M;
 792         u32 savePIPEA_GMCH_DATA_N;
 793         u32 savePIPEB_GMCH_DATA_N;
 794         u32 savePIPEA_DP_LINK_M;
 795         u32 savePIPEB_DP_LINK_M;
 796         u32 savePIPEA_DP_LINK_N;
 797         u32 savePIPEB_DP_LINK_N;
 798         u32 saveFDI_RXA_CTL;
 799         u32 saveFDI_TXA_CTL;
 800         u32 saveFDI_RXB_CTL;
 801         u32 saveFDI_TXB_CTL;
 802         u32 savePFA_CTL_1;
 803         u32 savePFB_CTL_1;
 804         u32 savePFA_WIN_SZ;
 805         u32 savePFB_WIN_SZ;
 806         u32 savePFA_WIN_POS;
 807         u32 savePFB_WIN_POS;
 808         u32 savePCH_DREF_CONTROL;
 809         u32 saveDISP_ARB_CTL;
 810         u32 savePIPEA_DATA_M1;
 811         u32 savePIPEA_DATA_N1;
 812         u32 savePIPEA_LINK_M1;
 813         u32 savePIPEA_LINK_N1;
 814         u32 savePIPEB_DATA_M1;
 815         u32 savePIPEB_DATA_N1;
 816         u32 savePIPEB_LINK_M1;
 817         u32 savePIPEB_LINK_N1;
 818         u32 saveMCHBAR_RENDER_STANDBY;
 819         u32 savePCH_PORT_HOTPLUG;
 820 };
 821
 822 struct vlv_s0ix_state {
 823         /* GAM */
 824         u32 wr_watermark;
 825         u32 gfx_prio_ctrl;
 826         u32 arb_mode;
 827         u32 gfx_pend_tlb0;
 828         u32 gfx_pend_tlb1;
 829         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
 830         u32 media_max_req_count;
 831         u32 gfx_max_req_count;
 832         u32 render_hwsp;
 833         u32 ecochk;
 834         u32 bsd_hwsp;
 835         u32 blt_hwsp;
 836         u32 tlb_rd_addr;
 837
 838         /* MBC */
 839         u32 g3dctl;
 840         u32 gsckgctl;
 841         u32 mbctl;
 842
 843         /* GCP */
 844         u32 ucgctl1;
 845         u32 ucgctl3;
 846         u32 rcgctl1;
 847         u32 rcgctl2;
 848         u32 rstctl;
 849         u32 misccpctl;
 850
 851         /* GPM */
 852         u32 gfxpause;
 853         u32 rpdeuhwtc;
 854         u32 rpdeuc;
 855         u32 ecobus;
 856         u32 pwrdwnupctl;
 857         u32 rp_down_timeout;
 858         u32 rp_deucsw;
 859         u32 rcubmabdtmr;
 860         u32 rcedata;
 861         u32 spare2gh;
 862
 863         /* Display 1 CZ domain */
 864         u32 gt_imr;
 865         u32 gt_ier;
 866         u32 pm_imr;
 867         u32 pm_ier;
 868         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 869
 870         /* GT SA CZ domain */
 871         u32 tilectl;
 872         u32 gt_fifoctl;
 873         u32 gtlc_wake_ctrl;
 874         u32 gtlc_survive;
 875         u32 pmwgicz;
 876
 877         /* Display 2 CZ domain */
 878         u32 gu_ctl0;
 879         u32 gu_ctl1;
 880         u32 clock_gate_dis2;
 881 };
 882
 883 struct intel_gen6_power_mgmt {
 884         /* work and pm_iir are protected by dev_priv->irq_lock */
 885         struct work_struct work;
 886         u32 pm_iir;
 887
 888         /* Frequencies are stored in potentially platform dependent multiples.
 889          * In other words, *_freq needs to be multiplied by X to be interesting.
 890          * Soft limits are those which are used for the dynamic reclocking done
 891          * by the driver (raise frequencies under heavy loads, and lower for
 892          * lighter loads). Hard limits are those imposed by the hardware.
 893          *
 894          * A distinction is made for overclocking, which is never enabled by
 895          * default, and is considered to be above the hard limit if it's
 896          * possible at all.
 897          */
 898         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
 899         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
 900         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
 901         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
 902         u8 min_freq;            /* AKA RPn. Minimum frequency */
 903         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
 904         u8 rp1_freq;            /* "less than" RP0 power/freqency */
 905         u8 rp0_freq;            /* Non-overclocked max frequency. */
 906
 907         int last_adj;
 908         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
 909
 910         bool enabled;
 911         struct delayed_work delayed_resume_work;
 912
 913         /*
 914          * Protects RPS/RC6 register access and PCU communication.
 915          * Must be taken after struct_mutex if nested.
 916          */
 917         struct mutex hw_lock;
 918 };
 919
 920 /* defined intel_pm.c */
 921 extern spinlock_t mchdev_lock;
 922
 923 struct intel_ilk_power_mgmt {
 924         u8 cur_delay;
 925         u8 min_delay;
 926         u8 max_delay;
 927         u8 fmax;
 928         u8 fstart;
 929
 930         u64 last_count1;
 931         unsigned long last_time1;
 932         unsigned long chipset_power;
 933         u64 last_count2;
 934         struct timespec last_time2;
 935         unsigned long gfx_power;
 936         u8 corr;
 937
 938         int c_m;
 939         int r_t;
 940
 941         struct drm_i915_gem_object *pwrctx;
 942         struct drm_i915_gem_object *renderctx;
 943 };
 944
 945 struct drm_i915_private;
 946 struct i915_power_well;
 947
 948 struct i915_power_well_ops {
 949         /*
 950          * Synchronize the well's hw state to match the current sw state, for
 951          * example enable/disable it based on the current refcount. Called
 952          * during driver init and resume time, possibly after first calling
 953          * the enable/disable handlers.
 954          */
 955         void (*sync_hw)(struct drm_i915_private *dev_priv,
 956                         struct i915_power_well *power_well);
 957         /*
 958          * Enable the well and resources that depend on it (for example
 959          * interrupts located on the well). Called after the 0->1 refcount
 960          * transition.
 961          */
 962         void (*enable)(struct drm_i915_private *dev_priv,
 963                        struct i915_power_well *power_well);
 964         /*
 965          * Disable the well and resources that depend on it. Called after
 966          * the 1->0 refcount transition.
 967          */
 968         void (*disable)(struct drm_i915_private *dev_priv,
 969                         struct i915_power_well *power_well);
 970         /* Returns the hw enabled state. */
 971         bool (*is_enabled)(struct drm_i915_private *dev_priv,
 972                            struct i915_power_well *power_well);
 973 };
 974
 975 /* Power well structure for haswell */
 976 struct i915_power_well {
 977         const char *name;
 978         bool always_on;
 979         /* power well enable/disable usage count */
 980         int count;
 981         unsigned long domains;
 982         unsigned long data;
 983         const struct i915_power_well_ops *ops;
 984 };
 985
 986 struct i915_power_domains {
 987         /*
 988          * Power wells needed for initialization at driver init and suspend
 989          * time are on. They are kept on until after the first modeset.
 990          */
 991         bool init_power_on;
 992         bool initializing;
 993         int power_well_count;
 994
 995         struct mutex lock;
 996         int domain_use_count[POWER_DOMAIN_NUM];
 997         struct i915_power_well *power_wells;
 998 };
 999
1000 struct i915_dri1_state {
1001         unsigned allow_batchbuffer : 1;
1002         u32 __iomem *gfx_hws_cpu_addr;
1003
1004         unsigned int cpp;
1005         int back_offset;
1006         int front_offset;
1007         int current_page;
1008         int page_flipping;
1009
1010         uint32_t counter;
1011 };
1012
1013 struct i915_ums_state {
1014         /**
1015          * Flag if the X Server, and thus DRM, is not currently in
1016          * control of the device.
1017          *
1018          * This is set between LeaveVT and EnterVT.  It needs to be
1019          * replaced with a semaphore.  It also needs to be
1020          * transitioned away from for kernel modesetting.
1021          */
1022         int mm_suspended;
1023 };
1024
1025 #define MAX_L3_SLICES 2
1026 struct intel_l3_parity {
1027         u32 *remap_info[MAX_L3_SLICES];
1028         struct work_struct error_work;
1029         int which_slice;
1030 };
1031
1032 struct i915_gem_mm {
1033         /** Memory allocator for GTT stolen memory */
1034         struct drm_mm stolen;
1035         /** List of all objects in gtt_space. Used to restore gtt
1036          * mappings on resume */
1037         struct list_head bound_list;
1038         /**
1039          * List of objects which are not bound to the GTT (thus
1040          * are idle and not used by the GPU) but still have
1041          * (presumably uncached) pages still attached.
1042          */
1043         struct list_head unbound_list;
1044
1045         /** Usable portion of the GTT for GEM */
1046         unsigned long stolen_base; /* limited to low memory (32-bit) */
1047
1048         /** PPGTT used for aliasing the PPGTT with the GTT */
1049         struct i915_hw_ppgtt *aliasing_ppgtt;
1050
1051         struct shrinker inactive_shrinker;
1052         bool shrinker_no_lock_stealing;
1053
1054         /** LRU list of objects with fence regs on them. */
1055         struct list_head fence_list;
1056
1057         /**
1058          * We leave the user IRQ off as much as possible,
1059          * but this means that requests will finish and never
1060          * be retired once the system goes idle. Set a timer to
1061          * fire periodically while the ring is running. When it
1062          * fires, go retire requests.
1063          */
1064         struct delayed_work retire_work;
1065
1066         /**
1067          * When we detect an idle GPU, we want to turn on
1068          * powersaving features. So once we see that there
1069          * are no more requests outstanding and no more
1070          * arrive within a small period of time, we fire
1071          * off the idle_work.
1072          */
1073         struct delayed_work idle_work;
1074
1075         /**
1076          * Are we in a non-interruptible section of code like
1077          * modesetting?
1078          */
1079         bool interruptible;
1080
1081         /**
1082          * Is the GPU currently considered idle, or busy executing userspace
1083          * requests?  Whilst idle, we attempt to power down the hardware and
1084          * display clocks. In order to reduce the effect on performance, there
1085          * is a slight delay before we do so.
1086          */
1087         bool busy;
1088
1089         /** Bit 6 swizzling required for X tiling */
1090         uint32_t bit_6_swizzle_x;
1091         /** Bit 6 swizzling required for Y tiling */
1092         uint32_t bit_6_swizzle_y;
1093
1094         /* storage for physical objects */
1095         struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1096
1097         /* accounting, useful for userland debugging */
1098         spinlock_t object_stat_lock;
1099         size_t object_memory;
1100         u32 object_count;
1101 };
1102
1103 struct drm_i915_error_state_buf {
1104         unsigned bytes;
1105         unsigned size;
1106         int err;
1107         u8 *buf;
1108         loff_t start;
1109         loff_t pos;
1110 };
1111
1112 struct i915_error_state_file_priv {
1113         struct drm_device *dev;
1114         struct drm_i915_error_state *error;
1115 };
1116
1117 struct i915_gpu_error {
1118         /* For hangcheck timer */
1119 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1120 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1121         /* Hang gpu twice in this window and your context gets banned */
1122 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1123
1124         struct timer_list hangcheck_timer;
1125
1126         /* For reset and error_state handling. */
1127         spinlock_t lock;
1128         /* Protected by the above dev->gpu_error.lock. */
1129         struct drm_i915_error_state *first_error;
1130         struct work_struct work;
1131
1132
1133         unsigned long missed_irq_rings;
1134
1135         /**
1136          * State variable controlling the reset flow and count
1137          *
1138          * This is a counter which gets incremented when reset is triggered,
1139          * and again when reset has been handled. So odd values (lowest bit set)
1140          * means that reset is in progress and even values that
1141          * (reset_counter >> 1):th reset was successfully completed.
1142          *
1143          * If reset is not completed succesfully, the I915_WEDGE bit is
1144          * set meaning that hardware is terminally sour and there is no
1145          * recovery. All waiters on the reset_queue will be woken when
1146          * that happens.
1147          *
1148          * This counter is used by the wait_seqno code to notice that reset
1149          * event happened and it needs to restart the entire ioctl (since most
1150          * likely the seqno it waited for won't ever signal anytime soon).
1151          *
1152          * This is important for lock-free wait paths, where no contended lock
1153          * naturally enforces the correct ordering between the bail-out of the
1154          * waiter and the gpu reset work code.
1155          */
1156         atomic_t reset_counter;
1157
1158 #define I915_RESET_IN_PROGRESS_FLAG     1
1159 #define I915_WEDGED                     (1 << 31)
1160
1161         /**
1162          * Waitqueue to signal when the reset has completed. Used by clients
1163          * that wait for dev_priv->mm.wedged to settle.
1164          */
1165         wait_queue_head_t reset_queue;
1166
1167         /* Userspace knobs for gpu hang simulation;
1168          * combines both a ring mask, and extra flags
1169          */
1170         u32 stop_rings;
1171 #define I915_STOP_RING_ALLOW_BAN       (1 << 31)
1172 #define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1173
1174         /* For missed irq/seqno simulation. */
1175         unsigned int test_irq_rings;
1176 };
1177
1178 enum modeset_restore {
1179         MODESET_ON_LID_OPEN,
1180         MODESET_DONE,
1181         MODESET_SUSPENDED,
1182 };
1183
1184 struct ddi_vbt_port_info {
1185         uint8_t hdmi_level_shift;
1186
1187         uint8_t supports_dvi:1;
1188         uint8_t supports_hdmi:1;
1189         uint8_t supports_dp:1;
1190 };
1191
1192 enum drrs_support_type {
1193         DRRS_NOT_SUPPORTED = 0,
1194         STATIC_DRRS_SUPPORT = 1,
1195         SEAMLESS_DRRS_SUPPORT = 2
1196 };
1197
1198 struct intel_vbt_data {
1199         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1200         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1201
1202         /* Feature bits */
1203         unsigned int int_tv_support:1;
1204         unsigned int lvds_dither:1;
1205         unsigned int lvds_vbt:1;
1206         unsigned int int_crt_support:1;
1207         unsigned int lvds_use_ssc:1;
1208         unsigned int display_clock_mode:1;
1209         unsigned int fdi_rx_polarity_inverted:1;
1210         int lvds_ssc_freq;
1211         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1212
1213         enum drrs_support_type drrs_type;
1214
1215         /* eDP */
1216         int edp_rate;
1217         int edp_lanes;
1218         int edp_preemphasis;
1219         int edp_vswing;
1220         bool edp_initialized;
1221         bool edp_support;
1222         int edp_bpp;
1223         struct edp_power_seq edp_pps;
1224
1225         struct {
1226                 u16 pwm_freq_hz;
1227                 bool present;
1228                 bool active_low_pwm;
1229         } backlight;
1230
1231         /* MIPI DSI */
1232         struct {
1233                 u16 panel_id;
1234                 struct mipi_config *config;
1235                 struct mipi_pps_data *pps;
1236                 u8 seq_version;
1237                 u32 size;
1238                 u8 *data;
1239                 u8 *sequence[MIPI_SEQ_MAX];
1240         } dsi;
1241
1242         int crt_ddc_pin;
1243
1244         int child_dev_num;
1245         union child_device_config *child_dev;
1246
1247         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1248 };
1249
1250 enum intel_ddb_partitioning {
1251         INTEL_DDB_PART_1_2,
1252         INTEL_DDB_PART_5_6, /* IVB+ */
1253 };
1254
1255 struct intel_wm_level {
1256         bool enable;
1257         uint32_t pri_val;
1258         uint32_t spr_val;
1259         uint32_t cur_val;
1260         uint32_t fbc_val;
1261 };
1262
1263 struct ilk_wm_values {
1264         uint32_t wm_pipe[3];
1265         uint32_t wm_lp[3];
1266         uint32_t wm_lp_spr[3];
1267         uint32_t wm_linetime[3];
1268         bool enable_fbc_wm;
1269         enum intel_ddb_partitioning partitioning;
1270 };
1271
1272 /*
1273  * This struct helps tracking the state needed for runtime PM, which puts the
1274  * device in PCI D3 state. Notice that when this happens, nothing on the
1275  * graphics device works, even register access, so we don't get interrupts nor
1276  * anything else.
1277  *
1278  * Every piece of our code that needs to actually touch the hardware needs to
1279  * either call intel_runtime_pm_get or call intel_display_power_get with the
1280  * appropriate power domain.
1281  *
1282  * Our driver uses the autosuspend delay feature, which means we'll only really
1283  * suspend if we stay with zero refcount for a certain amount of time. The
1284  * default value is currently very conservative (see intel_init_runtime_pm), but
1285  * it can be changed with the standard runtime PM files from sysfs.
1286  *
1287  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1288  * goes back to false exactly before we reenable the IRQs. We use this variable
1289  * to check if someone is trying to enable/disable IRQs while they're supposed
1290  * to be disabled. This shouldn't happen and we'll print some error messages in
1291  * case it happens.
1292  *
1293  * For more, read the Documentation/power/runtime_pm.txt.
1294  */
1295 struct i915_runtime_pm {
1296         bool suspended;
1297         bool irqs_disabled;
1298 };
1299
1300 enum intel_pipe_crc_source {
1301         INTEL_PIPE_CRC_SOURCE_NONE,
1302         INTEL_PIPE_CRC_SOURCE_PLANE1,
1303         INTEL_PIPE_CRC_SOURCE_PLANE2,
1304         INTEL_PIPE_CRC_SOURCE_PF,
1305         INTEL_PIPE_CRC_SOURCE_PIPE,
1306         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1307         INTEL_PIPE_CRC_SOURCE_TV,
1308         INTEL_PIPE_CRC_SOURCE_DP_B,
1309         INTEL_PIPE_CRC_SOURCE_DP_C,
1310         INTEL_PIPE_CRC_SOURCE_DP_D,
1311         INTEL_PIPE_CRC_SOURCE_AUTO,
1312         INTEL_PIPE_CRC_SOURCE_MAX,
1313 };
1314
1315 struct intel_pipe_crc_entry {
1316         uint32_t frame;
1317         uint32_t crc[5];
1318 };
1319
1320 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1321 struct intel_pipe_crc {
1322         spinlock_t lock;
1323         bool opened;            /* exclusive access to the result file */
1324         struct intel_pipe_crc_entry *entries;
1325         enum intel_pipe_crc_source source;
1326         int head, tail;
1327         wait_queue_head_t wq;
1328 };
1329
1330 struct drm_i915_private {
1331         struct drm_device *dev;
1332         struct kmem_cache *slab;
1333
1334         const struct intel_device_info info;
1335
1336         int relative_constants_mode;
1337
1338         void __iomem *regs;
1339
1340         struct intel_uncore uncore;
1341
1342         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1343
1344
1345         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1346          * controller on different i2c buses. */
1347         struct mutex gmbus_mutex;
1348
1349         /**
1350          * Base address of the gmbus and gpio block.
1351          */
1352         uint32_t gpio_mmio_base;
1353
1354         wait_queue_head_t gmbus_wait_queue;
1355
1356         struct pci_dev *bridge_dev;
1357         struct intel_ring_buffer ring[I915_NUM_RINGS];
1358         uint32_t last_seqno, next_seqno;
1359
1360         drm_dma_handle_t *status_page_dmah;
1361         struct resource mch_res;
1362
1363         /* protects the irq masks */
1364         spinlock_t irq_lock;
1365
1366         bool display_irqs_enabled;
1367
1368         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1369         struct pm_qos_request pm_qos;
1370
1371         /* DPIO indirect register protection */
1372         struct mutex dpio_lock;
1373
1374         /** Cached value of IMR to avoid reads in updating the bitfield */
1375         union {
1376                 u32 irq_mask;
1377                 u32 de_irq_mask[I915_MAX_PIPES];
1378         };
1379         u32 gt_irq_mask;
1380         u32 pm_irq_mask;
1381         u32 pm_rps_events;
1382         u32 pipestat_irq_mask[I915_MAX_PIPES];
1383
1384         struct work_struct hotplug_work;
1385         bool enable_hotplug_processing;
1386         struct {
1387                 unsigned long hpd_last_jiffies;
1388                 int hpd_cnt;
1389                 enum {
1390                         HPD_ENABLED = 0,
1391                         HPD_DISABLED = 1,
1392                         HPD_MARK_DISABLED = 2
1393                 } hpd_mark;
1394         } hpd_stats[HPD_NUM_PINS];
1395         u32 hpd_event_bits;
1396         struct timer_list hotplug_reenable_timer;
1397
1398         struct i915_fbc fbc;
1399         struct i915_drrs drrs;
1400         struct intel_opregion opregion;
1401         struct intel_vbt_data vbt;
1402
1403         /* overlay */
1404         struct intel_overlay *overlay;
1405
1406         /* backlight registers and fields in struct intel_panel */
1407         spinlock_t backlight_lock;
1408
1409         /* LVDS info */
1410         bool no_aux_handshake;
1411
1412         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1413         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1414         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1415
1416         unsigned int fsb_freq, mem_freq, is_ddr3;
1417         unsigned int vlv_cdclk_freq;
1418
1419         /**
1420          * wq - Driver workqueue for GEM.
1421          *
1422          * NOTE: Work items scheduled here are not allowed to grab any modeset
1423          * locks, for otherwise the flushing done in the pageflip code will
1424          * result in deadlocks.
1425          */
1426         struct workqueue_struct *wq;
1427
1428         /* Display functions */
1429         struct drm_i915_display_funcs display;
1430
1431         /* PCH chipset type */
1432         enum intel_pch pch_type;
1433         unsigned short pch_id;
1434
1435         unsigned long quirks;
1436
1437         enum modeset_restore modeset_restore;
1438         struct mutex modeset_restore_lock;
1439
1440         struct list_head vm_list; /* Global list of all address spaces */
1441         struct i915_gtt gtt; /* VM representing the global address space */
1442
1443         struct i915_gem_mm mm;
1444
1445         /* Kernel Modesetting */
1446
1447         struct sdvo_device_mapping sdvo_mappings[2];
1448
1449         struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1450         struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1451         wait_queue_head_t pending_flip_queue;
1452
1453 #ifdef CONFIG_DEBUG_FS
1454         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1455 #endif
1456
1457         int num_shared_dpll;
1458         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1459         struct intel_ddi_plls ddi_plls;
1460         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1461
1462         /* Reclocking support */
1463         bool render_reclock_avail;
1464         bool lvds_downclock_avail;
1465         /* indicates the reduced downclock for LVDS*/
1466         int lvds_downclock;
1467         u16 orig_clock;
1468
1469         bool mchbar_need_disable;
1470
1471         struct intel_l3_parity l3_parity;
1472
1473         /* Cannot be determined by PCIID. You must always read a register. */
1474         size_t ellc_size;
1475
1476         /* gen6+ rps state */
1477         struct intel_gen6_power_mgmt rps;
1478
1479         /* ilk-only ips/rps state. Everything in here is protected by the global
1480          * mchdev_lock in intel_pm.c */
1481         struct intel_ilk_power_mgmt ips;
1482
1483         struct i915_power_domains power_domains;
1484
1485         struct i915_psr psr;
1486
1487         struct i915_gpu_error gpu_error;
1488
1489         struct drm_i915_gem_object *vlv_pctx;
1490
1491 #ifdef CONFIG_DRM_I915_FBDEV
1492         /* list of fbdev register on this device */
1493         struct intel_fbdev *fbdev;
1494 #endif
1495
1496         /*
1497          * The console may be contended at resume, but we don't
1498          * want it to block on it.
1499          */
1500         struct work_struct console_resume_work;
1501
1502         struct drm_property *broadcast_rgb_property;
1503         struct drm_property *force_audio_property;
1504
1505         uint32_t hw_context_size;
1506         struct list_head context_list;
1507
1508         u32 fdi_rx_config;
1509
1510         u32 suspend_count;
1511         struct i915_suspend_saved_registers regfile;
1512         struct vlv_s0ix_state vlv_s0ix_state;
1513
1514         struct {
1515                 /*
1516                  * Raw watermark latency values:
1517                  * in 0.1us units for WM0,
1518                  * in 0.5us units for WM1+.
1519                  */
1520                 /* primary */
1521                 uint16_t pri_latency[5];
1522                 /* sprite */
1523                 uint16_t spr_latency[5];
1524                 /* cursor */
1525                 uint16_t cur_latency[5];
1526
1527                 /* current hardware state */
1528                 struct ilk_wm_values hw;
1529         } wm;
1530
1531         struct i915_runtime_pm pm;
1532
1533         /* Old dri1 support infrastructure, beware the dragons ya fools entering
1534          * here! */
1535         struct i915_dri1_state dri1;
1536         /* Old ums support infrastructure, same warning applies. */
1537         struct i915_ums_state ums;
1538         /* the indicator for dispatch video commands on two BSD rings */
1539         int ring_index;
1540 };
1541
1542 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1543 {
1544         return dev->dev_private;
1545 }
1546
1547 /* Iterate over initialised rings */
1548 #define for_each_ring(ring__, dev_priv__, i__) \
1549         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1550                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1551
1552 enum hdmi_force_audio {
1553         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
1554         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
1555         HDMI_AUDIO_AUTO,                /* trust EDID */
1556         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
1557 };
1558
1559 #define I915_GTT_OFFSET_NONE ((u32)-1)
1560
1561 struct drm_i915_gem_object_ops {
1562         /* Interface between the GEM object and its backing storage.
1563          * get_pages() is called once prior to the use of the associated set
1564          * of pages before to binding them into the GTT, and put_pages() is
1565          * called after we no longer need them. As we expect there to be
1566          * associated cost with migrating pages between the backing storage
1567          * and making them available for the GPU (e.g. clflush), we may hold
1568          * onto the pages after they are no longer referenced by the GPU
1569          * in case they may be used again shortly (for example migrating the
1570          * pages to a different memory domain within the GTT). put_pages()
1571          * will therefore most likely be called when the object itself is
1572          * being released or under memory pressure (where we attempt to
1573          * reap pages for the shrinker).
1574          */
1575         int (*get_pages)(struct drm_i915_gem_object *);
1576         void (*put_pages)(struct drm_i915_gem_object *);
1577 };
1578
1579 struct drm_i915_gem_object {
1580         struct drm_gem_object base;
1581
1582         const struct drm_i915_gem_object_ops *ops;
1583
1584         /** List of VMAs backed by this object */
1585         struct list_head vma_list;
1586
1587         /** Stolen memory for this object, instead of being backed by shmem. */
1588         struct drm_mm_node *stolen;
1589         struct list_head global_list;
1590
1591         struct list_head ring_list;
1592         /** Used in execbuf to temporarily hold a ref */
1593         struct list_head obj_exec_link;
1594
1595         /**
1596          * This is set if the object is on the active lists (has pending
1597          * rendering and so a non-zero seqno), and is not set if it i s on
1598          * inactive (ready to be unbound) list.
1599          */
1600         unsigned int active:1;
1601
1602         /**
1603          * This is set if the object has been written to since last bound
1604          * to the GTT
1605          */
1606         unsigned int dirty:1;
1607
1608         /**
1609          * Fence register bits (if any) for this object.  Will be set
1610          * as needed when mapped into the GTT.
1611          * Protected by dev->struct_mutex.
1612          */
1613         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1614
1615         /**
1616          * Advice: are the backing pages purgeable?
1617          */
1618         unsigned int madv:2;
1619
1620         /**
1621          * Current tiling mode for the object.
1622          */
1623         unsigned int tiling_mode:2;
1624         /**
1625          * Whether the tiling parameters for the currently associated fence
1626          * register have changed. Note that for the purposes of tracking
1627          * tiling changes we also treat the unfenced register, the register
1628          * slot that the object occupies whilst it executes a fenced
1629          * command (such as BLT on gen2/3), as a "fence".
1630          */
1631         unsigned int fence_dirty:1;
1632
1633         /**
1634          * Is the object at the current location in the gtt mappable and
1635          * fenceable? Used to avoid costly recalculations.
1636          */
1637         unsigned int map_and_fenceable:1;
1638
1639         /**
1640          * Whether the current gtt mapping needs to be mappable (and isn't just
1641          * mappable by accident). Track pin and fault separate for a more
1642          * accurate mappable working set.
1643          */
1644         unsigned int fault_mappable:1;
1645         unsigned int pin_mappable:1;
1646         unsigned int pin_display:1;
1647
1648         /*
1649          * Is the GPU currently using a fence to access this buffer,
1650          */
1651         unsigned int pending_fenced_gpu_access:1;
1652         unsigned int fenced_gpu_access:1;
1653
1654         unsigned int cache_level:3;
1655
1656         unsigned int has_aliasing_ppgtt_mapping:1;
1657         unsigned int has_global_gtt_mapping:1;
1658         unsigned int has_dma_mapping:1;
1659
1660         struct sg_table *pages;
1661         int pages_pin_count;
1662
1663         /* prime dma-buf support */
1664         void *dma_buf_vmapping;
1665         int vmapping_count;
1666
1667         struct intel_ring_buffer *ring;
1668
1669         /** Breadcrumb of last rendering to the buffer. */
1670         uint32_t last_read_seqno;
1671         uint32_t last_write_seqno;
1672         /** Breadcrumb of last fenced GPU access to the buffer. */
1673         uint32_t last_fenced_seqno;
1674
1675         /** Current tiling stride for the object, if it's tiled. */
1676         uint32_t stride;
1677
1678         /** References from framebuffers, locks out tiling changes. */
1679         unsigned long framebuffer_references;
1680
1681         /** Record of address bit 17 of each page at last unbind. */
1682         unsigned long *bit_17;
1683
1684         /** User space pin count and filp owning the pin */
1685         unsigned long user_pin_count;
1686         struct drm_file *pin_filp;
1687
1688         /** for phy allocated objects */
1689         struct drm_i915_gem_phys_object *phys_obj;
1690 };
1691
1692 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1693
1694 /**
1695  * Request queue structure.
1696  *
1697  * The request queue allows us to note sequence numbers that have been emitted
1698  * and may be associated with active buffers to be retired.
1699  *
1700  * By keeping this list, we can avoid having to do questionable
1701  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1702  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1703  */
1704 struct drm_i915_gem_request {
1705         /** On Which ring this request was generated */
1706         struct intel_ring_buffer *ring;
1707
1708         /** GEM sequence number associated with this request. */
1709         uint32_t seqno;
1710
1711         /** Position in the ringbuffer of the start of the request */
1712         u32 head;
1713
1714         /** Position in the ringbuffer of the end of the request */
1715         u32 tail;
1716
1717         /** Context related to this request */
1718         struct i915_hw_context *ctx;
1719
1720         /** Batch buffer related to this request if any */
1721         struct drm_i915_gem_object *batch_obj;
1722
1723         /** Time at which this request was emitted, in jiffies. */
1724         unsigned long emitted_jiffies;
1725
1726         /** global list entry for this request */
1727         struct list_head list;
1728
1729         struct drm_i915_file_private *file_priv;
1730         /** file_priv list entry for this request */
1731         struct list_head client_list;
1732 };
1733
1734 struct drm_i915_file_private {
1735         struct drm_i915_private *dev_priv;
1736         struct drm_file *file;
1737
1738         struct {
1739                 spinlock_t lock;
1740                 struct list_head request_list;
1741                 struct delayed_work idle_work;
1742         } mm;
1743         struct idr context_idr;
1744
1745         struct i915_hw_context *private_default_ctx;
1746         atomic_t rps_wait_boost;
1747         struct  intel_ring_buffer *bsd_ring;
1748 };
1749
1750 /*
1751  * A command that requires special handling by the command parser.
1752  */
1753 struct drm_i915_cmd_descriptor {
1754         /*
1755          * Flags describing how the command parser processes the command.
1756          *
1757          * CMD_DESC_FIXED: The command has a fixed length if this is set,
1758          *                 a length mask if not set
1759          * CMD_DESC_SKIP: The command is allowed but does not follow the
1760          *                standard length encoding for the opcode range in
1761          *                which it falls
1762          * CMD_DESC_REJECT: The command is never allowed
1763          * CMD_DESC_REGISTER: The command should be checked against the
1764          *                    register whitelist for the appropriate ring
1765          * CMD_DESC_MASTER: The command is allowed if the submitting process
1766          *                  is the DRM master
1767          */
1768         u32 flags;
1769 #define CMD_DESC_FIXED    (1<<0)
1770 #define CMD_DESC_SKIP     (1<<1)
1771 #define CMD_DESC_REJECT   (1<<2)
1772 #define CMD_DESC_REGISTER (1<<3)
1773 #define CMD_DESC_BITMASK  (1<<4)
1774 #define CMD_DESC_MASTER   (1<<5)
1775
1776         /*
1777          * The command's unique identification bits and the bitmask to get them.
1778          * This isn't strictly the opcode field as defined in the spec and may
1779          * also include type, subtype, and/or subop fields.
1780          */
1781         struct {
1782                 u32 value;
1783                 u32 mask;
1784         } cmd;
1785
1786         /*
1787          * The command's length. The command is either fixed length (i.e. does
1788          * not include a length field) or has a length field mask. The flag
1789          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1790          * a length mask. All command entries in a command table must include
1791          * length information.
1792          */
1793         union {
1794                 u32 fixed;
1795                 u32 mask;
1796         } length;
1797
1798         /*
1799          * Describes where to find a register address in the command to check
1800          * against the ring's register whitelist. Only valid if flags has the
1801          * CMD_DESC_REGISTER bit set.
1802          */
1803         struct {
1804                 u32 offset;
1805                 u32 mask;
1806         } reg;
1807
1808 #define MAX_CMD_DESC_BITMASKS 3
1809         /*
1810          * Describes command checks where a particular dword is masked and
1811          * compared against an expected value. If the command does not match
1812          * the expected value, the parser rejects it. Only valid if flags has
1813          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1814          * are valid.
1815          *
1816          * If the check specifies a non-zero condition_mask then the parser
1817          * only performs the check when the bits specified by condition_mask
1818          * are non-zero.
1819          */
1820         struct {
1821                 u32 offset;
1822                 u32 mask;
1823                 u32 expected;
1824                 u32 condition_offset;
1825                 u32 condition_mask;
1826         } bits[MAX_CMD_DESC_BITMASKS];
1827 };
1828
1829 /*
1830  * A table of commands requiring special handling by the command parser.
1831  *
1832  * Each ring has an array of tables. Each table consists of an array of command
1833  * descriptors, which must be sorted with command opcodes in ascending order.
1834  */
1835 struct drm_i915_cmd_table {
1836         const struct drm_i915_cmd_descriptor *table;
1837         int count;
1838 };
1839
1840 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1841
1842 #define IS_I830(dev)            ((dev)->pdev->device == 0x3577)
1843 #define IS_845G(dev)            ((dev)->pdev->device == 0x2562)
1844 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1845 #define IS_I865G(dev)           ((dev)->pdev->device == 0x2572)
1846 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1847 #define IS_I915GM(dev)          ((dev)->pdev->device == 0x2592)
1848 #define IS_I945G(dev)           ((dev)->pdev->device == 0x2772)
1849 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1850 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1851 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1852 #define IS_GM45(dev)            ((dev)->pdev->device == 0x2A42)
1853 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1854 #define IS_PINEVIEW_G(dev)      ((dev)->pdev->device == 0xa001)
1855 #define IS_PINEVIEW_M(dev)      ((dev)->pdev->device == 0xa011)
1856 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1857 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1858 #define IS_IRONLAKE_M(dev)      ((dev)->pdev->device == 0x0046)
1859 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1860 #define IS_IVB_GT1(dev)         ((dev)->pdev->device == 0x0156 || \
1861                                  (dev)->pdev->device == 0x0152 || \
1862                                  (dev)->pdev->device == 0x015a)
1863 #define IS_SNB_GT1(dev)         ((dev)->pdev->device == 0x0102 || \
1864                                  (dev)->pdev->device == 0x0106 || \
1865                                  (dev)->pdev->device == 0x010A)
1866 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1867 #define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1868 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1869 #define IS_BROADWELL(dev)       (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1870 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1871 #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
1872                                  ((dev)->pdev->device & 0xFF00) == 0x0C00)
1873 #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
1874                                  (((dev)->pdev->device & 0xf) == 0x2  || \
1875                                  ((dev)->pdev->device & 0xf) == 0x6 || \
1876                                  ((dev)->pdev->device & 0xf) == 0xe))
1877 #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
1878                                  ((dev)->pdev->device & 0xFF00) == 0x0A00)
1879 #define IS_ULT(dev)             (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1880 #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
1881                                  ((dev)->pdev->device & 0x00F0) == 0x0020)
1882 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1883
1884 /*
1885  * The genX designation typically refers to the render engine, so render
1886  * capability related checks should use IS_GEN, while display and other checks
1887  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1888  * chips, etc.).
1889  */
1890 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1891 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1892 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1893 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1894 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1895 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1896 #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
1897
1898 #define RENDER_RING             (1<<RCS)
1899 #define BSD_RING                (1<<VCS)
1900 #define BLT_RING                (1<<BCS)
1901 #define VEBOX_RING              (1<<VECS)
1902 #define BSD2_RING               (1<<VCS2)
1903 #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
1904 #define HAS_BSD2(dev)           (INTEL_INFO(dev)->ring_mask & BSD2_RING)
1905 #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
1906 #define HAS_VEBOX(dev)          (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1907 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1908 #define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
1909                                  to_i915(dev)->ellc_size)
1910 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1911
1912 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1913 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && \
1914                                  (!IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
1915 #define HAS_PPGTT(dev)          (INTEL_INFO(dev)->gen >= 7 \
1916                                  && !IS_GEN8(dev))
1917 #define USES_PPGTT(dev)         intel_enable_ppgtt(dev, false)
1918 #define USES_FULL_PPGTT(dev)    intel_enable_ppgtt(dev, true)
1919
1920 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1921 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1922
1923 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1924 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
1925 /*
1926  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1927  * even when in MSI mode. This results in spurious interrupt warnings if the
1928  * legacy irq no. is shared with another device. The kernel then disables that
1929  * interrupt source and so prevents the other device from working properly.
1930  */
1931 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1932 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1933
1934 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1935  * rows, which changed the alignment requirements and fence programming.
1936  */
1937 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1938                                                       IS_I915GM(dev)))
1939 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1940 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1941 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1942 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1943 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1944
1945 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1946 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1947 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1948
1949 #define HAS_IPS(dev)            (IS_ULT(dev) || IS_BROADWELL(dev))
1950
1951 #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
1952 #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
1953 #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
1954 #define HAS_RUNTIME_PM(dev)     (IS_GEN6(dev) || IS_HASWELL(dev) || \
1955                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
1956
1957 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
1958 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
1959 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
1960 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
1961 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
1962 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
1963
1964 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1965 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1966 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1967 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1968 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1969 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1970
1971 /* DPF == dynamic parity feature */
1972 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1973 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1974
1975 #define GT_FREQUENCY_MULTIPLIER 50
1976
1977 #include "i915_trace.h"
1978
1979 extern const struct drm_ioctl_desc i915_ioctls[];
1980 extern int i915_max_ioctl;
1981
1982 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1983 extern int i915_resume(struct drm_device *dev);
1984 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1985 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1986
1987 /* i915_params.c */
1988 struct i915_params {
1989         int modeset;
1990         int panel_ignore_lid;
1991         unsigned int powersave;
1992         int semaphores;
1993         unsigned int lvds_downclock;
1994         int lvds_channel_mode;
1995         int panel_use_ssc;
1996         int vbt_sdvo_panel_type;
1997         int enable_rc6;
1998         int enable_fbc;
1999         int enable_ppgtt;
2000         int enable_psr;
2001         unsigned int preliminary_hw_support;
2002         int disable_power_well;
2003         int enable_ips;
2004         int invert_brightness;
2005         int enable_cmd_parser;
2006         /* leave bools at the end to not create holes */
2007         bool enable_hangcheck;
2008         bool fastboot;
2009         bool prefault_disable;
2010         bool reset;
2011         bool disable_display;
2012         bool disable_vtd_wa;
2013 };
2014 extern struct i915_params i915 __read_mostly;
2015
2016                                 /* i915_dma.c */
2017 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2018 extern void i915_kernel_lost_context(struct drm_device * dev);
2019 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2020 extern int i915_driver_unload(struct drm_device *);
2021 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2022 extern void i915_driver_lastclose(struct drm_device * dev);
2023 extern void i915_driver_preclose(struct drm_device *dev,
2024                                  struct drm_file *file_priv);
2025 extern void i915_driver_postclose(struct drm_device *dev,
2026                                   struct drm_file *file_priv);
2027 extern int i915_driver_device_is_agp(struct drm_device * dev);
2028 #ifdef CONFIG_COMPAT
2029 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2030                               unsigned long arg);
2031 #endif
2032 extern int i915_emit_box(struct drm_device *dev,
2033                          struct drm_clip_rect *box,
2034                          int DR1, int DR4);
2035 extern int intel_gpu_reset(struct drm_device *dev);
2036 extern int i915_reset(struct drm_device *dev);
2037 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2038 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2039 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2040 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2041 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2042
2043 extern void intel_console_resume(struct work_struct *work);
2044
2045 /* i915_irq.c */
2046 void i915_queue_hangcheck(struct drm_device *dev);
2047 __printf(3, 4)
2048 void i915_handle_error(struct drm_device *dev, bool wedged,
2049                        const char *fmt, ...);
2050
2051 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2052                                                         int new_delay);
2053 extern void intel_irq_init(struct drm_device *dev);
2054 extern void intel_hpd_init(struct drm_device *dev);
2055
2056 extern void intel_uncore_sanitize(struct drm_device *dev);
2057 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2058 extern void intel_uncore_init(struct drm_device *dev);
2059 extern void intel_uncore_check_errors(struct drm_device *dev);
2060 extern void intel_uncore_fini(struct drm_device *dev);
2061
2062 void
2063 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2064                      u32 status_mask);
2065
2066 void
2067 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2068                       u32 status_mask);
2069
2070 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2071 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2072
2073 /* i915_gem.c */
2074 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2075                         struct drm_file *file_priv);
2076 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2077                           struct drm_file *file_priv);
2078 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2079                          struct drm_file *file_priv);
2080 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2081                           struct drm_file *file_priv);
2082 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2083                         struct drm_file *file_priv);
2084 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2085                         struct drm_file *file_priv);
2086 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2087                               struct drm_file *file_priv);
2088 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2089                              struct drm_file *file_priv);
2090 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2091                         struct drm_file *file_priv);
2092 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2093                          struct drm_file *file_priv);
2094 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2095                        struct drm_file *file_priv);
2096 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2097                          struct drm_file *file_priv);
2098 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2099                         struct drm_file *file_priv);
2100 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2101                                struct drm_file *file);
2102 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2103                                struct drm_file *file);
2104 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2105                             struct drm_file *file_priv);
2106 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2107                            struct drm_file *file_priv);
2108 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2109                            struct drm_file *file_priv);
2110 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2111                            struct drm_file *file_priv);
2112 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2113                         struct drm_file *file_priv);
2114 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2115                         struct drm_file *file_priv);
2116 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2117                                 struct drm_file *file_priv);
2118 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2119                         struct drm_file *file_priv);
2120 void i915_gem_load(struct drm_device *dev);
2121 void *i915_gem_object_alloc(struct drm_device *dev);
2122 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2123 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2124                          const struct drm_i915_gem_object_ops *ops);
2125 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2126                                                   size_t size);
2127 void i915_init_vm(struct drm_i915_private *dev_priv,
2128                   struct i915_address_space *vm);
2129 void i915_gem_free_object(struct drm_gem_object *obj);
2130 void i915_gem_vma_destroy(struct i915_vma *vma);
2131
2132 #define PIN_MAPPABLE 0x1
2133 #define PIN_NONBLOCK 0x2
2134 #define PIN_GLOBAL 0x4
2135 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2136                                      struct i915_address_space *vm,
2137                                      uint32_t alignment,
2138                                      unsigned flags);
2139 int __must_check i915_vma_unbind(struct i915_vma *vma);
2140 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2141 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2142 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2143 void i915_gem_lastclose(struct drm_device *dev);
2144
2145 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2146                                     int *needs_clflush);
2147
2148 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2149 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2150 {
2151         struct sg_page_iter sg_iter;
2152
2153         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2154                 return sg_page_iter_page(&sg_iter);
2155
2156         return NULL;
2157 }
2158 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2159 {
2160         BUG_ON(obj->pages == NULL);
2161         obj->pages_pin_count++;
2162 }
2163 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2164 {
2165         BUG_ON(obj->pages_pin_count == 0);
2166         obj->pages_pin_count--;
2167 }
2168
2169 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2170 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2171                          struct intel_ring_buffer *to);
2172 void i915_vma_move_to_active(struct i915_vma *vma,
2173                              struct intel_ring_buffer *ring);
2174 int i915_gem_dumb_create(struct drm_file *file_priv,
2175                          struct drm_device *dev,
2176                          struct drm_mode_create_dumb *args);
2177 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2178                       uint32_t handle, uint64_t *offset);
2179 /**
2180  * Returns true if seq1 is later than seq2.
2181  */
2182 static inline bool
2183 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2184 {
2185         return (int32_t)(seq1 - seq2) >= 0;
2186 }
2187
2188 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2189 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2190 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2191 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2192
2193 static inline bool
2194 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2195 {
2196         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2197                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2198                 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2199                 return true;
2200         } else
2201                 return false;
2202 }
2203
2204 static inline void
2205 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2206 {
2207         if (obj->fence_reg != I915_FENCE_REG_NONE) {
2208                 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2209                 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2210                 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2211         }
2212 }
2213
2214 struct drm_i915_gem_request *
2215 i915_gem_find_active_request(struct intel_ring_buffer *ring);
2216
2217 bool i915_gem_retire_requests(struct drm_device *dev);
2218 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2219 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2220                                       bool interruptible);
2221 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2222 {
2223         return unlikely(atomic_read(&error->reset_counter)
2224                         & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2225 }
2226
2227 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2228 {
2229         return atomic_read(&error->reset_counter) & I915_WEDGED;
2230 }
2231
2232 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2233 {
2234         return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2235 }
2236
2237 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2238 {
2239         return dev_priv->gpu_error.stop_rings == 0 ||
2240                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2241 }
2242
2243 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2244 {
2245         return dev_priv->gpu_error.stop_rings == 0 ||
2246                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2247 }
2248
2249 void i915_gem_reset(struct drm_device *dev);
2250 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2251 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2252 int __must_check i915_gem_init(struct drm_device *dev);
2253 int __must_check i915_gem_init_hw(struct drm_device *dev);
2254 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2255 void i915_gem_init_swizzling(struct drm_device *dev);
2256 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2257 int __must_check i915_gpu_idle(struct drm_device *dev);
2258 int __must_check i915_gem_suspend(struct drm_device *dev);
2259 int __i915_add_request(struct intel_ring_buffer *ring,
2260                        struct drm_file *file,
2261                        struct drm_i915_gem_object *batch_obj,
2262                        u32 *seqno);
2263 #define i915_add_request(ring, seqno) \
2264         __i915_add_request(ring, NULL, NULL, seqno)
2265 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2266                                  uint32_t seqno);
2267 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2268 int __must_check
2269 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2270                                   bool write);
2271 int __must_check
2272 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2273 int __must_check
2274 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2275                                      u32 alignment,
2276                                      struct intel_ring_buffer *pipelined);
2277 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2278 int i915_gem_attach_phys_object(struct drm_device *dev,
2279                                 struct drm_i915_gem_object *obj,
2280                                 int id,
2281                                 int align);
2282 void i915_gem_detach_phys_object(struct drm_device *dev,
2283                                  struct drm_i915_gem_object *obj);
2284 void i915_gem_free_all_phys_object(struct drm_device *dev);
2285 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2286 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2287
2288 uint32_t
2289 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2290 uint32_t
2291 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2292                             int tiling_mode, bool fenced);
2293
2294 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2295                                     enum i915_cache_level cache_level);
2296
2297 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2298                                 struct dma_buf *dma_buf);
2299
2300 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2301                                 struct drm_gem_object *gem_obj, int flags);
2302
2303 void i915_gem_restore_fences(struct drm_device *dev);
2304
2305 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2306                                   struct i915_address_space *vm);
2307 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2308 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2309                         struct i915_address_space *vm);
2310 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2311                                 struct i915_address_space *vm);
2312 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2313                                      struct i915_address_space *vm);
2314 struct i915_vma *
2315 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2316                                   struct i915_address_space *vm);
2317
2318 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2319 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2320         struct i915_vma *vma;
2321         list_for_each_entry(vma, &obj->vma_list, vma_link)
2322                 if (vma->pin_count > 0)
2323                         return true;
2324         return false;
2325 }
2326
2327 /* Some GGTT VM helpers */
2328 #define obj_to_ggtt(obj) \
2329         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2330 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2331 {
2332         struct i915_address_space *ggtt =
2333                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2334         return vm == ggtt;
2335 }
2336
2337 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2338 {
2339         return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2340 }
2341
2342 static inline unsigned long
2343 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2344 {
2345         return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2346 }
2347
2348 static inline unsigned long
2349 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2350 {
2351         return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2352 }
2353
2354 static inline int __must_check
2355 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2356                       uint32_t alignment,
2357                       unsigned flags)
2358 {
2359         return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2360 }
2361
2362 static inline int
2363 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2364 {
2365         return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2366 }
2367
2368 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2369
2370 /* i915_gem_context.c */
2371 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2372 int __must_check i915_gem_context_init(struct drm_device *dev);
2373 void i915_gem_context_fini(struct drm_device *dev);
2374 void i915_gem_context_reset(struct drm_device *dev);
2375 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2376 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2377 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2378 int i915_switch_context(struct intel_ring_buffer *ring,
2379                         struct i915_hw_context *to);
2380 struct i915_hw_context *
2381 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2382 void i915_gem_context_free(struct kref *ctx_ref);
2383 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2384 {
2385         kref_get(&ctx->ref);
2386 }
2387
2388 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2389 {
2390         kref_put(&ctx->ref, i915_gem_context_free);
2391 }
2392
2393 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2394 {
2395         return c->id == DEFAULT_CONTEXT_ID;
2396 }
2397
2398 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2399                                   struct drm_file *file);
2400 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2401                                    struct drm_file *file);
2402
2403 /* i915_gem_evict.c */
2404 int __must_check i915_gem_evict_something(struct drm_device *dev,
2405                                           struct i915_address_space *vm,
2406                                           int min_size,
2407                                           unsigned alignment,
2408                                           unsigned cache_level,
2409                                           unsigned flags);
2410 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2411 int i915_gem_evict_everything(struct drm_device *dev);
2412
2413 /* belongs in i915_gem_gtt.h */
2414 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2415 {
2416         if (INTEL_INFO(dev)->gen < 6)
2417                 intel_gtt_chipset_flush();
2418 }
2419
2420 /* i915_gem_stolen.c */
2421 int i915_gem_init_stolen(struct drm_device *dev);
2422 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2423 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2424 void i915_gem_cleanup_stolen(struct drm_device *dev);
2425 struct drm_i915_gem_object *
2426 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2427 struct drm_i915_gem_object *
2428 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2429                                                u32 stolen_offset,
2430                                                u32 gtt_offset,
2431                                                u32 size);
2432 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2433
2434 /* i915_gem_tiling.c */
2435 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2436 {
2437         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2438
2439         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2440                 obj->tiling_mode != I915_TILING_NONE;
2441 }
2442
2443 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2444 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2445 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2446
2447 /* i915_gem_debug.c */
2448 #if WATCH_LISTS
2449 int i915_verify_lists(struct drm_device *dev);
2450 #else
2451 #define i915_verify_lists(dev) 0
2452 #endif
2453
2454 /* i915_debugfs.c */
2455 int i915_debugfs_init(struct drm_minor *minor);
2456 void i915_debugfs_cleanup(struct drm_minor *minor);
2457 #ifdef CONFIG_DEBUG_FS
2458 void intel_display_crc_init(struct drm_device *dev);
2459 #else
2460 static inline void intel_display_crc_init(struct drm_device *dev) {}
2461 #endif
2462
2463 /* i915_gpu_error.c */
2464 __printf(2, 3)
2465 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2466 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2467                             const struct i915_error_state_file_priv *error);
2468 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2469                               size_t count, loff_t pos);
2470 static inline void i915_error_state_buf_release(
2471         struct drm_i915_error_state_buf *eb)
2472 {
2473         kfree(eb->buf);
2474 }
2475 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2476                               const char *error_msg);
2477 void i915_error_state_get(struct drm_device *dev,
2478                           struct i915_error_state_file_priv *error_priv);
2479 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2480 void i915_destroy_error_state(struct drm_device *dev);
2481
2482 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2483 const char *i915_cache_level_str(int type);
2484
2485 /* i915_cmd_parser.c */
2486 int i915_cmd_parser_get_version(void);
2487 int i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2488 void i915_cmd_parser_fini_ring(struct intel_ring_buffer *ring);
2489 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2490 int i915_parse_cmds(struct intel_ring_buffer *ring,
2491                     struct drm_i915_gem_object *batch_obj,
2492                     u32 batch_start_offset,
2493                     bool is_master);
2494
2495 /* i915_suspend.c */
2496 extern int i915_save_state(struct drm_device *dev);
2497 extern int i915_restore_state(struct drm_device *dev);
2498
2499 /* i915_ums.c */
2500 void i915_save_display_reg(struct drm_device *dev);
2501 void i915_restore_display_reg(struct drm_device *dev);
2502
2503 /* i915_sysfs.c */
2504 void i915_setup_sysfs(struct drm_device *dev_priv);
2505 void i915_teardown_sysfs(struct drm_device *dev_priv);
2506
2507 /* intel_i2c.c */
2508 extern int intel_setup_gmbus(struct drm_device *dev);
2509 extern void intel_teardown_gmbus(struct drm_device *dev);
2510 static inline bool intel_gmbus_is_port_valid(unsigned port)
2511 {
2512         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2513 }
2514
2515 extern struct i2c_adapter *intel_gmbus_get_adapter(
2516                 struct drm_i915_private *dev_priv, unsigned port);
2517 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2518 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2519 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2520 {
2521         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2522 }
2523 extern void intel_i2c_reset(struct drm_device *dev);
2524
2525 /* intel_opregion.c */
2526 struct intel_encoder;
2527 #ifdef CONFIG_ACPI
2528 extern int intel_opregion_setup(struct drm_device *dev);
2529 extern void intel_opregion_init(struct drm_device *dev);
2530 extern void intel_opregion_fini(struct drm_device *dev);
2531 extern void intel_opregion_asle_intr(struct drm_device *dev);
2532 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2533                                          bool enable);
2534 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2535                                          pci_power_t state);
2536 #else
2537 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2538 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2539 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2540 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2541 static inline int
2542 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2543 {
2544         return 0;
2545 }
2546 static inline int
2547 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2548 {
2549         return 0;
2550 }
2551 #endif
2552
2553 /* intel_acpi.c */
2554 #ifdef CONFIG_ACPI
2555 extern void intel_register_dsm_handler(void);
2556 extern void intel_unregister_dsm_handler(void);
2557 #else
2558 static inline void intel_register_dsm_handler(void) { return; }
2559 static inline void intel_unregister_dsm_handler(void) { return; }
2560 #endif /* CONFIG_ACPI */
2561
2562 /* modesetting */
2563 extern void intel_modeset_init_hw(struct drm_device *dev);
2564 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2565 extern void intel_modeset_init(struct drm_device *dev);
2566 extern void intel_modeset_gem_init(struct drm_device *dev);
2567 extern void intel_modeset_cleanup(struct drm_device *dev);
2568 extern void intel_connector_unregister(struct intel_connector *);
2569 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2570 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2571                                          bool force_restore);
2572 extern void i915_redisable_vga(struct drm_device *dev);
2573 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2574 extern bool intel_fbc_enabled(struct drm_device *dev);
2575 extern void intel_disable_fbc(struct drm_device *dev);
2576 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2577 extern void intel_init_pch_refclk(struct drm_device *dev);
2578 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2579 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2580 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2581 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2582 extern void intel_detect_pch(struct drm_device *dev);
2583 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2584 extern int intel_enable_rc6(const struct drm_device *dev);
2585
2586 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2587 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2588                         struct drm_file *file);
2589 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2590                                struct drm_file *file);
2591
2592 /* overlay */
2593 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2594 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2595                                             struct intel_overlay_error_state *error);
2596
2597 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2598 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2599                                             struct drm_device *dev,
2600                                             struct intel_display_error_state *error);
2601
2602 /* On SNB platform, before reading ring registers forcewake bit
2603  * must be set to prevent GT core from power down and stale values being
2604  * returned.
2605  */
2606 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2607 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2608 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2609
2610 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2611 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2612
2613 /* intel_sideband.c */
2614 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2615 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2616 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2617 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2618 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2619 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2620 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2621 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2622 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2623 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2624 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2625 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2626 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2627 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2628 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2629 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2630                    enum intel_sbi_destination destination);
2631 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2632                      enum intel_sbi_destination destination);
2633 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2634 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2635
2636 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2637 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2638
2639 #define FORCEWAKE_RENDER        (1 << 0)
2640 #define FORCEWAKE_MEDIA         (1 << 1)
2641 #define FORCEWAKE_ALL           (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2642
2643
2644 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2645 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2646
2647 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2648 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2649 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2650 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2651
2652 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2653 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2654 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2655 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2656
2657 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2658  * will be implemented using 2 32-bit writes in an arbitrary order with
2659  * an arbitrary delay between them. This can cause the hardware to
2660  * act upon the intermediate value, possibly leading to corruption and
2661  * machine death. You have been warned.
2662  */
2663 #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2664 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2665
2666 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
2667                 u32 upper = I915_READ(upper_reg);                       \
2668                 u32 lower = I915_READ(lower_reg);                       \
2669                 u32 tmp = I915_READ(upper_reg);                         \
2670                 if (upper != tmp) {                                     \
2671                         upper = tmp;                                    \
2672                         lower = I915_READ(lower_reg);                   \
2673                         WARN_ON(I915_READ(upper_reg) != upper);         \
2674                 }                                                       \
2675                 (u64)upper << 32 | lower; })
2676
2677 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
2678 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
2679
2680 /* "Broadcast RGB" property */
2681 #define INTEL_BROADCAST_RGB_AUTO 0
2682 #define INTEL_BROADCAST_RGB_FULL 1
2683 #define INTEL_BROADCAST_RGB_LIMITED 2
2684
2685 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2686 {
2687         if (HAS_PCH_SPLIT(dev))
2688                 return CPU_VGACNTRL;
2689         else if (IS_VALLEYVIEW(dev))
2690                 return VLV_VGACNTRL;
2691         else
2692                 return VGACNTRL;
2693 }
2694
2695 static inline void __user *to_user_ptr(u64 address)
2696 {
2697         return (void __user *)(uintptr_t)address;
2698 }
2699
2700 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2701 {
2702         unsigned long j = msecs_to_jiffies(m);
2703
2704         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2705 }
2706
2707 static inline unsigned long
2708 timespec_to_jiffies_timeout(const struct timespec *value)
2709 {
2710         unsigned long j = timespec_to_jiffies(value);
2711
2712         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2713 }
2714
2715 /*
2716  * If you need to wait X milliseconds between events A and B, but event B
2717  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2718  * when event A happened, then just before event B you call this function and
2719  * pass the timestamp as the first argument, and X as the second argument.
2720  */
2721 static inline void
2722 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2723 {
2724         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2725
2726         /*
2727          * Don't re-read the value of "jiffies" every time since it may change
2728          * behind our back and break the math.
2729          */
2730         tmp_jiffies = jiffies;
2731         target_jiffies = timestamp_jiffies +
2732                          msecs_to_jiffies_timeout(to_wait_ms);
2733
2734         if (time_after(target_jiffies, tmp_jiffies)) {
2735                 remaining_jiffies = target_jiffies - tmp_jiffies;
2736                 while (remaining_jiffies)
2737                         remaining_jiffies =
2738                             schedule_timeout_uninterruptible(remaining_jiffies);
2739         }
2740 }
2741
2742 #endif