1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
= POWER_DOMAIN_TRANSCODER_A
+ 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
112 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct intel_pch_pll
{
136 int refcount
; /* count of number of CRTCs sharing this PLL */
137 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
138 bool on
; /* is the PLL actually active? Disabled during modeset */
143 #define I915_NUM_PLLS 2
145 /* Used by dp and fdi links */
146 struct intel_link_m_n
{
154 void intel_link_compute_m_n(int bpp
, int nlanes
,
155 int pixel_clock
, int link_clock
,
156 struct intel_link_m_n
*m_n
);
158 struct intel_ddi_plls
{
164 /* Interface history:
167 * 1.2: Add Power Management
168 * 1.3: Add vblank support
169 * 1.4: Fix cmdbuffer path, add heap destroy
170 * 1.5: Add vblank pipe configuration
171 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
172 * - Support vertical blank on secondary display pipe
174 #define DRIVER_MAJOR 1
175 #define DRIVER_MINOR 6
176 #define DRIVER_PATCHLEVEL 0
178 #define WATCH_COHERENCY 0
179 #define WATCH_LISTS 0
182 #define I915_GEM_PHYS_CURSOR_0 1
183 #define I915_GEM_PHYS_CURSOR_1 2
184 #define I915_GEM_PHYS_OVERLAY_REGS 3
185 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
187 struct drm_i915_gem_phys_object
{
189 struct page
**page_list
;
190 drm_dma_handle_t
*handle
;
191 struct drm_i915_gem_object
*cur_obj
;
194 struct opregion_header
;
195 struct opregion_acpi
;
196 struct opregion_swsci
;
197 struct opregion_asle
;
198 struct drm_i915_private
;
200 struct intel_opregion
{
201 struct opregion_header __iomem
*header
;
202 struct opregion_acpi __iomem
*acpi
;
203 struct opregion_swsci __iomem
*swsci
;
204 struct opregion_asle __iomem
*asle
;
206 u32 __iomem
*lid_state
;
208 #define OPREGION_SIZE (8*1024)
210 struct intel_overlay
;
211 struct intel_overlay_error_state
;
213 struct drm_i915_master_private
{
214 drm_local_map_t
*sarea
;
215 struct _drm_i915_sarea
*sarea_priv
;
217 #define I915_FENCE_REG_NONE -1
218 #define I915_MAX_NUM_FENCES 32
219 /* 32 fences + sign bit for FENCE_REG_NONE */
220 #define I915_MAX_NUM_FENCE_BITS 6
222 struct drm_i915_fence_reg
{
223 struct list_head lru_list
;
224 struct drm_i915_gem_object
*obj
;
228 struct sdvo_device_mapping
{
237 struct intel_display_error_state
;
239 struct drm_i915_error_state
{
247 bool waiting
[I915_NUM_RINGS
];
248 u32 pipestat
[I915_MAX_PIPES
];
249 u32 tail
[I915_NUM_RINGS
];
250 u32 head
[I915_NUM_RINGS
];
251 u32 ctl
[I915_NUM_RINGS
];
252 u32 ipeir
[I915_NUM_RINGS
];
253 u32 ipehr
[I915_NUM_RINGS
];
254 u32 instdone
[I915_NUM_RINGS
];
255 u32 acthd
[I915_NUM_RINGS
];
256 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
257 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
258 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
259 /* our own tracking of ring head and tail */
260 u32 cpu_ring_head
[I915_NUM_RINGS
];
261 u32 cpu_ring_tail
[I915_NUM_RINGS
];
262 u32 error
; /* gen6+ */
263 u32 err_int
; /* gen7 */
264 u32 instpm
[I915_NUM_RINGS
];
265 u32 instps
[I915_NUM_RINGS
];
266 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
267 u32 seqno
[I915_NUM_RINGS
];
269 u32 fault_reg
[I915_NUM_RINGS
];
271 u32 faddr
[I915_NUM_RINGS
];
272 u64 fence
[I915_MAX_NUM_FENCES
];
274 struct drm_i915_error_ring
{
275 struct drm_i915_error_object
{
279 } *ringbuffer
, *batchbuffer
, *ctx
;
280 struct drm_i915_error_request
{
286 } ring
[I915_NUM_RINGS
];
287 struct drm_i915_error_buffer
{
294 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
301 } *active_bo
, *pinned_bo
;
302 u32 active_bo_count
, pinned_bo_count
;
303 struct intel_overlay_error_state
*overlay
;
304 struct intel_display_error_state
*display
;
307 struct intel_crtc_config
;
312 struct drm_i915_display_funcs
{
313 bool (*fbc_enabled
)(struct drm_device
*dev
);
314 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
315 void (*disable_fbc
)(struct drm_device
*dev
);
316 int (*get_display_clock_speed
)(struct drm_device
*dev
);
317 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
319 * find_dpll() - Find the best values for the PLL
320 * @limit: limits for the PLL
321 * @crtc: current CRTC
322 * @target: target frequency in kHz
323 * @refclk: reference clock frequency in kHz
324 * @match_clock: if provided, @best_clock P divider must
325 * match the P divider from @match_clock
326 * used for LVDS downclocking
327 * @best_clock: best PLL values found
329 * Returns true on success, false on failure.
331 bool (*find_dpll
)(const struct intel_limit
*limit
,
332 struct drm_crtc
*crtc
,
333 int target
, int refclk
,
334 struct dpll
*match_clock
,
335 struct dpll
*best_clock
);
336 void (*update_wm
)(struct drm_device
*dev
);
337 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
338 uint32_t sprite_width
, int pixel_size
,
340 void (*modeset_global_resources
)(struct drm_device
*dev
);
341 /* Returns the active state of the crtc, and if the crtc is active,
342 * fills out the pipe-config with the hw state. */
343 bool (*get_pipe_config
)(struct intel_crtc
*,
344 struct intel_crtc_config
*);
345 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
347 struct drm_framebuffer
*old_fb
);
348 void (*crtc_enable
)(struct drm_crtc
*crtc
);
349 void (*crtc_disable
)(struct drm_crtc
*crtc
);
350 void (*off
)(struct drm_crtc
*crtc
);
351 void (*write_eld
)(struct drm_connector
*connector
,
352 struct drm_crtc
*crtc
);
353 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
354 void (*init_clock_gating
)(struct drm_device
*dev
);
355 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
356 struct drm_framebuffer
*fb
,
357 struct drm_i915_gem_object
*obj
);
358 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
360 void (*hpd_irq_setup
)(struct drm_device
*dev
);
361 /* clock updates for mode set */
363 /* render clock increase/decrease */
364 /* display clock increase/decrease */
365 /* pll clock increase/decrease */
368 struct drm_i915_gt_funcs
{
369 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
370 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
373 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
374 func(is_mobile) sep \
377 func(is_i945gm) sep \
379 func(need_gfx_hws) sep \
381 func(is_pineview) sep \
382 func(is_broadwater) sep \
383 func(is_crestline) sep \
384 func(is_ivybridge) sep \
385 func(is_valleyview) sep \
386 func(is_haswell) sep \
387 func(has_force_wake) sep \
389 func(has_pipe_cxsr) sep \
390 func(has_hotplug) sep \
391 func(cursor_needs_physical) sep \
392 func(has_overlay) sep \
393 func(overlay_needs_physical) sep \
394 func(supports_tv) sep \
395 func(has_bsd_ring) sep \
396 func(has_blt_ring) sep \
397 func(has_vebox_ring) sep \
402 #define DEFINE_FLAG(name) u8 name:1
403 #define SEP_SEMICOLON ;
405 struct intel_device_info
{
406 u32 display_mmio_offset
;
409 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
415 enum i915_cache_level
{
418 I915_CACHE_LLC_MLC
, /* gen6+, in docs at least! */
421 typedef uint32_t gen6_gtt_pte_t
;
423 /* The Graphics Translation Table is the way in which GEN hardware translates a
424 * Graphics Virtual Address into a Physical Address. In addition to the normal
425 * collateral associated with any va->pa translations GEN hardware also has a
426 * portion of the GTT which can be mapped by the CPU and remain both coherent
427 * and correct (in cases like swizzling). That region is referred to as GMADR in
431 unsigned long start
; /* Start offset of used GTT */
432 size_t total
; /* Total size GTT can map */
433 size_t stolen_size
; /* Total size of stolen memory */
435 unsigned long mappable_end
; /* End offset that we can CPU map */
436 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
437 phys_addr_t mappable_base
; /* PA of our GMADR */
439 /** "Graphics Stolen Memory" holds the global PTEs */
443 dma_addr_t scratch_page_dma
;
444 struct page
*scratch_page
;
447 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
448 size_t *stolen
, phys_addr_t
*mappable_base
,
449 unsigned long *mappable_end
);
450 void (*gtt_remove
)(struct drm_device
*dev
);
451 void (*gtt_clear_range
)(struct drm_device
*dev
,
452 unsigned int first_entry
,
453 unsigned int num_entries
);
454 void (*gtt_insert_entries
)(struct drm_device
*dev
,
456 unsigned int pg_start
,
457 enum i915_cache_level cache_level
);
458 gen6_gtt_pte_t (*pte_encode
)(struct drm_device
*dev
,
460 enum i915_cache_level level
);
462 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
464 #define I915_PPGTT_PD_ENTRIES 512
465 #define I915_PPGTT_PT_ENTRIES 1024
466 struct i915_hw_ppgtt
{
467 struct drm_device
*dev
;
468 unsigned num_pd_entries
;
469 struct page
**pt_pages
;
471 dma_addr_t
*pt_dma_addr
;
472 dma_addr_t scratch_page_dma_addr
;
474 /* pte functions, mirroring the interface of the global gtt. */
475 void (*clear_range
)(struct i915_hw_ppgtt
*ppgtt
,
476 unsigned int first_entry
,
477 unsigned int num_entries
);
478 void (*insert_entries
)(struct i915_hw_ppgtt
*ppgtt
,
480 unsigned int pg_start
,
481 enum i915_cache_level cache_level
);
482 gen6_gtt_pte_t (*pte_encode
)(struct drm_device
*dev
,
484 enum i915_cache_level level
);
485 int (*enable
)(struct drm_device
*dev
);
486 void (*cleanup
)(struct i915_hw_ppgtt
*ppgtt
);
490 /* This must match up with the value previously used for execbuf2.rsvd1. */
491 #define DEFAULT_CONTEXT_ID 0
492 struct i915_hw_context
{
496 struct drm_i915_file_private
*file_priv
;
497 struct intel_ring_buffer
*ring
;
498 struct drm_i915_gem_object
*obj
;
502 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
503 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
504 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
505 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
506 FBC_BAD_PLANE
, /* fbc not supported on plane */
507 FBC_NOT_TILED
, /* buffer not tiled */
508 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
513 PCH_NONE
= 0, /* No PCH present */
514 PCH_IBX
, /* Ibexpeak PCH */
515 PCH_CPT
, /* Cougarpoint PCH */
516 PCH_LPT
, /* Lynxpoint PCH */
520 enum intel_sbi_destination
{
525 #define QUIRK_PIPEA_FORCE (1<<0)
526 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
527 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
530 struct intel_fbc_work
;
533 struct i2c_adapter adapter
;
537 struct i2c_algo_bit_data bit_algo
;
538 struct drm_i915_private
*dev_priv
;
541 struct i915_suspend_saved_registers
{
562 u32 saveTRANS_HTOTAL_A
;
563 u32 saveTRANS_HBLANK_A
;
564 u32 saveTRANS_HSYNC_A
;
565 u32 saveTRANS_VTOTAL_A
;
566 u32 saveTRANS_VBLANK_A
;
567 u32 saveTRANS_VSYNC_A
;
575 u32 savePFIT_PGM_RATIOS
;
576 u32 saveBLC_HIST_CTL
;
578 u32 saveBLC_PWM_CTL2
;
579 u32 saveBLC_CPU_PWM_CTL
;
580 u32 saveBLC_CPU_PWM_CTL2
;
593 u32 saveTRANS_HTOTAL_B
;
594 u32 saveTRANS_HBLANK_B
;
595 u32 saveTRANS_HSYNC_B
;
596 u32 saveTRANS_VTOTAL_B
;
597 u32 saveTRANS_VBLANK_B
;
598 u32 saveTRANS_VSYNC_B
;
612 u32 savePP_ON_DELAYS
;
613 u32 savePP_OFF_DELAYS
;
621 u32 savePFIT_CONTROL
;
622 u32 save_palette_a
[256];
623 u32 save_palette_b
[256];
624 u32 saveDPFC_CB_BASE
;
625 u32 saveFBC_CFB_BASE
;
628 u32 saveFBC_CONTROL2
;
638 u32 saveCACHE_MODE_0
;
639 u32 saveMI_ARB_STATE
;
650 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
661 u32 savePIPEA_GMCH_DATA_M
;
662 u32 savePIPEB_GMCH_DATA_M
;
663 u32 savePIPEA_GMCH_DATA_N
;
664 u32 savePIPEB_GMCH_DATA_N
;
665 u32 savePIPEA_DP_LINK_M
;
666 u32 savePIPEB_DP_LINK_M
;
667 u32 savePIPEA_DP_LINK_N
;
668 u32 savePIPEB_DP_LINK_N
;
679 u32 savePCH_DREF_CONTROL
;
680 u32 saveDISP_ARB_CTL
;
681 u32 savePIPEA_DATA_M1
;
682 u32 savePIPEA_DATA_N1
;
683 u32 savePIPEA_LINK_M1
;
684 u32 savePIPEA_LINK_N1
;
685 u32 savePIPEB_DATA_M1
;
686 u32 savePIPEB_DATA_N1
;
687 u32 savePIPEB_LINK_M1
;
688 u32 savePIPEB_LINK_N1
;
689 u32 saveMCHBAR_RENDER_STANDBY
;
690 u32 savePCH_PORT_HOTPLUG
;
693 struct intel_gen6_power_mgmt
{
694 struct work_struct work
;
695 struct delayed_work vlv_work
;
697 /* lock - irqsave spinlock that protectects the work_struct and
701 /* The below variables an all the rps hw state are protected by
702 * dev->struct mutext. */
709 struct delayed_work delayed_resume_work
;
712 * Protects RPS/RC6 register access and PCU communication.
713 * Must be taken after struct_mutex if nested.
715 struct mutex hw_lock
;
718 /* defined intel_pm.c */
719 extern spinlock_t mchdev_lock
;
721 struct intel_ilk_power_mgmt
{
729 unsigned long last_time1
;
730 unsigned long chipset_power
;
732 struct timespec last_time2
;
733 unsigned long gfx_power
;
739 struct drm_i915_gem_object
*pwrctx
;
740 struct drm_i915_gem_object
*renderctx
;
743 /* Power well structure for haswell */
744 struct i915_power_well
{
745 struct drm_device
*device
;
747 /* power well enable/disable usage count */
752 struct i915_dri1_state
{
753 unsigned allow_batchbuffer
: 1;
754 u32 __iomem
*gfx_hws_cpu_addr
;
765 struct intel_l3_parity
{
767 struct work_struct error_work
;
771 /** Memory allocator for GTT stolen memory */
772 struct drm_mm stolen
;
773 /** Memory allocator for GTT */
774 struct drm_mm gtt_space
;
775 /** List of all objects in gtt_space. Used to restore gtt
776 * mappings on resume */
777 struct list_head bound_list
;
779 * List of objects which are not bound to the GTT (thus
780 * are idle and not used by the GPU) but still have
781 * (presumably uncached) pages still attached.
783 struct list_head unbound_list
;
785 /** Usable portion of the GTT for GEM */
786 unsigned long stolen_base
; /* limited to low memory (32-bit) */
790 /** PPGTT used for aliasing the PPGTT with the GTT */
791 struct i915_hw_ppgtt
*aliasing_ppgtt
;
793 struct shrinker inactive_shrinker
;
794 bool shrinker_no_lock_stealing
;
797 * List of objects currently involved in rendering.
799 * Includes buffers having the contents of their GPU caches
800 * flushed, not necessarily primitives. last_rendering_seqno
801 * represents when the rendering involved will be completed.
803 * A reference is held on the buffer while on this list.
805 struct list_head active_list
;
808 * LRU list of objects which are not in the ringbuffer and
809 * are ready to unbind, but are still in the GTT.
811 * last_rendering_seqno is 0 while an object is in this list.
813 * A reference is not held on the buffer while on this list,
814 * as merely being GTT-bound shouldn't prevent its being
815 * freed, and we'll pull it off the list in the free path.
817 struct list_head inactive_list
;
819 /** LRU list of objects with fence regs on them. */
820 struct list_head fence_list
;
823 * We leave the user IRQ off as much as possible,
824 * but this means that requests will finish and never
825 * be retired once the system goes idle. Set a timer to
826 * fire periodically while the ring is running. When it
827 * fires, go retire requests.
829 struct delayed_work retire_work
;
832 * Are we in a non-interruptible section of code like
838 * Flag if the X Server, and thus DRM, is not currently in
839 * control of the device.
841 * This is set between LeaveVT and EnterVT. It needs to be
842 * replaced with a semaphore. It also needs to be
843 * transitioned away from for kernel modesetting.
847 /** Bit 6 swizzling required for X tiling */
848 uint32_t bit_6_swizzle_x
;
849 /** Bit 6 swizzling required for Y tiling */
850 uint32_t bit_6_swizzle_y
;
852 /* storage for physical objects */
853 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
855 /* accounting, useful for userland debugging */
856 size_t object_memory
;
860 struct drm_i915_error_state_buf
{
869 struct i915_gpu_error
{
870 /* For hangcheck timer */
871 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
872 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
873 struct timer_list hangcheck_timer
;
875 /* For reset and error_state handling. */
877 /* Protected by the above dev->gpu_error.lock. */
878 struct drm_i915_error_state
*first_error
;
879 struct work_struct work
;
881 unsigned long last_reset
;
884 * State variable and reset counter controlling the reset flow
886 * Upper bits are for the reset counter. This counter is used by the
887 * wait_seqno code to race-free noticed that a reset event happened and
888 * that it needs to restart the entire ioctl (since most likely the
889 * seqno it waited for won't ever signal anytime soon).
891 * This is important for lock-free wait paths, where no contended lock
892 * naturally enforces the correct ordering between the bail-out of the
893 * waiter and the gpu reset work code.
895 * Lowest bit controls the reset state machine: Set means a reset is in
896 * progress. This state will (presuming we don't have any bugs) decay
897 * into either unset (successful reset) or the special WEDGED value (hw
898 * terminally sour). All waiters on the reset_queue will be woken when
901 atomic_t reset_counter
;
904 * Special values/flags for reset_counter
906 * Note that the code relies on
907 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
910 #define I915_RESET_IN_PROGRESS_FLAG 1
911 #define I915_WEDGED 0xffffffff
914 * Waitqueue to signal when the reset has completed. Used by clients
915 * that wait for dev_priv->mm.wedged to settle.
917 wait_queue_head_t reset_queue
;
919 /* For gpu hang simulation. */
920 unsigned int stop_rings
;
923 enum modeset_restore
{
929 struct intel_vbt_data
{
930 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
931 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
934 unsigned int int_tv_support
:1;
935 unsigned int lvds_dither
:1;
936 unsigned int lvds_vbt
:1;
937 unsigned int int_crt_support
:1;
938 unsigned int lvds_use_ssc
:1;
939 unsigned int display_clock_mode
:1;
940 unsigned int fdi_rx_polarity_inverted
:1;
942 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
949 bool edp_initialized
;
952 struct edp_power_seq edp_pps
;
957 struct child_device_config
*child_dev
;
960 typedef struct drm_i915_private
{
961 struct drm_device
*dev
;
962 struct kmem_cache
*slab
;
964 const struct intel_device_info
*info
;
966 int relative_constants_mode
;
970 struct drm_i915_gt_funcs gt
;
971 /** gt_fifo_count and the subsequent register write are synchronized
972 * with dev->struct_mutex. */
973 unsigned gt_fifo_count
;
974 /** forcewake_count is protected by gt_lock */
975 unsigned forcewake_count
;
976 /** gt_lock is also taken in irq contexts. */
979 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
982 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
983 * controller on different i2c buses. */
984 struct mutex gmbus_mutex
;
987 * Base address of the gmbus and gpio block.
989 uint32_t gpio_mmio_base
;
991 wait_queue_head_t gmbus_wait_queue
;
993 struct pci_dev
*bridge_dev
;
994 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
995 uint32_t last_seqno
, next_seqno
;
997 drm_dma_handle_t
*status_page_dmah
;
998 struct resource mch_res
;
1000 atomic_t irq_received
;
1002 /* protects the irq masks */
1003 spinlock_t irq_lock
;
1005 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1006 struct pm_qos_request pm_qos
;
1008 /* DPIO indirect register protection */
1009 struct mutex dpio_lock
;
1011 /** Cached value of IMR to avoid reads in updating the bitfield */
1015 struct work_struct hotplug_work
;
1016 bool enable_hotplug_processing
;
1018 unsigned long hpd_last_jiffies
;
1023 HPD_MARK_DISABLED
= 2
1025 } hpd_stats
[HPD_NUM_PINS
];
1027 struct timer_list hotplug_reenable_timer
;
1032 unsigned long cfb_size
;
1033 unsigned int cfb_fb
;
1034 enum plane cfb_plane
;
1036 struct intel_fbc_work
*fbc_work
;
1038 struct intel_opregion opregion
;
1039 struct intel_vbt_data vbt
;
1042 struct intel_overlay
*overlay
;
1043 unsigned int sprite_scaling_enabled
;
1049 spinlock_t lock
; /* bl registers and the above bl fields */
1050 struct backlight_device
*device
;
1054 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1055 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1056 bool no_aux_handshake
;
1058 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1059 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1060 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1062 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1064 struct workqueue_struct
*wq
;
1066 /* Display functions */
1067 struct drm_i915_display_funcs display
;
1069 /* PCH chipset type */
1070 enum intel_pch pch_type
;
1071 unsigned short pch_id
;
1073 unsigned long quirks
;
1075 enum modeset_restore modeset_restore
;
1076 struct mutex modeset_restore_lock
;
1078 struct i915_gtt gtt
;
1080 struct i915_gem_mm mm
;
1082 /* Kernel Modesetting */
1084 struct sdvo_device_mapping sdvo_mappings
[2];
1086 struct drm_crtc
*plane_to_crtc_mapping
[3];
1087 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1088 wait_queue_head_t pending_flip_queue
;
1090 struct intel_pch_pll pch_plls
[I915_NUM_PLLS
];
1091 struct intel_ddi_plls ddi_plls
;
1093 /* Reclocking support */
1094 bool render_reclock_avail
;
1095 bool lvds_downclock_avail
;
1096 /* indicates the reduced downclock for LVDS*/
1100 bool mchbar_need_disable
;
1102 struct intel_l3_parity l3_parity
;
1104 /* gen6+ rps state */
1105 struct intel_gen6_power_mgmt rps
;
1107 /* ilk-only ips/rps state. Everything in here is protected by the global
1108 * mchdev_lock in intel_pm.c */
1109 struct intel_ilk_power_mgmt ips
;
1111 /* Haswell power well */
1112 struct i915_power_well power_well
;
1114 enum no_fbc_reason no_fbc_reason
;
1116 struct drm_mm_node
*compressed_fb
;
1117 struct drm_mm_node
*compressed_llb
;
1119 struct i915_gpu_error gpu_error
;
1121 struct drm_i915_gem_object
*vlv_pctx
;
1123 /* list of fbdev register on this device */
1124 struct intel_fbdev
*fbdev
;
1127 * The console may be contended at resume, but we don't
1128 * want it to block on it.
1130 struct work_struct console_resume_work
;
1132 struct drm_property
*broadcast_rgb_property
;
1133 struct drm_property
*force_audio_property
;
1135 bool hw_contexts_disabled
;
1136 uint32_t hw_context_size
;
1140 struct i915_suspend_saved_registers regfile
;
1142 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1144 struct i915_dri1_state dri1
;
1145 } drm_i915_private_t
;
1147 /* Iterate over initialised rings */
1148 #define for_each_ring(ring__, dev_priv__, i__) \
1149 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1150 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1152 enum hdmi_force_audio
{
1153 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1154 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1155 HDMI_AUDIO_AUTO
, /* trust EDID */
1156 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1159 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1161 struct drm_i915_gem_object_ops
{
1162 /* Interface between the GEM object and its backing storage.
1163 * get_pages() is called once prior to the use of the associated set
1164 * of pages before to binding them into the GTT, and put_pages() is
1165 * called after we no longer need them. As we expect there to be
1166 * associated cost with migrating pages between the backing storage
1167 * and making them available for the GPU (e.g. clflush), we may hold
1168 * onto the pages after they are no longer referenced by the GPU
1169 * in case they may be used again shortly (for example migrating the
1170 * pages to a different memory domain within the GTT). put_pages()
1171 * will therefore most likely be called when the object itself is
1172 * being released or under memory pressure (where we attempt to
1173 * reap pages for the shrinker).
1175 int (*get_pages
)(struct drm_i915_gem_object
*);
1176 void (*put_pages
)(struct drm_i915_gem_object
*);
1179 struct drm_i915_gem_object
{
1180 struct drm_gem_object base
;
1182 const struct drm_i915_gem_object_ops
*ops
;
1184 /** Current space allocated to this object in the GTT, if any. */
1185 struct drm_mm_node
*gtt_space
;
1186 /** Stolen memory for this object, instead of being backed by shmem. */
1187 struct drm_mm_node
*stolen
;
1188 struct list_head global_list
;
1190 /** This object's place on the active/inactive lists */
1191 struct list_head ring_list
;
1192 struct list_head mm_list
;
1193 /** This object's place in the batchbuffer or on the eviction list */
1194 struct list_head exec_list
;
1197 * This is set if the object is on the active lists (has pending
1198 * rendering and so a non-zero seqno), and is not set if it i s on
1199 * inactive (ready to be unbound) list.
1201 unsigned int active
:1;
1204 * This is set if the object has been written to since last bound
1207 unsigned int dirty
:1;
1210 * Fence register bits (if any) for this object. Will be set
1211 * as needed when mapped into the GTT.
1212 * Protected by dev->struct_mutex.
1214 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1217 * Advice: are the backing pages purgeable?
1219 unsigned int madv
:2;
1222 * Current tiling mode for the object.
1224 unsigned int tiling_mode
:2;
1226 * Whether the tiling parameters for the currently associated fence
1227 * register have changed. Note that for the purposes of tracking
1228 * tiling changes we also treat the unfenced register, the register
1229 * slot that the object occupies whilst it executes a fenced
1230 * command (such as BLT on gen2/3), as a "fence".
1232 unsigned int fence_dirty
:1;
1234 /** How many users have pinned this object in GTT space. The following
1235 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1236 * (via user_pin_count), execbuffer (objects are not allowed multiple
1237 * times for the same batchbuffer), and the framebuffer code. When
1238 * switching/pageflipping, the framebuffer code has at most two buffers
1241 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1242 * bits with absolutely no headroom. So use 4 bits. */
1243 unsigned int pin_count
:4;
1244 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1247 * Is the object at the current location in the gtt mappable and
1248 * fenceable? Used to avoid costly recalculations.
1250 unsigned int map_and_fenceable
:1;
1253 * Whether the current gtt mapping needs to be mappable (and isn't just
1254 * mappable by accident). Track pin and fault separate for a more
1255 * accurate mappable working set.
1257 unsigned int fault_mappable
:1;
1258 unsigned int pin_mappable
:1;
1261 * Is the GPU currently using a fence to access this buffer,
1263 unsigned int pending_fenced_gpu_access
:1;
1264 unsigned int fenced_gpu_access
:1;
1266 unsigned int cache_level
:2;
1268 unsigned int has_aliasing_ppgtt_mapping
:1;
1269 unsigned int has_global_gtt_mapping
:1;
1270 unsigned int has_dma_mapping
:1;
1272 struct sg_table
*pages
;
1273 int pages_pin_count
;
1275 /* prime dma-buf support */
1276 void *dma_buf_vmapping
;
1280 * Used for performing relocations during execbuffer insertion.
1282 struct hlist_node exec_node
;
1283 unsigned long exec_handle
;
1284 struct drm_i915_gem_exec_object2
*exec_entry
;
1287 * Current offset of the object in GTT space.
1289 * This is the same as gtt_space->start
1291 uint32_t gtt_offset
;
1293 struct intel_ring_buffer
*ring
;
1295 /** Breadcrumb of last rendering to the buffer. */
1296 uint32_t last_read_seqno
;
1297 uint32_t last_write_seqno
;
1298 /** Breadcrumb of last fenced GPU access to the buffer. */
1299 uint32_t last_fenced_seqno
;
1301 /** Current tiling stride for the object, if it's tiled. */
1304 /** Record of address bit 17 of each page at last unbind. */
1305 unsigned long *bit_17
;
1307 /** User space pin count and filp owning the pin */
1308 uint32_t user_pin_count
;
1309 struct drm_file
*pin_filp
;
1311 /** for phy allocated objects */
1312 struct drm_i915_gem_phys_object
*phys_obj
;
1314 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1316 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1319 * Request queue structure.
1321 * The request queue allows us to note sequence numbers that have been emitted
1322 * and may be associated with active buffers to be retired.
1324 * By keeping this list, we can avoid having to do questionable
1325 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1326 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1328 struct drm_i915_gem_request
{
1329 /** On Which ring this request was generated */
1330 struct intel_ring_buffer
*ring
;
1332 /** GEM sequence number associated with this request. */
1335 /** Postion in the ringbuffer of the end of the request */
1338 /** Context related to this request */
1339 struct i915_hw_context
*ctx
;
1341 /** Time at which this request was emitted, in jiffies. */
1342 unsigned long emitted_jiffies
;
1344 /** global list entry for this request */
1345 struct list_head list
;
1347 struct drm_i915_file_private
*file_priv
;
1348 /** file_priv list entry for this request */
1349 struct list_head client_list
;
1352 struct drm_i915_file_private
{
1355 struct list_head request_list
;
1357 struct idr context_idr
;
1360 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1362 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1363 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1364 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1365 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1366 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1367 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1368 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1369 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1370 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1371 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1372 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1373 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1374 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1375 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1376 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1377 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1378 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1379 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1380 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1381 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1382 (dev)->pci_device == 0x0152 || \
1383 (dev)->pci_device == 0x015a)
1384 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1385 (dev)->pci_device == 0x0106 || \
1386 (dev)->pci_device == 0x010A)
1387 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1388 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1389 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1390 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1391 ((dev)->pci_device & 0xFF00) == 0x0A00)
1394 * The genX designation typically refers to the render engine, so render
1395 * capability related checks should use IS_GEN, while display and other checks
1396 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1399 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1400 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1401 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1402 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1403 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1404 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1406 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1407 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1408 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1409 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1410 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1412 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1413 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1415 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1416 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1418 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1419 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1421 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1422 * rows, which changed the alignment requirements and fence programming.
1424 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1426 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1427 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1428 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1429 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1430 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1431 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1432 /* dsparb controlled by hw only */
1433 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1435 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1436 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1437 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1439 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1441 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1442 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1443 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1445 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1446 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1447 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1448 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1449 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1450 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1452 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1453 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1454 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1455 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1456 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1457 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1459 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1461 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1463 #define GT_FREQUENCY_MULTIPLIER 50
1465 #include "i915_trace.h"
1468 * RC6 is a special power stage which allows the GPU to enter an very
1469 * low-voltage mode when idle, using down to 0V while at this stage. This
1470 * stage is entered automatically when the GPU is idle when RC6 support is
1471 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1473 * There are different RC6 modes available in Intel GPU, which differentiate
1474 * among each other with the latency required to enter and leave RC6 and
1475 * voltage consumed by the GPU in different states.
1477 * The combination of the following flags define which states GPU is allowed
1478 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1479 * RC6pp is deepest RC6. Their support by hardware varies according to the
1480 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1481 * which brings the most power savings; deeper states save more power, but
1482 * require higher latency to switch to and wake up.
1484 #define INTEL_RC6_ENABLE (1<<0)
1485 #define INTEL_RC6p_ENABLE (1<<1)
1486 #define INTEL_RC6pp_ENABLE (1<<2)
1488 extern struct drm_ioctl_desc i915_ioctls
[];
1489 extern int i915_max_ioctl
;
1490 extern unsigned int i915_fbpercrtc __always_unused
;
1491 extern int i915_panel_ignore_lid __read_mostly
;
1492 extern unsigned int i915_powersave __read_mostly
;
1493 extern int i915_semaphores __read_mostly
;
1494 extern unsigned int i915_lvds_downclock __read_mostly
;
1495 extern int i915_lvds_channel_mode __read_mostly
;
1496 extern int i915_panel_use_ssc __read_mostly
;
1497 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1498 extern int i915_enable_rc6 __read_mostly
;
1499 extern int i915_enable_fbc __read_mostly
;
1500 extern bool i915_enable_hangcheck __read_mostly
;
1501 extern int i915_enable_ppgtt __read_mostly
;
1502 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1503 extern int i915_disable_power_well __read_mostly
;
1504 extern int i915_enable_ips __read_mostly
;
1506 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1507 extern int i915_resume(struct drm_device
*dev
);
1508 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1509 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1512 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1513 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1514 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1515 extern int i915_driver_unload(struct drm_device
*);
1516 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1517 extern void i915_driver_lastclose(struct drm_device
* dev
);
1518 extern void i915_driver_preclose(struct drm_device
*dev
,
1519 struct drm_file
*file_priv
);
1520 extern void i915_driver_postclose(struct drm_device
*dev
,
1521 struct drm_file
*file_priv
);
1522 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1523 #ifdef CONFIG_COMPAT
1524 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1527 extern int i915_emit_box(struct drm_device
*dev
,
1528 struct drm_clip_rect
*box
,
1530 extern int intel_gpu_reset(struct drm_device
*dev
);
1531 extern int i915_reset(struct drm_device
*dev
);
1532 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1533 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1534 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1535 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1537 extern void intel_console_resume(struct work_struct
*work
);
1540 void i915_hangcheck_elapsed(unsigned long data
);
1541 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1543 extern void intel_irq_init(struct drm_device
*dev
);
1544 extern void intel_hpd_init(struct drm_device
*dev
);
1545 extern void intel_gt_init(struct drm_device
*dev
);
1546 extern void intel_gt_reset(struct drm_device
*dev
);
1548 void i915_error_state_free(struct kref
*error_ref
);
1551 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1554 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1556 #ifdef CONFIG_DEBUG_FS
1557 extern void i915_destroy_error_state(struct drm_device
*dev
);
1559 #define i915_destroy_error_state(x)
1564 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1565 struct drm_file
*file_priv
);
1566 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1567 struct drm_file
*file_priv
);
1568 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1569 struct drm_file
*file_priv
);
1570 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1571 struct drm_file
*file_priv
);
1572 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1573 struct drm_file
*file_priv
);
1574 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1575 struct drm_file
*file_priv
);
1576 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1577 struct drm_file
*file_priv
);
1578 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1579 struct drm_file
*file_priv
);
1580 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1581 struct drm_file
*file_priv
);
1582 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1583 struct drm_file
*file_priv
);
1584 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1585 struct drm_file
*file_priv
);
1586 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1587 struct drm_file
*file_priv
);
1588 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1589 struct drm_file
*file_priv
);
1590 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1591 struct drm_file
*file
);
1592 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1593 struct drm_file
*file
);
1594 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1595 struct drm_file
*file_priv
);
1596 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1597 struct drm_file
*file_priv
);
1598 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1599 struct drm_file
*file_priv
);
1600 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1601 struct drm_file
*file_priv
);
1602 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1603 struct drm_file
*file_priv
);
1604 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1605 struct drm_file
*file_priv
);
1606 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1607 struct drm_file
*file_priv
);
1608 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1609 struct drm_file
*file_priv
);
1610 void i915_gem_load(struct drm_device
*dev
);
1611 void *i915_gem_object_alloc(struct drm_device
*dev
);
1612 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1613 int i915_gem_init_object(struct drm_gem_object
*obj
);
1614 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1615 const struct drm_i915_gem_object_ops
*ops
);
1616 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1618 void i915_gem_free_object(struct drm_gem_object
*obj
);
1620 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1622 bool map_and_fenceable
,
1624 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1625 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1626 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1627 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1628 void i915_gem_lastclose(struct drm_device
*dev
);
1630 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1631 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1633 struct sg_page_iter sg_iter
;
1635 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1636 return sg_page_iter_page(&sg_iter
);
1640 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1642 BUG_ON(obj
->pages
== NULL
);
1643 obj
->pages_pin_count
++;
1645 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1647 BUG_ON(obj
->pages_pin_count
== 0);
1648 obj
->pages_pin_count
--;
1651 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1652 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1653 struct intel_ring_buffer
*to
);
1654 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1655 struct intel_ring_buffer
*ring
);
1657 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1658 struct drm_device
*dev
,
1659 struct drm_mode_create_dumb
*args
);
1660 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1661 uint32_t handle
, uint64_t *offset
);
1662 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1665 * Returns true if seq1 is later than seq2.
1668 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1670 return (int32_t)(seq1
- seq2
) >= 0;
1673 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1674 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1675 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1676 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1679 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1681 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1682 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1683 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1690 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1692 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1693 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1694 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1698 void i915_gem_retire_requests(struct drm_device
*dev
);
1699 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1700 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1701 bool interruptible
);
1702 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1704 return unlikely(atomic_read(&error
->reset_counter
)
1705 & I915_RESET_IN_PROGRESS_FLAG
);
1708 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1710 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1713 void i915_gem_reset(struct drm_device
*dev
);
1714 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1715 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1716 uint32_t read_domains
,
1717 uint32_t write_domain
);
1718 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1719 int __must_check
i915_gem_init(struct drm_device
*dev
);
1720 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1721 void i915_gem_l3_remap(struct drm_device
*dev
);
1722 void i915_gem_init_swizzling(struct drm_device
*dev
);
1723 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1724 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1725 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1726 int i915_add_request(struct intel_ring_buffer
*ring
,
1727 struct drm_file
*file
,
1729 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1731 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1733 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1736 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1738 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1740 struct intel_ring_buffer
*pipelined
);
1741 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1742 struct drm_i915_gem_object
*obj
,
1745 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1746 struct drm_i915_gem_object
*obj
);
1747 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1748 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1751 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
1753 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1754 int tiling_mode
, bool fenced
);
1756 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1757 enum i915_cache_level cache_level
);
1759 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1760 struct dma_buf
*dma_buf
);
1762 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1763 struct drm_gem_object
*gem_obj
, int flags
);
1765 /* i915_gem_context.c */
1766 void i915_gem_context_init(struct drm_device
*dev
);
1767 void i915_gem_context_fini(struct drm_device
*dev
);
1768 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1769 int i915_switch_context(struct intel_ring_buffer
*ring
,
1770 struct drm_file
*file
, int to_id
);
1771 void i915_gem_context_free(struct kref
*ctx_ref
);
1772 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
1774 kref_get(&ctx
->ref
);
1777 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
1779 kref_put(&ctx
->ref
, i915_gem_context_free
);
1782 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1783 struct drm_file
*file
);
1784 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1785 struct drm_file
*file
);
1787 /* i915_gem_gtt.c */
1788 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1789 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1790 struct drm_i915_gem_object
*obj
,
1791 enum i915_cache_level cache_level
);
1792 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1793 struct drm_i915_gem_object
*obj
);
1795 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1796 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1797 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1798 enum i915_cache_level cache_level
);
1799 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1800 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1801 void i915_gem_init_global_gtt(struct drm_device
*dev
);
1802 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
1803 unsigned long mappable_end
, unsigned long end
);
1804 int i915_gem_gtt_init(struct drm_device
*dev
);
1805 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
1807 if (INTEL_INFO(dev
)->gen
< 6)
1808 intel_gtt_chipset_flush();
1812 /* i915_gem_evict.c */
1813 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1815 unsigned cache_level
,
1818 int i915_gem_evict_everything(struct drm_device
*dev
);
1820 /* i915_gem_stolen.c */
1821 int i915_gem_init_stolen(struct drm_device
*dev
);
1822 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
1823 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
1824 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1825 struct drm_i915_gem_object
*
1826 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
1827 struct drm_i915_gem_object
*
1828 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
1832 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
1834 /* i915_gem_tiling.c */
1835 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
1837 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
1839 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
1840 obj
->tiling_mode
!= I915_TILING_NONE
;
1843 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1844 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1845 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1847 /* i915_gem_debug.c */
1848 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1849 const char *where
, uint32_t mark
);
1851 int i915_verify_lists(struct drm_device
*dev
);
1853 #define i915_verify_lists(dev) 0
1855 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1857 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1858 const char *where
, uint32_t mark
);
1860 /* i915_debugfs.c */
1861 int i915_debugfs_init(struct drm_minor
*minor
);
1862 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1864 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
1866 /* i915_suspend.c */
1867 extern int i915_save_state(struct drm_device
*dev
);
1868 extern int i915_restore_state(struct drm_device
*dev
);
1871 void i915_save_display_reg(struct drm_device
*dev
);
1872 void i915_restore_display_reg(struct drm_device
*dev
);
1875 void i915_setup_sysfs(struct drm_device
*dev_priv
);
1876 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
1879 extern int intel_setup_gmbus(struct drm_device
*dev
);
1880 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1881 static inline bool intel_gmbus_is_port_valid(unsigned port
)
1883 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
1886 extern struct i2c_adapter
*intel_gmbus_get_adapter(
1887 struct drm_i915_private
*dev_priv
, unsigned port
);
1888 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1889 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1890 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1892 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1894 extern void intel_i2c_reset(struct drm_device
*dev
);
1896 /* intel_opregion.c */
1897 extern int intel_opregion_setup(struct drm_device
*dev
);
1899 extern void intel_opregion_init(struct drm_device
*dev
);
1900 extern void intel_opregion_fini(struct drm_device
*dev
);
1901 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1903 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1904 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1905 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1910 extern void intel_register_dsm_handler(void);
1911 extern void intel_unregister_dsm_handler(void);
1913 static inline void intel_register_dsm_handler(void) { return; }
1914 static inline void intel_unregister_dsm_handler(void) { return; }
1915 #endif /* CONFIG_ACPI */
1918 extern void intel_modeset_init_hw(struct drm_device
*dev
);
1919 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
1920 extern void intel_modeset_init(struct drm_device
*dev
);
1921 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1922 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1923 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1924 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
1925 bool force_restore
);
1926 extern void i915_redisable_vga(struct drm_device
*dev
);
1927 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1928 extern void intel_disable_fbc(struct drm_device
*dev
);
1929 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1930 extern void intel_init_pch_refclk(struct drm_device
*dev
);
1931 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1932 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
1933 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
1934 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
1935 extern void intel_detect_pch(struct drm_device
*dev
);
1936 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1937 extern int intel_enable_rc6(const struct drm_device
*dev
);
1939 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
1940 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
1941 struct drm_file
*file
);
1944 #ifdef CONFIG_DEBUG_FS
1945 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1946 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
1947 struct intel_overlay_error_state
*error
);
1949 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1950 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
1951 struct drm_device
*dev
,
1952 struct intel_display_error_state
*error
);
1955 /* On SNB platform, before reading ring registers forcewake bit
1956 * must be set to prevent GT core from power down and stale values being
1959 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1960 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1961 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1963 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
1964 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
1966 /* intel_sideband.c */
1967 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
1968 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
1969 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
1970 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, int reg
);
1971 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, int reg
, u32 val
);
1972 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
1973 enum intel_sbi_destination destination
);
1974 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
1975 enum intel_sbi_destination destination
);
1977 int vlv_gpu_freq(int ddr_freq
, int val
);
1978 int vlv_freq_opcode(int ddr_freq
, int val
);
1980 #define __i915_read(x, y) \
1981 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1989 #define __i915_write(x, y) \
1990 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1998 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1999 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2001 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
2002 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2003 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2004 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2006 #define I915_READ(reg) i915_read32(dev_priv, (reg))
2007 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
2008 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2009 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
2011 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2012 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
2014 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2015 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2017 /* "Broadcast RGB" property */
2018 #define INTEL_BROADCAST_RGB_AUTO 0
2019 #define INTEL_BROADCAST_RGB_FULL 1
2020 #define INTEL_BROADCAST_RGB_LIMITED 2
2022 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2024 if (HAS_PCH_SPLIT(dev
))
2025 return CPU_VGACNTRL
;
2026 else if (IS_VALLEYVIEW(dev
))
2027 return VLV_VGACNTRL
;
2032 static inline void __user
*to_user_ptr(u64 address
)
2034 return (void __user
*)(uintptr_t)address
;