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drm/i915: add power monitoring support
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37
38 /* General customization:
39 */
40
41 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42
43 #define DRIVER_NAME "i915"
44 #define DRIVER_DESC "Intel Graphics"
45 #define DRIVER_DATE "20080730"
46
47 enum pipe {
48 PIPE_A = 0,
49 PIPE_B,
50 };
51
52 enum plane {
53 PLANE_A = 0,
54 PLANE_B,
55 };
56
57 #define I915_NUM_PIPE 2
58
59 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
60
61 /* Interface history:
62 *
63 * 1.1: Original.
64 * 1.2: Add Power Management
65 * 1.3: Add vblank support
66 * 1.4: Fix cmdbuffer path, add heap destroy
67 * 1.5: Add vblank pipe configuration
68 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
69 * - Support vertical blank on secondary display pipe
70 */
71 #define DRIVER_MAJOR 1
72 #define DRIVER_MINOR 6
73 #define DRIVER_PATCHLEVEL 0
74
75 #define WATCH_COHERENCY 0
76 #define WATCH_BUF 0
77 #define WATCH_EXEC 0
78 #define WATCH_LRU 0
79 #define WATCH_RELOC 0
80 #define WATCH_INACTIVE 0
81 #define WATCH_PWRITE 0
82
83 #define I915_GEM_PHYS_CURSOR_0 1
84 #define I915_GEM_PHYS_CURSOR_1 2
85 #define I915_GEM_PHYS_OVERLAY_REGS 3
86 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
87
88 struct drm_i915_gem_phys_object {
89 int id;
90 struct page **page_list;
91 drm_dma_handle_t *handle;
92 struct drm_gem_object *cur_obj;
93 };
94
95 struct mem_block {
96 struct mem_block *next;
97 struct mem_block *prev;
98 int start;
99 int size;
100 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
101 };
102
103 struct opregion_header;
104 struct opregion_acpi;
105 struct opregion_swsci;
106 struct opregion_asle;
107
108 struct intel_opregion {
109 struct opregion_header *header;
110 struct opregion_acpi *acpi;
111 struct opregion_swsci *swsci;
112 struct opregion_asle *asle;
113 int enabled;
114 };
115
116 struct drm_i915_master_private {
117 drm_local_map_t *sarea;
118 struct _drm_i915_sarea *sarea_priv;
119 };
120 #define I915_FENCE_REG_NONE -1
121
122 struct drm_i915_fence_reg {
123 struct drm_gem_object *obj;
124 struct list_head lru_list;
125 };
126
127 struct sdvo_device_mapping {
128 u8 dvo_port;
129 u8 slave_addr;
130 u8 dvo_wiring;
131 u8 initialized;
132 u8 ddc_pin;
133 };
134
135 struct drm_i915_error_state {
136 u32 eir;
137 u32 pgtbl_er;
138 u32 pipeastat;
139 u32 pipebstat;
140 u32 ipeir;
141 u32 ipehr;
142 u32 instdone;
143 u32 acthd;
144 u32 instpm;
145 u32 instps;
146 u32 instdone1;
147 u32 seqno;
148 u64 bbaddr;
149 struct timeval time;
150 struct drm_i915_error_object {
151 int page_count;
152 u32 gtt_offset;
153 u32 *pages[0];
154 } *ringbuffer, *batchbuffer[2];
155 struct drm_i915_error_buffer {
156 size_t size;
157 u32 name;
158 u32 seqno;
159 u32 gtt_offset;
160 u32 read_domains;
161 u32 write_domain;
162 u32 fence_reg;
163 s32 pinned:2;
164 u32 tiling:2;
165 u32 dirty:1;
166 u32 purgeable:1;
167 } *active_bo;
168 u32 active_bo_count;
169 };
170
171 struct drm_i915_display_funcs {
172 void (*dpms)(struct drm_crtc *crtc, int mode);
173 bool (*fbc_enabled)(struct drm_device *dev);
174 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
175 void (*disable_fbc)(struct drm_device *dev);
176 int (*get_display_clock_speed)(struct drm_device *dev);
177 int (*get_fifo_size)(struct drm_device *dev, int plane);
178 void (*update_wm)(struct drm_device *dev, int planea_clock,
179 int planeb_clock, int sr_hdisplay, int pixel_size);
180 /* clock updates for mode set */
181 /* cursor updates */
182 /* render clock increase/decrease */
183 /* display clock increase/decrease */
184 /* pll clock increase/decrease */
185 /* clock gating init */
186 };
187
188 struct intel_overlay;
189
190 struct intel_device_info {
191 u8 is_mobile : 1;
192 u8 is_i8xx : 1;
193 u8 is_i85x : 1;
194 u8 is_i915g : 1;
195 u8 is_i9xx : 1;
196 u8 is_i945gm : 1;
197 u8 is_i965g : 1;
198 u8 is_i965gm : 1;
199 u8 is_g33 : 1;
200 u8 need_gfx_hws : 1;
201 u8 is_g4x : 1;
202 u8 is_pineview : 1;
203 u8 is_ironlake : 1;
204 u8 is_gen6 : 1;
205 u8 has_fbc : 1;
206 u8 has_rc6 : 1;
207 u8 has_pipe_cxsr : 1;
208 u8 has_hotplug : 1;
209 u8 cursor_needs_physical : 1;
210 };
211
212 enum no_fbc_reason {
213 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
214 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
215 FBC_MODE_TOO_LARGE, /* mode too large for compression */
216 FBC_BAD_PLANE, /* fbc not supported on plane */
217 FBC_NOT_TILED, /* buffer not tiled */
218 };
219
220 enum intel_pch {
221 PCH_IBX, /* Ibexpeak PCH */
222 PCH_CPT, /* Cougarpoint PCH */
223 };
224
225 struct intel_fbdev;
226
227 typedef struct drm_i915_private {
228 struct drm_device *dev;
229
230 const struct intel_device_info *info;
231
232 int has_gem;
233
234 void __iomem *regs;
235
236 struct pci_dev *bridge_dev;
237 struct intel_ring_buffer render_ring;
238 struct intel_ring_buffer bsd_ring;
239
240 drm_dma_handle_t *status_page_dmah;
241 void *hw_status_page;
242 void *seqno_page;
243 dma_addr_t dma_status_page;
244 uint32_t counter;
245 unsigned int status_gfx_addr;
246 unsigned int seqno_gfx_addr;
247 drm_local_map_t hws_map;
248 struct drm_gem_object *hws_obj;
249 struct drm_gem_object *seqno_obj;
250 struct drm_gem_object *pwrctx;
251
252 struct resource mch_res;
253
254 unsigned int cpp;
255 int back_offset;
256 int front_offset;
257 int current_page;
258 int page_flipping;
259
260 wait_queue_head_t irq_queue;
261 atomic_t irq_received;
262 /** Protects user_irq_refcount and irq_mask_reg */
263 spinlock_t user_irq_lock;
264 u32 trace_irq_seqno;
265 /** Cached value of IMR to avoid reads in updating the bitfield */
266 u32 irq_mask_reg;
267 u32 pipestat[2];
268 /** splitted irq regs for graphics and display engine on Ironlake,
269 irq_mask_reg is still used for display irq. */
270 u32 gt_irq_mask_reg;
271 u32 gt_irq_enable_reg;
272 u32 de_irq_enable_reg;
273 u32 pch_irq_mask_reg;
274 u32 pch_irq_enable_reg;
275
276 u32 hotplug_supported_mask;
277 struct work_struct hotplug_work;
278
279 int tex_lru_log_granularity;
280 int allow_batchbuffer;
281 struct mem_block *agp_heap;
282 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
283 int vblank_pipe;
284
285 /* For hangcheck timer */
286 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
287 struct timer_list hangcheck_timer;
288 int hangcheck_count;
289 uint32_t last_acthd;
290
291 struct drm_mm vram;
292
293 unsigned long cfb_size;
294 unsigned long cfb_pitch;
295 int cfb_fence;
296 int cfb_plane;
297
298 int irq_enabled;
299
300 struct intel_opregion opregion;
301
302 /* overlay */
303 struct intel_overlay *overlay;
304
305 /* LVDS info */
306 int backlight_duty_cycle; /* restore backlight to this value */
307 bool panel_wants_dither;
308 struct drm_display_mode *panel_fixed_mode;
309 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
310 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
311
312 /* Feature bits from the VBIOS */
313 unsigned int int_tv_support:1;
314 unsigned int lvds_dither:1;
315 unsigned int lvds_vbt:1;
316 unsigned int int_crt_support:1;
317 unsigned int lvds_use_ssc:1;
318 unsigned int edp_support:1;
319 int lvds_ssc_freq;
320 int edp_bpp;
321
322 struct notifier_block lid_notifier;
323
324 int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
325 struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
326 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
327 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
328
329 unsigned int fsb_freq, mem_freq;
330
331 spinlock_t error_lock;
332 struct drm_i915_error_state *first_error;
333 struct work_struct error_work;
334 struct workqueue_struct *wq;
335
336 /* Display functions */
337 struct drm_i915_display_funcs display;
338
339 /* PCH chipset type */
340 enum intel_pch pch_type;
341
342 /* Register state */
343 bool modeset_on_lid;
344 u8 saveLBB;
345 u32 saveDSPACNTR;
346 u32 saveDSPBCNTR;
347 u32 saveDSPARB;
348 u32 saveHWS;
349 u32 savePIPEACONF;
350 u32 savePIPEBCONF;
351 u32 savePIPEASRC;
352 u32 savePIPEBSRC;
353 u32 saveFPA0;
354 u32 saveFPA1;
355 u32 saveDPLL_A;
356 u32 saveDPLL_A_MD;
357 u32 saveHTOTAL_A;
358 u32 saveHBLANK_A;
359 u32 saveHSYNC_A;
360 u32 saveVTOTAL_A;
361 u32 saveVBLANK_A;
362 u32 saveVSYNC_A;
363 u32 saveBCLRPAT_A;
364 u32 saveTRANSACONF;
365 u32 saveTRANS_HTOTAL_A;
366 u32 saveTRANS_HBLANK_A;
367 u32 saveTRANS_HSYNC_A;
368 u32 saveTRANS_VTOTAL_A;
369 u32 saveTRANS_VBLANK_A;
370 u32 saveTRANS_VSYNC_A;
371 u32 savePIPEASTAT;
372 u32 saveDSPASTRIDE;
373 u32 saveDSPASIZE;
374 u32 saveDSPAPOS;
375 u32 saveDSPAADDR;
376 u32 saveDSPASURF;
377 u32 saveDSPATILEOFF;
378 u32 savePFIT_PGM_RATIOS;
379 u32 saveBLC_HIST_CTL;
380 u32 saveBLC_PWM_CTL;
381 u32 saveBLC_PWM_CTL2;
382 u32 saveBLC_CPU_PWM_CTL;
383 u32 saveBLC_CPU_PWM_CTL2;
384 u32 saveFPB0;
385 u32 saveFPB1;
386 u32 saveDPLL_B;
387 u32 saveDPLL_B_MD;
388 u32 saveHTOTAL_B;
389 u32 saveHBLANK_B;
390 u32 saveHSYNC_B;
391 u32 saveVTOTAL_B;
392 u32 saveVBLANK_B;
393 u32 saveVSYNC_B;
394 u32 saveBCLRPAT_B;
395 u32 saveTRANSBCONF;
396 u32 saveTRANS_HTOTAL_B;
397 u32 saveTRANS_HBLANK_B;
398 u32 saveTRANS_HSYNC_B;
399 u32 saveTRANS_VTOTAL_B;
400 u32 saveTRANS_VBLANK_B;
401 u32 saveTRANS_VSYNC_B;
402 u32 savePIPEBSTAT;
403 u32 saveDSPBSTRIDE;
404 u32 saveDSPBSIZE;
405 u32 saveDSPBPOS;
406 u32 saveDSPBADDR;
407 u32 saveDSPBSURF;
408 u32 saveDSPBTILEOFF;
409 u32 saveVGA0;
410 u32 saveVGA1;
411 u32 saveVGA_PD;
412 u32 saveVGACNTRL;
413 u32 saveADPA;
414 u32 saveLVDS;
415 u32 savePP_ON_DELAYS;
416 u32 savePP_OFF_DELAYS;
417 u32 saveDVOA;
418 u32 saveDVOB;
419 u32 saveDVOC;
420 u32 savePP_ON;
421 u32 savePP_OFF;
422 u32 savePP_CONTROL;
423 u32 savePP_DIVISOR;
424 u32 savePFIT_CONTROL;
425 u32 save_palette_a[256];
426 u32 save_palette_b[256];
427 u32 saveDPFC_CB_BASE;
428 u32 saveFBC_CFB_BASE;
429 u32 saveFBC_LL_BASE;
430 u32 saveFBC_CONTROL;
431 u32 saveFBC_CONTROL2;
432 u32 saveIER;
433 u32 saveIIR;
434 u32 saveIMR;
435 u32 saveDEIER;
436 u32 saveDEIMR;
437 u32 saveGTIER;
438 u32 saveGTIMR;
439 u32 saveFDI_RXA_IMR;
440 u32 saveFDI_RXB_IMR;
441 u32 saveCACHE_MODE_0;
442 u32 saveMI_ARB_STATE;
443 u32 saveSWF0[16];
444 u32 saveSWF1[16];
445 u32 saveSWF2[3];
446 u8 saveMSR;
447 u8 saveSR[8];
448 u8 saveGR[25];
449 u8 saveAR_INDEX;
450 u8 saveAR[21];
451 u8 saveDACMASK;
452 u8 saveCR[37];
453 uint64_t saveFENCE[16];
454 u32 saveCURACNTR;
455 u32 saveCURAPOS;
456 u32 saveCURABASE;
457 u32 saveCURBCNTR;
458 u32 saveCURBPOS;
459 u32 saveCURBBASE;
460 u32 saveCURSIZE;
461 u32 saveDP_B;
462 u32 saveDP_C;
463 u32 saveDP_D;
464 u32 savePIPEA_GMCH_DATA_M;
465 u32 savePIPEB_GMCH_DATA_M;
466 u32 savePIPEA_GMCH_DATA_N;
467 u32 savePIPEB_GMCH_DATA_N;
468 u32 savePIPEA_DP_LINK_M;
469 u32 savePIPEB_DP_LINK_M;
470 u32 savePIPEA_DP_LINK_N;
471 u32 savePIPEB_DP_LINK_N;
472 u32 saveFDI_RXA_CTL;
473 u32 saveFDI_TXA_CTL;
474 u32 saveFDI_RXB_CTL;
475 u32 saveFDI_TXB_CTL;
476 u32 savePFA_CTL_1;
477 u32 savePFB_CTL_1;
478 u32 savePFA_WIN_SZ;
479 u32 savePFB_WIN_SZ;
480 u32 savePFA_WIN_POS;
481 u32 savePFB_WIN_POS;
482 u32 savePCH_DREF_CONTROL;
483 u32 saveDISP_ARB_CTL;
484 u32 savePIPEA_DATA_M1;
485 u32 savePIPEA_DATA_N1;
486 u32 savePIPEA_LINK_M1;
487 u32 savePIPEA_LINK_N1;
488 u32 savePIPEB_DATA_M1;
489 u32 savePIPEB_DATA_N1;
490 u32 savePIPEB_LINK_M1;
491 u32 savePIPEB_LINK_N1;
492 u32 saveMCHBAR_RENDER_STANDBY;
493
494 struct {
495 struct drm_mm gtt_space;
496
497 struct io_mapping *gtt_mapping;
498 int gtt_mtrr;
499
500 /**
501 * Membership on list of all loaded devices, used to evict
502 * inactive buffers under memory pressure.
503 *
504 * Modifications should only be done whilst holding the
505 * shrink_list_lock spinlock.
506 */
507 struct list_head shrink_list;
508
509 spinlock_t active_list_lock;
510
511 /**
512 * List of objects which are not in the ringbuffer but which
513 * still have a write_domain which needs to be flushed before
514 * unbinding.
515 *
516 * last_rendering_seqno is 0 while an object is in this list.
517 *
518 * A reference is held on the buffer while on this list.
519 */
520 struct list_head flushing_list;
521
522 /**
523 * List of objects currently pending a GPU write flush.
524 *
525 * All elements on this list will belong to either the
526 * active_list or flushing_list, last_rendering_seqno can
527 * be used to differentiate between the two elements.
528 */
529 struct list_head gpu_write_list;
530
531 /**
532 * LRU list of objects which are not in the ringbuffer and
533 * are ready to unbind, but are still in the GTT.
534 *
535 * last_rendering_seqno is 0 while an object is in this list.
536 *
537 * A reference is not held on the buffer while on this list,
538 * as merely being GTT-bound shouldn't prevent its being
539 * freed, and we'll pull it off the list in the free path.
540 */
541 struct list_head inactive_list;
542
543 /** LRU list of objects with fence regs on them. */
544 struct list_head fence_list;
545
546 /**
547 * We leave the user IRQ off as much as possible,
548 * but this means that requests will finish and never
549 * be retired once the system goes idle. Set a timer to
550 * fire periodically while the ring is running. When it
551 * fires, go retire requests.
552 */
553 struct delayed_work retire_work;
554
555 uint32_t next_gem_seqno;
556
557 /**
558 * Waiting sequence number, if any
559 */
560 uint32_t waiting_gem_seqno;
561
562 /**
563 * Last seq seen at irq time
564 */
565 uint32_t irq_gem_seqno;
566
567 /**
568 * Flag if the X Server, and thus DRM, is not currently in
569 * control of the device.
570 *
571 * This is set between LeaveVT and EnterVT. It needs to be
572 * replaced with a semaphore. It also needs to be
573 * transitioned away from for kernel modesetting.
574 */
575 int suspended;
576
577 /**
578 * Flag if the hardware appears to be wedged.
579 *
580 * This is set when attempts to idle the device timeout.
581 * It prevents command submission from occuring and makes
582 * every pending request fail
583 */
584 atomic_t wedged;
585
586 /** Bit 6 swizzling required for X tiling */
587 uint32_t bit_6_swizzle_x;
588 /** Bit 6 swizzling required for Y tiling */
589 uint32_t bit_6_swizzle_y;
590
591 /* storage for physical objects */
592 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
593 } mm;
594 struct sdvo_device_mapping sdvo_mappings[2];
595 /* indicate whether the LVDS_BORDER should be enabled or not */
596 unsigned int lvds_border_bits;
597
598 struct drm_crtc *plane_to_crtc_mapping[2];
599 struct drm_crtc *pipe_to_crtc_mapping[2];
600 wait_queue_head_t pending_flip_queue;
601
602 /* Reclocking support */
603 bool render_reclock_avail;
604 bool lvds_downclock_avail;
605 /* indicate whether the LVDS EDID is OK */
606 bool lvds_edid_good;
607 /* indicates the reduced downclock for LVDS*/
608 int lvds_downclock;
609 struct work_struct idle_work;
610 struct timer_list idle_timer;
611 bool busy;
612 u16 orig_clock;
613 int child_dev_num;
614 struct child_device_config *child_dev;
615 struct drm_connector *int_lvds_connector;
616
617 bool mchbar_need_disable;
618
619 u8 cur_delay;
620 u8 min_delay;
621 u8 max_delay;
622 u8 fmax;
623 u8 fstart;
624
625 u64 last_count1;
626 unsigned long last_time1;
627 u64 last_count2;
628 struct timespec last_time2;
629 unsigned long gfx_power;
630 int c_m;
631 int r_t;
632 u8 corr;
633 spinlock_t *mchdev_lock;
634
635 enum no_fbc_reason no_fbc_reason;
636
637 struct drm_mm_node *compressed_fb;
638 struct drm_mm_node *compressed_llb;
639
640 /* list of fbdev register on this device */
641 struct intel_fbdev *fbdev;
642 } drm_i915_private_t;
643
644 /** driver private structure attached to each drm_gem_object */
645 struct drm_i915_gem_object {
646 struct drm_gem_object base;
647
648 /** Current space allocated to this object in the GTT, if any. */
649 struct drm_mm_node *gtt_space;
650
651 /** This object's place on the active/flushing/inactive lists */
652 struct list_head list;
653 /** This object's place on GPU write list */
654 struct list_head gpu_write_list;
655
656 /**
657 * This is set if the object is on the active or flushing lists
658 * (has pending rendering), and is not set if it's on inactive (ready
659 * to be unbound).
660 */
661 int active;
662
663 /**
664 * This is set if the object has been written to since last bound
665 * to the GTT
666 */
667 int dirty;
668
669 /** AGP memory structure for our GTT binding. */
670 DRM_AGP_MEM *agp_mem;
671
672 struct page **pages;
673 int pages_refcount;
674
675 /**
676 * Current offset of the object in GTT space.
677 *
678 * This is the same as gtt_space->start
679 */
680 uint32_t gtt_offset;
681
682 /* Which ring is refering to is this object */
683 struct intel_ring_buffer *ring;
684
685 /**
686 * Fake offset for use by mmap(2)
687 */
688 uint64_t mmap_offset;
689
690 /**
691 * Fence register bits (if any) for this object. Will be set
692 * as needed when mapped into the GTT.
693 * Protected by dev->struct_mutex.
694 */
695 int fence_reg;
696
697 /** How many users have pinned this object in GTT space */
698 int pin_count;
699
700 /** Breadcrumb of last rendering to the buffer. */
701 uint32_t last_rendering_seqno;
702
703 /** Current tiling mode for the object. */
704 uint32_t tiling_mode;
705 uint32_t stride;
706
707 /** Record of address bit 17 of each page at last unbind. */
708 long *bit_17;
709
710 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
711 uint32_t agp_type;
712
713 /**
714 * If present, while GEM_DOMAIN_CPU is in the read domain this array
715 * flags which individual pages are valid.
716 */
717 uint8_t *page_cpu_valid;
718
719 /** User space pin count and filp owning the pin */
720 uint32_t user_pin_count;
721 struct drm_file *pin_filp;
722
723 /** for phy allocated objects */
724 struct drm_i915_gem_phys_object *phys_obj;
725
726 /**
727 * Used for checking the object doesn't appear more than once
728 * in an execbuffer object list.
729 */
730 int in_execbuffer;
731
732 /**
733 * Advice: are the backing pages purgeable?
734 */
735 int madv;
736
737 /**
738 * Number of crtcs where this object is currently the fb, but
739 * will be page flipped away on the next vblank. When it
740 * reaches 0, dev_priv->pending_flip_queue will be woken up.
741 */
742 atomic_t pending_flip;
743 };
744
745 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
746
747 /**
748 * Request queue structure.
749 *
750 * The request queue allows us to note sequence numbers that have been emitted
751 * and may be associated with active buffers to be retired.
752 *
753 * By keeping this list, we can avoid having to do questionable
754 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
755 * an emission time with seqnos for tracking how far ahead of the GPU we are.
756 */
757 struct drm_i915_gem_request {
758 /** On Which ring this request was generated */
759 struct intel_ring_buffer *ring;
760
761 /** GEM sequence number associated with this request. */
762 uint32_t seqno;
763
764 /** Time at which this request was emitted, in jiffies. */
765 unsigned long emitted_jiffies;
766
767 /** global list entry for this request */
768 struct list_head list;
769
770 /** file_priv list entry for this request */
771 struct list_head client_list;
772 };
773
774 struct drm_i915_file_private {
775 struct {
776 struct list_head request_list;
777 } mm;
778 };
779
780 enum intel_chip_family {
781 CHIP_I8XX = 0x01,
782 CHIP_I9XX = 0x02,
783 CHIP_I915 = 0x04,
784 CHIP_I965 = 0x08,
785 };
786
787 extern struct drm_ioctl_desc i915_ioctls[];
788 extern int i915_max_ioctl;
789 extern unsigned int i915_fbpercrtc;
790 extern unsigned int i915_powersave;
791 extern unsigned int i915_lvds_downclock;
792
793 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
794 extern int i915_resume(struct drm_device *dev);
795 extern void i915_save_display(struct drm_device *dev);
796 extern void i915_restore_display(struct drm_device *dev);
797 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
798 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
799
800 /* i915_dma.c */
801 extern void i915_kernel_lost_context(struct drm_device * dev);
802 extern int i915_driver_load(struct drm_device *, unsigned long flags);
803 extern int i915_driver_unload(struct drm_device *);
804 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
805 extern void i915_driver_lastclose(struct drm_device * dev);
806 extern void i915_driver_preclose(struct drm_device *dev,
807 struct drm_file *file_priv);
808 extern void i915_driver_postclose(struct drm_device *dev,
809 struct drm_file *file_priv);
810 extern int i915_driver_device_is_agp(struct drm_device * dev);
811 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
812 unsigned long arg);
813 extern int i915_emit_box(struct drm_device *dev,
814 struct drm_clip_rect *boxes,
815 int i, int DR1, int DR4);
816 extern int i965_reset(struct drm_device *dev, u8 flags);
817 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
818 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
819 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
820 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
821
822
823 /* i915_irq.c */
824 void i915_hangcheck_elapsed(unsigned long data);
825 void i915_destroy_error_state(struct drm_device *dev);
826 extern int i915_irq_emit(struct drm_device *dev, void *data,
827 struct drm_file *file_priv);
828 extern int i915_irq_wait(struct drm_device *dev, void *data,
829 struct drm_file *file_priv);
830 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
831 extern void i915_enable_interrupt (struct drm_device *dev);
832
833 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
834 extern void i915_driver_irq_preinstall(struct drm_device * dev);
835 extern int i915_driver_irq_postinstall(struct drm_device *dev);
836 extern void i915_driver_irq_uninstall(struct drm_device * dev);
837 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
838 struct drm_file *file_priv);
839 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
840 struct drm_file *file_priv);
841 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
842 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
843 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
844 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
845 extern int i915_vblank_swap(struct drm_device *dev, void *data,
846 struct drm_file *file_priv);
847 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
848 extern void i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask);
849 extern void ironlake_enable_graphics_irq(drm_i915_private_t *dev_priv,
850 u32 mask);
851 extern void ironlake_disable_graphics_irq(drm_i915_private_t *dev_priv,
852 u32 mask);
853
854 void
855 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
856
857 void
858 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
859
860 void intel_enable_asle (struct drm_device *dev);
861
862
863 /* i915_mem.c */
864 extern int i915_mem_alloc(struct drm_device *dev, void *data,
865 struct drm_file *file_priv);
866 extern int i915_mem_free(struct drm_device *dev, void *data,
867 struct drm_file *file_priv);
868 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
869 struct drm_file *file_priv);
870 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
871 struct drm_file *file_priv);
872 extern void i915_mem_takedown(struct mem_block **heap);
873 extern void i915_mem_release(struct drm_device * dev,
874 struct drm_file *file_priv, struct mem_block *heap);
875 /* i915_gem.c */
876 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
877 struct drm_file *file_priv);
878 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
879 struct drm_file *file_priv);
880 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
881 struct drm_file *file_priv);
882 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
883 struct drm_file *file_priv);
884 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
885 struct drm_file *file_priv);
886 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
887 struct drm_file *file_priv);
888 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
889 struct drm_file *file_priv);
890 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
891 struct drm_file *file_priv);
892 int i915_gem_execbuffer(struct drm_device *dev, void *data,
893 struct drm_file *file_priv);
894 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
895 struct drm_file *file_priv);
896 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
897 struct drm_file *file_priv);
898 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
899 struct drm_file *file_priv);
900 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
901 struct drm_file *file_priv);
902 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
903 struct drm_file *file_priv);
904 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
905 struct drm_file *file_priv);
906 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
907 struct drm_file *file_priv);
908 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
909 struct drm_file *file_priv);
910 int i915_gem_set_tiling(struct drm_device *dev, void *data,
911 struct drm_file *file_priv);
912 int i915_gem_get_tiling(struct drm_device *dev, void *data,
913 struct drm_file *file_priv);
914 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
915 struct drm_file *file_priv);
916 void i915_gem_load(struct drm_device *dev);
917 int i915_gem_init_object(struct drm_gem_object *obj);
918 struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev,
919 size_t size);
920 void i915_gem_free_object(struct drm_gem_object *obj);
921 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
922 void i915_gem_object_unpin(struct drm_gem_object *obj);
923 int i915_gem_object_unbind(struct drm_gem_object *obj);
924 void i915_gem_release_mmap(struct drm_gem_object *obj);
925 void i915_gem_lastclose(struct drm_device *dev);
926 uint32_t i915_get_gem_seqno(struct drm_device *dev,
927 struct intel_ring_buffer *ring);
928 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
929 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
930 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
931 void i915_gem_retire_requests(struct drm_device *dev,
932 struct intel_ring_buffer *ring);
933 void i915_gem_retire_work_handler(struct work_struct *work);
934 void i915_gem_clflush_object(struct drm_gem_object *obj);
935 int i915_gem_object_set_domain(struct drm_gem_object *obj,
936 uint32_t read_domains,
937 uint32_t write_domain);
938 int i915_gem_init_ringbuffer(struct drm_device *dev);
939 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
940 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
941 unsigned long end);
942 int i915_gem_idle(struct drm_device *dev);
943 uint32_t i915_add_request(struct drm_device *dev,
944 struct drm_file *file_priv,
945 uint32_t flush_domains,
946 struct intel_ring_buffer *ring);
947 int i915_do_wait_request(struct drm_device *dev,
948 uint32_t seqno, int interruptible,
949 struct intel_ring_buffer *ring);
950 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
951 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
952 int write);
953 int i915_gem_object_set_to_display_plane(struct drm_gem_object *obj);
954 int i915_gem_attach_phys_object(struct drm_device *dev,
955 struct drm_gem_object *obj, int id);
956 void i915_gem_detach_phys_object(struct drm_device *dev,
957 struct drm_gem_object *obj);
958 void i915_gem_free_all_phys_object(struct drm_device *dev);
959 int i915_gem_object_get_pages(struct drm_gem_object *obj, gfp_t gfpmask);
960 void i915_gem_object_put_pages(struct drm_gem_object *obj);
961 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
962 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
963
964 void i915_gem_shrinker_init(void);
965 void i915_gem_shrinker_exit(void);
966
967 /* i915_gem_tiling.c */
968 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
969 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
970 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
971 bool i915_tiling_ok(struct drm_device *dev, int stride, int size,
972 int tiling_mode);
973 bool i915_gem_object_fence_offset_ok(struct drm_gem_object *obj,
974 int tiling_mode);
975
976 /* i915_gem_debug.c */
977 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
978 const char *where, uint32_t mark);
979 #if WATCH_INACTIVE
980 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
981 #else
982 #define i915_verify_inactive(dev, file, line)
983 #endif
984 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
985 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
986 const char *where, uint32_t mark);
987 void i915_dump_lru(struct drm_device *dev, const char *where);
988
989 /* i915_debugfs.c */
990 int i915_debugfs_init(struct drm_minor *minor);
991 void i915_debugfs_cleanup(struct drm_minor *minor);
992
993 /* i915_suspend.c */
994 extern int i915_save_state(struct drm_device *dev);
995 extern int i915_restore_state(struct drm_device *dev);
996
997 /* i915_suspend.c */
998 extern int i915_save_state(struct drm_device *dev);
999 extern int i915_restore_state(struct drm_device *dev);
1000
1001 #ifdef CONFIG_ACPI
1002 /* i915_opregion.c */
1003 extern int intel_opregion_init(struct drm_device *dev, int resume);
1004 extern void intel_opregion_free(struct drm_device *dev, int suspend);
1005 extern void opregion_asle_intr(struct drm_device *dev);
1006 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
1007 extern void opregion_enable_asle(struct drm_device *dev);
1008 #else
1009 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
1010 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
1011 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
1012 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
1013 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
1014 #endif
1015
1016 /* modesetting */
1017 extern void intel_modeset_init(struct drm_device *dev);
1018 extern void intel_modeset_cleanup(struct drm_device *dev);
1019 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1020 extern void i8xx_disable_fbc(struct drm_device *dev);
1021 extern void g4x_disable_fbc(struct drm_device *dev);
1022 extern void intel_disable_fbc(struct drm_device *dev);
1023 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1024 extern bool intel_fbc_enabled(struct drm_device *dev);
1025 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1026 extern void intel_detect_pch (struct drm_device *dev);
1027 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1028
1029 /**
1030 * Lock test for when it's just for synchronization of ring access.
1031 *
1032 * In that case, we don't need to do it when GEM is initialized as nobody else
1033 * has access to the ring.
1034 */
1035 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
1036 if (((drm_i915_private_t *)dev->dev_private)->render_ring.gem_object \
1037 == NULL) \
1038 LOCK_TEST_WITH_RETURN(dev, file_priv); \
1039 } while (0)
1040
1041 #define I915_READ(reg) readl(dev_priv->regs + (reg))
1042 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
1043 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
1044 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
1045 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
1046 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
1047 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
1048 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
1049 #define POSTING_READ(reg) (void)I915_READ(reg)
1050 #define POSTING_READ16(reg) (void)I915_READ16(reg)
1051
1052 #define I915_VERBOSE 0
1053
1054 #define BEGIN_LP_RING(n) do { \
1055 drm_i915_private_t *dev_priv = dev->dev_private; \
1056 if (I915_VERBOSE) \
1057 DRM_DEBUG(" BEGIN_LP_RING %x\n", (int)(n)); \
1058 intel_ring_begin(dev, &dev_priv->render_ring, 4*(n)); \
1059 } while (0)
1060
1061
1062 #define OUT_RING(x) do { \
1063 drm_i915_private_t *dev_priv = dev->dev_private; \
1064 if (I915_VERBOSE) \
1065 DRM_DEBUG(" OUT_RING %x\n", (int)(x)); \
1066 intel_ring_emit(dev, &dev_priv->render_ring, x); \
1067 } while (0)
1068
1069 #define ADVANCE_LP_RING() do { \
1070 drm_i915_private_t *dev_priv = dev->dev_private; \
1071 if (I915_VERBOSE) \
1072 DRM_DEBUG("ADVANCE_LP_RING %x\n", \
1073 dev_priv->render_ring.tail); \
1074 intel_ring_advance(dev, &dev_priv->render_ring); \
1075 } while(0)
1076
1077 /**
1078 * Reads a dword out of the status page, which is written to from the command
1079 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
1080 * MI_STORE_DATA_IMM.
1081 *
1082 * The following dwords have a reserved meaning:
1083 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
1084 * 0x04: ring 0 head pointer
1085 * 0x05: ring 1 head pointer (915-class)
1086 * 0x06: ring 2 head pointer (915-class)
1087 * 0x10-0x1b: Context status DWords (GM45)
1088 * 0x1f: Last written status offset. (GM45)
1089 *
1090 * The area from dword 0x20 to 0x3ff is available for driver usage.
1091 */
1092 #define READ_HWSP(dev_priv, reg) (((volatile u32 *)\
1093 (dev_priv->render_ring.status_page.page_addr))[reg])
1094 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1095 #define I915_GEM_HWS_INDEX 0x20
1096 #define I915_BREADCRUMB_INDEX 0x21
1097
1098 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1099
1100 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1101 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1102 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1103 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1104 #define IS_GEN2(dev) (INTEL_INFO(dev)->is_i8xx)
1105 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1106 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1107 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1108 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1109 #define IS_I965G(dev) (INTEL_INFO(dev)->is_i965g)
1110 #define IS_I965GM(dev) (INTEL_INFO(dev)->is_i965gm)
1111 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1112 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1113 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1114 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1115 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1116 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1117 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1118 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1119 #define IS_IRONLAKE(dev) (INTEL_INFO(dev)->is_ironlake)
1120 #define IS_I9XX(dev) (INTEL_INFO(dev)->is_i9xx)
1121 #define IS_GEN6(dev) (INTEL_INFO(dev)->is_gen6)
1122 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1123
1124 #define IS_GEN3(dev) (IS_I915G(dev) || \
1125 IS_I915GM(dev) || \
1126 IS_I945G(dev) || \
1127 IS_I945GM(dev) || \
1128 IS_G33(dev) || \
1129 IS_PINEVIEW(dev))
1130 #define IS_GEN4(dev) ((dev)->pci_device == 0x2972 || \
1131 (dev)->pci_device == 0x2982 || \
1132 (dev)->pci_device == 0x2992 || \
1133 (dev)->pci_device == 0x29A2 || \
1134 (dev)->pci_device == 0x2A02 || \
1135 (dev)->pci_device == 0x2A12 || \
1136 (dev)->pci_device == 0x2E02 || \
1137 (dev)->pci_device == 0x2E12 || \
1138 (dev)->pci_device == 0x2E22 || \
1139 (dev)->pci_device == 0x2E32 || \
1140 (dev)->pci_device == 0x2A42 || \
1141 (dev)->pci_device == 0x2E42)
1142
1143 #define HAS_BSD(dev) (IS_IRONLAKE(dev) || IS_G4X(dev))
1144 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1145
1146 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1147 * rows, which changed the alignment requirements and fence programming.
1148 */
1149 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1150 IS_I915GM(dev)))
1151 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1152 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1153 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1154 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1155 #define SUPPORTS_TV(dev) (IS_I9XX(dev) && IS_MOBILE(dev) && \
1156 !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev) && \
1157 !IS_GEN6(dev))
1158 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1159 /* dsparb controlled by hw only */
1160 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1161
1162 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1163 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1164 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1165 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1166
1167 #define HAS_PCH_SPLIT(dev) (IS_IRONLAKE(dev) || \
1168 IS_GEN6(dev))
1169 #define HAS_PIPE_CONTROL(dev) (IS_IRONLAKE(dev) || IS_GEN6(dev))
1170
1171 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1172 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1173
1174 #define PRIMARY_RINGBUFFER_SIZE (128*1024)
1175
1176 #endif
Linux kernel - Deliverables
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