1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include <linux/io-mapping.h>
41 #include <linux/i2c.h>
42 #include <linux/i2c-algo-bit.h>
43 #include <drm/intel-gtt.h>
44 #include <linux/backlight.h>
45 #include <linux/hashtable.h>
46 #include <linux/intel-iommu.h>
47 #include <linux/kref.h>
48 #include <linux/pm_qos.h>
50 /* General customization:
53 #define DRIVER_NAME "i915"
54 #define DRIVER_DESC "Intel Graphics"
55 #define DRIVER_DATE "20140822"
63 I915_MAX_PIPES
= _PIPE_EDP
65 #define pipe_name(p) ((p) + 'A')
74 #define transcoder_name(t) ((t) + 'A')
81 #define plane_name(p) ((p) + 'A')
83 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
93 #define port_name(p) ((p) + 'A')
95 #define I915_NUM_PHYS_VLV 2
107 enum intel_display_power_domain
{
111 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
112 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
113 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
114 POWER_DOMAIN_TRANSCODER_A
,
115 POWER_DOMAIN_TRANSCODER_B
,
116 POWER_DOMAIN_TRANSCODER_C
,
117 POWER_DOMAIN_TRANSCODER_EDP
,
118 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
119 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
120 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
121 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
122 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
123 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
124 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
125 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
126 POWER_DOMAIN_PORT_DSI
,
127 POWER_DOMAIN_PORT_CRT
,
128 POWER_DOMAIN_PORT_OTHER
,
137 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
138 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
139 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
140 #define POWER_DOMAIN_TRANSCODER(tran) \
141 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
142 (tran) + POWER_DOMAIN_TRANSCODER_A)
146 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
147 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
157 #define I915_GEM_GPU_DOMAINS \
158 (I915_GEM_DOMAIN_RENDER | \
159 I915_GEM_DOMAIN_SAMPLER | \
160 I915_GEM_DOMAIN_COMMAND | \
161 I915_GEM_DOMAIN_INSTRUCTION | \
162 I915_GEM_DOMAIN_VERTEX)
164 #define for_each_pipe(__dev_priv, __p) \
165 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
166 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
168 #define for_each_crtc(dev, crtc) \
169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
171 #define for_each_intel_crtc(dev, intel_crtc) \
172 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
174 #define for_each_intel_encoder(dev, intel_encoder) \
175 list_for_each_entry(intel_encoder, \
176 &(dev)->mode_config.encoder_list, \
179 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
180 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
181 if ((intel_encoder)->base.crtc == (__crtc))
183 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
184 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
185 if ((intel_connector)->base.encoder == (__encoder))
187 #define for_each_power_domain(domain, mask) \
188 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
189 if ((1 << (domain)) & (mask))
191 struct drm_i915_private
;
192 struct i915_mmu_object
;
195 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
196 /* real shared dpll ids must be >= 0 */
197 DPLL_ID_PCH_PLL_A
= 0,
198 DPLL_ID_PCH_PLL_B
= 1,
202 #define I915_NUM_PLLS 2
204 struct intel_dpll_hw_state
{
215 struct intel_shared_dpll
{
216 int refcount
; /* count of number of CRTCs sharing this PLL */
217 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
218 bool on
; /* is the PLL actually active? Disabled during modeset */
220 /* should match the index in the dev_priv->shared_dplls array */
221 enum intel_dpll_id id
;
222 struct intel_dpll_hw_state hw_state
;
223 /* The mode_set hook is optional and should be used together with the
224 * intel_prepare_shared_dpll function. */
225 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
226 struct intel_shared_dpll
*pll
);
227 void (*enable
)(struct drm_i915_private
*dev_priv
,
228 struct intel_shared_dpll
*pll
);
229 void (*disable
)(struct drm_i915_private
*dev_priv
,
230 struct intel_shared_dpll
*pll
);
231 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
232 struct intel_shared_dpll
*pll
,
233 struct intel_dpll_hw_state
*hw_state
);
236 /* Used by dp and fdi links */
237 struct intel_link_m_n
{
245 void intel_link_compute_m_n(int bpp
, int nlanes
,
246 int pixel_clock
, int link_clock
,
247 struct intel_link_m_n
*m_n
);
249 /* Interface history:
252 * 1.2: Add Power Management
253 * 1.3: Add vblank support
254 * 1.4: Fix cmdbuffer path, add heap destroy
255 * 1.5: Add vblank pipe configuration
256 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
257 * - Support vertical blank on secondary display pipe
259 #define DRIVER_MAJOR 1
260 #define DRIVER_MINOR 6
261 #define DRIVER_PATCHLEVEL 0
263 #define WATCH_LISTS 0
266 struct opregion_header
;
267 struct opregion_acpi
;
268 struct opregion_swsci
;
269 struct opregion_asle
;
271 struct intel_opregion
{
272 struct opregion_header __iomem
*header
;
273 struct opregion_acpi __iomem
*acpi
;
274 struct opregion_swsci __iomem
*swsci
;
275 u32 swsci_gbda_sub_functions
;
276 u32 swsci_sbcb_sub_functions
;
277 struct opregion_asle __iomem
*asle
;
279 u32 __iomem
*lid_state
;
280 struct work_struct asle_work
;
282 #define OPREGION_SIZE (8*1024)
284 struct intel_overlay
;
285 struct intel_overlay_error_state
;
287 struct drm_i915_master_private
{
288 drm_local_map_t
*sarea
;
289 struct _drm_i915_sarea
*sarea_priv
;
291 #define I915_FENCE_REG_NONE -1
292 #define I915_MAX_NUM_FENCES 32
293 /* 32 fences + sign bit for FENCE_REG_NONE */
294 #define I915_MAX_NUM_FENCE_BITS 6
296 struct drm_i915_fence_reg
{
297 struct list_head lru_list
;
298 struct drm_i915_gem_object
*obj
;
302 struct sdvo_device_mapping
{
311 struct intel_display_error_state
;
313 struct drm_i915_error_state
{
321 /* Generic register state */
329 u32 error
; /* gen6+ */
330 u32 err_int
; /* gen7 */
336 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
337 u64 fence
[I915_MAX_NUM_FENCES
];
338 struct intel_overlay_error_state
*overlay
;
339 struct intel_display_error_state
*display
;
340 struct drm_i915_error_object
*semaphore_obj
;
342 struct drm_i915_error_ring
{
344 /* Software tracked state */
347 enum intel_ring_hangcheck_action hangcheck_action
;
350 /* our own tracking of ring head and tail */
354 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
372 u32 rc_psmi
; /* sleep state */
373 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
375 struct drm_i915_error_object
{
379 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
381 struct drm_i915_error_request
{
396 char comm
[TASK_COMM_LEN
];
397 } ring
[I915_NUM_RINGS
];
399 struct drm_i915_error_buffer
{
406 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
414 } **active_bo
, **pinned_bo
;
416 u32
*active_bo_count
, *pinned_bo_count
;
420 struct intel_connector
;
421 struct intel_crtc_config
;
422 struct intel_plane_config
;
427 struct drm_i915_display_funcs
{
428 bool (*fbc_enabled
)(struct drm_device
*dev
);
429 void (*enable_fbc
)(struct drm_crtc
*crtc
);
430 void (*disable_fbc
)(struct drm_device
*dev
);
431 int (*get_display_clock_speed
)(struct drm_device
*dev
);
432 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
434 * find_dpll() - Find the best values for the PLL
435 * @limit: limits for the PLL
436 * @crtc: current CRTC
437 * @target: target frequency in kHz
438 * @refclk: reference clock frequency in kHz
439 * @match_clock: if provided, @best_clock P divider must
440 * match the P divider from @match_clock
441 * used for LVDS downclocking
442 * @best_clock: best PLL values found
444 * Returns true on success, false on failure.
446 bool (*find_dpll
)(const struct intel_limit
*limit
,
447 struct drm_crtc
*crtc
,
448 int target
, int refclk
,
449 struct dpll
*match_clock
,
450 struct dpll
*best_clock
);
451 void (*update_wm
)(struct drm_crtc
*crtc
);
452 void (*update_sprite_wm
)(struct drm_plane
*plane
,
453 struct drm_crtc
*crtc
,
454 uint32_t sprite_width
, uint32_t sprite_height
,
455 int pixel_size
, bool enable
, bool scaled
);
456 void (*modeset_global_resources
)(struct drm_device
*dev
);
457 /* Returns the active state of the crtc, and if the crtc is active,
458 * fills out the pipe-config with the hw state. */
459 bool (*get_pipe_config
)(struct intel_crtc
*,
460 struct intel_crtc_config
*);
461 void (*get_plane_config
)(struct intel_crtc
*,
462 struct intel_plane_config
*);
463 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
465 struct drm_framebuffer
*old_fb
);
466 void (*crtc_enable
)(struct drm_crtc
*crtc
);
467 void (*crtc_disable
)(struct drm_crtc
*crtc
);
468 void (*off
)(struct drm_crtc
*crtc
);
469 void (*write_eld
)(struct drm_connector
*connector
,
470 struct drm_crtc
*crtc
,
471 struct drm_display_mode
*mode
);
472 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
473 void (*init_clock_gating
)(struct drm_device
*dev
);
474 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
475 struct drm_framebuffer
*fb
,
476 struct drm_i915_gem_object
*obj
,
477 struct intel_engine_cs
*ring
,
479 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
480 struct drm_framebuffer
*fb
,
482 void (*hpd_irq_setup
)(struct drm_device
*dev
);
483 /* clock updates for mode set */
485 /* render clock increase/decrease */
486 /* display clock increase/decrease */
487 /* pll clock increase/decrease */
489 int (*setup_backlight
)(struct intel_connector
*connector
);
490 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
491 void (*set_backlight
)(struct intel_connector
*connector
,
493 void (*disable_backlight
)(struct intel_connector
*connector
);
494 void (*enable_backlight
)(struct intel_connector
*connector
);
497 struct intel_uncore_funcs
{
498 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
500 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
503 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
504 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
505 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
506 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
508 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
509 uint8_t val
, bool trace
);
510 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
511 uint16_t val
, bool trace
);
512 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
513 uint32_t val
, bool trace
);
514 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
515 uint64_t val
, bool trace
);
518 struct intel_uncore
{
519 spinlock_t lock
; /** lock is also taken in irq contexts. */
521 struct intel_uncore_funcs funcs
;
524 unsigned forcewake_count
;
526 unsigned fw_rendercount
;
527 unsigned fw_mediacount
;
529 struct timer_list force_wake_timer
;
532 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
533 func(is_mobile) sep \
536 func(is_i945gm) sep \
538 func(need_gfx_hws) sep \
540 func(is_pineview) sep \
541 func(is_broadwater) sep \
542 func(is_crestline) sep \
543 func(is_ivybridge) sep \
544 func(is_valleyview) sep \
545 func(is_haswell) sep \
546 func(is_preliminary) sep \
548 func(has_pipe_cxsr) sep \
549 func(has_hotplug) sep \
550 func(cursor_needs_physical) sep \
551 func(has_overlay) sep \
552 func(overlay_needs_physical) sep \
553 func(supports_tv) sep \
558 #define DEFINE_FLAG(name) u8 name:1
559 #define SEP_SEMICOLON ;
561 struct intel_device_info
{
562 u32 display_mmio_offset
;
565 u8 num_sprites
[I915_MAX_PIPES
];
567 u8 ring_mask
; /* Rings supported by the HW */
568 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
569 /* Register offsets for the various display pipes and transcoders */
570 int pipe_offsets
[I915_MAX_TRANSCODERS
];
571 int trans_offsets
[I915_MAX_TRANSCODERS
];
572 int palette_offsets
[I915_MAX_PIPES
];
573 int cursor_offsets
[I915_MAX_PIPES
];
579 enum i915_cache_level
{
581 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
582 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
583 caches, eg sampler/render caches, and the
584 large Last-Level-Cache. LLC is coherent with
585 the CPU, but L3 is only visible to the GPU. */
586 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
589 struct i915_ctx_hang_stats
{
590 /* This context had batch pending when hang was declared */
591 unsigned batch_pending
;
593 /* This context had batch active when hang was declared */
594 unsigned batch_active
;
596 /* Time when this context was last blamed for a GPU reset */
597 unsigned long guilty_ts
;
599 /* This context is banned to submit more work */
603 /* This must match up with the value previously used for execbuf2.rsvd1. */
604 #define DEFAULT_CONTEXT_HANDLE 0
606 * struct intel_context - as the name implies, represents a context.
607 * @ref: reference count.
608 * @user_handle: userspace tracking identity for this context.
609 * @remap_slice: l3 row remapping information.
610 * @file_priv: filp associated with this context (NULL for global default
612 * @hang_stats: information about the role of this context in possible GPU
614 * @vm: virtual memory space used by this context.
615 * @legacy_hw_ctx: render context backing object and whether it is correctly
616 * initialized (legacy ring submission mechanism only).
617 * @link: link in the global list of contexts.
619 * Contexts are memory images used by the hardware to store copies of their
622 struct intel_context
{
626 struct drm_i915_file_private
*file_priv
;
627 struct i915_ctx_hang_stats hang_stats
;
628 struct i915_hw_ppgtt
*ppgtt
;
630 /* Legacy ring buffer submission */
632 struct drm_i915_gem_object
*rcs_state
;
638 struct drm_i915_gem_object
*state
;
639 struct intel_ringbuffer
*ringbuf
;
640 } engine
[I915_NUM_RINGS
];
642 struct list_head link
;
652 struct drm_mm_node compressed_fb
;
653 struct drm_mm_node
*compressed_llb
;
657 struct intel_fbc_work
{
658 struct delayed_work work
;
659 struct drm_crtc
*crtc
;
660 struct drm_framebuffer
*fb
;
664 FBC_OK
, /* FBC is enabled */
665 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
666 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
667 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
668 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
669 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
670 FBC_BAD_PLANE
, /* fbc not supported on plane */
671 FBC_NOT_TILED
, /* buffer not tiled */
672 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
674 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
679 struct intel_connector
*connector
;
687 struct intel_dp
*enabled
;
689 struct delayed_work work
;
690 unsigned busy_frontbuffer_bits
;
694 PCH_NONE
= 0, /* No PCH present */
695 PCH_IBX
, /* Ibexpeak PCH */
696 PCH_CPT
, /* Cougarpoint PCH */
697 PCH_LPT
, /* Lynxpoint PCH */
701 enum intel_sbi_destination
{
706 #define QUIRK_PIPEA_FORCE (1<<0)
707 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
708 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
709 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
712 struct intel_fbc_work
;
715 struct i2c_adapter adapter
;
719 struct i2c_algo_bit_data bit_algo
;
720 struct drm_i915_private
*dev_priv
;
723 struct i915_suspend_saved_registers
{
744 u32 saveTRANS_HTOTAL_A
;
745 u32 saveTRANS_HBLANK_A
;
746 u32 saveTRANS_HSYNC_A
;
747 u32 saveTRANS_VTOTAL_A
;
748 u32 saveTRANS_VBLANK_A
;
749 u32 saveTRANS_VSYNC_A
;
757 u32 savePFIT_PGM_RATIOS
;
758 u32 saveBLC_HIST_CTL
;
760 u32 saveBLC_PWM_CTL2
;
761 u32 saveBLC_HIST_CTL_B
;
762 u32 saveBLC_CPU_PWM_CTL
;
763 u32 saveBLC_CPU_PWM_CTL2
;
776 u32 saveTRANS_HTOTAL_B
;
777 u32 saveTRANS_HBLANK_B
;
778 u32 saveTRANS_HSYNC_B
;
779 u32 saveTRANS_VTOTAL_B
;
780 u32 saveTRANS_VBLANK_B
;
781 u32 saveTRANS_VSYNC_B
;
795 u32 savePP_ON_DELAYS
;
796 u32 savePP_OFF_DELAYS
;
804 u32 savePFIT_CONTROL
;
805 u32 save_palette_a
[256];
806 u32 save_palette_b
[256];
817 u32 saveCACHE_MODE_0
;
818 u32 saveMI_ARB_STATE
;
829 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
840 u32 savePIPEA_GMCH_DATA_M
;
841 u32 savePIPEB_GMCH_DATA_M
;
842 u32 savePIPEA_GMCH_DATA_N
;
843 u32 savePIPEB_GMCH_DATA_N
;
844 u32 savePIPEA_DP_LINK_M
;
845 u32 savePIPEB_DP_LINK_M
;
846 u32 savePIPEA_DP_LINK_N
;
847 u32 savePIPEB_DP_LINK_N
;
858 u32 savePCH_DREF_CONTROL
;
859 u32 saveDISP_ARB_CTL
;
860 u32 savePIPEA_DATA_M1
;
861 u32 savePIPEA_DATA_N1
;
862 u32 savePIPEA_LINK_M1
;
863 u32 savePIPEA_LINK_N1
;
864 u32 savePIPEB_DATA_M1
;
865 u32 savePIPEB_DATA_N1
;
866 u32 savePIPEB_LINK_M1
;
867 u32 savePIPEB_LINK_N1
;
868 u32 saveMCHBAR_RENDER_STANDBY
;
869 u32 savePCH_PORT_HOTPLUG
;
872 struct vlv_s0ix_state
{
879 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
880 u32 media_max_req_count
;
881 u32 gfx_max_req_count
;
913 /* Display 1 CZ domain */
918 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
920 /* GT SA CZ domain */
927 /* Display 2 CZ domain */
933 struct intel_rps_ei
{
939 struct intel_gen6_power_mgmt
{
940 /* work and pm_iir are protected by dev_priv->irq_lock */
941 struct work_struct work
;
944 /* Frequencies are stored in potentially platform dependent multiples.
945 * In other words, *_freq needs to be multiplied by X to be interesting.
946 * Soft limits are those which are used for the dynamic reclocking done
947 * by the driver (raise frequencies under heavy loads, and lower for
948 * lighter loads). Hard limits are those imposed by the hardware.
950 * A distinction is made for overclocking, which is never enabled by
951 * default, and is considered to be above the hard limit if it's
954 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
955 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
956 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
957 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
958 u8 min_freq
; /* AKA RPn. Minimum frequency */
959 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
960 u8 rp1_freq
; /* "less than" RP0 power/freqency */
961 u8 rp0_freq
; /* Non-overclocked max frequency. */
964 u32 ei_interrupt_count
;
967 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
970 struct delayed_work delayed_resume_work
;
972 /* manual wa residency calculations */
973 struct intel_rps_ei up_ei
, down_ei
;
976 * Protects RPS/RC6 register access and PCU communication.
977 * Must be taken after struct_mutex if nested.
979 struct mutex hw_lock
;
982 /* defined intel_pm.c */
983 extern spinlock_t mchdev_lock
;
985 struct intel_ilk_power_mgmt
{
993 unsigned long last_time1
;
994 unsigned long chipset_power
;
997 unsigned long gfx_power
;
1003 struct drm_i915_gem_object
*pwrctx
;
1004 struct drm_i915_gem_object
*renderctx
;
1007 struct drm_i915_private
;
1008 struct i915_power_well
;
1010 struct i915_power_well_ops
{
1012 * Synchronize the well's hw state to match the current sw state, for
1013 * example enable/disable it based on the current refcount. Called
1014 * during driver init and resume time, possibly after first calling
1015 * the enable/disable handlers.
1017 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1018 struct i915_power_well
*power_well
);
1020 * Enable the well and resources that depend on it (for example
1021 * interrupts located on the well). Called after the 0->1 refcount
1024 void (*enable
)(struct drm_i915_private
*dev_priv
,
1025 struct i915_power_well
*power_well
);
1027 * Disable the well and resources that depend on it. Called after
1028 * the 1->0 refcount transition.
1030 void (*disable
)(struct drm_i915_private
*dev_priv
,
1031 struct i915_power_well
*power_well
);
1032 /* Returns the hw enabled state. */
1033 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1034 struct i915_power_well
*power_well
);
1037 /* Power well structure for haswell */
1038 struct i915_power_well
{
1041 /* power well enable/disable usage count */
1043 /* cached hw enabled state */
1045 unsigned long domains
;
1047 const struct i915_power_well_ops
*ops
;
1050 struct i915_power_domains
{
1052 * Power wells needed for initialization at driver init and suspend
1053 * time are on. They are kept on until after the first modeset.
1057 int power_well_count
;
1060 int domain_use_count
[POWER_DOMAIN_NUM
];
1061 struct i915_power_well
*power_wells
;
1064 struct i915_dri1_state
{
1065 unsigned allow_batchbuffer
: 1;
1066 u32 __iomem
*gfx_hws_cpu_addr
;
1077 struct i915_ums_state
{
1079 * Flag if the X Server, and thus DRM, is not currently in
1080 * control of the device.
1082 * This is set between LeaveVT and EnterVT. It needs to be
1083 * replaced with a semaphore. It also needs to be
1084 * transitioned away from for kernel modesetting.
1089 #define MAX_L3_SLICES 2
1090 struct intel_l3_parity
{
1091 u32
*remap_info
[MAX_L3_SLICES
];
1092 struct work_struct error_work
;
1096 struct i915_gem_mm
{
1097 /** Memory allocator for GTT stolen memory */
1098 struct drm_mm stolen
;
1099 /** List of all objects in gtt_space. Used to restore gtt
1100 * mappings on resume */
1101 struct list_head bound_list
;
1103 * List of objects which are not bound to the GTT (thus
1104 * are idle and not used by the GPU) but still have
1105 * (presumably uncached) pages still attached.
1107 struct list_head unbound_list
;
1109 /** Usable portion of the GTT for GEM */
1110 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1112 /** PPGTT used for aliasing the PPGTT with the GTT */
1113 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1115 struct notifier_block oom_notifier
;
1116 struct shrinker shrinker
;
1117 bool shrinker_no_lock_stealing
;
1119 /** LRU list of objects with fence regs on them. */
1120 struct list_head fence_list
;
1123 * We leave the user IRQ off as much as possible,
1124 * but this means that requests will finish and never
1125 * be retired once the system goes idle. Set a timer to
1126 * fire periodically while the ring is running. When it
1127 * fires, go retire requests.
1129 struct delayed_work retire_work
;
1132 * When we detect an idle GPU, we want to turn on
1133 * powersaving features. So once we see that there
1134 * are no more requests outstanding and no more
1135 * arrive within a small period of time, we fire
1136 * off the idle_work.
1138 struct delayed_work idle_work
;
1141 * Are we in a non-interruptible section of code like
1147 * Is the GPU currently considered idle, or busy executing userspace
1148 * requests? Whilst idle, we attempt to power down the hardware and
1149 * display clocks. In order to reduce the effect on performance, there
1150 * is a slight delay before we do so.
1154 /* the indicator for dispatch video commands on two BSD rings */
1155 int bsd_ring_dispatch_index
;
1157 /** Bit 6 swizzling required for X tiling */
1158 uint32_t bit_6_swizzle_x
;
1159 /** Bit 6 swizzling required for Y tiling */
1160 uint32_t bit_6_swizzle_y
;
1162 /* accounting, useful for userland debugging */
1163 spinlock_t object_stat_lock
;
1164 size_t object_memory
;
1168 struct drm_i915_error_state_buf
{
1169 struct drm_i915_private
*i915
;
1178 struct i915_error_state_file_priv
{
1179 struct drm_device
*dev
;
1180 struct drm_i915_error_state
*error
;
1183 struct i915_gpu_error
{
1184 /* For hangcheck timer */
1185 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1186 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1187 /* Hang gpu twice in this window and your context gets banned */
1188 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1190 struct timer_list hangcheck_timer
;
1192 /* For reset and error_state handling. */
1194 /* Protected by the above dev->gpu_error.lock. */
1195 struct drm_i915_error_state
*first_error
;
1196 struct work_struct work
;
1199 unsigned long missed_irq_rings
;
1202 * State variable controlling the reset flow and count
1204 * This is a counter which gets incremented when reset is triggered,
1205 * and again when reset has been handled. So odd values (lowest bit set)
1206 * means that reset is in progress and even values that
1207 * (reset_counter >> 1):th reset was successfully completed.
1209 * If reset is not completed succesfully, the I915_WEDGE bit is
1210 * set meaning that hardware is terminally sour and there is no
1211 * recovery. All waiters on the reset_queue will be woken when
1214 * This counter is used by the wait_seqno code to notice that reset
1215 * event happened and it needs to restart the entire ioctl (since most
1216 * likely the seqno it waited for won't ever signal anytime soon).
1218 * This is important for lock-free wait paths, where no contended lock
1219 * naturally enforces the correct ordering between the bail-out of the
1220 * waiter and the gpu reset work code.
1222 atomic_t reset_counter
;
1224 #define I915_RESET_IN_PROGRESS_FLAG 1
1225 #define I915_WEDGED (1 << 31)
1228 * Waitqueue to signal when the reset has completed. Used by clients
1229 * that wait for dev_priv->mm.wedged to settle.
1231 wait_queue_head_t reset_queue
;
1233 /* Userspace knobs for gpu hang simulation;
1234 * combines both a ring mask, and extra flags
1237 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1238 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1240 /* For missed irq/seqno simulation. */
1241 unsigned int test_irq_rings
;
1243 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1244 bool reload_in_reset
;
1247 enum modeset_restore
{
1248 MODESET_ON_LID_OPEN
,
1253 struct ddi_vbt_port_info
{
1255 * This is an index in the HDMI/DVI DDI buffer translation table.
1256 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1257 * populate this field.
1259 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1260 uint8_t hdmi_level_shift
;
1262 uint8_t supports_dvi
:1;
1263 uint8_t supports_hdmi
:1;
1264 uint8_t supports_dp
:1;
1267 enum drrs_support_type
{
1268 DRRS_NOT_SUPPORTED
= 0,
1269 STATIC_DRRS_SUPPORT
= 1,
1270 SEAMLESS_DRRS_SUPPORT
= 2
1273 struct intel_vbt_data
{
1274 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1275 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1278 unsigned int int_tv_support
:1;
1279 unsigned int lvds_dither
:1;
1280 unsigned int lvds_vbt
:1;
1281 unsigned int int_crt_support
:1;
1282 unsigned int lvds_use_ssc
:1;
1283 unsigned int display_clock_mode
:1;
1284 unsigned int fdi_rx_polarity_inverted
:1;
1285 unsigned int has_mipi
:1;
1287 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1289 enum drrs_support_type drrs_type
;
1294 int edp_preemphasis
;
1296 bool edp_initialized
;
1299 struct edp_power_seq edp_pps
;
1304 bool active_low_pwm
;
1305 u8 min_brightness
; /* min_brightness/255 of max */
1312 struct mipi_config
*config
;
1313 struct mipi_pps_data
*pps
;
1317 u8
*sequence
[MIPI_SEQ_MAX
];
1323 union child_device_config
*child_dev
;
1325 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1328 enum intel_ddb_partitioning
{
1330 INTEL_DDB_PART_5_6
, /* IVB+ */
1333 struct intel_wm_level
{
1341 struct ilk_wm_values
{
1342 uint32_t wm_pipe
[3];
1344 uint32_t wm_lp_spr
[3];
1345 uint32_t wm_linetime
[3];
1347 enum intel_ddb_partitioning partitioning
;
1351 * This struct helps tracking the state needed for runtime PM, which puts the
1352 * device in PCI D3 state. Notice that when this happens, nothing on the
1353 * graphics device works, even register access, so we don't get interrupts nor
1356 * Every piece of our code that needs to actually touch the hardware needs to
1357 * either call intel_runtime_pm_get or call intel_display_power_get with the
1358 * appropriate power domain.
1360 * Our driver uses the autosuspend delay feature, which means we'll only really
1361 * suspend if we stay with zero refcount for a certain amount of time. The
1362 * default value is currently very conservative (see intel_init_runtime_pm), but
1363 * it can be changed with the standard runtime PM files from sysfs.
1365 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1366 * goes back to false exactly before we reenable the IRQs. We use this variable
1367 * to check if someone is trying to enable/disable IRQs while they're supposed
1368 * to be disabled. This shouldn't happen and we'll print some error messages in
1371 * For more, read the Documentation/power/runtime_pm.txt.
1373 struct i915_runtime_pm
{
1375 bool _irqs_disabled
;
1378 enum intel_pipe_crc_source
{
1379 INTEL_PIPE_CRC_SOURCE_NONE
,
1380 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1381 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1382 INTEL_PIPE_CRC_SOURCE_PF
,
1383 INTEL_PIPE_CRC_SOURCE_PIPE
,
1384 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1385 INTEL_PIPE_CRC_SOURCE_TV
,
1386 INTEL_PIPE_CRC_SOURCE_DP_B
,
1387 INTEL_PIPE_CRC_SOURCE_DP_C
,
1388 INTEL_PIPE_CRC_SOURCE_DP_D
,
1389 INTEL_PIPE_CRC_SOURCE_AUTO
,
1390 INTEL_PIPE_CRC_SOURCE_MAX
,
1393 struct intel_pipe_crc_entry
{
1398 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1399 struct intel_pipe_crc
{
1401 bool opened
; /* exclusive access to the result file */
1402 struct intel_pipe_crc_entry
*entries
;
1403 enum intel_pipe_crc_source source
;
1405 wait_queue_head_t wq
;
1408 struct i915_frontbuffer_tracking
{
1412 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1419 struct drm_i915_private
{
1420 struct drm_device
*dev
;
1421 struct kmem_cache
*slab
;
1423 const struct intel_device_info info
;
1425 int relative_constants_mode
;
1429 struct intel_uncore uncore
;
1431 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1434 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1435 * controller on different i2c buses. */
1436 struct mutex gmbus_mutex
;
1439 * Base address of the gmbus and gpio block.
1441 uint32_t gpio_mmio_base
;
1443 /* MMIO base address for MIPI regs */
1444 uint32_t mipi_mmio_base
;
1446 wait_queue_head_t gmbus_wait_queue
;
1448 struct pci_dev
*bridge_dev
;
1449 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1450 struct drm_i915_gem_object
*semaphore_obj
;
1451 uint32_t last_seqno
, next_seqno
;
1453 drm_dma_handle_t
*status_page_dmah
;
1454 struct resource mch_res
;
1456 /* protects the irq masks */
1457 spinlock_t irq_lock
;
1459 /* protects the mmio flip data */
1460 spinlock_t mmio_flip_lock
;
1462 bool display_irqs_enabled
;
1464 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1465 struct pm_qos_request pm_qos
;
1467 /* DPIO indirect register protection */
1468 struct mutex dpio_lock
;
1470 /** Cached value of IMR to avoid reads in updating the bitfield */
1473 u32 de_irq_mask
[I915_MAX_PIPES
];
1478 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1480 struct work_struct hotplug_work
;
1482 unsigned long hpd_last_jiffies
;
1487 HPD_MARK_DISABLED
= 2
1489 } hpd_stats
[HPD_NUM_PINS
];
1491 struct delayed_work hotplug_reenable_work
;
1493 struct i915_fbc fbc
;
1494 struct i915_drrs drrs
;
1495 struct intel_opregion opregion
;
1496 struct intel_vbt_data vbt
;
1499 struct intel_overlay
*overlay
;
1501 /* backlight registers and fields in struct intel_panel */
1502 spinlock_t backlight_lock
;
1505 bool no_aux_handshake
;
1507 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1508 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1509 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1511 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1512 unsigned int vlv_cdclk_freq
;
1515 * wq - Driver workqueue for GEM.
1517 * NOTE: Work items scheduled here are not allowed to grab any modeset
1518 * locks, for otherwise the flushing done in the pageflip code will
1519 * result in deadlocks.
1521 struct workqueue_struct
*wq
;
1523 /* Display functions */
1524 struct drm_i915_display_funcs display
;
1526 /* PCH chipset type */
1527 enum intel_pch pch_type
;
1528 unsigned short pch_id
;
1530 unsigned long quirks
;
1532 enum modeset_restore modeset_restore
;
1533 struct mutex modeset_restore_lock
;
1535 struct list_head vm_list
; /* Global list of all address spaces */
1536 struct i915_gtt gtt
; /* VM representing the global address space */
1538 struct i915_gem_mm mm
;
1539 #if defined(CONFIG_MMU_NOTIFIER)
1540 DECLARE_HASHTABLE(mmu_notifiers
, 7);
1543 /* Kernel Modesetting */
1545 struct sdvo_device_mapping sdvo_mappings
[2];
1547 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1548 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1549 wait_queue_head_t pending_flip_queue
;
1551 #ifdef CONFIG_DEBUG_FS
1552 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1555 int num_shared_dpll
;
1556 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1557 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1560 * workarounds are currently applied at different places and
1561 * changes are being done to consolidate them so exact count is
1562 * not clear at this point, use a max value for now.
1564 #define I915_MAX_WA_REGS 16
1568 /* bitmask representing WA bits */
1570 } intel_wa_regs
[I915_MAX_WA_REGS
];
1573 /* Reclocking support */
1574 bool render_reclock_avail
;
1575 bool lvds_downclock_avail
;
1576 /* indicates the reduced downclock for LVDS*/
1579 struct i915_frontbuffer_tracking fb_tracking
;
1583 bool mchbar_need_disable
;
1585 struct intel_l3_parity l3_parity
;
1587 /* Cannot be determined by PCIID. You must always read a register. */
1590 /* gen6+ rps state */
1591 struct intel_gen6_power_mgmt rps
;
1593 /* ilk-only ips/rps state. Everything in here is protected by the global
1594 * mchdev_lock in intel_pm.c */
1595 struct intel_ilk_power_mgmt ips
;
1597 struct i915_power_domains power_domains
;
1599 struct i915_psr psr
;
1601 struct i915_gpu_error gpu_error
;
1603 struct drm_i915_gem_object
*vlv_pctx
;
1605 #ifdef CONFIG_DRM_I915_FBDEV
1606 /* list of fbdev register on this device */
1607 struct intel_fbdev
*fbdev
;
1608 struct work_struct fbdev_suspend_work
;
1611 struct drm_property
*broadcast_rgb_property
;
1612 struct drm_property
*force_audio_property
;
1614 uint32_t hw_context_size
;
1615 struct list_head context_list
;
1620 struct i915_suspend_saved_registers regfile
;
1621 struct vlv_s0ix_state vlv_s0ix_state
;
1625 * Raw watermark latency values:
1626 * in 0.1us units for WM0,
1627 * in 0.5us units for WM1+.
1630 uint16_t pri_latency
[5];
1632 uint16_t spr_latency
[5];
1634 uint16_t cur_latency
[5];
1636 /* current hardware state */
1637 struct ilk_wm_values hw
;
1640 struct i915_runtime_pm pm
;
1642 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1643 u32 long_hpd_port_mask
;
1644 u32 short_hpd_port_mask
;
1645 struct work_struct dig_port_work
;
1648 * if we get a HPD irq from DP and a HPD irq from non-DP
1649 * the non-DP HPD could block the workqueue on a mode config
1650 * mutex getting, that userspace may have taken. However
1651 * userspace is waiting on the DP workqueue to run which is
1652 * blocked behind the non-DP one.
1654 struct workqueue_struct
*dp_wq
;
1656 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1658 struct i915_dri1_state dri1
;
1659 /* Old ums support infrastructure, same warning applies. */
1660 struct i915_ums_state ums
;
1662 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1664 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1665 struct intel_engine_cs
*ring
,
1666 struct intel_context
*ctx
,
1667 struct drm_i915_gem_execbuffer2
*args
,
1668 struct list_head
*vmas
,
1669 struct drm_i915_gem_object
*batch_obj
,
1670 u64 exec_start
, u32 flags
);
1671 int (*init_rings
)(struct drm_device
*dev
);
1672 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1673 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1677 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1678 * will be rejected. Instead look for a better place.
1682 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1684 return dev
->dev_private
;
1687 /* Iterate over initialised rings */
1688 #define for_each_ring(ring__, dev_priv__, i__) \
1689 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1690 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1692 enum hdmi_force_audio
{
1693 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1694 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1695 HDMI_AUDIO_AUTO
, /* trust EDID */
1696 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1699 #define I915_GTT_OFFSET_NONE ((u32)-1)
1701 struct drm_i915_gem_object_ops
{
1702 /* Interface between the GEM object and its backing storage.
1703 * get_pages() is called once prior to the use of the associated set
1704 * of pages before to binding them into the GTT, and put_pages() is
1705 * called after we no longer need them. As we expect there to be
1706 * associated cost with migrating pages between the backing storage
1707 * and making them available for the GPU (e.g. clflush), we may hold
1708 * onto the pages after they are no longer referenced by the GPU
1709 * in case they may be used again shortly (for example migrating the
1710 * pages to a different memory domain within the GTT). put_pages()
1711 * will therefore most likely be called when the object itself is
1712 * being released or under memory pressure (where we attempt to
1713 * reap pages for the shrinker).
1715 int (*get_pages
)(struct drm_i915_gem_object
*);
1716 void (*put_pages
)(struct drm_i915_gem_object
*);
1717 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1718 void (*release
)(struct drm_i915_gem_object
*);
1722 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1723 * considered to be the frontbuffer for the given plane interface-vise. This
1724 * doesn't mean that the hw necessarily already scans it out, but that any
1725 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1727 * We have one bit per pipe and per scanout plane type.
1729 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1730 #define INTEL_FRONTBUFFER_BITS \
1731 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1732 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1733 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1734 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1735 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1736 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1737 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1738 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1739 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1740 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1741 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1743 struct drm_i915_gem_object
{
1744 struct drm_gem_object base
;
1746 const struct drm_i915_gem_object_ops
*ops
;
1748 /** List of VMAs backed by this object */
1749 struct list_head vma_list
;
1751 /** Stolen memory for this object, instead of being backed by shmem. */
1752 struct drm_mm_node
*stolen
;
1753 struct list_head global_list
;
1755 struct list_head ring_list
;
1756 /** Used in execbuf to temporarily hold a ref */
1757 struct list_head obj_exec_link
;
1760 * This is set if the object is on the active lists (has pending
1761 * rendering and so a non-zero seqno), and is not set if it i s on
1762 * inactive (ready to be unbound) list.
1764 unsigned int active
:1;
1767 * This is set if the object has been written to since last bound
1770 unsigned int dirty
:1;
1773 * Fence register bits (if any) for this object. Will be set
1774 * as needed when mapped into the GTT.
1775 * Protected by dev->struct_mutex.
1777 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1780 * Advice: are the backing pages purgeable?
1782 unsigned int madv
:2;
1785 * Current tiling mode for the object.
1787 unsigned int tiling_mode
:2;
1789 * Whether the tiling parameters for the currently associated fence
1790 * register have changed. Note that for the purposes of tracking
1791 * tiling changes we also treat the unfenced register, the register
1792 * slot that the object occupies whilst it executes a fenced
1793 * command (such as BLT on gen2/3), as a "fence".
1795 unsigned int fence_dirty
:1;
1798 * Is the object at the current location in the gtt mappable and
1799 * fenceable? Used to avoid costly recalculations.
1801 unsigned int map_and_fenceable
:1;
1804 * Whether the current gtt mapping needs to be mappable (and isn't just
1805 * mappable by accident). Track pin and fault separate for a more
1806 * accurate mappable working set.
1808 unsigned int fault_mappable
:1;
1809 unsigned int pin_mappable
:1;
1810 unsigned int pin_display
:1;
1813 * Is the object to be mapped as read-only to the GPU
1814 * Only honoured if hardware has relevant pte bit
1816 unsigned long gt_ro
:1;
1817 unsigned int cache_level
:3;
1819 unsigned int has_aliasing_ppgtt_mapping
:1;
1820 unsigned int has_global_gtt_mapping
:1;
1821 unsigned int has_dma_mapping
:1;
1823 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1825 struct sg_table
*pages
;
1826 int pages_pin_count
;
1828 /* prime dma-buf support */
1829 void *dma_buf_vmapping
;
1832 struct intel_engine_cs
*ring
;
1834 /** Breadcrumb of last rendering to the buffer. */
1835 uint32_t last_read_seqno
;
1836 uint32_t last_write_seqno
;
1837 /** Breadcrumb of last fenced GPU access to the buffer. */
1838 uint32_t last_fenced_seqno
;
1840 /** Current tiling stride for the object, if it's tiled. */
1843 /** References from framebuffers, locks out tiling changes. */
1844 unsigned long framebuffer_references
;
1846 /** Record of address bit 17 of each page at last unbind. */
1847 unsigned long *bit_17
;
1849 /** User space pin count and filp owning the pin */
1850 unsigned long user_pin_count
;
1851 struct drm_file
*pin_filp
;
1853 /** for phy allocated objects */
1854 drm_dma_handle_t
*phys_handle
;
1857 struct i915_gem_userptr
{
1859 unsigned read_only
:1;
1860 unsigned workers
:4;
1861 #define I915_GEM_USERPTR_MAX_WORKERS 15
1863 struct mm_struct
*mm
;
1864 struct i915_mmu_object
*mn
;
1865 struct work_struct
*work
;
1869 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1871 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1872 struct drm_i915_gem_object
*new,
1873 unsigned frontbuffer_bits
);
1876 * Request queue structure.
1878 * The request queue allows us to note sequence numbers that have been emitted
1879 * and may be associated with active buffers to be retired.
1881 * By keeping this list, we can avoid having to do questionable
1882 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1883 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1885 struct drm_i915_gem_request
{
1886 /** On Which ring this request was generated */
1887 struct intel_engine_cs
*ring
;
1889 /** GEM sequence number associated with this request. */
1892 /** Position in the ringbuffer of the start of the request */
1895 /** Position in the ringbuffer of the end of the request */
1898 /** Context related to this request */
1899 struct intel_context
*ctx
;
1901 /** Batch buffer related to this request if any */
1902 struct drm_i915_gem_object
*batch_obj
;
1904 /** Time at which this request was emitted, in jiffies. */
1905 unsigned long emitted_jiffies
;
1907 /** global list entry for this request */
1908 struct list_head list
;
1910 struct drm_i915_file_private
*file_priv
;
1911 /** file_priv list entry for this request */
1912 struct list_head client_list
;
1915 struct drm_i915_file_private
{
1916 struct drm_i915_private
*dev_priv
;
1917 struct drm_file
*file
;
1921 struct list_head request_list
;
1922 struct delayed_work idle_work
;
1924 struct idr context_idr
;
1926 atomic_t rps_wait_boost
;
1927 struct intel_engine_cs
*bsd_ring
;
1931 * A command that requires special handling by the command parser.
1933 struct drm_i915_cmd_descriptor
{
1935 * Flags describing how the command parser processes the command.
1937 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1938 * a length mask if not set
1939 * CMD_DESC_SKIP: The command is allowed but does not follow the
1940 * standard length encoding for the opcode range in
1942 * CMD_DESC_REJECT: The command is never allowed
1943 * CMD_DESC_REGISTER: The command should be checked against the
1944 * register whitelist for the appropriate ring
1945 * CMD_DESC_MASTER: The command is allowed if the submitting process
1949 #define CMD_DESC_FIXED (1<<0)
1950 #define CMD_DESC_SKIP (1<<1)
1951 #define CMD_DESC_REJECT (1<<2)
1952 #define CMD_DESC_REGISTER (1<<3)
1953 #define CMD_DESC_BITMASK (1<<4)
1954 #define CMD_DESC_MASTER (1<<5)
1957 * The command's unique identification bits and the bitmask to get them.
1958 * This isn't strictly the opcode field as defined in the spec and may
1959 * also include type, subtype, and/or subop fields.
1967 * The command's length. The command is either fixed length (i.e. does
1968 * not include a length field) or has a length field mask. The flag
1969 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1970 * a length mask. All command entries in a command table must include
1971 * length information.
1979 * Describes where to find a register address in the command to check
1980 * against the ring's register whitelist. Only valid if flags has the
1981 * CMD_DESC_REGISTER bit set.
1988 #define MAX_CMD_DESC_BITMASKS 3
1990 * Describes command checks where a particular dword is masked and
1991 * compared against an expected value. If the command does not match
1992 * the expected value, the parser rejects it. Only valid if flags has
1993 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1996 * If the check specifies a non-zero condition_mask then the parser
1997 * only performs the check when the bits specified by condition_mask
2004 u32 condition_offset
;
2006 } bits
[MAX_CMD_DESC_BITMASKS
];
2010 * A table of commands requiring special handling by the command parser.
2012 * Each ring has an array of tables. Each table consists of an array of command
2013 * descriptors, which must be sorted with command opcodes in ascending order.
2015 struct drm_i915_cmd_table
{
2016 const struct drm_i915_cmd_descriptor
*table
;
2020 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2021 #define __I915__(p) ({ \
2022 struct drm_i915_private *__p; \
2023 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2024 __p = (struct drm_i915_private *)p; \
2025 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2026 __p = to_i915((struct drm_device *)p); \
2031 #define INTEL_INFO(p) (&__I915__(p)->info)
2032 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2034 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2035 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2036 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2037 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2038 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2039 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2040 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2041 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2042 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2043 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2044 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2045 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2046 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2047 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2048 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2049 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2050 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2051 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2052 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2053 INTEL_DEVID(dev) == 0x0152 || \
2054 INTEL_DEVID(dev) == 0x015a)
2055 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2056 INTEL_DEVID(dev) == 0x0106 || \
2057 INTEL_DEVID(dev) == 0x010A)
2058 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2059 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2060 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2061 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2062 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2063 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2064 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2065 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2066 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2067 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2068 (INTEL_DEVID(dev) & 0xf) == 0xe))
2069 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2070 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2071 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
2072 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2073 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2074 /* ULX machines are also considered ULT. */
2075 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2076 INTEL_DEVID(dev) == 0x0A1E)
2077 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2080 * The genX designation typically refers to the render engine, so render
2081 * capability related checks should use IS_GEN, while display and other checks
2082 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2085 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2086 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2087 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2088 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2089 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2090 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2091 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2093 #define RENDER_RING (1<<RCS)
2094 #define BSD_RING (1<<VCS)
2095 #define BLT_RING (1<<BCS)
2096 #define VEBOX_RING (1<<VECS)
2097 #define BSD2_RING (1<<VCS2)
2098 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2099 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2100 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2101 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2102 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2103 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2104 to_i915(dev)->ellc_size)
2105 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2107 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2108 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2109 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2110 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2111 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2112 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2114 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2115 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2117 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2118 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2120 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2121 * even when in MSI mode. This results in spurious interrupt warnings if the
2122 * legacy irq no. is shared with another device. The kernel then disables that
2123 * interrupt source and so prevents the other device from working properly.
2125 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2126 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2128 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2129 * rows, which changed the alignment requirements and fence programming.
2131 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2133 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2134 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2135 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2136 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2137 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2139 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2140 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2141 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2143 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2145 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2146 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2147 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2148 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2149 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2151 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2152 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2153 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2154 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2155 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2156 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2158 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2159 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2160 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2161 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2162 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2163 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2165 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2167 /* DPF == dynamic parity feature */
2168 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2169 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2171 #define GT_FREQUENCY_MULTIPLIER 50
2173 #include "i915_trace.h"
2175 extern const struct drm_ioctl_desc i915_ioctls
[];
2176 extern int i915_max_ioctl
;
2178 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
2179 extern int i915_resume(struct drm_device
*dev
);
2180 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2181 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2184 struct i915_params
{
2186 int panel_ignore_lid
;
2187 unsigned int powersave
;
2189 unsigned int lvds_downclock
;
2190 int lvds_channel_mode
;
2192 int vbt_sdvo_panel_type
;
2196 int enable_execlists
;
2198 unsigned int preliminary_hw_support
;
2199 int disable_power_well
;
2201 int invert_brightness
;
2202 int enable_cmd_parser
;
2203 /* leave bools at the end to not create holes */
2204 bool enable_hangcheck
;
2206 bool prefault_disable
;
2208 bool disable_display
;
2209 bool disable_vtd_wa
;
2213 extern struct i915_params i915 __read_mostly
;
2216 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2217 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2218 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2219 extern int i915_driver_unload(struct drm_device
*);
2220 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2221 extern void i915_driver_lastclose(struct drm_device
* dev
);
2222 extern void i915_driver_preclose(struct drm_device
*dev
,
2223 struct drm_file
*file
);
2224 extern void i915_driver_postclose(struct drm_device
*dev
,
2225 struct drm_file
*file
);
2226 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2227 #ifdef CONFIG_COMPAT
2228 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2231 extern int i915_emit_box(struct drm_device
*dev
,
2232 struct drm_clip_rect
*box
,
2234 extern int intel_gpu_reset(struct drm_device
*dev
);
2235 extern int i915_reset(struct drm_device
*dev
);
2236 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2237 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2238 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2239 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2240 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2241 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2244 void i915_queue_hangcheck(struct drm_device
*dev
);
2246 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2247 const char *fmt
, ...);
2249 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2251 extern void intel_irq_init(struct drm_device
*dev
);
2252 extern void intel_hpd_init(struct drm_device
*dev
);
2254 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2255 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2256 bool restore_forcewake
);
2257 extern void intel_uncore_init(struct drm_device
*dev
);
2258 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2259 extern void intel_uncore_fini(struct drm_device
*dev
);
2260 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2263 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2267 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2270 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2271 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2274 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2275 struct drm_file
*file_priv
);
2276 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2277 struct drm_file
*file_priv
);
2278 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2279 struct drm_file
*file_priv
);
2280 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2281 struct drm_file
*file_priv
);
2282 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2283 struct drm_file
*file_priv
);
2284 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2285 struct drm_file
*file_priv
);
2286 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2287 struct drm_file
*file_priv
);
2288 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2289 struct drm_file
*file_priv
);
2290 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2291 struct intel_engine_cs
*ring
);
2292 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2293 struct drm_file
*file
,
2294 struct intel_engine_cs
*ring
,
2295 struct drm_i915_gem_object
*obj
);
2296 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2297 struct drm_file
*file
,
2298 struct intel_engine_cs
*ring
,
2299 struct intel_context
*ctx
,
2300 struct drm_i915_gem_execbuffer2
*args
,
2301 struct list_head
*vmas
,
2302 struct drm_i915_gem_object
*batch_obj
,
2303 u64 exec_start
, u32 flags
);
2304 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2305 struct drm_file
*file_priv
);
2306 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2307 struct drm_file
*file_priv
);
2308 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2309 struct drm_file
*file_priv
);
2310 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2311 struct drm_file
*file_priv
);
2312 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2313 struct drm_file
*file_priv
);
2314 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2315 struct drm_file
*file
);
2316 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2317 struct drm_file
*file
);
2318 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2319 struct drm_file
*file_priv
);
2320 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2321 struct drm_file
*file_priv
);
2322 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2323 struct drm_file
*file_priv
);
2324 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2325 struct drm_file
*file_priv
);
2326 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2327 struct drm_file
*file_priv
);
2328 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2329 struct drm_file
*file_priv
);
2330 int i915_gem_init_userptr(struct drm_device
*dev
);
2331 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2332 struct drm_file
*file
);
2333 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2334 struct drm_file
*file_priv
);
2335 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2336 struct drm_file
*file_priv
);
2337 void i915_gem_load(struct drm_device
*dev
);
2338 void *i915_gem_object_alloc(struct drm_device
*dev
);
2339 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2340 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2341 const struct drm_i915_gem_object_ops
*ops
);
2342 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2344 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2345 struct i915_address_space
*vm
);
2346 void i915_gem_free_object(struct drm_gem_object
*obj
);
2347 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2349 #define PIN_MAPPABLE 0x1
2350 #define PIN_NONBLOCK 0x2
2351 #define PIN_GLOBAL 0x4
2352 #define PIN_OFFSET_BIAS 0x8
2353 #define PIN_OFFSET_MASK (~4095)
2354 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2355 struct i915_address_space
*vm
,
2358 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2359 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2360 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2361 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2362 void i915_gem_lastclose(struct drm_device
*dev
);
2364 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2365 int *needs_clflush
);
2367 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2368 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2370 struct sg_page_iter sg_iter
;
2372 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2373 return sg_page_iter_page(&sg_iter
);
2377 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2379 BUG_ON(obj
->pages
== NULL
);
2380 obj
->pages_pin_count
++;
2382 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2384 BUG_ON(obj
->pages_pin_count
== 0);
2385 obj
->pages_pin_count
--;
2388 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2389 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2390 struct intel_engine_cs
*to
);
2391 void i915_vma_move_to_active(struct i915_vma
*vma
,
2392 struct intel_engine_cs
*ring
);
2393 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2394 struct drm_device
*dev
,
2395 struct drm_mode_create_dumb
*args
);
2396 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2397 uint32_t handle
, uint64_t *offset
);
2399 * Returns true if seq1 is later than seq2.
2402 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2404 return (int32_t)(seq1
- seq2
) >= 0;
2407 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2408 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2409 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2410 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2412 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2413 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2415 struct drm_i915_gem_request
*
2416 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2418 bool i915_gem_retire_requests(struct drm_device
*dev
);
2419 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2420 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2421 bool interruptible
);
2422 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2424 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2426 return unlikely(atomic_read(&error
->reset_counter
)
2427 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2430 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2432 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2435 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2437 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2440 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2442 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2443 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2446 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2448 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2449 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2452 void i915_gem_reset(struct drm_device
*dev
);
2453 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2454 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2455 int __must_check
i915_gem_init(struct drm_device
*dev
);
2456 int i915_gem_init_rings(struct drm_device
*dev
);
2457 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2458 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2459 void i915_gem_init_swizzling(struct drm_device
*dev
);
2460 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2461 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2462 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2463 int __i915_add_request(struct intel_engine_cs
*ring
,
2464 struct drm_file
*file
,
2465 struct drm_i915_gem_object
*batch_obj
,
2467 #define i915_add_request(ring, seqno) \
2468 __i915_add_request(ring, NULL, NULL, seqno)
2469 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2471 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2473 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2476 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2478 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2480 struct intel_engine_cs
*pipelined
);
2481 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2482 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2484 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2485 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2488 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2490 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2491 int tiling_mode
, bool fenced
);
2493 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2494 enum i915_cache_level cache_level
);
2496 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2497 struct dma_buf
*dma_buf
);
2499 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2500 struct drm_gem_object
*gem_obj
, int flags
);
2502 void i915_gem_restore_fences(struct drm_device
*dev
);
2504 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2505 struct i915_address_space
*vm
);
2506 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2507 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2508 struct i915_address_space
*vm
);
2509 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2510 struct i915_address_space
*vm
);
2511 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2512 struct i915_address_space
*vm
);
2514 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2515 struct i915_address_space
*vm
);
2517 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2518 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2519 struct i915_vma
*vma
;
2520 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2521 if (vma
->pin_count
> 0)
2526 /* Some GGTT VM helpers */
2527 #define i915_obj_to_ggtt(obj) \
2528 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2529 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2531 struct i915_address_space
*ggtt
=
2532 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2536 static inline struct i915_hw_ppgtt
*
2537 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2539 WARN_ON(i915_is_ggtt(vm
));
2541 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2545 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2547 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2550 static inline unsigned long
2551 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2553 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2556 static inline unsigned long
2557 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2559 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2562 static inline int __must_check
2563 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2567 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2568 alignment
, flags
| PIN_GLOBAL
);
2572 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2574 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2577 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2579 /* i915_gem_context.c */
2580 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2581 void i915_gem_context_fini(struct drm_device
*dev
);
2582 void i915_gem_context_reset(struct drm_device
*dev
);
2583 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2584 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2585 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2586 int i915_switch_context(struct intel_engine_cs
*ring
,
2587 struct intel_context
*to
);
2588 struct intel_context
*
2589 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2590 void i915_gem_context_free(struct kref
*ctx_ref
);
2591 struct drm_i915_gem_object
*
2592 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2593 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2595 kref_get(&ctx
->ref
);
2598 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2600 kref_put(&ctx
->ref
, i915_gem_context_free
);
2603 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2605 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2608 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2609 struct drm_file
*file
);
2610 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2611 struct drm_file
*file
);
2613 /* i915_gem_render_state.c */
2614 int i915_gem_render_state_init(struct intel_engine_cs
*ring
);
2615 /* i915_gem_evict.c */
2616 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2617 struct i915_address_space
*vm
,
2620 unsigned cache_level
,
2621 unsigned long start
,
2624 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2625 int i915_gem_evict_everything(struct drm_device
*dev
);
2627 /* belongs in i915_gem_gtt.h */
2628 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2630 if (INTEL_INFO(dev
)->gen
< 6)
2631 intel_gtt_chipset_flush();
2634 /* i915_gem_stolen.c */
2635 int i915_gem_init_stolen(struct drm_device
*dev
);
2636 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2637 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2638 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2639 struct drm_i915_gem_object
*
2640 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2641 struct drm_i915_gem_object
*
2642 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2647 /* i915_gem_tiling.c */
2648 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2650 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2652 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2653 obj
->tiling_mode
!= I915_TILING_NONE
;
2656 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2657 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2658 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2660 /* i915_gem_debug.c */
2662 int i915_verify_lists(struct drm_device
*dev
);
2664 #define i915_verify_lists(dev) 0
2667 /* i915_debugfs.c */
2668 int i915_debugfs_init(struct drm_minor
*minor
);
2669 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2670 #ifdef CONFIG_DEBUG_FS
2671 void intel_display_crc_init(struct drm_device
*dev
);
2673 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2676 /* i915_gpu_error.c */
2678 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2679 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2680 const struct i915_error_state_file_priv
*error
);
2681 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2682 struct drm_i915_private
*i915
,
2683 size_t count
, loff_t pos
);
2684 static inline void i915_error_state_buf_release(
2685 struct drm_i915_error_state_buf
*eb
)
2689 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2690 const char *error_msg
);
2691 void i915_error_state_get(struct drm_device
*dev
,
2692 struct i915_error_state_file_priv
*error_priv
);
2693 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2694 void i915_destroy_error_state(struct drm_device
*dev
);
2696 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2697 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
2699 /* i915_cmd_parser.c */
2700 int i915_cmd_parser_get_version(void);
2701 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2702 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2703 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2704 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2705 struct drm_i915_gem_object
*batch_obj
,
2706 u32 batch_start_offset
,
2709 /* i915_suspend.c */
2710 extern int i915_save_state(struct drm_device
*dev
);
2711 extern int i915_restore_state(struct drm_device
*dev
);
2714 void i915_save_display_reg(struct drm_device
*dev
);
2715 void i915_restore_display_reg(struct drm_device
*dev
);
2718 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2719 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2722 extern int intel_setup_gmbus(struct drm_device
*dev
);
2723 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2724 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2726 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2729 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2730 struct drm_i915_private
*dev_priv
, unsigned port
);
2731 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2732 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2733 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2735 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2737 extern void intel_i2c_reset(struct drm_device
*dev
);
2739 /* intel_opregion.c */
2740 struct intel_encoder
;
2742 extern int intel_opregion_setup(struct drm_device
*dev
);
2743 extern void intel_opregion_init(struct drm_device
*dev
);
2744 extern void intel_opregion_fini(struct drm_device
*dev
);
2745 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2746 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2748 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2751 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2752 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2753 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2754 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2756 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2761 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2769 extern void intel_register_dsm_handler(void);
2770 extern void intel_unregister_dsm_handler(void);
2772 static inline void intel_register_dsm_handler(void) { return; }
2773 static inline void intel_unregister_dsm_handler(void) { return; }
2774 #endif /* CONFIG_ACPI */
2777 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2778 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2779 extern void intel_modeset_init(struct drm_device
*dev
);
2780 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2781 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2782 extern void intel_connector_unregister(struct intel_connector
*);
2783 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2784 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2785 bool force_restore
);
2786 extern void i915_redisable_vga(struct drm_device
*dev
);
2787 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2788 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2789 extern void gen8_fbc_sw_flush(struct drm_device
*dev
, u32 value
);
2790 extern void intel_disable_fbc(struct drm_device
*dev
);
2791 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2792 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2793 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2794 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2795 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2797 extern void intel_detect_pch(struct drm_device
*dev
);
2798 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2799 extern int intel_enable_rc6(const struct drm_device
*dev
);
2801 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2802 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2803 struct drm_file
*file
);
2804 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2805 struct drm_file
*file
);
2807 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2810 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2811 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2812 struct intel_overlay_error_state
*error
);
2814 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2815 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2816 struct drm_device
*dev
,
2817 struct intel_display_error_state
*error
);
2819 /* On SNB platform, before reading ring registers forcewake bit
2820 * must be set to prevent GT core from power down and stale values being
2823 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2824 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2825 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2827 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2828 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2830 /* intel_sideband.c */
2831 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2832 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2833 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2834 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2835 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2836 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2837 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2838 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2839 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2840 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2841 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2842 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2843 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2844 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2845 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2846 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2847 enum intel_sbi_destination destination
);
2848 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2849 enum intel_sbi_destination destination
);
2850 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2851 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2853 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2854 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2856 #define FORCEWAKE_RENDER (1 << 0)
2857 #define FORCEWAKE_MEDIA (1 << 1)
2858 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2861 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2862 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2864 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2865 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2866 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2867 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2869 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2870 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2871 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2872 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2874 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2875 * will be implemented using 2 32-bit writes in an arbitrary order with
2876 * an arbitrary delay between them. This can cause the hardware to
2877 * act upon the intermediate value, possibly leading to corruption and
2878 * machine death. You have been warned.
2880 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2881 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2883 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2884 u32 upper = I915_READ(upper_reg); \
2885 u32 lower = I915_READ(lower_reg); \
2886 u32 tmp = I915_READ(upper_reg); \
2887 if (upper != tmp) { \
2889 lower = I915_READ(lower_reg); \
2890 WARN_ON(I915_READ(upper_reg) != upper); \
2892 (u64)upper << 32 | lower; })
2894 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2895 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2897 /* "Broadcast RGB" property */
2898 #define INTEL_BROADCAST_RGB_AUTO 0
2899 #define INTEL_BROADCAST_RGB_FULL 1
2900 #define INTEL_BROADCAST_RGB_LIMITED 2
2902 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2904 if (IS_VALLEYVIEW(dev
))
2905 return VLV_VGACNTRL
;
2906 else if (INTEL_INFO(dev
)->gen
>= 5)
2907 return CPU_VGACNTRL
;
2912 static inline void __user
*to_user_ptr(u64 address
)
2914 return (void __user
*)(uintptr_t)address
;
2917 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2919 unsigned long j
= msecs_to_jiffies(m
);
2921 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2924 static inline unsigned long
2925 timespec_to_jiffies_timeout(const struct timespec
*value
)
2927 unsigned long j
= timespec_to_jiffies(value
);
2929 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2933 * If you need to wait X milliseconds between events A and B, but event B
2934 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2935 * when event A happened, then just before event B you call this function and
2936 * pass the timestamp as the first argument, and X as the second argument.
2939 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
2941 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
2944 * Don't re-read the value of "jiffies" every time since it may change
2945 * behind our back and break the math.
2947 tmp_jiffies
= jiffies
;
2948 target_jiffies
= timestamp_jiffies
+
2949 msecs_to_jiffies_timeout(to_wait_ms
);
2951 if (time_after(target_jiffies
, tmp_jiffies
)) {
2952 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
2953 while (remaining_jiffies
)
2955 schedule_timeout_uninterruptible(remaining_jiffies
);