drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include <linux/io-mapping.h>
  36
  37 /* General customization:
  38  */
  39
  40 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  41
  42 #define DRIVER_NAME             "i915"
  43 #define DRIVER_DESC             "Intel Graphics"
  44 #define DRIVER_DATE             "20080730"
  45
  46 enum pipe {
  47         PIPE_A = 0,
  48         PIPE_B,
  49 };
  50
  51 enum plane {
  52         PLANE_A = 0,
  53         PLANE_B,
  54 };
  55
  56 #define I915_NUM_PIPE   2
  57
  58 /* Interface history:
  59  *
  60  * 1.1: Original.
  61  * 1.2: Add Power Management
  62  * 1.3: Add vblank support
  63  * 1.4: Fix cmdbuffer path, add heap destroy
  64  * 1.5: Add vblank pipe configuration
  65  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  66  *      - Support vertical blank on secondary display pipe
  67  */
  68 #define DRIVER_MAJOR            1
  69 #define DRIVER_MINOR            6
  70 #define DRIVER_PATCHLEVEL       0
  71
  72 #define WATCH_COHERENCY 0
  73 #define WATCH_BUF       0
  74 #define WATCH_EXEC      0
  75 #define WATCH_LRU       0
  76 #define WATCH_RELOC     0
  77 #define WATCH_INACTIVE  0
  78 #define WATCH_PWRITE    0
  79
  80 #define I915_GEM_PHYS_CURSOR_0 1
  81 #define I915_GEM_PHYS_CURSOR_1 2
  82 #define I915_GEM_PHYS_OVERLAY_REGS 3
  83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  84
  85 struct drm_i915_gem_phys_object {
  86         int id;
  87         struct page **page_list;
  88         drm_dma_handle_t *handle;
  89         struct drm_gem_object *cur_obj;
  90 };
  91
  92 typedef struct _drm_i915_ring_buffer {
  93         unsigned long Size;
  94         u8 *virtual_start;
  95         int head;
  96         int tail;
  97         int space;
  98         drm_local_map_t map;
  99         struct drm_gem_object *ring_obj;
 100 } drm_i915_ring_buffer_t;
 101
 102 struct mem_block {
 103         struct mem_block *next;
 104         struct mem_block *prev;
 105         int start;
 106         int size;
 107         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 108 };
 109
 110 struct opregion_header;
 111 struct opregion_acpi;
 112 struct opregion_swsci;
 113 struct opregion_asle;
 114
 115 struct intel_opregion {
 116         struct opregion_header *header;
 117         struct opregion_acpi *acpi;
 118         struct opregion_swsci *swsci;
 119         struct opregion_asle *asle;
 120         int enabled;
 121 };
 122
 123 struct drm_i915_master_private {
 124         drm_local_map_t *sarea;
 125         struct _drm_i915_sarea *sarea_priv;
 126 };
 127 #define I915_FENCE_REG_NONE -1
 128
 129 struct drm_i915_fence_reg {
 130         struct drm_gem_object *obj;
 131 };
 132
 133 struct sdvo_device_mapping {
 134         u8 dvo_port;
 135         u8 slave_addr;
 136         u8 dvo_wiring;
 137         u8 initialized;
 138 };
 139
 140 struct drm_i915_error_state {
 141         u32 eir;
 142         u32 pgtbl_er;
 143         u32 pipeastat;
 144         u32 pipebstat;
 145         u32 ipeir;
 146         u32 ipehr;
 147         u32 instdone;
 148         u32 acthd;
 149         u32 instpm;
 150         u32 instps;
 151         u32 instdone1;
 152         u32 seqno;
 153         struct timeval time;
 154 };
 155
 156 struct drm_i915_display_funcs {
 157         void (*dpms)(struct drm_crtc *crtc, int mode);
 158         bool (*fbc_enabled)(struct drm_crtc *crtc);
 159         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 160         void (*disable_fbc)(struct drm_device *dev);
 161         int (*get_display_clock_speed)(struct drm_device *dev);
 162         int (*get_fifo_size)(struct drm_device *dev, int plane);
 163         void (*update_wm)(struct drm_device *dev, int planea_clock,
 164                           int planeb_clock, int sr_hdisplay, int pixel_size);
 165         /* clock updates for mode set */
 166         /* cursor updates */
 167         /* render clock increase/decrease */
 168         /* display clock increase/decrease */
 169         /* pll clock increase/decrease */
 170         /* clock gating init */
 171 };
 172
 173 struct intel_overlay;
 174
 175 struct intel_device_info {
 176         u8 is_mobile : 1;
 177         u8 is_i8xx : 1;
 178         u8 is_i915g : 1;
 179         u8 is_i9xx : 1;
 180         u8 is_i945gm : 1;
 181         u8 is_i965g : 1;
 182         u8 is_i965gm : 1;
 183         u8 is_g33 : 1;
 184         u8 need_gfx_hws : 1;
 185         u8 is_g4x : 1;
 186         u8 is_pineview : 1;
 187         u8 is_ironlake : 1;
 188         u8 has_fbc : 1;
 189         u8 has_rc6 : 1;
 190         u8 has_pipe_cxsr : 1;
 191         u8 has_hotplug : 1;
 192         u8 cursor_needs_physical : 1;
 193 };
 194
 195 typedef struct drm_i915_private {
 196         struct drm_device *dev;
 197
 198         const struct intel_device_info *info;
 199
 200         int has_gem;
 201
 202         void __iomem *regs;
 203
 204         struct pci_dev *bridge_dev;
 205         drm_i915_ring_buffer_t ring;
 206
 207         drm_dma_handle_t *status_page_dmah;
 208         void *hw_status_page;
 209         dma_addr_t dma_status_page;
 210         uint32_t counter;
 211         unsigned int status_gfx_addr;
 212         drm_local_map_t hws_map;
 213         struct drm_gem_object *hws_obj;
 214         struct drm_gem_object *pwrctx;
 215
 216         struct resource mch_res;
 217
 218         unsigned int cpp;
 219         int back_offset;
 220         int front_offset;
 221         int current_page;
 222         int page_flipping;
 223
 224         wait_queue_head_t irq_queue;
 225         atomic_t irq_received;
 226         /** Protects user_irq_refcount and irq_mask_reg */
 227         spinlock_t user_irq_lock;
 228         /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
 229         int user_irq_refcount;
 230         u32 trace_irq_seqno;
 231         /** Cached value of IMR to avoid reads in updating the bitfield */
 232         u32 irq_mask_reg;
 233         u32 pipestat[2];
 234         /** splitted irq regs for graphics and display engine on Ironlake,
 235             irq_mask_reg is still used for display irq. */
 236         u32 gt_irq_mask_reg;
 237         u32 gt_irq_enable_reg;
 238         u32 de_irq_enable_reg;
 239         u32 pch_irq_mask_reg;
 240         u32 pch_irq_enable_reg;
 241
 242         u32 hotplug_supported_mask;
 243         struct work_struct hotplug_work;
 244
 245         int tex_lru_log_granularity;
 246         int allow_batchbuffer;
 247         struct mem_block *agp_heap;
 248         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 249         int vblank_pipe;
 250
 251         /* For hangcheck timer */
 252 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
 253         struct timer_list hangcheck_timer;
 254         int hangcheck_count;
 255         uint32_t last_acthd;
 256
 257         struct drm_mm vram;
 258
 259         unsigned long cfb_size;
 260         unsigned long cfb_pitch;
 261         int cfb_fence;
 262         int cfb_plane;
 263
 264         int irq_enabled;
 265
 266         struct intel_opregion opregion;
 267
 268         /* overlay */
 269         struct intel_overlay *overlay;
 270
 271         /* LVDS info */
 272         int backlight_duty_cycle;  /* restore backlight to this value */
 273         bool panel_wants_dither;
 274         struct drm_display_mode *panel_fixed_mode;
 275         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 276         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 277
 278         /* Feature bits from the VBIOS */
 279         unsigned int int_tv_support:1;
 280         unsigned int lvds_dither:1;
 281         unsigned int lvds_vbt:1;
 282         unsigned int int_crt_support:1;
 283         unsigned int lvds_use_ssc:1;
 284         unsigned int edp_support:1;
 285         int lvds_ssc_freq;
 286
 287         struct notifier_block lid_notifier;
 288
 289         int crt_ddc_bus; /* 0 = unknown, else GPIO to use for CRT DDC */
 290         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 291         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 292         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 293
 294         unsigned int fsb_freq, mem_freq;
 295
 296         spinlock_t error_lock;
 297         struct drm_i915_error_state *first_error;
 298         struct work_struct error_work;
 299         struct workqueue_struct *wq;
 300
 301         /* Display functions */
 302         struct drm_i915_display_funcs display;
 303
 304         /* Register state */
 305         bool modeset_on_lid;
 306         u8 saveLBB;
 307         u32 saveDSPACNTR;
 308         u32 saveDSPBCNTR;
 309         u32 saveDSPARB;
 310         u32 saveRENDERSTANDBY;
 311         u32 savePWRCTXA;
 312         u32 saveHWS;
 313         u32 savePIPEACONF;
 314         u32 savePIPEBCONF;
 315         u32 savePIPEASRC;
 316         u32 savePIPEBSRC;
 317         u32 saveFPA0;
 318         u32 saveFPA1;
 319         u32 saveDPLL_A;
 320         u32 saveDPLL_A_MD;
 321         u32 saveHTOTAL_A;
 322         u32 saveHBLANK_A;
 323         u32 saveHSYNC_A;
 324         u32 saveVTOTAL_A;
 325         u32 saveVBLANK_A;
 326         u32 saveVSYNC_A;
 327         u32 saveBCLRPAT_A;
 328         u32 saveTRANSACONF;
 329         u32 saveTRANS_HTOTAL_A;
 330         u32 saveTRANS_HBLANK_A;
 331         u32 saveTRANS_HSYNC_A;
 332         u32 saveTRANS_VTOTAL_A;
 333         u32 saveTRANS_VBLANK_A;
 334         u32 saveTRANS_VSYNC_A;
 335         u32 savePIPEASTAT;
 336         u32 saveDSPASTRIDE;
 337         u32 saveDSPASIZE;
 338         u32 saveDSPAPOS;
 339         u32 saveDSPAADDR;
 340         u32 saveDSPASURF;
 341         u32 saveDSPATILEOFF;
 342         u32 savePFIT_PGM_RATIOS;
 343         u32 saveBLC_HIST_CTL;
 344         u32 saveBLC_PWM_CTL;
 345         u32 saveBLC_PWM_CTL2;
 346         u32 saveBLC_CPU_PWM_CTL;
 347         u32 saveBLC_CPU_PWM_CTL2;
 348         u32 saveFPB0;
 349         u32 saveFPB1;
 350         u32 saveDPLL_B;
 351         u32 saveDPLL_B_MD;
 352         u32 saveHTOTAL_B;
 353         u32 saveHBLANK_B;
 354         u32 saveHSYNC_B;
 355         u32 saveVTOTAL_B;
 356         u32 saveVBLANK_B;
 357         u32 saveVSYNC_B;
 358         u32 saveBCLRPAT_B;
 359         u32 saveTRANSBCONF;
 360         u32 saveTRANS_HTOTAL_B;
 361         u32 saveTRANS_HBLANK_B;
 362         u32 saveTRANS_HSYNC_B;
 363         u32 saveTRANS_VTOTAL_B;
 364         u32 saveTRANS_VBLANK_B;
 365         u32 saveTRANS_VSYNC_B;
 366         u32 savePIPEBSTAT;
 367         u32 saveDSPBSTRIDE;
 368         u32 saveDSPBSIZE;
 369         u32 saveDSPBPOS;
 370         u32 saveDSPBADDR;
 371         u32 saveDSPBSURF;
 372         u32 saveDSPBTILEOFF;
 373         u32 saveVGA0;
 374         u32 saveVGA1;
 375         u32 saveVGA_PD;
 376         u32 saveVGACNTRL;
 377         u32 saveADPA;
 378         u32 saveLVDS;
 379         u32 savePP_ON_DELAYS;
 380         u32 savePP_OFF_DELAYS;
 381         u32 saveDVOA;
 382         u32 saveDVOB;
 383         u32 saveDVOC;
 384         u32 savePP_ON;
 385         u32 savePP_OFF;
 386         u32 savePP_CONTROL;
 387         u32 savePP_DIVISOR;
 388         u32 savePFIT_CONTROL;
 389         u32 save_palette_a[256];
 390         u32 save_palette_b[256];
 391         u32 saveDPFC_CB_BASE;
 392         u32 saveFBC_CFB_BASE;
 393         u32 saveFBC_LL_BASE;
 394         u32 saveFBC_CONTROL;
 395         u32 saveFBC_CONTROL2;
 396         u32 saveIER;
 397         u32 saveIIR;
 398         u32 saveIMR;
 399         u32 saveDEIER;
 400         u32 saveDEIMR;
 401         u32 saveGTIER;
 402         u32 saveGTIMR;
 403         u32 saveFDI_RXA_IMR;
 404         u32 saveFDI_RXB_IMR;
 405         u32 saveCACHE_MODE_0;
 406         u32 saveMI_ARB_STATE;
 407         u32 saveSWF0[16];
 408         u32 saveSWF1[16];
 409         u32 saveSWF2[3];
 410         u8 saveMSR;
 411         u8 saveSR[8];
 412         u8 saveGR[25];
 413         u8 saveAR_INDEX;
 414         u8 saveAR[21];
 415         u8 saveDACMASK;
 416         u8 saveCR[37];
 417         uint64_t saveFENCE[16];
 418         u32 saveCURACNTR;
 419         u32 saveCURAPOS;
 420         u32 saveCURABASE;
 421         u32 saveCURBCNTR;
 422         u32 saveCURBPOS;
 423         u32 saveCURBBASE;
 424         u32 saveCURSIZE;
 425         u32 saveDP_B;
 426         u32 saveDP_C;
 427         u32 saveDP_D;
 428         u32 savePIPEA_GMCH_DATA_M;
 429         u32 savePIPEB_GMCH_DATA_M;
 430         u32 savePIPEA_GMCH_DATA_N;
 431         u32 savePIPEB_GMCH_DATA_N;
 432         u32 savePIPEA_DP_LINK_M;
 433         u32 savePIPEB_DP_LINK_M;
 434         u32 savePIPEA_DP_LINK_N;
 435         u32 savePIPEB_DP_LINK_N;
 436         u32 saveFDI_RXA_CTL;
 437         u32 saveFDI_TXA_CTL;
 438         u32 saveFDI_RXB_CTL;
 439         u32 saveFDI_TXB_CTL;
 440         u32 savePFA_CTL_1;
 441         u32 savePFB_CTL_1;
 442         u32 savePFA_WIN_SZ;
 443         u32 savePFB_WIN_SZ;
 444         u32 savePFA_WIN_POS;
 445         u32 savePFB_WIN_POS;
 446         u32 savePCH_DREF_CONTROL;
 447         u32 saveDISP_ARB_CTL;
 448         u32 savePIPEA_DATA_M1;
 449         u32 savePIPEA_DATA_N1;
 450         u32 savePIPEA_LINK_M1;
 451         u32 savePIPEA_LINK_N1;
 452         u32 savePIPEB_DATA_M1;
 453         u32 savePIPEB_DATA_N1;
 454         u32 savePIPEB_LINK_M1;
 455         u32 savePIPEB_LINK_N1;
 456
 457         struct {
 458                 struct drm_mm gtt_space;
 459
 460                 struct io_mapping *gtt_mapping;
 461                 int gtt_mtrr;
 462
 463                 /**
 464                  * Membership on list of all loaded devices, used to evict
 465                  * inactive buffers under memory pressure.
 466                  *
 467                  * Modifications should only be done whilst holding the
 468                  * shrink_list_lock spinlock.
 469                  */
 470                 struct list_head shrink_list;
 471
 472                 /**
 473                  * List of objects currently involved in rendering from the
 474                  * ringbuffer.
 475                  *
 476                  * Includes buffers having the contents of their GPU caches
 477                  * flushed, not necessarily primitives.  last_rendering_seqno
 478                  * represents when the rendering involved will be completed.
 479                  *
 480                  * A reference is held on the buffer while on this list.
 481                  */
 482                 spinlock_t active_list_lock;
 483                 struct list_head active_list;
 484
 485                 /**
 486                  * List of objects which are not in the ringbuffer but which
 487                  * still have a write_domain which needs to be flushed before
 488                  * unbinding.
 489                  *
 490                  * last_rendering_seqno is 0 while an object is in this list.
 491                  *
 492                  * A reference is held on the buffer while on this list.
 493                  */
 494                 struct list_head flushing_list;
 495
 496                 /**
 497                  * LRU list of objects which are not in the ringbuffer and
 498                  * are ready to unbind, but are still in the GTT.
 499                  *
 500                  * last_rendering_seqno is 0 while an object is in this list.
 501                  *
 502                  * A reference is not held on the buffer while on this list,
 503                  * as merely being GTT-bound shouldn't prevent its being
 504                  * freed, and we'll pull it off the list in the free path.
 505                  */
 506                 struct list_head inactive_list;
 507
 508                 /** LRU list of objects with fence regs on them. */
 509                 struct list_head fence_list;
 510
 511                 /**
 512                  * List of breadcrumbs associated with GPU requests currently
 513                  * outstanding.
 514                  */
 515                 struct list_head request_list;
 516
 517                 /**
 518                  * We leave the user IRQ off as much as possible,
 519                  * but this means that requests will finish and never
 520                  * be retired once the system goes idle. Set a timer to
 521                  * fire periodically while the ring is running. When it
 522                  * fires, go retire requests.
 523                  */
 524                 struct delayed_work retire_work;
 525
 526                 uint32_t next_gem_seqno;
 527
 528                 /**
 529                  * Waiting sequence number, if any
 530                  */
 531                 uint32_t waiting_gem_seqno;
 532
 533                 /**
 534                  * Last seq seen at irq time
 535                  */
 536                 uint32_t irq_gem_seqno;
 537
 538                 /**
 539                  * Flag if the X Server, and thus DRM, is not currently in
 540                  * control of the device.
 541                  *
 542                  * This is set between LeaveVT and EnterVT.  It needs to be
 543                  * replaced with a semaphore.  It also needs to be
 544                  * transitioned away from for kernel modesetting.
 545                  */
 546                 int suspended;
 547
 548                 /**
 549                  * Flag if the hardware appears to be wedged.
 550                  *
 551                  * This is set when attempts to idle the device timeout.
 552                  * It prevents command submission from occuring and makes
 553                  * every pending request fail
 554                  */
 555                 atomic_t wedged;
 556
 557                 /** Bit 6 swizzling required for X tiling */
 558                 uint32_t bit_6_swizzle_x;
 559                 /** Bit 6 swizzling required for Y tiling */
 560                 uint32_t bit_6_swizzle_y;
 561
 562                 /* storage for physical objects */
 563                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 564         } mm;
 565         struct sdvo_device_mapping sdvo_mappings[2];
 566         /* indicate whether the LVDS_BORDER should be enabled or not */
 567         unsigned int lvds_border_bits;
 568
 569         struct drm_crtc *plane_to_crtc_mapping[2];
 570         struct drm_crtc *pipe_to_crtc_mapping[2];
 571         wait_queue_head_t pending_flip_queue;
 572
 573         /* Reclocking support */
 574         bool render_reclock_avail;
 575         bool lvds_downclock_avail;
 576         /* indicates the reduced downclock for LVDS*/
 577         int lvds_downclock;
 578         struct work_struct idle_work;
 579         struct timer_list idle_timer;
 580         bool busy;
 581         u16 orig_clock;
 582         int child_dev_num;
 583         struct child_device_config *child_dev;
 584         struct drm_connector *int_lvds_connector;
 585 } drm_i915_private_t;
 586
 587 /** driver private structure attached to each drm_gem_object */
 588 struct drm_i915_gem_object {
 589         struct drm_gem_object *obj;
 590
 591         /** Current space allocated to this object in the GTT, if any. */
 592         struct drm_mm_node *gtt_space;
 593
 594         /** This object's place on the active/flushing/inactive lists */
 595         struct list_head list;
 596
 597         /** This object's place on the fenced object LRU */
 598         struct list_head fence_list;
 599
 600         /**
 601          * This is set if the object is on the active or flushing lists
 602          * (has pending rendering), and is not set if it's on inactive (ready
 603          * to be unbound).
 604          */
 605         int active;
 606
 607         /**
 608          * This is set if the object has been written to since last bound
 609          * to the GTT
 610          */
 611         int dirty;
 612
 613         /** AGP memory structure for our GTT binding. */
 614         DRM_AGP_MEM *agp_mem;
 615
 616         struct page **pages;
 617         int pages_refcount;
 618
 619         /**
 620          * Current offset of the object in GTT space.
 621          *
 622          * This is the same as gtt_space->start
 623          */
 624         uint32_t gtt_offset;
 625
 626         /**
 627          * Fake offset for use by mmap(2)
 628          */
 629         uint64_t mmap_offset;
 630
 631         /**
 632          * Fence register bits (if any) for this object.  Will be set
 633          * as needed when mapped into the GTT.
 634          * Protected by dev->struct_mutex.
 635          */
 636         int fence_reg;
 637
 638         /** How many users have pinned this object in GTT space */
 639         int pin_count;
 640
 641         /** Breadcrumb of last rendering to the buffer. */
 642         uint32_t last_rendering_seqno;
 643
 644         /** Current tiling mode for the object. */
 645         uint32_t tiling_mode;
 646         uint32_t stride;
 647
 648         /** Record of address bit 17 of each page at last unbind. */
 649         long *bit_17;
 650
 651         /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
 652         uint32_t agp_type;
 653
 654         /**
 655          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 656          * flags which individual pages are valid.
 657          */
 658         uint8_t *page_cpu_valid;
 659
 660         /** User space pin count and filp owning the pin */
 661         uint32_t user_pin_count;
 662         struct drm_file *pin_filp;
 663
 664         /** for phy allocated objects */
 665         struct drm_i915_gem_phys_object *phys_obj;
 666
 667         /**
 668          * Used for checking the object doesn't appear more than once
 669          * in an execbuffer object list.
 670          */
 671         int in_execbuffer;
 672
 673         /**
 674          * Advice: are the backing pages purgeable?
 675          */
 676         int madv;
 677
 678         /**
 679          * Number of crtcs where this object is currently the fb, but
 680          * will be page flipped away on the next vblank.  When it
 681          * reaches 0, dev_priv->pending_flip_queue will be woken up.
 682          */
 683         atomic_t pending_flip;
 684 };
 685
 686 /**
 687  * Request queue structure.
 688  *
 689  * The request queue allows us to note sequence numbers that have been emitted
 690  * and may be associated with active buffers to be retired.
 691  *
 692  * By keeping this list, we can avoid having to do questionable
 693  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 694  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 695  */
 696 struct drm_i915_gem_request {
 697         /** GEM sequence number associated with this request. */
 698         uint32_t seqno;
 699
 700         /** Time at which this request was emitted, in jiffies. */
 701         unsigned long emitted_jiffies;
 702
 703         /** global list entry for this request */
 704         struct list_head list;
 705
 706         /** file_priv list entry for this request */
 707         struct list_head client_list;
 708 };
 709
 710 struct drm_i915_file_private {
 711         struct {
 712                 struct list_head request_list;
 713         } mm;
 714 };
 715
 716 enum intel_chip_family {
 717         CHIP_I8XX = 0x01,
 718         CHIP_I9XX = 0x02,
 719         CHIP_I915 = 0x04,
 720         CHIP_I965 = 0x08,
 721 };
 722
 723 extern struct drm_ioctl_desc i915_ioctls[];
 724 extern int i915_max_ioctl;
 725 extern unsigned int i915_fbpercrtc;
 726 extern unsigned int i915_powersave;
 727
 728 extern void i915_save_display(struct drm_device *dev);
 729 extern void i915_restore_display(struct drm_device *dev);
 730 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
 731 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
 732
 733                                 /* i915_dma.c */
 734 extern void i915_kernel_lost_context(struct drm_device * dev);
 735 extern int i915_driver_load(struct drm_device *, unsigned long flags);
 736 extern int i915_driver_unload(struct drm_device *);
 737 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
 738 extern void i915_driver_lastclose(struct drm_device * dev);
 739 extern void i915_driver_preclose(struct drm_device *dev,
 740                                  struct drm_file *file_priv);
 741 extern void i915_driver_postclose(struct drm_device *dev,
 742                                   struct drm_file *file_priv);
 743 extern int i915_driver_device_is_agp(struct drm_device * dev);
 744 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
 745                               unsigned long arg);
 746 extern int i915_emit_box(struct drm_device *dev,
 747                          struct drm_clip_rect *boxes,
 748                          int i, int DR1, int DR4);
 749 extern int i965_reset(struct drm_device *dev, u8 flags);
 750
 751 /* i915_irq.c */
 752 void i915_hangcheck_elapsed(unsigned long data);
 753 extern int i915_irq_emit(struct drm_device *dev, void *data,
 754                          struct drm_file *file_priv);
 755 extern int i915_irq_wait(struct drm_device *dev, void *data,
 756                          struct drm_file *file_priv);
 757 void i915_user_irq_get(struct drm_device *dev);
 758 void i915_trace_irq_get(struct drm_device *dev, u32 seqno);
 759 void i915_user_irq_put(struct drm_device *dev);
 760 extern void i915_enable_interrupt (struct drm_device *dev);
 761
 762 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
 763 extern void i915_driver_irq_preinstall(struct drm_device * dev);
 764 extern int i915_driver_irq_postinstall(struct drm_device *dev);
 765 extern void i915_driver_irq_uninstall(struct drm_device * dev);
 766 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
 767                                 struct drm_file *file_priv);
 768 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
 769                                 struct drm_file *file_priv);
 770 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
 771 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
 772 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
 773 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
 774 extern int i915_vblank_swap(struct drm_device *dev, void *data,
 775                             struct drm_file *file_priv);
 776 extern void i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask);
 777
 778 void
 779 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 780
 781 void
 782 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
 783
 784 void intel_enable_asle (struct drm_device *dev);
 785
 786
 787 /* i915_mem.c */
 788 extern int i915_mem_alloc(struct drm_device *dev, void *data,
 789                           struct drm_file *file_priv);
 790 extern int i915_mem_free(struct drm_device *dev, void *data,
 791                          struct drm_file *file_priv);
 792 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
 793                               struct drm_file *file_priv);
 794 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
 795                                  struct drm_file *file_priv);
 796 extern void i915_mem_takedown(struct mem_block **heap);
 797 extern void i915_mem_release(struct drm_device * dev,
 798                              struct drm_file *file_priv, struct mem_block *heap);
 799 /* i915_gem.c */
 800 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
 801                         struct drm_file *file_priv);
 802 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
 803                           struct drm_file *file_priv);
 804 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
 805                          struct drm_file *file_priv);
 806 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
 807                           struct drm_file *file_priv);
 808 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 809                         struct drm_file *file_priv);
 810 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
 811                         struct drm_file *file_priv);
 812 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 813                               struct drm_file *file_priv);
 814 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 815                              struct drm_file *file_priv);
 816 int i915_gem_execbuffer(struct drm_device *dev, void *data,
 817                         struct drm_file *file_priv);
 818 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
 819                        struct drm_file *file_priv);
 820 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
 821                          struct drm_file *file_priv);
 822 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
 823                         struct drm_file *file_priv);
 824 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
 825                             struct drm_file *file_priv);
 826 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
 827                            struct drm_file *file_priv);
 828 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
 829                            struct drm_file *file_priv);
 830 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
 831                            struct drm_file *file_priv);
 832 int i915_gem_set_tiling(struct drm_device *dev, void *data,
 833                         struct drm_file *file_priv);
 834 int i915_gem_get_tiling(struct drm_device *dev, void *data,
 835                         struct drm_file *file_priv);
 836 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
 837                                 struct drm_file *file_priv);
 838 void i915_gem_load(struct drm_device *dev);
 839 int i915_gem_init_object(struct drm_gem_object *obj);
 840 void i915_gem_free_object(struct drm_gem_object *obj);
 841 int i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment);
 842 void i915_gem_object_unpin(struct drm_gem_object *obj);
 843 int i915_gem_object_unbind(struct drm_gem_object *obj);
 844 void i915_gem_release_mmap(struct drm_gem_object *obj);
 845 void i915_gem_lastclose(struct drm_device *dev);
 846 uint32_t i915_get_gem_seqno(struct drm_device *dev);
 847 bool i915_seqno_passed(uint32_t seq1, uint32_t seq2);
 848 int i915_gem_object_get_fence_reg(struct drm_gem_object *obj);
 849 int i915_gem_object_put_fence_reg(struct drm_gem_object *obj);
 850 void i915_gem_retire_requests(struct drm_device *dev);
 851 void i915_gem_retire_work_handler(struct work_struct *work);
 852 void i915_gem_clflush_object(struct drm_gem_object *obj);
 853 int i915_gem_object_set_domain(struct drm_gem_object *obj,
 854                                uint32_t read_domains,
 855                                uint32_t write_domain);
 856 int i915_gem_init_ringbuffer(struct drm_device *dev);
 857 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
 858 int i915_gem_do_init(struct drm_device *dev, unsigned long start,
 859                      unsigned long end);
 860 int i915_gem_idle(struct drm_device *dev);
 861 uint32_t i915_add_request(struct drm_device *dev, struct drm_file *file_priv,
 862                           uint32_t flush_domains);
 863 int i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible);
 864 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
 865 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj,
 866                                       int write);
 867 int i915_gem_attach_phys_object(struct drm_device *dev,
 868                                 struct drm_gem_object *obj, int id);
 869 void i915_gem_detach_phys_object(struct drm_device *dev,
 870                                  struct drm_gem_object *obj);
 871 void i915_gem_free_all_phys_object(struct drm_device *dev);
 872 int i915_gem_object_get_pages(struct drm_gem_object *obj);
 873 void i915_gem_object_put_pages(struct drm_gem_object *obj);
 874 void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv);
 875 void i915_gem_object_flush_write_domain(struct drm_gem_object *obj);
 876
 877 void i915_gem_shrinker_init(void);
 878 void i915_gem_shrinker_exit(void);
 879
 880 /* i915_gem_tiling.c */
 881 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
 882 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object *obj);
 883 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object *obj);
 884
 885 /* i915_gem_debug.c */
 886 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 887                           const char *where, uint32_t mark);
 888 #if WATCH_INACTIVE
 889 void i915_verify_inactive(struct drm_device *dev, char *file, int line);
 890 #else
 891 #define i915_verify_inactive(dev, file, line)
 892 #endif
 893 void i915_gem_object_check_coherency(struct drm_gem_object *obj, int handle);
 894 void i915_gem_dump_object(struct drm_gem_object *obj, int len,
 895                           const char *where, uint32_t mark);
 896 void i915_dump_lru(struct drm_device *dev, const char *where);
 897
 898 /* i915_debugfs.c */
 899 int i915_debugfs_init(struct drm_minor *minor);
 900 void i915_debugfs_cleanup(struct drm_minor *minor);
 901
 902 /* i915_suspend.c */
 903 extern int i915_save_state(struct drm_device *dev);
 904 extern int i915_restore_state(struct drm_device *dev);
 905
 906 /* i915_suspend.c */
 907 extern int i915_save_state(struct drm_device *dev);
 908 extern int i915_restore_state(struct drm_device *dev);
 909
 910 #ifdef CONFIG_ACPI
 911 /* i915_opregion.c */
 912 extern int intel_opregion_init(struct drm_device *dev, int resume);
 913 extern void intel_opregion_free(struct drm_device *dev, int suspend);
 914 extern void opregion_asle_intr(struct drm_device *dev);
 915 extern void ironlake_opregion_gse_intr(struct drm_device *dev);
 916 extern void opregion_enable_asle(struct drm_device *dev);
 917 #else
 918 static inline int intel_opregion_init(struct drm_device *dev, int resume) { return 0; }
 919 static inline void intel_opregion_free(struct drm_device *dev, int suspend) { return; }
 920 static inline void opregion_asle_intr(struct drm_device *dev) { return; }
 921 static inline void ironlake_opregion_gse_intr(struct drm_device *dev) { return; }
 922 static inline void opregion_enable_asle(struct drm_device *dev) { return; }
 923 #endif
 924
 925 /* modesetting */
 926 extern void intel_modeset_init(struct drm_device *dev);
 927 extern void intel_modeset_cleanup(struct drm_device *dev);
 928 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
 929 extern void i8xx_disable_fbc(struct drm_device *dev);
 930 extern void g4x_disable_fbc(struct drm_device *dev);
 931
 932 /**
 933  * Lock test for when it's just for synchronization of ring access.
 934  *
 935  * In that case, we don't need to do it when GEM is initialized as nobody else
 936  * has access to the ring.
 937  */
 938 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do {                 \
 939         if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
 940                 LOCK_TEST_WITH_RETURN(dev, file_priv);                  \
 941 } while (0)
 942
 943 #define I915_READ(reg)          readl(dev_priv->regs + (reg))
 944 #define I915_WRITE(reg, val)     writel(val, dev_priv->regs + (reg))
 945 #define I915_READ16(reg)        readw(dev_priv->regs + (reg))
 946 #define I915_WRITE16(reg, val)  writel(val, dev_priv->regs + (reg))
 947 #define I915_READ8(reg)         readb(dev_priv->regs + (reg))
 948 #define I915_WRITE8(reg, val)   writeb(val, dev_priv->regs + (reg))
 949 #define I915_WRITE64(reg, val)  writeq(val, dev_priv->regs + (reg))
 950 #define I915_READ64(reg)        readq(dev_priv->regs + (reg))
 951 #define POSTING_READ(reg)       (void)I915_READ(reg)
 952
 953 #define I915_VERBOSE 0
 954
 955 #define RING_LOCALS     volatile unsigned int *ring_virt__;
 956
 957 #define BEGIN_LP_RING(n) do {                                           \
 958         int bytes__ = 4*(n);                                            \
 959         if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n));        \
 960         /* a wrap must occur between instructions so pad beforehand */  \
 961         if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
 962                 i915_wrap_ring(dev);                                    \
 963         if (unlikely (dev_priv->ring.space < bytes__))                  \
 964                 i915_wait_ring(dev, bytes__, __func__);                 \
 965         ring_virt__ = (unsigned int *)                                  \
 966                 (dev_priv->ring.virtual_start + dev_priv->ring.tail);   \
 967         dev_priv->ring.tail += bytes__;                                 \
 968         dev_priv->ring.tail &= dev_priv->ring.Size - 1;                 \
 969         dev_priv->ring.space -= bytes__;                                \
 970 } while (0)
 971
 972 #define OUT_RING(n) do {                                                \
 973         if (I915_VERBOSE) DRM_DEBUG("   OUT_RING %x\n", (int)(n));      \
 974         *ring_virt__++ = (n);                                           \
 975 } while (0)
 976
 977 #define ADVANCE_LP_RING() do {                                          \
 978         if (I915_VERBOSE)                                               \
 979                 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
 980         I915_WRITE(PRB0_TAIL, dev_priv->ring.tail);                     \
 981 } while(0)
 982
 983 /**
 984  * Reads a dword out of the status page, which is written to from the command
 985  * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
 986  * MI_STORE_DATA_IMM.
 987  *
 988  * The following dwords have a reserved meaning:
 989  * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
 990  * 0x04: ring 0 head pointer
 991  * 0x05: ring 1 head pointer (915-class)
 992  * 0x06: ring 2 head pointer (915-class)
 993  * 0x10-0x1b: Context status DWords (GM45)
 994  * 0x1f: Last written status offset. (GM45)
 995  *
 996  * The area from dword 0x20 to 0x3ff is available for driver usage.
 997  */
 998 #define READ_HWSP(dev_priv, reg)  (((volatile u32*)(dev_priv->hw_status_page))[reg])
 999 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
1000 #define I915_GEM_HWS_INDEX              0x20
1001 #define I915_BREADCRUMB_INDEX           0x21
1002
1003 extern int i915_wrap_ring(struct drm_device * dev);
1004 extern int i915_wait_ring(struct drm_device * dev, int n, const char *caller);
1005
1006 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1007
1008 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
1009 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
1010 #define IS_I85X(dev)            ((dev)->pci_device == 0x3582)
1011 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
1012 #define IS_I8XX(dev)            (INTEL_INFO(dev)->is_i8xx)
1013 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1014 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
1015 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
1016 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1017 #define IS_I965G(dev)           (INTEL_INFO(dev)->is_i965g)
1018 #define IS_I965GM(dev)          (INTEL_INFO(dev)->is_i965gm)
1019 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
1020 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1021 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
1022 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
1023 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1024 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1025 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
1026 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
1027 #define IS_IRONLAKE(dev)        (INTEL_INFO(dev)->is_ironlake)
1028 #define IS_I9XX(dev)            (INTEL_INFO(dev)->is_i9xx)
1029 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1030
1031 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1032
1033 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1034  * rows, which changed the alignment requirements and fence programming.
1035  */
1036 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1037                                                       IS_I915GM(dev)))
1038 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (IS_I9XX(dev) && !IS_PINEVIEW(dev))
1039 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_IRONLAKE(dev))
1040 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_IRONLAKE(dev))
1041 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
1042 #define SUPPORTS_TV(dev)                (IS_I9XX(dev) && IS_MOBILE(dev) && \
1043                                         !IS_IRONLAKE(dev) && !IS_PINEVIEW(dev))
1044 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1045 /* dsparb controlled by hw only */
1046 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1047
1048 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IRONLAKE(dev))
1049 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1050 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1051 #define I915_HAS_RC6(dev) (INTEL_INFO(dev)->has_rc6)
1052
1053 #define PRIMARY_RINGBUFFER_SIZE         (128*1024)
1054
1055 #endif