1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "i915_gem_gtt.h"
39 #include <linux/io-mapping.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 #include <drm/intel-gtt.h>
43 #include <linux/backlight.h>
44 #include <linux/hashtable.h>
45 #include <linux/intel-iommu.h>
46 #include <linux/kref.h>
47 #include <linux/pm_qos.h>
49 /* General customization:
52 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
54 #define DRIVER_NAME "i915"
55 #define DRIVER_DESC "Intel Graphics"
56 #define DRIVER_DATE "20140620"
64 I915_MAX_PIPES
= _PIPE_EDP
66 #define pipe_name(p) ((p) + 'A')
75 #define transcoder_name(t) ((t) + 'A')
82 #define plane_name(p) ((p) + 'A')
84 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
94 #define port_name(p) ((p) + 'A')
96 #define I915_NUM_PHYS_VLV 2
108 enum intel_display_power_domain
{
112 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
113 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
114 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
115 POWER_DOMAIN_TRANSCODER_A
,
116 POWER_DOMAIN_TRANSCODER_B
,
117 POWER_DOMAIN_TRANSCODER_C
,
118 POWER_DOMAIN_TRANSCODER_EDP
,
119 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
120 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
121 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
122 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
123 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
124 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
125 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
126 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
127 POWER_DOMAIN_PORT_DSI
,
128 POWER_DOMAIN_PORT_CRT
,
129 POWER_DOMAIN_PORT_OTHER
,
137 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
138 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
139 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
140 #define POWER_DOMAIN_TRANSCODER(tran) \
141 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
142 (tran) + POWER_DOMAIN_TRANSCODER_A)
146 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
147 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
157 #define I915_GEM_GPU_DOMAINS \
158 (I915_GEM_DOMAIN_RENDER | \
159 I915_GEM_DOMAIN_SAMPLER | \
160 I915_GEM_DOMAIN_COMMAND | \
161 I915_GEM_DOMAIN_INSTRUCTION | \
162 I915_GEM_DOMAIN_VERTEX)
164 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
165 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
167 #define for_each_crtc(dev, crtc) \
168 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
170 #define for_each_intel_crtc(dev, intel_crtc) \
171 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
173 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
174 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
175 if ((intel_encoder)->base.crtc == (__crtc))
177 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
178 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
179 if ((intel_connector)->base.encoder == (__encoder))
181 struct drm_i915_private
;
182 struct i915_mmu_object
;
185 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
186 /* real shared dpll ids must be >= 0 */
190 #define I915_NUM_PLLS 2
192 struct intel_dpll_hw_state
{
199 struct intel_shared_dpll
{
200 int refcount
; /* count of number of CRTCs sharing this PLL */
201 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
202 bool on
; /* is the PLL actually active? Disabled during modeset */
204 /* should match the index in the dev_priv->shared_dplls array */
205 enum intel_dpll_id id
;
206 struct intel_dpll_hw_state hw_state
;
207 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
208 struct intel_shared_dpll
*pll
);
209 void (*enable
)(struct drm_i915_private
*dev_priv
,
210 struct intel_shared_dpll
*pll
);
211 void (*disable
)(struct drm_i915_private
*dev_priv
,
212 struct intel_shared_dpll
*pll
);
213 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
214 struct intel_shared_dpll
*pll
,
215 struct intel_dpll_hw_state
*hw_state
);
218 /* Used by dp and fdi links */
219 struct intel_link_m_n
{
227 void intel_link_compute_m_n(int bpp
, int nlanes
,
228 int pixel_clock
, int link_clock
,
229 struct intel_link_m_n
*m_n
);
231 struct intel_ddi_plls
{
236 /* Interface history:
239 * 1.2: Add Power Management
240 * 1.3: Add vblank support
241 * 1.4: Fix cmdbuffer path, add heap destroy
242 * 1.5: Add vblank pipe configuration
243 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
244 * - Support vertical blank on secondary display pipe
246 #define DRIVER_MAJOR 1
247 #define DRIVER_MINOR 6
248 #define DRIVER_PATCHLEVEL 0
250 #define WATCH_LISTS 0
253 struct opregion_header
;
254 struct opregion_acpi
;
255 struct opregion_swsci
;
256 struct opregion_asle
;
258 struct intel_opregion
{
259 struct opregion_header __iomem
*header
;
260 struct opregion_acpi __iomem
*acpi
;
261 struct opregion_swsci __iomem
*swsci
;
262 u32 swsci_gbda_sub_functions
;
263 u32 swsci_sbcb_sub_functions
;
264 struct opregion_asle __iomem
*asle
;
266 u32 __iomem
*lid_state
;
267 struct work_struct asle_work
;
269 #define OPREGION_SIZE (8*1024)
271 struct intel_overlay
;
272 struct intel_overlay_error_state
;
274 struct drm_i915_master_private
{
275 drm_local_map_t
*sarea
;
276 struct _drm_i915_sarea
*sarea_priv
;
278 #define I915_FENCE_REG_NONE -1
279 #define I915_MAX_NUM_FENCES 32
280 /* 32 fences + sign bit for FENCE_REG_NONE */
281 #define I915_MAX_NUM_FENCE_BITS 6
283 struct drm_i915_fence_reg
{
284 struct list_head lru_list
;
285 struct drm_i915_gem_object
*obj
;
289 struct sdvo_device_mapping
{
298 struct intel_display_error_state
;
300 struct drm_i915_error_state
{
308 /* Generic register state */
315 u32 error
; /* gen6+ */
316 u32 err_int
; /* gen7 */
322 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
323 u64 fence
[I915_MAX_NUM_FENCES
];
324 struct intel_overlay_error_state
*overlay
;
325 struct intel_display_error_state
*display
;
326 struct drm_i915_error_object
*semaphore_obj
;
328 struct drm_i915_error_ring
{
330 /* Software tracked state */
333 enum intel_ring_hangcheck_action hangcheck_action
;
336 /* our own tracking of ring head and tail */
340 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
358 u32 rc_psmi
; /* sleep state */
359 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
361 struct drm_i915_error_object
{
365 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
367 struct drm_i915_error_request
{
382 char comm
[TASK_COMM_LEN
];
383 } ring
[I915_NUM_RINGS
];
384 struct drm_i915_error_buffer
{
391 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
399 } **active_bo
, **pinned_bo
;
401 u32
*active_bo_count
, *pinned_bo_count
;
404 struct intel_connector
;
405 struct intel_crtc_config
;
406 struct intel_plane_config
;
411 struct drm_i915_display_funcs
{
412 bool (*fbc_enabled
)(struct drm_device
*dev
);
413 void (*enable_fbc
)(struct drm_crtc
*crtc
);
414 void (*disable_fbc
)(struct drm_device
*dev
);
415 int (*get_display_clock_speed
)(struct drm_device
*dev
);
416 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
418 * find_dpll() - Find the best values for the PLL
419 * @limit: limits for the PLL
420 * @crtc: current CRTC
421 * @target: target frequency in kHz
422 * @refclk: reference clock frequency in kHz
423 * @match_clock: if provided, @best_clock P divider must
424 * match the P divider from @match_clock
425 * used for LVDS downclocking
426 * @best_clock: best PLL values found
428 * Returns true on success, false on failure.
430 bool (*find_dpll
)(const struct intel_limit
*limit
,
431 struct drm_crtc
*crtc
,
432 int target
, int refclk
,
433 struct dpll
*match_clock
,
434 struct dpll
*best_clock
);
435 void (*update_wm
)(struct drm_crtc
*crtc
);
436 void (*update_sprite_wm
)(struct drm_plane
*plane
,
437 struct drm_crtc
*crtc
,
438 uint32_t sprite_width
, int pixel_size
,
439 bool enable
, bool scaled
);
440 void (*modeset_global_resources
)(struct drm_device
*dev
);
441 /* Returns the active state of the crtc, and if the crtc is active,
442 * fills out the pipe-config with the hw state. */
443 bool (*get_pipe_config
)(struct intel_crtc
*,
444 struct intel_crtc_config
*);
445 void (*get_plane_config
)(struct intel_crtc
*,
446 struct intel_plane_config
*);
447 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
449 struct drm_framebuffer
*old_fb
);
450 void (*crtc_enable
)(struct drm_crtc
*crtc
);
451 void (*crtc_disable
)(struct drm_crtc
*crtc
);
452 void (*off
)(struct drm_crtc
*crtc
);
453 void (*write_eld
)(struct drm_connector
*connector
,
454 struct drm_crtc
*crtc
,
455 struct drm_display_mode
*mode
);
456 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
457 void (*init_clock_gating
)(struct drm_device
*dev
);
458 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
459 struct drm_framebuffer
*fb
,
460 struct drm_i915_gem_object
*obj
,
461 struct intel_engine_cs
*ring
,
463 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
464 struct drm_framebuffer
*fb
,
466 void (*hpd_irq_setup
)(struct drm_device
*dev
);
467 /* clock updates for mode set */
469 /* render clock increase/decrease */
470 /* display clock increase/decrease */
471 /* pll clock increase/decrease */
473 int (*setup_backlight
)(struct intel_connector
*connector
);
474 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
475 void (*set_backlight
)(struct intel_connector
*connector
,
477 void (*disable_backlight
)(struct intel_connector
*connector
);
478 void (*enable_backlight
)(struct intel_connector
*connector
);
481 struct intel_uncore_funcs
{
482 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
484 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
487 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
488 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
489 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
490 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
492 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
493 uint8_t val
, bool trace
);
494 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
495 uint16_t val
, bool trace
);
496 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
497 uint32_t val
, bool trace
);
498 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
499 uint64_t val
, bool trace
);
502 struct intel_uncore
{
503 spinlock_t lock
; /** lock is also taken in irq contexts. */
505 struct intel_uncore_funcs funcs
;
508 unsigned forcewake_count
;
510 unsigned fw_rendercount
;
511 unsigned fw_mediacount
;
513 struct timer_list force_wake_timer
;
516 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
517 func(is_mobile) sep \
520 func(is_i945gm) sep \
522 func(need_gfx_hws) sep \
524 func(is_pineview) sep \
525 func(is_broadwater) sep \
526 func(is_crestline) sep \
527 func(is_ivybridge) sep \
528 func(is_valleyview) sep \
529 func(is_haswell) sep \
530 func(is_preliminary) sep \
532 func(has_pipe_cxsr) sep \
533 func(has_hotplug) sep \
534 func(cursor_needs_physical) sep \
535 func(has_overlay) sep \
536 func(overlay_needs_physical) sep \
537 func(supports_tv) sep \
542 #define DEFINE_FLAG(name) u8 name:1
543 #define SEP_SEMICOLON ;
545 struct intel_device_info
{
546 u32 display_mmio_offset
;
548 u8 num_sprites
[I915_MAX_PIPES
];
550 u8 ring_mask
; /* Rings supported by the HW */
551 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
552 /* Register offsets for the various display pipes and transcoders */
553 int pipe_offsets
[I915_MAX_TRANSCODERS
];
554 int trans_offsets
[I915_MAX_TRANSCODERS
];
555 int palette_offsets
[I915_MAX_PIPES
];
556 int cursor_offsets
[I915_MAX_PIPES
];
562 enum i915_cache_level
{
564 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
565 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
566 caches, eg sampler/render caches, and the
567 large Last-Level-Cache. LLC is coherent with
568 the CPU, but L3 is only visible to the GPU. */
569 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
572 struct i915_ctx_hang_stats
{
573 /* This context had batch pending when hang was declared */
574 unsigned batch_pending
;
576 /* This context had batch active when hang was declared */
577 unsigned batch_active
;
579 /* Time when this context was last blamed for a GPU reset */
580 unsigned long guilty_ts
;
582 /* This context is banned to submit more work */
586 /* This must match up with the value previously used for execbuf2.rsvd1. */
587 #define DEFAULT_CONTEXT_HANDLE 0
589 * struct intel_context - as the name implies, represents a context.
590 * @ref: reference count.
591 * @user_handle: userspace tracking identity for this context.
592 * @remap_slice: l3 row remapping information.
593 * @file_priv: filp associated with this context (NULL for global default
595 * @hang_stats: information about the role of this context in possible GPU
597 * @vm: virtual memory space used by this context.
598 * @legacy_hw_ctx: render context backing object and whether it is correctly
599 * initialized (legacy ring submission mechanism only).
600 * @link: link in the global list of contexts.
602 * Contexts are memory images used by the hardware to store copies of their
605 struct intel_context
{
609 struct drm_i915_file_private
*file_priv
;
610 struct i915_ctx_hang_stats hang_stats
;
611 struct i915_address_space
*vm
;
614 struct drm_i915_gem_object
*rcs_state
;
618 struct list_head link
;
628 struct drm_mm_node compressed_fb
;
629 struct drm_mm_node
*compressed_llb
;
631 struct intel_fbc_work
{
632 struct delayed_work work
;
633 struct drm_crtc
*crtc
;
634 struct drm_framebuffer
*fb
;
638 FBC_OK
, /* FBC is enabled */
639 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
640 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
641 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
642 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
643 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
644 FBC_BAD_PLANE
, /* fbc not supported on plane */
645 FBC_NOT_TILED
, /* buffer not tiled */
646 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
648 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
653 struct intel_connector
*connector
;
662 struct delayed_work work
;
666 PCH_NONE
= 0, /* No PCH present */
667 PCH_IBX
, /* Ibexpeak PCH */
668 PCH_CPT
, /* Cougarpoint PCH */
669 PCH_LPT
, /* Lynxpoint PCH */
673 enum intel_sbi_destination
{
678 #define QUIRK_PIPEA_FORCE (1<<0)
679 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
680 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
683 struct intel_fbc_work
;
686 struct i2c_adapter adapter
;
690 struct i2c_algo_bit_data bit_algo
;
691 struct drm_i915_private
*dev_priv
;
694 struct i915_suspend_saved_registers
{
715 u32 saveTRANS_HTOTAL_A
;
716 u32 saveTRANS_HBLANK_A
;
717 u32 saveTRANS_HSYNC_A
;
718 u32 saveTRANS_VTOTAL_A
;
719 u32 saveTRANS_VBLANK_A
;
720 u32 saveTRANS_VSYNC_A
;
728 u32 savePFIT_PGM_RATIOS
;
729 u32 saveBLC_HIST_CTL
;
731 u32 saveBLC_PWM_CTL2
;
732 u32 saveBLC_HIST_CTL_B
;
733 u32 saveBLC_CPU_PWM_CTL
;
734 u32 saveBLC_CPU_PWM_CTL2
;
747 u32 saveTRANS_HTOTAL_B
;
748 u32 saveTRANS_HBLANK_B
;
749 u32 saveTRANS_HSYNC_B
;
750 u32 saveTRANS_VTOTAL_B
;
751 u32 saveTRANS_VBLANK_B
;
752 u32 saveTRANS_VSYNC_B
;
766 u32 savePP_ON_DELAYS
;
767 u32 savePP_OFF_DELAYS
;
775 u32 savePFIT_CONTROL
;
776 u32 save_palette_a
[256];
777 u32 save_palette_b
[256];
788 u32 saveCACHE_MODE_0
;
789 u32 saveMI_ARB_STATE
;
800 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
811 u32 savePIPEA_GMCH_DATA_M
;
812 u32 savePIPEB_GMCH_DATA_M
;
813 u32 savePIPEA_GMCH_DATA_N
;
814 u32 savePIPEB_GMCH_DATA_N
;
815 u32 savePIPEA_DP_LINK_M
;
816 u32 savePIPEB_DP_LINK_M
;
817 u32 savePIPEA_DP_LINK_N
;
818 u32 savePIPEB_DP_LINK_N
;
829 u32 savePCH_DREF_CONTROL
;
830 u32 saveDISP_ARB_CTL
;
831 u32 savePIPEA_DATA_M1
;
832 u32 savePIPEA_DATA_N1
;
833 u32 savePIPEA_LINK_M1
;
834 u32 savePIPEA_LINK_N1
;
835 u32 savePIPEB_DATA_M1
;
836 u32 savePIPEB_DATA_N1
;
837 u32 savePIPEB_LINK_M1
;
838 u32 savePIPEB_LINK_N1
;
839 u32 saveMCHBAR_RENDER_STANDBY
;
840 u32 savePCH_PORT_HOTPLUG
;
843 struct vlv_s0ix_state
{
850 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
851 u32 media_max_req_count
;
852 u32 gfx_max_req_count
;
884 /* Display 1 CZ domain */
889 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
891 /* GT SA CZ domain */
898 /* Display 2 CZ domain */
904 struct intel_rps_ei_calc
{
910 struct intel_gen6_power_mgmt
{
911 /* work and pm_iir are protected by dev_priv->irq_lock */
912 struct work_struct work
;
915 /* Frequencies are stored in potentially platform dependent multiples.
916 * In other words, *_freq needs to be multiplied by X to be interesting.
917 * Soft limits are those which are used for the dynamic reclocking done
918 * by the driver (raise frequencies under heavy loads, and lower for
919 * lighter loads). Hard limits are those imposed by the hardware.
921 * A distinction is made for overclocking, which is never enabled by
922 * default, and is considered to be above the hard limit if it's
925 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
926 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
927 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
928 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
929 u8 min_freq
; /* AKA RPn. Minimum frequency */
930 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
931 u8 rp1_freq
; /* "less than" RP0 power/freqency */
932 u8 rp0_freq
; /* Non-overclocked max frequency. */
934 u32 ei_interrupt_count
;
937 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
940 struct delayed_work delayed_resume_work
;
943 * Protects RPS/RC6 register access and PCU communication.
944 * Must be taken after struct_mutex if nested.
946 struct mutex hw_lock
;
949 /* defined intel_pm.c */
950 extern spinlock_t mchdev_lock
;
952 struct intel_ilk_power_mgmt
{
960 unsigned long last_time1
;
961 unsigned long chipset_power
;
963 struct timespec last_time2
;
964 unsigned long gfx_power
;
970 struct drm_i915_gem_object
*pwrctx
;
971 struct drm_i915_gem_object
*renderctx
;
974 struct drm_i915_private
;
975 struct i915_power_well
;
977 struct i915_power_well_ops
{
979 * Synchronize the well's hw state to match the current sw state, for
980 * example enable/disable it based on the current refcount. Called
981 * during driver init and resume time, possibly after first calling
982 * the enable/disable handlers.
984 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
985 struct i915_power_well
*power_well
);
987 * Enable the well and resources that depend on it (for example
988 * interrupts located on the well). Called after the 0->1 refcount
991 void (*enable
)(struct drm_i915_private
*dev_priv
,
992 struct i915_power_well
*power_well
);
994 * Disable the well and resources that depend on it. Called after
995 * the 1->0 refcount transition.
997 void (*disable
)(struct drm_i915_private
*dev_priv
,
998 struct i915_power_well
*power_well
);
999 /* Returns the hw enabled state. */
1000 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1001 struct i915_power_well
*power_well
);
1004 /* Power well structure for haswell */
1005 struct i915_power_well
{
1008 /* power well enable/disable usage count */
1010 /* cached hw enabled state */
1012 unsigned long domains
;
1014 const struct i915_power_well_ops
*ops
;
1017 struct i915_power_domains
{
1019 * Power wells needed for initialization at driver init and suspend
1020 * time are on. They are kept on until after the first modeset.
1024 int power_well_count
;
1027 int domain_use_count
[POWER_DOMAIN_NUM
];
1028 struct i915_power_well
*power_wells
;
1031 struct i915_dri1_state
{
1032 unsigned allow_batchbuffer
: 1;
1033 u32 __iomem
*gfx_hws_cpu_addr
;
1044 struct i915_ums_state
{
1046 * Flag if the X Server, and thus DRM, is not currently in
1047 * control of the device.
1049 * This is set between LeaveVT and EnterVT. It needs to be
1050 * replaced with a semaphore. It also needs to be
1051 * transitioned away from for kernel modesetting.
1056 #define MAX_L3_SLICES 2
1057 struct intel_l3_parity
{
1058 u32
*remap_info
[MAX_L3_SLICES
];
1059 struct work_struct error_work
;
1063 struct i915_gem_mm
{
1064 /** Memory allocator for GTT stolen memory */
1065 struct drm_mm stolen
;
1066 /** List of all objects in gtt_space. Used to restore gtt
1067 * mappings on resume */
1068 struct list_head bound_list
;
1070 * List of objects which are not bound to the GTT (thus
1071 * are idle and not used by the GPU) but still have
1072 * (presumably uncached) pages still attached.
1074 struct list_head unbound_list
;
1076 /** Usable portion of the GTT for GEM */
1077 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1079 /** PPGTT used for aliasing the PPGTT with the GTT */
1080 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1082 struct notifier_block oom_notifier
;
1083 struct shrinker shrinker
;
1084 bool shrinker_no_lock_stealing
;
1086 /** LRU list of objects with fence regs on them. */
1087 struct list_head fence_list
;
1090 * We leave the user IRQ off as much as possible,
1091 * but this means that requests will finish and never
1092 * be retired once the system goes idle. Set a timer to
1093 * fire periodically while the ring is running. When it
1094 * fires, go retire requests.
1096 struct delayed_work retire_work
;
1099 * When we detect an idle GPU, we want to turn on
1100 * powersaving features. So once we see that there
1101 * are no more requests outstanding and no more
1102 * arrive within a small period of time, we fire
1103 * off the idle_work.
1105 struct delayed_work idle_work
;
1108 * Are we in a non-interruptible section of code like
1114 * Is the GPU currently considered idle, or busy executing userspace
1115 * requests? Whilst idle, we attempt to power down the hardware and
1116 * display clocks. In order to reduce the effect on performance, there
1117 * is a slight delay before we do so.
1121 /* the indicator for dispatch video commands on two BSD rings */
1122 int bsd_ring_dispatch_index
;
1124 /** Bit 6 swizzling required for X tiling */
1125 uint32_t bit_6_swizzle_x
;
1126 /** Bit 6 swizzling required for Y tiling */
1127 uint32_t bit_6_swizzle_y
;
1129 /* accounting, useful for userland debugging */
1130 spinlock_t object_stat_lock
;
1131 size_t object_memory
;
1135 struct drm_i915_error_state_buf
{
1144 struct i915_error_state_file_priv
{
1145 struct drm_device
*dev
;
1146 struct drm_i915_error_state
*error
;
1149 struct i915_gpu_error
{
1150 /* For hangcheck timer */
1151 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1152 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1153 /* Hang gpu twice in this window and your context gets banned */
1154 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1156 struct timer_list hangcheck_timer
;
1158 /* For reset and error_state handling. */
1160 /* Protected by the above dev->gpu_error.lock. */
1161 struct drm_i915_error_state
*first_error
;
1162 struct work_struct work
;
1165 unsigned long missed_irq_rings
;
1168 * State variable controlling the reset flow and count
1170 * This is a counter which gets incremented when reset is triggered,
1171 * and again when reset has been handled. So odd values (lowest bit set)
1172 * means that reset is in progress and even values that
1173 * (reset_counter >> 1):th reset was successfully completed.
1175 * If reset is not completed succesfully, the I915_WEDGE bit is
1176 * set meaning that hardware is terminally sour and there is no
1177 * recovery. All waiters on the reset_queue will be woken when
1180 * This counter is used by the wait_seqno code to notice that reset
1181 * event happened and it needs to restart the entire ioctl (since most
1182 * likely the seqno it waited for won't ever signal anytime soon).
1184 * This is important for lock-free wait paths, where no contended lock
1185 * naturally enforces the correct ordering between the bail-out of the
1186 * waiter and the gpu reset work code.
1188 atomic_t reset_counter
;
1190 #define I915_RESET_IN_PROGRESS_FLAG 1
1191 #define I915_WEDGED (1 << 31)
1194 * Waitqueue to signal when the reset has completed. Used by clients
1195 * that wait for dev_priv->mm.wedged to settle.
1197 wait_queue_head_t reset_queue
;
1199 /* Userspace knobs for gpu hang simulation;
1200 * combines both a ring mask, and extra flags
1203 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1204 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1206 /* For missed irq/seqno simulation. */
1207 unsigned int test_irq_rings
;
1210 enum modeset_restore
{
1211 MODESET_ON_LID_OPEN
,
1216 struct ddi_vbt_port_info
{
1217 uint8_t hdmi_level_shift
;
1219 uint8_t supports_dvi
:1;
1220 uint8_t supports_hdmi
:1;
1221 uint8_t supports_dp
:1;
1224 enum drrs_support_type
{
1225 DRRS_NOT_SUPPORTED
= 0,
1226 STATIC_DRRS_SUPPORT
= 1,
1227 SEAMLESS_DRRS_SUPPORT
= 2
1230 struct intel_vbt_data
{
1231 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1232 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1235 unsigned int int_tv_support
:1;
1236 unsigned int lvds_dither
:1;
1237 unsigned int lvds_vbt
:1;
1238 unsigned int int_crt_support
:1;
1239 unsigned int lvds_use_ssc
:1;
1240 unsigned int display_clock_mode
:1;
1241 unsigned int fdi_rx_polarity_inverted
:1;
1242 unsigned int has_mipi
:1;
1244 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1246 enum drrs_support_type drrs_type
;
1251 int edp_preemphasis
;
1253 bool edp_initialized
;
1256 struct edp_power_seq edp_pps
;
1261 bool active_low_pwm
;
1268 struct mipi_config
*config
;
1269 struct mipi_pps_data
*pps
;
1273 u8
*sequence
[MIPI_SEQ_MAX
];
1279 union child_device_config
*child_dev
;
1281 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1284 enum intel_ddb_partitioning
{
1286 INTEL_DDB_PART_5_6
, /* IVB+ */
1289 struct intel_wm_level
{
1297 struct ilk_wm_values
{
1298 uint32_t wm_pipe
[3];
1300 uint32_t wm_lp_spr
[3];
1301 uint32_t wm_linetime
[3];
1303 enum intel_ddb_partitioning partitioning
;
1307 * This struct helps tracking the state needed for runtime PM, which puts the
1308 * device in PCI D3 state. Notice that when this happens, nothing on the
1309 * graphics device works, even register access, so we don't get interrupts nor
1312 * Every piece of our code that needs to actually touch the hardware needs to
1313 * either call intel_runtime_pm_get or call intel_display_power_get with the
1314 * appropriate power domain.
1316 * Our driver uses the autosuspend delay feature, which means we'll only really
1317 * suspend if we stay with zero refcount for a certain amount of time. The
1318 * default value is currently very conservative (see intel_init_runtime_pm), but
1319 * it can be changed with the standard runtime PM files from sysfs.
1321 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1322 * goes back to false exactly before we reenable the IRQs. We use this variable
1323 * to check if someone is trying to enable/disable IRQs while they're supposed
1324 * to be disabled. This shouldn't happen and we'll print some error messages in
1327 * For more, read the Documentation/power/runtime_pm.txt.
1329 struct i915_runtime_pm
{
1334 enum intel_pipe_crc_source
{
1335 INTEL_PIPE_CRC_SOURCE_NONE
,
1336 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1337 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1338 INTEL_PIPE_CRC_SOURCE_PF
,
1339 INTEL_PIPE_CRC_SOURCE_PIPE
,
1340 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1341 INTEL_PIPE_CRC_SOURCE_TV
,
1342 INTEL_PIPE_CRC_SOURCE_DP_B
,
1343 INTEL_PIPE_CRC_SOURCE_DP_C
,
1344 INTEL_PIPE_CRC_SOURCE_DP_D
,
1345 INTEL_PIPE_CRC_SOURCE_AUTO
,
1346 INTEL_PIPE_CRC_SOURCE_MAX
,
1349 struct intel_pipe_crc_entry
{
1354 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1355 struct intel_pipe_crc
{
1357 bool opened
; /* exclusive access to the result file */
1358 struct intel_pipe_crc_entry
*entries
;
1359 enum intel_pipe_crc_source source
;
1361 wait_queue_head_t wq
;
1364 struct i915_frontbuffer_tracking
{
1368 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1375 struct drm_i915_private
{
1376 struct drm_device
*dev
;
1377 struct kmem_cache
*slab
;
1379 const struct intel_device_info info
;
1381 int relative_constants_mode
;
1385 struct intel_uncore uncore
;
1387 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1390 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1391 * controller on different i2c buses. */
1392 struct mutex gmbus_mutex
;
1395 * Base address of the gmbus and gpio block.
1397 uint32_t gpio_mmio_base
;
1399 /* MMIO base address for MIPI regs */
1400 uint32_t mipi_mmio_base
;
1402 wait_queue_head_t gmbus_wait_queue
;
1404 struct pci_dev
*bridge_dev
;
1405 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1406 struct drm_i915_gem_object
*semaphore_obj
;
1407 uint32_t last_seqno
, next_seqno
;
1409 drm_dma_handle_t
*status_page_dmah
;
1410 struct resource mch_res
;
1412 /* protects the irq masks */
1413 spinlock_t irq_lock
;
1415 /* protects the mmio flip data */
1416 spinlock_t mmio_flip_lock
;
1418 bool display_irqs_enabled
;
1420 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1421 struct pm_qos_request pm_qos
;
1423 /* DPIO indirect register protection */
1424 struct mutex dpio_lock
;
1426 /** Cached value of IMR to avoid reads in updating the bitfield */
1429 u32 de_irq_mask
[I915_MAX_PIPES
];
1434 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1436 struct work_struct hotplug_work
;
1437 bool enable_hotplug_processing
;
1439 unsigned long hpd_last_jiffies
;
1444 HPD_MARK_DISABLED
= 2
1446 } hpd_stats
[HPD_NUM_PINS
];
1448 struct timer_list hotplug_reenable_timer
;
1450 struct i915_fbc fbc
;
1451 struct i915_drrs drrs
;
1452 struct intel_opregion opregion
;
1453 struct intel_vbt_data vbt
;
1456 struct intel_overlay
*overlay
;
1458 /* backlight registers and fields in struct intel_panel */
1459 spinlock_t backlight_lock
;
1462 bool no_aux_handshake
;
1464 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1465 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1466 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1468 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1469 unsigned int vlv_cdclk_freq
;
1472 * wq - Driver workqueue for GEM.
1474 * NOTE: Work items scheduled here are not allowed to grab any modeset
1475 * locks, for otherwise the flushing done in the pageflip code will
1476 * result in deadlocks.
1478 struct workqueue_struct
*wq
;
1480 /* Display functions */
1481 struct drm_i915_display_funcs display
;
1483 /* PCH chipset type */
1484 enum intel_pch pch_type
;
1485 unsigned short pch_id
;
1487 unsigned long quirks
;
1489 enum modeset_restore modeset_restore
;
1490 struct mutex modeset_restore_lock
;
1492 struct list_head vm_list
; /* Global list of all address spaces */
1493 struct i915_gtt gtt
; /* VM representing the global address space */
1495 struct i915_gem_mm mm
;
1496 #if defined(CONFIG_MMU_NOTIFIER)
1497 DECLARE_HASHTABLE(mmu_notifiers
, 7);
1500 /* Kernel Modesetting */
1502 struct sdvo_device_mapping sdvo_mappings
[2];
1504 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1505 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1506 wait_queue_head_t pending_flip_queue
;
1508 #ifdef CONFIG_DEBUG_FS
1509 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1512 int num_shared_dpll
;
1513 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1514 struct intel_ddi_plls ddi_plls
;
1515 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1517 /* Reclocking support */
1518 bool render_reclock_avail
;
1519 bool lvds_downclock_avail
;
1520 /* indicates the reduced downclock for LVDS*/
1523 struct i915_frontbuffer_tracking fb_tracking
;
1527 bool mchbar_need_disable
;
1529 struct intel_l3_parity l3_parity
;
1531 /* Cannot be determined by PCIID. You must always read a register. */
1534 /* gen6+ rps state */
1535 struct intel_gen6_power_mgmt rps
;
1537 /* rps wa up ei calculation */
1538 struct intel_rps_ei_calc rps_up_ei
;
1540 /* rps wa down ei calculation */
1541 struct intel_rps_ei_calc rps_down_ei
;
1544 /* ilk-only ips/rps state. Everything in here is protected by the global
1545 * mchdev_lock in intel_pm.c */
1546 struct intel_ilk_power_mgmt ips
;
1548 struct i915_power_domains power_domains
;
1550 struct i915_psr psr
;
1552 struct i915_gpu_error gpu_error
;
1554 struct drm_i915_gem_object
*vlv_pctx
;
1556 #ifdef CONFIG_DRM_I915_FBDEV
1557 /* list of fbdev register on this device */
1558 struct intel_fbdev
*fbdev
;
1562 * The console may be contended at resume, but we don't
1563 * want it to block on it.
1565 struct work_struct console_resume_work
;
1567 struct drm_property
*broadcast_rgb_property
;
1568 struct drm_property
*force_audio_property
;
1570 uint32_t hw_context_size
;
1571 struct list_head context_list
;
1576 struct i915_suspend_saved_registers regfile
;
1577 struct vlv_s0ix_state vlv_s0ix_state
;
1581 * Raw watermark latency values:
1582 * in 0.1us units for WM0,
1583 * in 0.5us units for WM1+.
1586 uint16_t pri_latency
[5];
1588 uint16_t spr_latency
[5];
1590 uint16_t cur_latency
[5];
1592 /* current hardware state */
1593 struct ilk_wm_values hw
;
1596 struct i915_runtime_pm pm
;
1598 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1599 u32 long_hpd_port_mask
;
1600 u32 short_hpd_port_mask
;
1601 struct work_struct dig_port_work
;
1603 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1605 struct i915_dri1_state dri1
;
1606 /* Old ums support infrastructure, same warning applies. */
1607 struct i915_ums_state ums
;
1610 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1611 * will be rejected. Instead look for a better place.
1615 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1617 return dev
->dev_private
;
1620 /* Iterate over initialised rings */
1621 #define for_each_ring(ring__, dev_priv__, i__) \
1622 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1623 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1625 enum hdmi_force_audio
{
1626 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1627 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1628 HDMI_AUDIO_AUTO
, /* trust EDID */
1629 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1632 #define I915_GTT_OFFSET_NONE ((u32)-1)
1634 struct drm_i915_gem_object_ops
{
1635 /* Interface between the GEM object and its backing storage.
1636 * get_pages() is called once prior to the use of the associated set
1637 * of pages before to binding them into the GTT, and put_pages() is
1638 * called after we no longer need them. As we expect there to be
1639 * associated cost with migrating pages between the backing storage
1640 * and making them available for the GPU (e.g. clflush), we may hold
1641 * onto the pages after they are no longer referenced by the GPU
1642 * in case they may be used again shortly (for example migrating the
1643 * pages to a different memory domain within the GTT). put_pages()
1644 * will therefore most likely be called when the object itself is
1645 * being released or under memory pressure (where we attempt to
1646 * reap pages for the shrinker).
1648 int (*get_pages
)(struct drm_i915_gem_object
*);
1649 void (*put_pages
)(struct drm_i915_gem_object
*);
1650 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1651 void (*release
)(struct drm_i915_gem_object
*);
1655 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1656 * considered to be the frontbuffer for the given plane interface-vise. This
1657 * doesn't mean that the hw necessarily already scans it out, but that any
1658 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1660 * We have one bit per pipe and per scanout plane type.
1662 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1663 #define INTEL_FRONTBUFFER_BITS \
1664 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1665 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1666 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1667 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1668 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1669 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1670 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1671 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1672 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1673 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1674 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1676 struct drm_i915_gem_object
{
1677 struct drm_gem_object base
;
1679 const struct drm_i915_gem_object_ops
*ops
;
1681 /** List of VMAs backed by this object */
1682 struct list_head vma_list
;
1684 /** Stolen memory for this object, instead of being backed by shmem. */
1685 struct drm_mm_node
*stolen
;
1686 struct list_head global_list
;
1688 struct list_head ring_list
;
1689 /** Used in execbuf to temporarily hold a ref */
1690 struct list_head obj_exec_link
;
1693 * This is set if the object is on the active lists (has pending
1694 * rendering and so a non-zero seqno), and is not set if it i s on
1695 * inactive (ready to be unbound) list.
1697 unsigned int active
:1;
1700 * This is set if the object has been written to since last bound
1703 unsigned int dirty
:1;
1706 * Fence register bits (if any) for this object. Will be set
1707 * as needed when mapped into the GTT.
1708 * Protected by dev->struct_mutex.
1710 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1713 * Advice: are the backing pages purgeable?
1715 unsigned int madv
:2;
1718 * Current tiling mode for the object.
1720 unsigned int tiling_mode
:2;
1722 * Whether the tiling parameters for the currently associated fence
1723 * register have changed. Note that for the purposes of tracking
1724 * tiling changes we also treat the unfenced register, the register
1725 * slot that the object occupies whilst it executes a fenced
1726 * command (such as BLT on gen2/3), as a "fence".
1728 unsigned int fence_dirty
:1;
1731 * Is the object at the current location in the gtt mappable and
1732 * fenceable? Used to avoid costly recalculations.
1734 unsigned int map_and_fenceable
:1;
1737 * Whether the current gtt mapping needs to be mappable (and isn't just
1738 * mappable by accident). Track pin and fault separate for a more
1739 * accurate mappable working set.
1741 unsigned int fault_mappable
:1;
1742 unsigned int pin_mappable
:1;
1743 unsigned int pin_display
:1;
1746 * Is the object to be mapped as read-only to the GPU
1747 * Only honoured if hardware has relevant pte bit
1749 unsigned long gt_ro
:1;
1752 * Is the GPU currently using a fence to access this buffer,
1754 unsigned int pending_fenced_gpu_access
:1;
1755 unsigned int fenced_gpu_access
:1;
1757 unsigned int cache_level
:3;
1759 unsigned int has_aliasing_ppgtt_mapping
:1;
1760 unsigned int has_global_gtt_mapping
:1;
1761 unsigned int has_dma_mapping
:1;
1763 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1765 struct sg_table
*pages
;
1766 int pages_pin_count
;
1768 /* prime dma-buf support */
1769 void *dma_buf_vmapping
;
1772 struct intel_engine_cs
*ring
;
1774 /** Breadcrumb of last rendering to the buffer. */
1775 uint32_t last_read_seqno
;
1776 uint32_t last_write_seqno
;
1777 /** Breadcrumb of last fenced GPU access to the buffer. */
1778 uint32_t last_fenced_seqno
;
1780 /** Current tiling stride for the object, if it's tiled. */
1783 /** References from framebuffers, locks out tiling changes. */
1784 unsigned long framebuffer_references
;
1786 /** Record of address bit 17 of each page at last unbind. */
1787 unsigned long *bit_17
;
1789 /** User space pin count and filp owning the pin */
1790 unsigned long user_pin_count
;
1791 struct drm_file
*pin_filp
;
1793 /** for phy allocated objects */
1794 drm_dma_handle_t
*phys_handle
;
1797 struct i915_gem_userptr
{
1799 unsigned read_only
:1;
1800 unsigned workers
:4;
1801 #define I915_GEM_USERPTR_MAX_WORKERS 15
1803 struct mm_struct
*mm
;
1804 struct i915_mmu_object
*mn
;
1805 struct work_struct
*work
;
1809 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1811 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1812 struct drm_i915_gem_object
*new,
1813 unsigned frontbuffer_bits
);
1816 * Request queue structure.
1818 * The request queue allows us to note sequence numbers that have been emitted
1819 * and may be associated with active buffers to be retired.
1821 * By keeping this list, we can avoid having to do questionable
1822 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1823 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1825 struct drm_i915_gem_request
{
1826 /** On Which ring this request was generated */
1827 struct intel_engine_cs
*ring
;
1829 /** GEM sequence number associated with this request. */
1832 /** Position in the ringbuffer of the start of the request */
1835 /** Position in the ringbuffer of the end of the request */
1838 /** Context related to this request */
1839 struct intel_context
*ctx
;
1841 /** Batch buffer related to this request if any */
1842 struct drm_i915_gem_object
*batch_obj
;
1844 /** Time at which this request was emitted, in jiffies. */
1845 unsigned long emitted_jiffies
;
1847 /** global list entry for this request */
1848 struct list_head list
;
1850 struct drm_i915_file_private
*file_priv
;
1851 /** file_priv list entry for this request */
1852 struct list_head client_list
;
1855 struct drm_i915_file_private
{
1856 struct drm_i915_private
*dev_priv
;
1857 struct drm_file
*file
;
1861 struct list_head request_list
;
1862 struct delayed_work idle_work
;
1864 struct idr context_idr
;
1866 atomic_t rps_wait_boost
;
1867 struct intel_engine_cs
*bsd_ring
;
1871 * A command that requires special handling by the command parser.
1873 struct drm_i915_cmd_descriptor
{
1875 * Flags describing how the command parser processes the command.
1877 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1878 * a length mask if not set
1879 * CMD_DESC_SKIP: The command is allowed but does not follow the
1880 * standard length encoding for the opcode range in
1882 * CMD_DESC_REJECT: The command is never allowed
1883 * CMD_DESC_REGISTER: The command should be checked against the
1884 * register whitelist for the appropriate ring
1885 * CMD_DESC_MASTER: The command is allowed if the submitting process
1889 #define CMD_DESC_FIXED (1<<0)
1890 #define CMD_DESC_SKIP (1<<1)
1891 #define CMD_DESC_REJECT (1<<2)
1892 #define CMD_DESC_REGISTER (1<<3)
1893 #define CMD_DESC_BITMASK (1<<4)
1894 #define CMD_DESC_MASTER (1<<5)
1897 * The command's unique identification bits and the bitmask to get them.
1898 * This isn't strictly the opcode field as defined in the spec and may
1899 * also include type, subtype, and/or subop fields.
1907 * The command's length. The command is either fixed length (i.e. does
1908 * not include a length field) or has a length field mask. The flag
1909 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1910 * a length mask. All command entries in a command table must include
1911 * length information.
1919 * Describes where to find a register address in the command to check
1920 * against the ring's register whitelist. Only valid if flags has the
1921 * CMD_DESC_REGISTER bit set.
1928 #define MAX_CMD_DESC_BITMASKS 3
1930 * Describes command checks where a particular dword is masked and
1931 * compared against an expected value. If the command does not match
1932 * the expected value, the parser rejects it. Only valid if flags has
1933 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1936 * If the check specifies a non-zero condition_mask then the parser
1937 * only performs the check when the bits specified by condition_mask
1944 u32 condition_offset
;
1946 } bits
[MAX_CMD_DESC_BITMASKS
];
1950 * A table of commands requiring special handling by the command parser.
1952 * Each ring has an array of tables. Each table consists of an array of command
1953 * descriptors, which must be sorted with command opcodes in ascending order.
1955 struct drm_i915_cmd_table
{
1956 const struct drm_i915_cmd_descriptor
*table
;
1960 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1962 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1963 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1964 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1965 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1966 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1967 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1968 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1969 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1970 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1971 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1972 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1973 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1974 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1975 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1976 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1977 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1978 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1979 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1980 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1981 (dev)->pdev->device == 0x0152 || \
1982 (dev)->pdev->device == 0x015a)
1983 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1984 (dev)->pdev->device == 0x0106 || \
1985 (dev)->pdev->device == 0x010A)
1986 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1987 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1988 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1989 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1990 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1991 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1992 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1993 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1994 (((dev)->pdev->device & 0xf) == 0x2 || \
1995 ((dev)->pdev->device & 0xf) == 0x6 || \
1996 ((dev)->pdev->device & 0xf) == 0xe))
1997 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1998 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1999 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
2000 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2001 ((dev)->pdev->device & 0x00F0) == 0x0020)
2002 /* ULX machines are also considered ULT. */
2003 #define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
2004 (dev)->pdev->device == 0x0A1E)
2005 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2008 * The genX designation typically refers to the render engine, so render
2009 * capability related checks should use IS_GEN, while display and other checks
2010 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2013 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2014 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2015 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2016 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2017 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2018 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2019 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2021 #define RENDER_RING (1<<RCS)
2022 #define BSD_RING (1<<VCS)
2023 #define BLT_RING (1<<BCS)
2024 #define VEBOX_RING (1<<VECS)
2025 #define BSD2_RING (1<<VCS2)
2026 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2027 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2028 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2029 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2030 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2031 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2032 to_i915(dev)->ellc_size)
2033 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2035 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2036 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2037 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2038 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
2039 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
2041 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2042 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2044 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2045 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2047 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2048 * even when in MSI mode. This results in spurious interrupt warnings if the
2049 * legacy irq no. is shared with another device. The kernel then disables that
2050 * interrupt source and so prevents the other device from working properly.
2052 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2053 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2055 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2056 * rows, which changed the alignment requirements and fence programming.
2058 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2060 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2061 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2062 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2063 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2064 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2066 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2067 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2068 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2070 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2072 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2073 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2074 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2075 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2076 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2078 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2079 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2080 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2081 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2082 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2083 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2085 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2086 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2087 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2088 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2089 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2090 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2092 /* DPF == dynamic parity feature */
2093 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2094 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2096 #define GT_FREQUENCY_MULTIPLIER 50
2098 #include "i915_trace.h"
2100 extern const struct drm_ioctl_desc i915_ioctls
[];
2101 extern int i915_max_ioctl
;
2103 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
2104 extern int i915_resume(struct drm_device
*dev
);
2105 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2106 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2109 struct i915_params
{
2111 int panel_ignore_lid
;
2112 unsigned int powersave
;
2114 unsigned int lvds_downclock
;
2115 int lvds_channel_mode
;
2117 int vbt_sdvo_panel_type
;
2122 unsigned int preliminary_hw_support
;
2123 int disable_power_well
;
2125 int invert_brightness
;
2126 int enable_cmd_parser
;
2127 /* leave bools at the end to not create holes */
2128 bool enable_hangcheck
;
2130 bool prefault_disable
;
2132 bool disable_display
;
2133 bool disable_vtd_wa
;
2136 extern struct i915_params i915 __read_mostly
;
2139 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2140 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2141 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2142 extern int i915_driver_unload(struct drm_device
*);
2143 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2144 extern void i915_driver_lastclose(struct drm_device
* dev
);
2145 extern void i915_driver_preclose(struct drm_device
*dev
,
2146 struct drm_file
*file
);
2147 extern void i915_driver_postclose(struct drm_device
*dev
,
2148 struct drm_file
*file
);
2149 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2150 #ifdef CONFIG_COMPAT
2151 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2154 extern int i915_emit_box(struct drm_device
*dev
,
2155 struct drm_clip_rect
*box
,
2157 extern int intel_gpu_reset(struct drm_device
*dev
);
2158 extern int i915_reset(struct drm_device
*dev
);
2159 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2160 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2161 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2162 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2163 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2165 extern void intel_console_resume(struct work_struct
*work
);
2168 void i915_queue_hangcheck(struct drm_device
*dev
);
2170 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2171 const char *fmt
, ...);
2173 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2175 extern void intel_irq_init(struct drm_device
*dev
);
2176 extern void intel_hpd_init(struct drm_device
*dev
);
2178 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2179 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2180 bool restore_forcewake
);
2181 extern void intel_uncore_init(struct drm_device
*dev
);
2182 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2183 extern void intel_uncore_fini(struct drm_device
*dev
);
2184 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2187 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2191 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2194 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2195 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2198 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2199 struct drm_file
*file_priv
);
2200 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2201 struct drm_file
*file_priv
);
2202 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2203 struct drm_file
*file_priv
);
2204 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2205 struct drm_file
*file_priv
);
2206 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2207 struct drm_file
*file_priv
);
2208 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2209 struct drm_file
*file_priv
);
2210 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2211 struct drm_file
*file_priv
);
2212 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2213 struct drm_file
*file_priv
);
2214 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2215 struct drm_file
*file_priv
);
2216 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2217 struct drm_file
*file_priv
);
2218 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2219 struct drm_file
*file_priv
);
2220 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2221 struct drm_file
*file_priv
);
2222 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2223 struct drm_file
*file_priv
);
2224 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2225 struct drm_file
*file
);
2226 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2227 struct drm_file
*file
);
2228 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2229 struct drm_file
*file_priv
);
2230 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2231 struct drm_file
*file_priv
);
2232 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2233 struct drm_file
*file_priv
);
2234 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2235 struct drm_file
*file_priv
);
2236 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2237 struct drm_file
*file_priv
);
2238 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2239 struct drm_file
*file_priv
);
2240 int i915_gem_init_userptr(struct drm_device
*dev
);
2241 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2242 struct drm_file
*file
);
2243 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2244 struct drm_file
*file_priv
);
2245 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2246 struct drm_file
*file_priv
);
2247 void i915_gem_load(struct drm_device
*dev
);
2248 void *i915_gem_object_alloc(struct drm_device
*dev
);
2249 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2250 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2251 const struct drm_i915_gem_object_ops
*ops
);
2252 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2254 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2255 struct i915_address_space
*vm
);
2256 void i915_gem_free_object(struct drm_gem_object
*obj
);
2257 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2259 #define PIN_MAPPABLE 0x1
2260 #define PIN_NONBLOCK 0x2
2261 #define PIN_GLOBAL 0x4
2262 #define PIN_OFFSET_BIAS 0x8
2263 #define PIN_OFFSET_MASK (~4095)
2264 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2265 struct i915_address_space
*vm
,
2268 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2269 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2270 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2271 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2272 void i915_gem_lastclose(struct drm_device
*dev
);
2274 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2275 int *needs_clflush
);
2277 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2278 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2280 struct sg_page_iter sg_iter
;
2282 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2283 return sg_page_iter_page(&sg_iter
);
2287 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2289 BUG_ON(obj
->pages
== NULL
);
2290 obj
->pages_pin_count
++;
2292 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2294 BUG_ON(obj
->pages_pin_count
== 0);
2295 obj
->pages_pin_count
--;
2298 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2299 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2300 struct intel_engine_cs
*to
);
2301 void i915_vma_move_to_active(struct i915_vma
*vma
,
2302 struct intel_engine_cs
*ring
);
2303 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2304 struct drm_device
*dev
,
2305 struct drm_mode_create_dumb
*args
);
2306 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2307 uint32_t handle
, uint64_t *offset
);
2309 * Returns true if seq1 is later than seq2.
2312 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2314 return (int32_t)(seq1
- seq2
) >= 0;
2317 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2318 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2319 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2320 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2322 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2323 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2325 struct drm_i915_gem_request
*
2326 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2328 bool i915_gem_retire_requests(struct drm_device
*dev
);
2329 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2330 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2331 bool interruptible
);
2332 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2334 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2336 return unlikely(atomic_read(&error
->reset_counter
)
2337 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2340 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2342 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2345 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2347 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2350 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2352 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2353 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2356 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2358 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2359 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2362 void i915_gem_reset(struct drm_device
*dev
);
2363 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2364 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2365 int __must_check
i915_gem_init(struct drm_device
*dev
);
2366 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2367 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2368 void i915_gem_init_swizzling(struct drm_device
*dev
);
2369 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2370 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2371 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2372 int __i915_add_request(struct intel_engine_cs
*ring
,
2373 struct drm_file
*file
,
2374 struct drm_i915_gem_object
*batch_obj
,
2376 #define i915_add_request(ring, seqno) \
2377 __i915_add_request(ring, NULL, NULL, seqno)
2378 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2380 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2382 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2385 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2387 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2389 struct intel_engine_cs
*pipelined
);
2390 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2391 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2393 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2394 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2397 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2399 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2400 int tiling_mode
, bool fenced
);
2402 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2403 enum i915_cache_level cache_level
);
2405 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2406 struct dma_buf
*dma_buf
);
2408 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2409 struct drm_gem_object
*gem_obj
, int flags
);
2411 void i915_gem_restore_fences(struct drm_device
*dev
);
2413 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2414 struct i915_address_space
*vm
);
2415 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2416 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2417 struct i915_address_space
*vm
);
2418 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2419 struct i915_address_space
*vm
);
2420 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2421 struct i915_address_space
*vm
);
2423 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2424 struct i915_address_space
*vm
);
2426 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2427 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2428 struct i915_vma
*vma
;
2429 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2430 if (vma
->pin_count
> 0)
2435 /* Some GGTT VM helpers */
2436 #define obj_to_ggtt(obj) \
2437 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2438 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2440 struct i915_address_space
*ggtt
=
2441 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2445 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2447 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
2450 static inline unsigned long
2451 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2453 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
2456 static inline unsigned long
2457 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2459 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
2462 static inline int __must_check
2463 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2467 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
, flags
| PIN_GLOBAL
);
2471 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2473 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2476 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2478 /* i915_gem_context.c */
2479 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2480 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2481 void i915_gem_context_fini(struct drm_device
*dev
);
2482 void i915_gem_context_reset(struct drm_device
*dev
);
2483 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2484 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2485 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2486 int i915_switch_context(struct intel_engine_cs
*ring
,
2487 struct intel_context
*to
);
2488 struct intel_context
*
2489 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2490 void i915_gem_context_free(struct kref
*ctx_ref
);
2491 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2493 kref_get(&ctx
->ref
);
2496 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2498 kref_put(&ctx
->ref
, i915_gem_context_free
);
2501 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2503 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2506 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2507 struct drm_file
*file
);
2508 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2509 struct drm_file
*file
);
2511 /* i915_gem_render_state.c */
2512 int i915_gem_render_state_init(struct intel_engine_cs
*ring
);
2513 /* i915_gem_evict.c */
2514 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2515 struct i915_address_space
*vm
,
2518 unsigned cache_level
,
2519 unsigned long start
,
2522 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2523 int i915_gem_evict_everything(struct drm_device
*dev
);
2525 /* belongs in i915_gem_gtt.h */
2526 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2528 if (INTEL_INFO(dev
)->gen
< 6)
2529 intel_gtt_chipset_flush();
2532 /* i915_gem_stolen.c */
2533 int i915_gem_init_stolen(struct drm_device
*dev
);
2534 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2535 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2536 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2537 struct drm_i915_gem_object
*
2538 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2539 struct drm_i915_gem_object
*
2540 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2545 /* i915_gem_tiling.c */
2546 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2548 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2550 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2551 obj
->tiling_mode
!= I915_TILING_NONE
;
2554 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2555 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2556 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2558 /* i915_gem_debug.c */
2560 int i915_verify_lists(struct drm_device
*dev
);
2562 #define i915_verify_lists(dev) 0
2565 /* i915_debugfs.c */
2566 int i915_debugfs_init(struct drm_minor
*minor
);
2567 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2568 #ifdef CONFIG_DEBUG_FS
2569 void intel_display_crc_init(struct drm_device
*dev
);
2571 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2574 /* i915_gpu_error.c */
2576 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2577 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2578 const struct i915_error_state_file_priv
*error
);
2579 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2580 size_t count
, loff_t pos
);
2581 static inline void i915_error_state_buf_release(
2582 struct drm_i915_error_state_buf
*eb
)
2586 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2587 const char *error_msg
);
2588 void i915_error_state_get(struct drm_device
*dev
,
2589 struct i915_error_state_file_priv
*error_priv
);
2590 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2591 void i915_destroy_error_state(struct drm_device
*dev
);
2593 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2594 const char *i915_cache_level_str(int type
);
2596 /* i915_cmd_parser.c */
2597 int i915_cmd_parser_get_version(void);
2598 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2599 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2600 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2601 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2602 struct drm_i915_gem_object
*batch_obj
,
2603 u32 batch_start_offset
,
2606 /* i915_suspend.c */
2607 extern int i915_save_state(struct drm_device
*dev
);
2608 extern int i915_restore_state(struct drm_device
*dev
);
2611 void i915_save_display_reg(struct drm_device
*dev
);
2612 void i915_restore_display_reg(struct drm_device
*dev
);
2615 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2616 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2619 extern int intel_setup_gmbus(struct drm_device
*dev
);
2620 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2621 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2623 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2626 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2627 struct drm_i915_private
*dev_priv
, unsigned port
);
2628 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2629 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2630 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2632 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2634 extern void intel_i2c_reset(struct drm_device
*dev
);
2636 /* intel_opregion.c */
2637 struct intel_encoder
;
2639 extern int intel_opregion_setup(struct drm_device
*dev
);
2640 extern void intel_opregion_init(struct drm_device
*dev
);
2641 extern void intel_opregion_fini(struct drm_device
*dev
);
2642 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2643 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2645 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2648 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2649 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2650 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2651 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2653 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2658 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2666 extern void intel_register_dsm_handler(void);
2667 extern void intel_unregister_dsm_handler(void);
2669 static inline void intel_register_dsm_handler(void) { return; }
2670 static inline void intel_unregister_dsm_handler(void) { return; }
2671 #endif /* CONFIG_ACPI */
2674 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2675 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2676 extern void intel_modeset_init(struct drm_device
*dev
);
2677 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2678 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2679 extern void intel_connector_unregister(struct intel_connector
*);
2680 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2681 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2682 bool force_restore
);
2683 extern void i915_redisable_vga(struct drm_device
*dev
);
2684 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2685 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2686 extern void intel_disable_fbc(struct drm_device
*dev
);
2687 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2688 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2689 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2690 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2691 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2692 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2693 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2695 extern void intel_detect_pch(struct drm_device
*dev
);
2696 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2697 extern int intel_enable_rc6(const struct drm_device
*dev
);
2699 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2700 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2701 struct drm_file
*file
);
2702 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2703 struct drm_file
*file
);
2705 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2708 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2709 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2710 struct intel_overlay_error_state
*error
);
2712 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2713 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2714 struct drm_device
*dev
,
2715 struct intel_display_error_state
*error
);
2717 /* On SNB platform, before reading ring registers forcewake bit
2718 * must be set to prevent GT core from power down and stale values being
2721 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2722 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2723 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2725 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2726 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2728 /* intel_sideband.c */
2729 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2730 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2731 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2732 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2733 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2734 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2735 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2736 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2737 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2738 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2739 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2740 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2741 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2742 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2743 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2744 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2745 enum intel_sbi_destination destination
);
2746 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2747 enum intel_sbi_destination destination
);
2748 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2749 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2751 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2752 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2754 #define FORCEWAKE_RENDER (1 << 0)
2755 #define FORCEWAKE_MEDIA (1 << 1)
2756 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2759 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2760 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2762 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2763 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2764 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2765 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2767 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2768 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2769 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2770 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2772 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2773 * will be implemented using 2 32-bit writes in an arbitrary order with
2774 * an arbitrary delay between them. This can cause the hardware to
2775 * act upon the intermediate value, possibly leading to corruption and
2776 * machine death. You have been warned.
2778 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2779 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2781 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2782 u32 upper = I915_READ(upper_reg); \
2783 u32 lower = I915_READ(lower_reg); \
2784 u32 tmp = I915_READ(upper_reg); \
2785 if (upper != tmp) { \
2787 lower = I915_READ(lower_reg); \
2788 WARN_ON(I915_READ(upper_reg) != upper); \
2790 (u64)upper << 32 | lower; })
2792 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2793 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2795 /* "Broadcast RGB" property */
2796 #define INTEL_BROADCAST_RGB_AUTO 0
2797 #define INTEL_BROADCAST_RGB_FULL 1
2798 #define INTEL_BROADCAST_RGB_LIMITED 2
2800 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2802 if (HAS_PCH_SPLIT(dev
))
2803 return CPU_VGACNTRL
;
2804 else if (IS_VALLEYVIEW(dev
))
2805 return VLV_VGACNTRL
;
2810 static inline void __user
*to_user_ptr(u64 address
)
2812 return (void __user
*)(uintptr_t)address
;
2815 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2817 unsigned long j
= msecs_to_jiffies(m
);
2819 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2822 static inline unsigned long
2823 timespec_to_jiffies_timeout(const struct timespec
*value
)
2825 unsigned long j
= timespec_to_jiffies(value
);
2827 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2831 * If you need to wait X milliseconds between events A and B, but event B
2832 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2833 * when event A happened, then just before event B you call this function and
2834 * pass the timestamp as the first argument, and X as the second argument.
2837 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
2839 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
2842 * Don't re-read the value of "jiffies" every time since it may change
2843 * behind our back and break the math.
2845 tmp_jiffies
= jiffies
;
2846 target_jiffies
= timestamp_jiffies
+
2847 msecs_to_jiffies_timeout(to_wait_ms
);
2849 if (time_after(target_jiffies
, tmp_jiffies
)) {
2850 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
2851 while (remaining_jiffies
)
2853 schedule_timeout_uninterruptible(remaining_jiffies
);