1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141107"
61 #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
69 I915_MAX_PIPES
= _PIPE_EDP
71 #define pipe_name(p) ((p) + 'A')
80 #define transcoder_name(t) ((t) + 'A')
83 * This is the maximum (across all platforms) number of planes (primary +
84 * sprites) that can be active at the same time on one pipe.
86 * This value doesn't count the cursor plane.
88 #define I915_MAX_PLANES 3
95 #define plane_name(p) ((p) + 'A')
97 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
107 #define port_name(p) ((p) + 'A')
109 #define I915_NUM_PHYS_VLV 2
121 enum intel_display_power_domain
{
125 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
126 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
127 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
128 POWER_DOMAIN_TRANSCODER_A
,
129 POWER_DOMAIN_TRANSCODER_B
,
130 POWER_DOMAIN_TRANSCODER_C
,
131 POWER_DOMAIN_TRANSCODER_EDP
,
132 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
133 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
134 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
135 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
136 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
137 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
138 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
139 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
140 POWER_DOMAIN_PORT_DSI
,
141 POWER_DOMAIN_PORT_CRT
,
142 POWER_DOMAIN_PORT_OTHER
,
151 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
152 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
154 #define POWER_DOMAIN_TRANSCODER(tran) \
155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
156 (tran) + POWER_DOMAIN_TRANSCODER_A)
160 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
161 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
171 #define I915_GEM_GPU_DOMAINS \
172 (I915_GEM_DOMAIN_RENDER | \
173 I915_GEM_DOMAIN_SAMPLER | \
174 I915_GEM_DOMAIN_COMMAND | \
175 I915_GEM_DOMAIN_INSTRUCTION | \
176 I915_GEM_DOMAIN_VERTEX)
178 #define for_each_pipe(__dev_priv, __p) \
179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
180 #define for_each_plane(pipe, p) \
181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
182 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
184 #define for_each_crtc(dev, crtc) \
185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
187 #define for_each_intel_crtc(dev, intel_crtc) \
188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
190 #define for_each_intel_encoder(dev, intel_encoder) \
191 list_for_each_entry(intel_encoder, \
192 &(dev)->mode_config.encoder_list, \
195 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
197 if ((intel_encoder)->base.crtc == (__crtc))
199 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
201 if ((intel_connector)->base.encoder == (__encoder))
203 #define for_each_power_domain(domain, mask) \
204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
205 if ((1 << (domain)) & (mask))
207 struct drm_i915_private
;
208 struct i915_mm_struct
;
209 struct i915_mmu_object
;
212 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
213 /* real shared dpll ids must be >= 0 */
214 DPLL_ID_PCH_PLL_A
= 0,
215 DPLL_ID_PCH_PLL_B
= 1,
220 DPLL_ID_SKL_DPLL1
= 0,
221 DPLL_ID_SKL_DPLL2
= 1,
222 DPLL_ID_SKL_DPLL3
= 2,
224 #define I915_NUM_PLLS 3
226 struct intel_dpll_hw_state
{
238 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
239 * lower part of crtl1 and they get shifted into position when writing
240 * the register. This allows us to easily compare the state to share
244 /* HDMI only, 0 when used for DP */
245 uint32_t cfgcr1
, cfgcr2
;
248 struct intel_shared_dpll_config
{
249 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
250 struct intel_dpll_hw_state hw_state
;
253 struct intel_shared_dpll
{
254 struct intel_shared_dpll_config config
;
255 struct intel_shared_dpll_config
*new_config
;
257 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
258 bool on
; /* is the PLL actually active? Disabled during modeset */
260 /* should match the index in the dev_priv->shared_dplls array */
261 enum intel_dpll_id id
;
262 /* The mode_set hook is optional and should be used together with the
263 * intel_prepare_shared_dpll function. */
264 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
265 struct intel_shared_dpll
*pll
);
266 void (*enable
)(struct drm_i915_private
*dev_priv
,
267 struct intel_shared_dpll
*pll
);
268 void (*disable
)(struct drm_i915_private
*dev_priv
,
269 struct intel_shared_dpll
*pll
);
270 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
271 struct intel_shared_dpll
*pll
,
272 struct intel_dpll_hw_state
*hw_state
);
280 /* Used by dp and fdi links */
281 struct intel_link_m_n
{
289 void intel_link_compute_m_n(int bpp
, int nlanes
,
290 int pixel_clock
, int link_clock
,
291 struct intel_link_m_n
*m_n
);
293 /* Interface history:
296 * 1.2: Add Power Management
297 * 1.3: Add vblank support
298 * 1.4: Fix cmdbuffer path, add heap destroy
299 * 1.5: Add vblank pipe configuration
300 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
301 * - Support vertical blank on secondary display pipe
303 #define DRIVER_MAJOR 1
304 #define DRIVER_MINOR 6
305 #define DRIVER_PATCHLEVEL 0
307 #define WATCH_LISTS 0
309 struct opregion_header
;
310 struct opregion_acpi
;
311 struct opregion_swsci
;
312 struct opregion_asle
;
314 struct intel_opregion
{
315 struct opregion_header __iomem
*header
;
316 struct opregion_acpi __iomem
*acpi
;
317 struct opregion_swsci __iomem
*swsci
;
318 u32 swsci_gbda_sub_functions
;
319 u32 swsci_sbcb_sub_functions
;
320 struct opregion_asle __iomem
*asle
;
322 u32 __iomem
*lid_state
;
323 struct work_struct asle_work
;
325 #define OPREGION_SIZE (8*1024)
327 struct intel_overlay
;
328 struct intel_overlay_error_state
;
330 #define I915_FENCE_REG_NONE -1
331 #define I915_MAX_NUM_FENCES 32
332 /* 32 fences + sign bit for FENCE_REG_NONE */
333 #define I915_MAX_NUM_FENCE_BITS 6
335 struct drm_i915_fence_reg
{
336 struct list_head lru_list
;
337 struct drm_i915_gem_object
*obj
;
341 struct sdvo_device_mapping
{
350 struct intel_display_error_state
;
352 struct drm_i915_error_state
{
360 /* Generic register state */
368 u32 error
; /* gen6+ */
369 u32 err_int
; /* gen7 */
375 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
376 u64 fence
[I915_MAX_NUM_FENCES
];
377 struct intel_overlay_error_state
*overlay
;
378 struct intel_display_error_state
*display
;
379 struct drm_i915_error_object
*semaphore_obj
;
381 struct drm_i915_error_ring
{
383 /* Software tracked state */
386 enum intel_ring_hangcheck_action hangcheck_action
;
389 /* our own tracking of ring head and tail */
393 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
411 u32 rc_psmi
; /* sleep state */
412 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
414 struct drm_i915_error_object
{
418 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
420 struct drm_i915_error_request
{
435 char comm
[TASK_COMM_LEN
];
436 } ring
[I915_NUM_RINGS
];
438 struct drm_i915_error_buffer
{
445 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
453 } **active_bo
, **pinned_bo
;
455 u32
*active_bo_count
, *pinned_bo_count
;
459 struct intel_connector
;
460 struct intel_encoder
;
461 struct intel_crtc_config
;
462 struct intel_plane_config
;
467 struct drm_i915_display_funcs
{
468 bool (*fbc_enabled
)(struct drm_device
*dev
);
469 void (*enable_fbc
)(struct drm_crtc
*crtc
);
470 void (*disable_fbc
)(struct drm_device
*dev
);
471 int (*get_display_clock_speed
)(struct drm_device
*dev
);
472 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
474 * find_dpll() - Find the best values for the PLL
475 * @limit: limits for the PLL
476 * @crtc: current CRTC
477 * @target: target frequency in kHz
478 * @refclk: reference clock frequency in kHz
479 * @match_clock: if provided, @best_clock P divider must
480 * match the P divider from @match_clock
481 * used for LVDS downclocking
482 * @best_clock: best PLL values found
484 * Returns true on success, false on failure.
486 bool (*find_dpll
)(const struct intel_limit
*limit
,
487 struct intel_crtc
*crtc
,
488 int target
, int refclk
,
489 struct dpll
*match_clock
,
490 struct dpll
*best_clock
);
491 void (*update_wm
)(struct drm_crtc
*crtc
);
492 void (*update_sprite_wm
)(struct drm_plane
*plane
,
493 struct drm_crtc
*crtc
,
494 uint32_t sprite_width
, uint32_t sprite_height
,
495 int pixel_size
, bool enable
, bool scaled
);
496 void (*modeset_global_resources
)(struct drm_device
*dev
);
497 /* Returns the active state of the crtc, and if the crtc is active,
498 * fills out the pipe-config with the hw state. */
499 bool (*get_pipe_config
)(struct intel_crtc
*,
500 struct intel_crtc_config
*);
501 void (*get_plane_config
)(struct intel_crtc
*,
502 struct intel_plane_config
*);
503 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
);
504 void (*crtc_enable
)(struct drm_crtc
*crtc
);
505 void (*crtc_disable
)(struct drm_crtc
*crtc
);
506 void (*off
)(struct drm_crtc
*crtc
);
507 void (*audio_codec_enable
)(struct drm_connector
*connector
,
508 struct intel_encoder
*encoder
,
509 struct drm_display_mode
*mode
);
510 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
511 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
512 void (*init_clock_gating
)(struct drm_device
*dev
);
513 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
514 struct drm_framebuffer
*fb
,
515 struct drm_i915_gem_object
*obj
,
516 struct intel_engine_cs
*ring
,
518 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
519 struct drm_framebuffer
*fb
,
521 void (*hpd_irq_setup
)(struct drm_device
*dev
);
522 /* clock updates for mode set */
524 /* render clock increase/decrease */
525 /* display clock increase/decrease */
526 /* pll clock increase/decrease */
528 int (*setup_backlight
)(struct intel_connector
*connector
, enum pipe pipe
);
529 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
530 void (*set_backlight
)(struct intel_connector
*connector
,
532 void (*disable_backlight
)(struct intel_connector
*connector
);
533 void (*enable_backlight
)(struct intel_connector
*connector
);
536 struct intel_uncore_funcs
{
537 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
539 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
542 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
543 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
544 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
545 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
547 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
548 uint8_t val
, bool trace
);
549 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
550 uint16_t val
, bool trace
);
551 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
552 uint32_t val
, bool trace
);
553 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
554 uint64_t val
, bool trace
);
557 struct intel_uncore
{
558 spinlock_t lock
; /** lock is also taken in irq contexts. */
560 struct intel_uncore_funcs funcs
;
563 unsigned forcewake_count
;
565 unsigned fw_rendercount
;
566 unsigned fw_mediacount
;
567 unsigned fw_blittercount
;
569 struct timer_list force_wake_timer
;
572 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
573 func(is_mobile) sep \
576 func(is_i945gm) sep \
578 func(need_gfx_hws) sep \
580 func(is_pineview) sep \
581 func(is_broadwater) sep \
582 func(is_crestline) sep \
583 func(is_ivybridge) sep \
584 func(is_valleyview) sep \
585 func(is_haswell) sep \
586 func(is_skylake) sep \
587 func(is_preliminary) sep \
589 func(has_pipe_cxsr) sep \
590 func(has_hotplug) sep \
591 func(cursor_needs_physical) sep \
592 func(has_overlay) sep \
593 func(overlay_needs_physical) sep \
594 func(supports_tv) sep \
599 #define DEFINE_FLAG(name) u8 name:1
600 #define SEP_SEMICOLON ;
602 struct intel_device_info
{
603 u32 display_mmio_offset
;
606 u8 num_sprites
[I915_MAX_PIPES
];
608 u8 ring_mask
; /* Rings supported by the HW */
609 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
610 /* Register offsets for the various display pipes and transcoders */
611 int pipe_offsets
[I915_MAX_TRANSCODERS
];
612 int trans_offsets
[I915_MAX_TRANSCODERS
];
613 int palette_offsets
[I915_MAX_PIPES
];
614 int cursor_offsets
[I915_MAX_PIPES
];
620 enum i915_cache_level
{
622 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
623 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
624 caches, eg sampler/render caches, and the
625 large Last-Level-Cache. LLC is coherent with
626 the CPU, but L3 is only visible to the GPU. */
627 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
630 struct i915_ctx_hang_stats
{
631 /* This context had batch pending when hang was declared */
632 unsigned batch_pending
;
634 /* This context had batch active when hang was declared */
635 unsigned batch_active
;
637 /* Time when this context was last blamed for a GPU reset */
638 unsigned long guilty_ts
;
640 /* This context is banned to submit more work */
644 /* This must match up with the value previously used for execbuf2.rsvd1. */
645 #define DEFAULT_CONTEXT_HANDLE 0
647 * struct intel_context - as the name implies, represents a context.
648 * @ref: reference count.
649 * @user_handle: userspace tracking identity for this context.
650 * @remap_slice: l3 row remapping information.
651 * @file_priv: filp associated with this context (NULL for global default
653 * @hang_stats: information about the role of this context in possible GPU
655 * @vm: virtual memory space used by this context.
656 * @legacy_hw_ctx: render context backing object and whether it is correctly
657 * initialized (legacy ring submission mechanism only).
658 * @link: link in the global list of contexts.
660 * Contexts are memory images used by the hardware to store copies of their
663 struct intel_context
{
667 struct drm_i915_file_private
*file_priv
;
668 struct i915_ctx_hang_stats hang_stats
;
669 struct i915_hw_ppgtt
*ppgtt
;
671 /* Legacy ring buffer submission */
673 struct drm_i915_gem_object
*rcs_state
;
678 bool rcs_initialized
;
680 struct drm_i915_gem_object
*state
;
681 struct intel_ringbuffer
*ringbuf
;
683 } engine
[I915_NUM_RINGS
];
685 struct list_head link
;
695 struct drm_mm_node compressed_fb
;
696 struct drm_mm_node
*compressed_llb
;
700 /* Tracks whether the HW is actually enabled, not whether the feature is
704 /* On gen8 some rings cannont perform fbc clean operation so for now
705 * we are doing this on SW with mmio.
706 * This variable works in the opposite information direction
707 * of ring->fbc_dirty telling software on frontbuffer tracking
708 * to perform the cache clean on sw side.
710 bool need_sw_cache_clean
;
712 struct intel_fbc_work
{
713 struct delayed_work work
;
714 struct drm_crtc
*crtc
;
715 struct drm_framebuffer
*fb
;
719 FBC_OK
, /* FBC is enabled */
720 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
721 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
722 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
723 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
724 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
725 FBC_BAD_PLANE
, /* fbc not supported on plane */
726 FBC_NOT_TILED
, /* buffer not tiled */
727 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
729 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
734 struct intel_connector
*connector
;
742 struct intel_dp
*enabled
;
744 struct delayed_work work
;
745 unsigned busy_frontbuffer_bits
;
749 PCH_NONE
= 0, /* No PCH present */
750 PCH_IBX
, /* Ibexpeak PCH */
751 PCH_CPT
, /* Cougarpoint PCH */
752 PCH_LPT
, /* Lynxpoint PCH */
753 PCH_SPT
, /* Sunrisepoint PCH */
757 enum intel_sbi_destination
{
762 #define QUIRK_PIPEA_FORCE (1<<0)
763 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
764 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
765 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
766 #define QUIRK_PIPEB_FORCE (1<<4)
769 struct intel_fbc_work
;
772 struct i2c_adapter adapter
;
776 struct i2c_algo_bit_data bit_algo
;
777 struct drm_i915_private
*dev_priv
;
780 struct i915_suspend_saved_registers
{
801 u32 saveTRANS_HTOTAL_A
;
802 u32 saveTRANS_HBLANK_A
;
803 u32 saveTRANS_HSYNC_A
;
804 u32 saveTRANS_VTOTAL_A
;
805 u32 saveTRANS_VBLANK_A
;
806 u32 saveTRANS_VSYNC_A
;
814 u32 savePFIT_PGM_RATIOS
;
815 u32 saveBLC_HIST_CTL
;
817 u32 saveBLC_PWM_CTL2
;
818 u32 saveBLC_CPU_PWM_CTL
;
819 u32 saveBLC_CPU_PWM_CTL2
;
832 u32 saveTRANS_HTOTAL_B
;
833 u32 saveTRANS_HBLANK_B
;
834 u32 saveTRANS_HSYNC_B
;
835 u32 saveTRANS_VTOTAL_B
;
836 u32 saveTRANS_VBLANK_B
;
837 u32 saveTRANS_VSYNC_B
;
851 u32 savePP_ON_DELAYS
;
852 u32 savePP_OFF_DELAYS
;
860 u32 savePFIT_CONTROL
;
861 u32 save_palette_a
[256];
862 u32 save_palette_b
[256];
873 u32 saveCACHE_MODE_0
;
874 u32 saveMI_ARB_STATE
;
885 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
896 u32 savePIPEA_GMCH_DATA_M
;
897 u32 savePIPEB_GMCH_DATA_M
;
898 u32 savePIPEA_GMCH_DATA_N
;
899 u32 savePIPEB_GMCH_DATA_N
;
900 u32 savePIPEA_DP_LINK_M
;
901 u32 savePIPEB_DP_LINK_M
;
902 u32 savePIPEA_DP_LINK_N
;
903 u32 savePIPEB_DP_LINK_N
;
914 u32 savePCH_DREF_CONTROL
;
915 u32 saveDISP_ARB_CTL
;
916 u32 savePIPEA_DATA_M1
;
917 u32 savePIPEA_DATA_N1
;
918 u32 savePIPEA_LINK_M1
;
919 u32 savePIPEA_LINK_N1
;
920 u32 savePIPEB_DATA_M1
;
921 u32 savePIPEB_DATA_N1
;
922 u32 savePIPEB_LINK_M1
;
923 u32 savePIPEB_LINK_N1
;
924 u32 saveMCHBAR_RENDER_STANDBY
;
925 u32 savePCH_PORT_HOTPLUG
;
928 struct vlv_s0ix_state
{
935 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
936 u32 media_max_req_count
;
937 u32 gfx_max_req_count
;
969 /* Display 1 CZ domain */
974 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
976 /* GT SA CZ domain */
983 /* Display 2 CZ domain */
989 struct intel_rps_ei
{
995 struct intel_gen6_power_mgmt
{
997 * work, interrupts_enabled and pm_iir are protected by
1000 struct work_struct work
;
1001 bool interrupts_enabled
;
1004 /* Frequencies are stored in potentially platform dependent multiples.
1005 * In other words, *_freq needs to be multiplied by X to be interesting.
1006 * Soft limits are those which are used for the dynamic reclocking done
1007 * by the driver (raise frequencies under heavy loads, and lower for
1008 * lighter loads). Hard limits are those imposed by the hardware.
1010 * A distinction is made for overclocking, which is never enabled by
1011 * default, and is considered to be above the hard limit if it's
1014 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1015 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1016 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1017 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1018 u8 min_freq
; /* AKA RPn. Minimum frequency */
1019 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1020 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1021 u8 rp0_freq
; /* Non-overclocked max frequency. */
1024 u32 ei_interrupt_count
;
1027 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1030 struct delayed_work delayed_resume_work
;
1032 /* manual wa residency calculations */
1033 struct intel_rps_ei up_ei
, down_ei
;
1036 * Protects RPS/RC6 register access and PCU communication.
1037 * Must be taken after struct_mutex if nested.
1039 struct mutex hw_lock
;
1042 /* defined intel_pm.c */
1043 extern spinlock_t mchdev_lock
;
1045 struct intel_ilk_power_mgmt
{
1053 unsigned long last_time1
;
1054 unsigned long chipset_power
;
1057 unsigned long gfx_power
;
1063 struct drm_i915_gem_object
*pwrctx
;
1064 struct drm_i915_gem_object
*renderctx
;
1067 struct drm_i915_private
;
1068 struct i915_power_well
;
1070 struct i915_power_well_ops
{
1072 * Synchronize the well's hw state to match the current sw state, for
1073 * example enable/disable it based on the current refcount. Called
1074 * during driver init and resume time, possibly after first calling
1075 * the enable/disable handlers.
1077 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1078 struct i915_power_well
*power_well
);
1080 * Enable the well and resources that depend on it (for example
1081 * interrupts located on the well). Called after the 0->1 refcount
1084 void (*enable
)(struct drm_i915_private
*dev_priv
,
1085 struct i915_power_well
*power_well
);
1087 * Disable the well and resources that depend on it. Called after
1088 * the 1->0 refcount transition.
1090 void (*disable
)(struct drm_i915_private
*dev_priv
,
1091 struct i915_power_well
*power_well
);
1092 /* Returns the hw enabled state. */
1093 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1094 struct i915_power_well
*power_well
);
1097 /* Power well structure for haswell */
1098 struct i915_power_well
{
1101 /* power well enable/disable usage count */
1103 /* cached hw enabled state */
1105 unsigned long domains
;
1107 const struct i915_power_well_ops
*ops
;
1110 struct i915_power_domains
{
1112 * Power wells needed for initialization at driver init and suspend
1113 * time are on. They are kept on until after the first modeset.
1117 int power_well_count
;
1120 int domain_use_count
[POWER_DOMAIN_NUM
];
1121 struct i915_power_well
*power_wells
;
1124 struct i915_ums_state
{
1126 * Flag if the X Server, and thus DRM, is not currently in
1127 * control of the device.
1129 * This is set between LeaveVT and EnterVT. It needs to be
1130 * replaced with a semaphore. It also needs to be
1131 * transitioned away from for kernel modesetting.
1136 #define MAX_L3_SLICES 2
1137 struct intel_l3_parity
{
1138 u32
*remap_info
[MAX_L3_SLICES
];
1139 struct work_struct error_work
;
1143 struct i915_gem_mm
{
1144 /** Memory allocator for GTT stolen memory */
1145 struct drm_mm stolen
;
1146 /** List of all objects in gtt_space. Used to restore gtt
1147 * mappings on resume */
1148 struct list_head bound_list
;
1150 * List of objects which are not bound to the GTT (thus
1151 * are idle and not used by the GPU) but still have
1152 * (presumably uncached) pages still attached.
1154 struct list_head unbound_list
;
1156 /** Usable portion of the GTT for GEM */
1157 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1159 /** PPGTT used for aliasing the PPGTT with the GTT */
1160 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1162 struct notifier_block oom_notifier
;
1163 struct shrinker shrinker
;
1164 bool shrinker_no_lock_stealing
;
1166 /** LRU list of objects with fence regs on them. */
1167 struct list_head fence_list
;
1170 * We leave the user IRQ off as much as possible,
1171 * but this means that requests will finish and never
1172 * be retired once the system goes idle. Set a timer to
1173 * fire periodically while the ring is running. When it
1174 * fires, go retire requests.
1176 struct delayed_work retire_work
;
1179 * When we detect an idle GPU, we want to turn on
1180 * powersaving features. So once we see that there
1181 * are no more requests outstanding and no more
1182 * arrive within a small period of time, we fire
1183 * off the idle_work.
1185 struct delayed_work idle_work
;
1188 * Are we in a non-interruptible section of code like
1194 * Is the GPU currently considered idle, or busy executing userspace
1195 * requests? Whilst idle, we attempt to power down the hardware and
1196 * display clocks. In order to reduce the effect on performance, there
1197 * is a slight delay before we do so.
1201 /* the indicator for dispatch video commands on two BSD rings */
1202 int bsd_ring_dispatch_index
;
1204 /** Bit 6 swizzling required for X tiling */
1205 uint32_t bit_6_swizzle_x
;
1206 /** Bit 6 swizzling required for Y tiling */
1207 uint32_t bit_6_swizzle_y
;
1209 /* accounting, useful for userland debugging */
1210 spinlock_t object_stat_lock
;
1211 size_t object_memory
;
1215 struct drm_i915_error_state_buf
{
1216 struct drm_i915_private
*i915
;
1225 struct i915_error_state_file_priv
{
1226 struct drm_device
*dev
;
1227 struct drm_i915_error_state
*error
;
1230 struct i915_gpu_error
{
1231 /* For hangcheck timer */
1232 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1233 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1234 /* Hang gpu twice in this window and your context gets banned */
1235 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1237 struct timer_list hangcheck_timer
;
1239 /* For reset and error_state handling. */
1241 /* Protected by the above dev->gpu_error.lock. */
1242 struct drm_i915_error_state
*first_error
;
1243 struct work_struct work
;
1246 unsigned long missed_irq_rings
;
1249 * State variable controlling the reset flow and count
1251 * This is a counter which gets incremented when reset is triggered,
1252 * and again when reset has been handled. So odd values (lowest bit set)
1253 * means that reset is in progress and even values that
1254 * (reset_counter >> 1):th reset was successfully completed.
1256 * If reset is not completed succesfully, the I915_WEDGE bit is
1257 * set meaning that hardware is terminally sour and there is no
1258 * recovery. All waiters on the reset_queue will be woken when
1261 * This counter is used by the wait_seqno code to notice that reset
1262 * event happened and it needs to restart the entire ioctl (since most
1263 * likely the seqno it waited for won't ever signal anytime soon).
1265 * This is important for lock-free wait paths, where no contended lock
1266 * naturally enforces the correct ordering between the bail-out of the
1267 * waiter and the gpu reset work code.
1269 atomic_t reset_counter
;
1271 #define I915_RESET_IN_PROGRESS_FLAG 1
1272 #define I915_WEDGED (1 << 31)
1275 * Waitqueue to signal when the reset has completed. Used by clients
1276 * that wait for dev_priv->mm.wedged to settle.
1278 wait_queue_head_t reset_queue
;
1280 /* Userspace knobs for gpu hang simulation;
1281 * combines both a ring mask, and extra flags
1284 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1285 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1287 /* For missed irq/seqno simulation. */
1288 unsigned int test_irq_rings
;
1290 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1291 bool reload_in_reset
;
1294 enum modeset_restore
{
1295 MODESET_ON_LID_OPEN
,
1300 struct ddi_vbt_port_info
{
1302 * This is an index in the HDMI/DVI DDI buffer translation table.
1303 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1304 * populate this field.
1306 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1307 uint8_t hdmi_level_shift
;
1309 uint8_t supports_dvi
:1;
1310 uint8_t supports_hdmi
:1;
1311 uint8_t supports_dp
:1;
1314 enum drrs_support_type
{
1315 DRRS_NOT_SUPPORTED
= 0,
1316 STATIC_DRRS_SUPPORT
= 1,
1317 SEAMLESS_DRRS_SUPPORT
= 2
1320 struct intel_vbt_data
{
1321 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1322 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1325 unsigned int int_tv_support
:1;
1326 unsigned int lvds_dither
:1;
1327 unsigned int lvds_vbt
:1;
1328 unsigned int int_crt_support
:1;
1329 unsigned int lvds_use_ssc
:1;
1330 unsigned int display_clock_mode
:1;
1331 unsigned int fdi_rx_polarity_inverted
:1;
1332 unsigned int has_mipi
:1;
1334 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1336 enum drrs_support_type drrs_type
;
1341 int edp_preemphasis
;
1343 bool edp_initialized
;
1346 struct edp_power_seq edp_pps
;
1351 bool active_low_pwm
;
1352 u8 min_brightness
; /* min_brightness/255 of max */
1359 struct mipi_config
*config
;
1360 struct mipi_pps_data
*pps
;
1364 u8
*sequence
[MIPI_SEQ_MAX
];
1370 union child_device_config
*child_dev
;
1372 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1375 enum intel_ddb_partitioning
{
1377 INTEL_DDB_PART_5_6
, /* IVB+ */
1380 struct intel_wm_level
{
1388 struct ilk_wm_values
{
1389 uint32_t wm_pipe
[3];
1391 uint32_t wm_lp_spr
[3];
1392 uint32_t wm_linetime
[3];
1394 enum intel_ddb_partitioning partitioning
;
1397 struct skl_ddb_entry
{
1398 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1401 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1403 return entry
->end
- entry
->start
;
1406 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1407 const struct skl_ddb_entry
*e2
)
1409 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1415 struct skl_ddb_allocation
{
1416 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1417 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1418 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1421 struct skl_wm_values
{
1422 bool dirty
[I915_MAX_PIPES
];
1423 struct skl_ddb_allocation ddb
;
1424 uint32_t wm_linetime
[I915_MAX_PIPES
];
1425 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1426 uint32_t cursor
[I915_MAX_PIPES
][8];
1427 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1428 uint32_t cursor_trans
[I915_MAX_PIPES
];
1431 struct skl_wm_level
{
1432 bool plane_en
[I915_MAX_PLANES
];
1434 uint16_t plane_res_b
[I915_MAX_PLANES
];
1435 uint8_t plane_res_l
[I915_MAX_PLANES
];
1436 uint16_t cursor_res_b
;
1437 uint8_t cursor_res_l
;
1441 * This struct helps tracking the state needed for runtime PM, which puts the
1442 * device in PCI D3 state. Notice that when this happens, nothing on the
1443 * graphics device works, even register access, so we don't get interrupts nor
1446 * Every piece of our code that needs to actually touch the hardware needs to
1447 * either call intel_runtime_pm_get or call intel_display_power_get with the
1448 * appropriate power domain.
1450 * Our driver uses the autosuspend delay feature, which means we'll only really
1451 * suspend if we stay with zero refcount for a certain amount of time. The
1452 * default value is currently very conservative (see intel_runtime_pm_enable), but
1453 * it can be changed with the standard runtime PM files from sysfs.
1455 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1456 * goes back to false exactly before we reenable the IRQs. We use this variable
1457 * to check if someone is trying to enable/disable IRQs while they're supposed
1458 * to be disabled. This shouldn't happen and we'll print some error messages in
1461 * For more, read the Documentation/power/runtime_pm.txt.
1463 struct i915_runtime_pm
{
1468 enum intel_pipe_crc_source
{
1469 INTEL_PIPE_CRC_SOURCE_NONE
,
1470 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1471 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1472 INTEL_PIPE_CRC_SOURCE_PF
,
1473 INTEL_PIPE_CRC_SOURCE_PIPE
,
1474 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1475 INTEL_PIPE_CRC_SOURCE_TV
,
1476 INTEL_PIPE_CRC_SOURCE_DP_B
,
1477 INTEL_PIPE_CRC_SOURCE_DP_C
,
1478 INTEL_PIPE_CRC_SOURCE_DP_D
,
1479 INTEL_PIPE_CRC_SOURCE_AUTO
,
1480 INTEL_PIPE_CRC_SOURCE_MAX
,
1483 struct intel_pipe_crc_entry
{
1488 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1489 struct intel_pipe_crc
{
1491 bool opened
; /* exclusive access to the result file */
1492 struct intel_pipe_crc_entry
*entries
;
1493 enum intel_pipe_crc_source source
;
1495 wait_queue_head_t wq
;
1498 struct i915_frontbuffer_tracking
{
1502 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1509 struct i915_wa_reg
{
1512 /* bitmask representing WA bits */
1516 #define I915_MAX_WA_REGS 16
1518 struct i915_workarounds
{
1519 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1523 struct drm_i915_private
{
1524 struct drm_device
*dev
;
1525 struct kmem_cache
*slab
;
1527 const struct intel_device_info info
;
1529 int relative_constants_mode
;
1533 struct intel_uncore uncore
;
1535 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1538 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1539 * controller on different i2c buses. */
1540 struct mutex gmbus_mutex
;
1543 * Base address of the gmbus and gpio block.
1545 uint32_t gpio_mmio_base
;
1547 /* MMIO base address for MIPI regs */
1548 uint32_t mipi_mmio_base
;
1550 wait_queue_head_t gmbus_wait_queue
;
1552 struct pci_dev
*bridge_dev
;
1553 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1554 struct drm_i915_gem_object
*semaphore_obj
;
1555 uint32_t last_seqno
, next_seqno
;
1557 struct drm_dma_handle
*status_page_dmah
;
1558 struct resource mch_res
;
1560 /* protects the irq masks */
1561 spinlock_t irq_lock
;
1563 /* protects the mmio flip data */
1564 spinlock_t mmio_flip_lock
;
1566 bool display_irqs_enabled
;
1568 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1569 struct pm_qos_request pm_qos
;
1571 /* DPIO indirect register protection */
1572 struct mutex dpio_lock
;
1574 /** Cached value of IMR to avoid reads in updating the bitfield */
1577 u32 de_irq_mask
[I915_MAX_PIPES
];
1582 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1584 struct work_struct hotplug_work
;
1586 unsigned long hpd_last_jiffies
;
1591 HPD_MARK_DISABLED
= 2
1593 } hpd_stats
[HPD_NUM_PINS
];
1595 struct delayed_work hotplug_reenable_work
;
1597 struct i915_fbc fbc
;
1598 struct i915_drrs drrs
;
1599 struct intel_opregion opregion
;
1600 struct intel_vbt_data vbt
;
1602 bool preserve_bios_swizzle
;
1605 struct intel_overlay
*overlay
;
1607 /* backlight registers and fields in struct intel_panel */
1608 struct mutex backlight_lock
;
1611 bool no_aux_handshake
;
1613 /* protects panel power sequencer state */
1614 struct mutex pps_mutex
;
1616 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1617 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1618 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1620 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1621 unsigned int vlv_cdclk_freq
;
1622 unsigned int hpll_freq
;
1625 * wq - Driver workqueue for GEM.
1627 * NOTE: Work items scheduled here are not allowed to grab any modeset
1628 * locks, for otherwise the flushing done in the pageflip code will
1629 * result in deadlocks.
1631 struct workqueue_struct
*wq
;
1633 /* Display functions */
1634 struct drm_i915_display_funcs display
;
1636 /* PCH chipset type */
1637 enum intel_pch pch_type
;
1638 unsigned short pch_id
;
1640 unsigned long quirks
;
1642 enum modeset_restore modeset_restore
;
1643 struct mutex modeset_restore_lock
;
1645 struct list_head vm_list
; /* Global list of all address spaces */
1646 struct i915_gtt gtt
; /* VM representing the global address space */
1648 struct i915_gem_mm mm
;
1649 DECLARE_HASHTABLE(mm_structs
, 7);
1650 struct mutex mm_lock
;
1652 /* Kernel Modesetting */
1654 struct sdvo_device_mapping sdvo_mappings
[2];
1656 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1657 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1658 wait_queue_head_t pending_flip_queue
;
1660 #ifdef CONFIG_DEBUG_FS
1661 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1664 int num_shared_dpll
;
1665 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1666 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1668 struct i915_workarounds workarounds
;
1670 /* Reclocking support */
1671 bool render_reclock_avail
;
1672 bool lvds_downclock_avail
;
1673 /* indicates the reduced downclock for LVDS*/
1676 struct i915_frontbuffer_tracking fb_tracking
;
1680 bool mchbar_need_disable
;
1682 struct intel_l3_parity l3_parity
;
1684 /* Cannot be determined by PCIID. You must always read a register. */
1687 /* gen6+ rps state */
1688 struct intel_gen6_power_mgmt rps
;
1690 /* ilk-only ips/rps state. Everything in here is protected by the global
1691 * mchdev_lock in intel_pm.c */
1692 struct intel_ilk_power_mgmt ips
;
1694 struct i915_power_domains power_domains
;
1696 struct i915_psr psr
;
1698 struct i915_gpu_error gpu_error
;
1700 struct drm_i915_gem_object
*vlv_pctx
;
1702 #ifdef CONFIG_DRM_I915_FBDEV
1703 /* list of fbdev register on this device */
1704 struct intel_fbdev
*fbdev
;
1705 struct work_struct fbdev_suspend_work
;
1708 struct drm_property
*broadcast_rgb_property
;
1709 struct drm_property
*force_audio_property
;
1711 uint32_t hw_context_size
;
1712 struct list_head context_list
;
1717 struct i915_suspend_saved_registers regfile
;
1718 struct vlv_s0ix_state vlv_s0ix_state
;
1722 * Raw watermark latency values:
1723 * in 0.1us units for WM0,
1724 * in 0.5us units for WM1+.
1727 uint16_t pri_latency
[5];
1729 uint16_t spr_latency
[5];
1731 uint16_t cur_latency
[5];
1733 * Raw watermark memory latency values
1734 * for SKL for all 8 levels
1737 uint16_t skl_latency
[8];
1740 * The skl_wm_values structure is a bit too big for stack
1741 * allocation, so we keep the staging struct where we store
1742 * intermediate results here instead.
1744 struct skl_wm_values skl_results
;
1746 /* current hardware state */
1748 struct ilk_wm_values hw
;
1749 struct skl_wm_values skl_hw
;
1753 struct i915_runtime_pm pm
;
1755 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1756 u32 long_hpd_port_mask
;
1757 u32 short_hpd_port_mask
;
1758 struct work_struct dig_port_work
;
1761 * if we get a HPD irq from DP and a HPD irq from non-DP
1762 * the non-DP HPD could block the workqueue on a mode config
1763 * mutex getting, that userspace may have taken. However
1764 * userspace is waiting on the DP workqueue to run which is
1765 * blocked behind the non-DP one.
1767 struct workqueue_struct
*dp_wq
;
1769 uint32_t bios_vgacntr
;
1771 /* Old ums support infrastructure, same warning applies. */
1772 struct i915_ums_state ums
;
1774 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1776 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1777 struct intel_engine_cs
*ring
,
1778 struct intel_context
*ctx
,
1779 struct drm_i915_gem_execbuffer2
*args
,
1780 struct list_head
*vmas
,
1781 struct drm_i915_gem_object
*batch_obj
,
1782 u64 exec_start
, u32 flags
);
1783 int (*init_rings
)(struct drm_device
*dev
);
1784 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1785 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1789 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1790 * will be rejected. Instead look for a better place.
1794 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1796 return dev
->dev_private
;
1799 /* Iterate over initialised rings */
1800 #define for_each_ring(ring__, dev_priv__, i__) \
1801 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1802 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1804 enum hdmi_force_audio
{
1805 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1806 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1807 HDMI_AUDIO_AUTO
, /* trust EDID */
1808 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1811 #define I915_GTT_OFFSET_NONE ((u32)-1)
1813 struct drm_i915_gem_object_ops
{
1814 /* Interface between the GEM object and its backing storage.
1815 * get_pages() is called once prior to the use of the associated set
1816 * of pages before to binding them into the GTT, and put_pages() is
1817 * called after we no longer need them. As we expect there to be
1818 * associated cost with migrating pages between the backing storage
1819 * and making them available for the GPU (e.g. clflush), we may hold
1820 * onto the pages after they are no longer referenced by the GPU
1821 * in case they may be used again shortly (for example migrating the
1822 * pages to a different memory domain within the GTT). put_pages()
1823 * will therefore most likely be called when the object itself is
1824 * being released or under memory pressure (where we attempt to
1825 * reap pages for the shrinker).
1827 int (*get_pages
)(struct drm_i915_gem_object
*);
1828 void (*put_pages
)(struct drm_i915_gem_object
*);
1829 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1830 void (*release
)(struct drm_i915_gem_object
*);
1834 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1835 * considered to be the frontbuffer for the given plane interface-vise. This
1836 * doesn't mean that the hw necessarily already scans it out, but that any
1837 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1839 * We have one bit per pipe and per scanout plane type.
1841 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1842 #define INTEL_FRONTBUFFER_BITS \
1843 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1844 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1845 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1846 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1847 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1848 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1849 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1850 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1851 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1852 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1853 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1855 struct drm_i915_gem_object
{
1856 struct drm_gem_object base
;
1858 const struct drm_i915_gem_object_ops
*ops
;
1860 /** List of VMAs backed by this object */
1861 struct list_head vma_list
;
1863 /** Stolen memory for this object, instead of being backed by shmem. */
1864 struct drm_mm_node
*stolen
;
1865 struct list_head global_list
;
1867 struct list_head ring_list
;
1868 /** Used in execbuf to temporarily hold a ref */
1869 struct list_head obj_exec_link
;
1872 * This is set if the object is on the active lists (has pending
1873 * rendering and so a non-zero seqno), and is not set if it i s on
1874 * inactive (ready to be unbound) list.
1876 unsigned int active
:1;
1879 * This is set if the object has been written to since last bound
1882 unsigned int dirty
:1;
1885 * Fence register bits (if any) for this object. Will be set
1886 * as needed when mapped into the GTT.
1887 * Protected by dev->struct_mutex.
1889 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1892 * Advice: are the backing pages purgeable?
1894 unsigned int madv
:2;
1897 * Current tiling mode for the object.
1899 unsigned int tiling_mode
:2;
1901 * Whether the tiling parameters for the currently associated fence
1902 * register have changed. Note that for the purposes of tracking
1903 * tiling changes we also treat the unfenced register, the register
1904 * slot that the object occupies whilst it executes a fenced
1905 * command (such as BLT on gen2/3), as a "fence".
1907 unsigned int fence_dirty
:1;
1910 * Is the object at the current location in the gtt mappable and
1911 * fenceable? Used to avoid costly recalculations.
1913 unsigned int map_and_fenceable
:1;
1916 * Whether the current gtt mapping needs to be mappable (and isn't just
1917 * mappable by accident). Track pin and fault separate for a more
1918 * accurate mappable working set.
1920 unsigned int fault_mappable
:1;
1921 unsigned int pin_mappable
:1;
1922 unsigned int pin_display
:1;
1925 * Is the object to be mapped as read-only to the GPU
1926 * Only honoured if hardware has relevant pte bit
1928 unsigned long gt_ro
:1;
1929 unsigned int cache_level
:3;
1931 unsigned int has_dma_mapping
:1;
1933 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1935 struct sg_table
*pages
;
1936 int pages_pin_count
;
1938 /* prime dma-buf support */
1939 void *dma_buf_vmapping
;
1942 struct intel_engine_cs
*ring
;
1944 /** Breadcrumb of last rendering to the buffer. */
1945 uint32_t last_read_seqno
;
1946 uint32_t last_write_seqno
;
1947 /** Breadcrumb of last fenced GPU access to the buffer. */
1948 uint32_t last_fenced_seqno
;
1950 /** Current tiling stride for the object, if it's tiled. */
1953 /** References from framebuffers, locks out tiling changes. */
1954 unsigned long framebuffer_references
;
1956 /** Record of address bit 17 of each page at last unbind. */
1957 unsigned long *bit_17
;
1959 /** User space pin count and filp owning the pin */
1960 unsigned long user_pin_count
;
1961 struct drm_file
*pin_filp
;
1964 /** for phy allocated objects */
1965 struct drm_dma_handle
*phys_handle
;
1967 struct i915_gem_userptr
{
1969 unsigned read_only
:1;
1970 unsigned workers
:4;
1971 #define I915_GEM_USERPTR_MAX_WORKERS 15
1973 struct i915_mm_struct
*mm
;
1974 struct i915_mmu_object
*mmu_object
;
1975 struct work_struct
*work
;
1979 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1981 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1982 struct drm_i915_gem_object
*new,
1983 unsigned frontbuffer_bits
);
1986 * Request queue structure.
1988 * The request queue allows us to note sequence numbers that have been emitted
1989 * and may be associated with active buffers to be retired.
1991 * By keeping this list, we can avoid having to do questionable
1992 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1993 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1995 struct drm_i915_gem_request
{
1996 /** On Which ring this request was generated */
1997 struct intel_engine_cs
*ring
;
1999 /** GEM sequence number associated with this request. */
2002 /** Position in the ringbuffer of the start of the request */
2005 /** Position in the ringbuffer of the end of the request */
2008 /** Context related to this request */
2009 struct intel_context
*ctx
;
2011 /** Batch buffer related to this request if any */
2012 struct drm_i915_gem_object
*batch_obj
;
2014 /** Time at which this request was emitted, in jiffies. */
2015 unsigned long emitted_jiffies
;
2017 /** global list entry for this request */
2018 struct list_head list
;
2020 struct drm_i915_file_private
*file_priv
;
2021 /** file_priv list entry for this request */
2022 struct list_head client_list
;
2025 struct drm_i915_file_private
{
2026 struct drm_i915_private
*dev_priv
;
2027 struct drm_file
*file
;
2031 struct list_head request_list
;
2032 struct delayed_work idle_work
;
2034 struct idr context_idr
;
2036 atomic_t rps_wait_boost
;
2037 struct intel_engine_cs
*bsd_ring
;
2041 * A command that requires special handling by the command parser.
2043 struct drm_i915_cmd_descriptor
{
2045 * Flags describing how the command parser processes the command.
2047 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2048 * a length mask if not set
2049 * CMD_DESC_SKIP: The command is allowed but does not follow the
2050 * standard length encoding for the opcode range in
2052 * CMD_DESC_REJECT: The command is never allowed
2053 * CMD_DESC_REGISTER: The command should be checked against the
2054 * register whitelist for the appropriate ring
2055 * CMD_DESC_MASTER: The command is allowed if the submitting process
2059 #define CMD_DESC_FIXED (1<<0)
2060 #define CMD_DESC_SKIP (1<<1)
2061 #define CMD_DESC_REJECT (1<<2)
2062 #define CMD_DESC_REGISTER (1<<3)
2063 #define CMD_DESC_BITMASK (1<<4)
2064 #define CMD_DESC_MASTER (1<<5)
2067 * The command's unique identification bits and the bitmask to get them.
2068 * This isn't strictly the opcode field as defined in the spec and may
2069 * also include type, subtype, and/or subop fields.
2077 * The command's length. The command is either fixed length (i.e. does
2078 * not include a length field) or has a length field mask. The flag
2079 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2080 * a length mask. All command entries in a command table must include
2081 * length information.
2089 * Describes where to find a register address in the command to check
2090 * against the ring's register whitelist. Only valid if flags has the
2091 * CMD_DESC_REGISTER bit set.
2098 #define MAX_CMD_DESC_BITMASKS 3
2100 * Describes command checks where a particular dword is masked and
2101 * compared against an expected value. If the command does not match
2102 * the expected value, the parser rejects it. Only valid if flags has
2103 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2106 * If the check specifies a non-zero condition_mask then the parser
2107 * only performs the check when the bits specified by condition_mask
2114 u32 condition_offset
;
2116 } bits
[MAX_CMD_DESC_BITMASKS
];
2120 * A table of commands requiring special handling by the command parser.
2122 * Each ring has an array of tables. Each table consists of an array of command
2123 * descriptors, which must be sorted with command opcodes in ascending order.
2125 struct drm_i915_cmd_table
{
2126 const struct drm_i915_cmd_descriptor
*table
;
2130 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2131 #define __I915__(p) ({ \
2132 struct drm_i915_private *__p; \
2133 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2134 __p = (struct drm_i915_private *)p; \
2135 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2136 __p = to_i915((struct drm_device *)p); \
2141 #define INTEL_INFO(p) (&__I915__(p)->info)
2142 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2144 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2145 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2146 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2147 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2148 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2149 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2150 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2151 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2152 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2153 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2154 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2155 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2156 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2157 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2158 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2159 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2160 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2161 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2162 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2163 INTEL_DEVID(dev) == 0x0152 || \
2164 INTEL_DEVID(dev) == 0x015a)
2165 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2166 INTEL_DEVID(dev) == 0x0106 || \
2167 INTEL_DEVID(dev) == 0x010A)
2168 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2169 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2170 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2171 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2172 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2173 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2174 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2175 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2176 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2177 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2178 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2179 (INTEL_DEVID(dev) & 0xf) == 0xe))
2180 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2181 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2182 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2183 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2184 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2185 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2186 /* ULX machines are also considered ULT. */
2187 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2188 INTEL_DEVID(dev) == 0x0A1E)
2189 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2192 * The genX designation typically refers to the render engine, so render
2193 * capability related checks should use IS_GEN, while display and other checks
2194 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2197 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2198 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2199 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2200 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2201 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2202 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2203 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2204 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2206 #define RENDER_RING (1<<RCS)
2207 #define BSD_RING (1<<VCS)
2208 #define BLT_RING (1<<BCS)
2209 #define VEBOX_RING (1<<VECS)
2210 #define BSD2_RING (1<<VCS2)
2211 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2212 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2213 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2214 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2215 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2216 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2217 __I915__(dev)->ellc_size)
2218 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2220 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2221 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2222 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2223 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2225 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2226 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2228 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2229 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2231 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2232 * even when in MSI mode. This results in spurious interrupt warnings if the
2233 * legacy irq no. is shared with another device. The kernel then disables that
2234 * interrupt source and so prevents the other device from working properly.
2236 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2237 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2239 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2240 * rows, which changed the alignment requirements and fence programming.
2242 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2244 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2245 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2246 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2247 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2248 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2250 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2251 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2252 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2254 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2256 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2257 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2258 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2259 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2260 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2261 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2262 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2264 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2265 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2266 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2267 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2268 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2269 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2270 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2271 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2273 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2274 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2275 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2276 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2277 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2278 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2279 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2281 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2283 /* DPF == dynamic parity feature */
2284 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2285 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2287 #define GT_FREQUENCY_MULTIPLIER 50
2289 #include "i915_trace.h"
2291 extern const struct drm_ioctl_desc i915_ioctls
[];
2292 extern int i915_max_ioctl
;
2294 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2295 extern int i915_resume_legacy(struct drm_device
*dev
);
2296 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2297 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2300 struct i915_params
{
2302 int panel_ignore_lid
;
2303 unsigned int powersave
;
2305 unsigned int lvds_downclock
;
2306 int lvds_channel_mode
;
2308 int vbt_sdvo_panel_type
;
2312 int enable_execlists
;
2314 unsigned int preliminary_hw_support
;
2315 int disable_power_well
;
2317 int invert_brightness
;
2318 int enable_cmd_parser
;
2319 /* leave bools at the end to not create holes */
2320 bool enable_hangcheck
;
2322 bool prefault_disable
;
2324 bool disable_display
;
2325 bool disable_vtd_wa
;
2329 extern struct i915_params i915 __read_mostly
;
2332 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2333 extern int i915_driver_unload(struct drm_device
*);
2334 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2335 extern void i915_driver_lastclose(struct drm_device
* dev
);
2336 extern void i915_driver_preclose(struct drm_device
*dev
,
2337 struct drm_file
*file
);
2338 extern void i915_driver_postclose(struct drm_device
*dev
,
2339 struct drm_file
*file
);
2340 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2341 #ifdef CONFIG_COMPAT
2342 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2345 extern int intel_gpu_reset(struct drm_device
*dev
);
2346 extern int i915_reset(struct drm_device
*dev
);
2347 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2348 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2349 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2350 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2351 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2352 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2355 void i915_queue_hangcheck(struct drm_device
*dev
);
2357 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2358 const char *fmt
, ...);
2360 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2361 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2362 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2363 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2365 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2366 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2367 bool restore_forcewake
);
2368 extern void intel_uncore_init(struct drm_device
*dev
);
2369 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2370 extern void intel_uncore_fini(struct drm_device
*dev
);
2371 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2374 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2378 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2381 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2382 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2384 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2386 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2387 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2388 uint32_t interrupt_mask
,
2389 uint32_t enabled_irq_mask
);
2390 #define ibx_enable_display_interrupt(dev_priv, bits) \
2391 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2392 #define ibx_disable_display_interrupt(dev_priv, bits) \
2393 ibx_display_interrupt_update((dev_priv), (bits), 0)
2396 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2397 struct drm_file
*file_priv
);
2398 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2399 struct drm_file
*file_priv
);
2400 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2401 struct drm_file
*file_priv
);
2402 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2403 struct drm_file
*file_priv
);
2404 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2405 struct drm_file
*file_priv
);
2406 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2407 struct drm_file
*file_priv
);
2408 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2409 struct drm_file
*file_priv
);
2410 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2411 struct drm_file
*file_priv
);
2412 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2413 struct intel_engine_cs
*ring
);
2414 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2415 struct drm_file
*file
,
2416 struct intel_engine_cs
*ring
,
2417 struct drm_i915_gem_object
*obj
);
2418 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2419 struct drm_file
*file
,
2420 struct intel_engine_cs
*ring
,
2421 struct intel_context
*ctx
,
2422 struct drm_i915_gem_execbuffer2
*args
,
2423 struct list_head
*vmas
,
2424 struct drm_i915_gem_object
*batch_obj
,
2425 u64 exec_start
, u32 flags
);
2426 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2427 struct drm_file
*file_priv
);
2428 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2429 struct drm_file
*file_priv
);
2430 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2431 struct drm_file
*file_priv
);
2432 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2433 struct drm_file
*file_priv
);
2434 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2435 struct drm_file
*file_priv
);
2436 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2437 struct drm_file
*file
);
2438 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2439 struct drm_file
*file
);
2440 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2441 struct drm_file
*file_priv
);
2442 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2443 struct drm_file
*file_priv
);
2444 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2445 struct drm_file
*file_priv
);
2446 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2447 struct drm_file
*file_priv
);
2448 int i915_gem_init_userptr(struct drm_device
*dev
);
2449 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2450 struct drm_file
*file
);
2451 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2452 struct drm_file
*file_priv
);
2453 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2454 struct drm_file
*file_priv
);
2455 void i915_gem_load(struct drm_device
*dev
);
2456 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2459 #define I915_SHRINK_PURGEABLE 0x1
2460 #define I915_SHRINK_UNBOUND 0x2
2461 #define I915_SHRINK_BOUND 0x4
2462 void *i915_gem_object_alloc(struct drm_device
*dev
);
2463 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2464 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2465 const struct drm_i915_gem_object_ops
*ops
);
2466 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2468 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2469 struct i915_address_space
*vm
);
2470 void i915_gem_free_object(struct drm_gem_object
*obj
);
2471 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2473 #define PIN_MAPPABLE 0x1
2474 #define PIN_NONBLOCK 0x2
2475 #define PIN_GLOBAL 0x4
2476 #define PIN_OFFSET_BIAS 0x8
2477 #define PIN_OFFSET_MASK (~4095)
2478 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2479 struct i915_address_space
*vm
,
2482 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2483 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2484 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2485 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2486 void i915_gem_lastclose(struct drm_device
*dev
);
2488 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2489 int *needs_clflush
);
2491 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2492 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2494 struct sg_page_iter sg_iter
;
2496 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2497 return sg_page_iter_page(&sg_iter
);
2501 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2503 BUG_ON(obj
->pages
== NULL
);
2504 obj
->pages_pin_count
++;
2506 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2508 BUG_ON(obj
->pages_pin_count
== 0);
2509 obj
->pages_pin_count
--;
2512 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2513 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2514 struct intel_engine_cs
*to
);
2515 void i915_vma_move_to_active(struct i915_vma
*vma
,
2516 struct intel_engine_cs
*ring
);
2517 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2518 struct drm_device
*dev
,
2519 struct drm_mode_create_dumb
*args
);
2520 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2521 uint32_t handle
, uint64_t *offset
);
2523 * Returns true if seq1 is later than seq2.
2526 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2528 return (int32_t)(seq1
- seq2
) >= 0;
2531 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2532 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2533 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2534 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2536 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2537 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2539 struct drm_i915_gem_request
*
2540 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2542 bool i915_gem_retire_requests(struct drm_device
*dev
);
2543 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2544 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2545 bool interruptible
);
2546 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2548 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2550 return unlikely(atomic_read(&error
->reset_counter
)
2551 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2554 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2556 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2559 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2561 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2564 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2566 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2567 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2570 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2572 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2573 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2576 void i915_gem_reset(struct drm_device
*dev
);
2577 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2578 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2579 int __must_check
i915_gem_init(struct drm_device
*dev
);
2580 int i915_gem_init_rings(struct drm_device
*dev
);
2581 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2582 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2583 void i915_gem_init_swizzling(struct drm_device
*dev
);
2584 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2585 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2586 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2587 int __i915_add_request(struct intel_engine_cs
*ring
,
2588 struct drm_file
*file
,
2589 struct drm_i915_gem_object
*batch_obj
,
2591 #define i915_add_request(ring, seqno) \
2592 __i915_add_request(ring, NULL, NULL, seqno)
2593 int __i915_wait_seqno(struct intel_engine_cs
*ring
, u32 seqno
,
2594 unsigned reset_counter
,
2597 struct drm_i915_file_private
*file_priv
);
2598 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2600 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2602 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2605 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2607 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2609 struct intel_engine_cs
*pipelined
);
2610 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2611 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2613 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2614 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2617 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2619 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2620 int tiling_mode
, bool fenced
);
2622 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2623 enum i915_cache_level cache_level
);
2625 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2626 struct dma_buf
*dma_buf
);
2628 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2629 struct drm_gem_object
*gem_obj
, int flags
);
2631 void i915_gem_restore_fences(struct drm_device
*dev
);
2633 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2634 struct i915_address_space
*vm
);
2635 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2636 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2637 struct i915_address_space
*vm
);
2638 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2639 struct i915_address_space
*vm
);
2640 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2641 struct i915_address_space
*vm
);
2643 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2644 struct i915_address_space
*vm
);
2646 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2647 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2648 struct i915_vma
*vma
;
2649 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2650 if (vma
->pin_count
> 0)
2655 /* Some GGTT VM helpers */
2656 #define i915_obj_to_ggtt(obj) \
2657 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2658 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2660 struct i915_address_space
*ggtt
=
2661 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2665 static inline struct i915_hw_ppgtt
*
2666 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2668 WARN_ON(i915_is_ggtt(vm
));
2670 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2674 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2676 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2679 static inline unsigned long
2680 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2682 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2685 static inline unsigned long
2686 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2688 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2691 static inline int __must_check
2692 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2696 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2697 alignment
, flags
| PIN_GLOBAL
);
2701 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2703 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2706 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2708 /* i915_gem_context.c */
2709 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2710 void i915_gem_context_fini(struct drm_device
*dev
);
2711 void i915_gem_context_reset(struct drm_device
*dev
);
2712 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2713 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2714 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2715 int i915_switch_context(struct intel_engine_cs
*ring
,
2716 struct intel_context
*to
);
2717 struct intel_context
*
2718 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2719 void i915_gem_context_free(struct kref
*ctx_ref
);
2720 struct drm_i915_gem_object
*
2721 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2722 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2724 kref_get(&ctx
->ref
);
2727 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2729 kref_put(&ctx
->ref
, i915_gem_context_free
);
2732 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2734 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2737 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2738 struct drm_file
*file
);
2739 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2740 struct drm_file
*file
);
2742 /* i915_gem_evict.c */
2743 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2744 struct i915_address_space
*vm
,
2747 unsigned cache_level
,
2748 unsigned long start
,
2751 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2752 int i915_gem_evict_everything(struct drm_device
*dev
);
2754 /* belongs in i915_gem_gtt.h */
2755 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2757 if (INTEL_INFO(dev
)->gen
< 6)
2758 intel_gtt_chipset_flush();
2761 /* i915_gem_stolen.c */
2762 int i915_gem_init_stolen(struct drm_device
*dev
);
2763 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2764 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2765 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2766 struct drm_i915_gem_object
*
2767 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2768 struct drm_i915_gem_object
*
2769 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2774 /* i915_gem_tiling.c */
2775 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2777 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2779 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2780 obj
->tiling_mode
!= I915_TILING_NONE
;
2783 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2784 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2785 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2787 /* i915_gem_debug.c */
2789 int i915_verify_lists(struct drm_device
*dev
);
2791 #define i915_verify_lists(dev) 0
2794 /* i915_debugfs.c */
2795 int i915_debugfs_init(struct drm_minor
*minor
);
2796 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2797 #ifdef CONFIG_DEBUG_FS
2798 void intel_display_crc_init(struct drm_device
*dev
);
2800 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2803 /* i915_gpu_error.c */
2805 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2806 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2807 const struct i915_error_state_file_priv
*error
);
2808 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2809 struct drm_i915_private
*i915
,
2810 size_t count
, loff_t pos
);
2811 static inline void i915_error_state_buf_release(
2812 struct drm_i915_error_state_buf
*eb
)
2816 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2817 const char *error_msg
);
2818 void i915_error_state_get(struct drm_device
*dev
,
2819 struct i915_error_state_file_priv
*error_priv
);
2820 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2821 void i915_destroy_error_state(struct drm_device
*dev
);
2823 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2824 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
2826 /* i915_cmd_parser.c */
2827 int i915_cmd_parser_get_version(void);
2828 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2829 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2830 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2831 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2832 struct drm_i915_gem_object
*batch_obj
,
2833 u32 batch_start_offset
,
2836 /* i915_suspend.c */
2837 extern int i915_save_state(struct drm_device
*dev
);
2838 extern int i915_restore_state(struct drm_device
*dev
);
2841 void i915_save_display_reg(struct drm_device
*dev
);
2842 void i915_restore_display_reg(struct drm_device
*dev
);
2845 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2846 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2849 extern int intel_setup_gmbus(struct drm_device
*dev
);
2850 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2851 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2853 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2856 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2857 struct drm_i915_private
*dev_priv
, unsigned port
);
2858 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2859 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2860 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2862 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2864 extern void intel_i2c_reset(struct drm_device
*dev
);
2866 /* intel_opregion.c */
2868 extern int intel_opregion_setup(struct drm_device
*dev
);
2869 extern void intel_opregion_init(struct drm_device
*dev
);
2870 extern void intel_opregion_fini(struct drm_device
*dev
);
2871 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2872 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2874 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2877 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2878 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2879 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2880 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2882 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2887 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2895 extern void intel_register_dsm_handler(void);
2896 extern void intel_unregister_dsm_handler(void);
2898 static inline void intel_register_dsm_handler(void) { return; }
2899 static inline void intel_unregister_dsm_handler(void) { return; }
2900 #endif /* CONFIG_ACPI */
2903 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2904 extern void intel_modeset_init(struct drm_device
*dev
);
2905 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2906 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2907 extern void intel_connector_unregister(struct intel_connector
*);
2908 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2909 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2910 bool force_restore
);
2911 extern void i915_redisable_vga(struct drm_device
*dev
);
2912 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2913 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2914 extern void bdw_fbc_sw_flush(struct drm_device
*dev
, u32 value
);
2915 extern void intel_disable_fbc(struct drm_device
*dev
);
2916 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2917 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2918 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2919 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2920 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2922 extern void intel_detect_pch(struct drm_device
*dev
);
2923 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2924 extern int intel_enable_rc6(const struct drm_device
*dev
);
2926 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2927 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2928 struct drm_file
*file
);
2929 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2930 struct drm_file
*file
);
2932 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2935 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2936 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2937 struct intel_overlay_error_state
*error
);
2939 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2940 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2941 struct drm_device
*dev
,
2942 struct intel_display_error_state
*error
);
2944 /* On SNB platform, before reading ring registers forcewake bit
2945 * must be set to prevent GT core from power down and stale values being
2948 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2949 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2950 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2952 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
2953 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
2955 /* intel_sideband.c */
2956 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2957 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2958 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2959 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2960 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2961 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2962 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2963 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2964 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2965 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2966 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2967 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2968 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2969 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2970 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2971 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2972 enum intel_sbi_destination destination
);
2973 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2974 enum intel_sbi_destination destination
);
2975 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2976 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2978 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2979 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2981 #define FORCEWAKE_RENDER (1 << 0)
2982 #define FORCEWAKE_MEDIA (1 << 1)
2983 #define FORCEWAKE_BLITTER (1 << 2)
2984 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA | \
2988 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2989 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2991 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2992 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2993 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2994 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2996 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2997 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2998 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2999 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3001 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3002 * will be implemented using 2 32-bit writes in an arbitrary order with
3003 * an arbitrary delay between them. This can cause the hardware to
3004 * act upon the intermediate value, possibly leading to corruption and
3005 * machine death. You have been warned.
3007 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3008 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3010 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3011 u32 upper = I915_READ(upper_reg); \
3012 u32 lower = I915_READ(lower_reg); \
3013 u32 tmp = I915_READ(upper_reg); \
3014 if (upper != tmp) { \
3016 lower = I915_READ(lower_reg); \
3017 WARN_ON(I915_READ(upper_reg) != upper); \
3019 (u64)upper << 32 | lower; })
3021 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3022 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3024 /* "Broadcast RGB" property */
3025 #define INTEL_BROADCAST_RGB_AUTO 0
3026 #define INTEL_BROADCAST_RGB_FULL 1
3027 #define INTEL_BROADCAST_RGB_LIMITED 2
3029 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3031 if (IS_VALLEYVIEW(dev
))
3032 return VLV_VGACNTRL
;
3033 else if (INTEL_INFO(dev
)->gen
>= 5)
3034 return CPU_VGACNTRL
;
3039 static inline void __user
*to_user_ptr(u64 address
)
3041 return (void __user
*)(uintptr_t)address
;
3044 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3046 unsigned long j
= msecs_to_jiffies(m
);
3048 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3051 static inline unsigned long
3052 timespec_to_jiffies_timeout(const struct timespec
*value
)
3054 unsigned long j
= timespec_to_jiffies(value
);
3056 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3060 * If you need to wait X milliseconds between events A and B, but event B
3061 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3062 * when event A happened, then just before event B you call this function and
3063 * pass the timestamp as the first argument, and X as the second argument.
3066 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3068 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3071 * Don't re-read the value of "jiffies" every time since it may change
3072 * behind our back and break the math.
3074 tmp_jiffies
= jiffies
;
3075 target_jiffies
= timestamp_jiffies
+
3076 msecs_to_jiffies_timeout(to_wait_ms
);
3078 if (time_after(target_jiffies
, tmp_jiffies
)) {
3079 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3080 while (remaining_jiffies
)
3082 schedule_timeout_uninterruptible(remaining_jiffies
);