1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
34 #include "intel_bios.h"
35 #include <linux/io-mapping.h>
37 /* General customization:
40 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
42 #define DRIVER_NAME "i915"
43 #define DRIVER_DESC "Intel Graphics"
44 #define DRIVER_DATE "20080730"
56 #define I915_NUM_PIPE 2
61 * 1.2: Add Power Management
62 * 1.3: Add vblank support
63 * 1.4: Fix cmdbuffer path, add heap destroy
64 * 1.5: Add vblank pipe configuration
65 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
66 * - Support vertical blank on secondary display pipe
68 #define DRIVER_MAJOR 1
69 #define DRIVER_MINOR 6
70 #define DRIVER_PATCHLEVEL 0
72 #define WATCH_COHERENCY 0
77 #define WATCH_INACTIVE 0
78 #define WATCH_PWRITE 0
80 #define I915_GEM_PHYS_CURSOR_0 1
81 #define I915_GEM_PHYS_CURSOR_1 2
82 #define I915_GEM_PHYS_OVERLAY_REGS 3
83 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
85 struct drm_i915_gem_phys_object
{
87 struct page
**page_list
;
88 drm_dma_handle_t
*handle
;
89 struct drm_gem_object
*cur_obj
;
92 typedef struct _drm_i915_ring_buffer
{
99 struct drm_gem_object
*ring_obj
;
100 } drm_i915_ring_buffer_t
;
103 struct mem_block
*next
;
104 struct mem_block
*prev
;
107 struct drm_file
*file_priv
; /* NULL: free, -1: heap, other: real files */
110 struct opregion_header
;
111 struct opregion_acpi
;
112 struct opregion_swsci
;
113 struct opregion_asle
;
115 struct intel_opregion
{
116 struct opregion_header
*header
;
117 struct opregion_acpi
*acpi
;
118 struct opregion_swsci
*swsci
;
119 struct opregion_asle
*asle
;
123 struct drm_i915_master_private
{
124 drm_local_map_t
*sarea
;
125 struct _drm_i915_sarea
*sarea_priv
;
127 #define I915_FENCE_REG_NONE -1
129 struct drm_i915_fence_reg
{
130 struct drm_gem_object
*obj
;
133 struct sdvo_device_mapping
{
140 struct drm_i915_error_state
{
156 struct drm_i915_display_funcs
{
157 void (*dpms
)(struct drm_crtc
*crtc
, int mode
);
158 bool (*fbc_enabled
)(struct drm_crtc
*crtc
);
159 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
160 void (*disable_fbc
)(struct drm_device
*dev
);
161 int (*get_display_clock_speed
)(struct drm_device
*dev
);
162 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
163 void (*update_wm
)(struct drm_device
*dev
, int planea_clock
,
164 int planeb_clock
, int sr_hdisplay
, int pixel_size
);
165 /* clock updates for mode set */
167 /* render clock increase/decrease */
168 /* display clock increase/decrease */
169 /* pll clock increase/decrease */
170 /* clock gating init */
173 typedef struct drm_i915_private
{
174 struct drm_device
*dev
;
180 struct pci_dev
*bridge_dev
;
181 drm_i915_ring_buffer_t ring
;
183 drm_dma_handle_t
*status_page_dmah
;
184 void *hw_status_page
;
185 dma_addr_t dma_status_page
;
187 unsigned int status_gfx_addr
;
188 drm_local_map_t hws_map
;
189 struct drm_gem_object
*hws_obj
;
191 struct resource mch_res
;
199 wait_queue_head_t irq_queue
;
200 atomic_t irq_received
;
201 /** Protects user_irq_refcount and irq_mask_reg */
202 spinlock_t user_irq_lock
;
203 /** Refcount for i915_user_irq_get() versus i915_user_irq_put(). */
204 int user_irq_refcount
;
206 /** Cached value of IMR to avoid reads in updating the bitfield */
209 /** splitted irq regs for graphics and display engine on IGDNG,
210 irq_mask_reg is still used for display irq. */
212 u32 gt_irq_enable_reg
;
213 u32 de_irq_enable_reg
;
215 u32 hotplug_supported_mask
;
216 struct work_struct hotplug_work
;
218 int tex_lru_log_granularity
;
219 int allow_batchbuffer
;
220 struct mem_block
*agp_heap
;
221 unsigned int sr01
, adpa
, ppcr
, dvob
, dvoc
, lvds
;
224 /* For hangcheck timer */
225 #define DRM_I915_HANGCHECK_PERIOD 75 /* in jiffies */
226 struct timer_list hangcheck_timer
;
230 bool cursor_needs_physical
;
234 unsigned long cfb_size
;
235 unsigned long cfb_pitch
;
241 struct intel_opregion opregion
;
244 int backlight_duty_cycle
; /* restore backlight to this value */
245 bool panel_wants_dither
;
246 struct drm_display_mode
*panel_fixed_mode
;
247 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
248 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
250 /* Feature bits from the VBIOS */
251 unsigned int int_tv_support
:1;
252 unsigned int lvds_dither
:1;
253 unsigned int lvds_vbt
:1;
254 unsigned int int_crt_support
:1;
255 unsigned int lvds_use_ssc
:1;
256 unsigned int edp_support
:1;
259 struct notifier_block lid_notifier
;
261 int crt_ddc_bus
; /* -1 = unknown, else GPIO to use for CRT DDC */
262 struct drm_i915_fence_reg fence_regs
[16]; /* assume 965 */
263 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
264 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
266 unsigned int fsb_freq
, mem_freq
;
268 spinlock_t error_lock
;
269 struct drm_i915_error_state
*first_error
;
270 struct work_struct error_work
;
271 struct workqueue_struct
*wq
;
273 /* Display functions */
274 struct drm_i915_display_funcs display
;
282 u32 saveRENDERSTANDBY
;
300 u32 saveTRANS_HTOTAL_A
;
301 u32 saveTRANS_HBLANK_A
;
302 u32 saveTRANS_HSYNC_A
;
303 u32 saveTRANS_VTOTAL_A
;
304 u32 saveTRANS_VBLANK_A
;
305 u32 saveTRANS_VSYNC_A
;
313 u32 savePFIT_PGM_RATIOS
;
314 u32 saveBLC_HIST_CTL
;
316 u32 saveBLC_PWM_CTL2
;
317 u32 saveBLC_CPU_PWM_CTL
;
318 u32 saveBLC_CPU_PWM_CTL2
;
331 u32 saveTRANS_HTOTAL_B
;
332 u32 saveTRANS_HBLANK_B
;
333 u32 saveTRANS_HSYNC_B
;
334 u32 saveTRANS_VTOTAL_B
;
335 u32 saveTRANS_VBLANK_B
;
336 u32 saveTRANS_VSYNC_B
;
350 u32 savePP_ON_DELAYS
;
351 u32 savePP_OFF_DELAYS
;
359 u32 savePFIT_CONTROL
;
360 u32 save_palette_a
[256];
361 u32 save_palette_b
[256];
362 u32 saveDPFC_CB_BASE
;
363 u32 saveFBC_CFB_BASE
;
366 u32 saveFBC_CONTROL2
;
376 u32 saveCACHE_MODE_0
;
378 u32 saveDSPCLK_GATE_D
;
379 u32 saveMI_ARB_STATE
;
390 uint64_t saveFENCE
[16];
401 u32 savePIPEA_GMCH_DATA_M
;
402 u32 savePIPEB_GMCH_DATA_M
;
403 u32 savePIPEA_GMCH_DATA_N
;
404 u32 savePIPEB_GMCH_DATA_N
;
405 u32 savePIPEA_DP_LINK_M
;
406 u32 savePIPEB_DP_LINK_M
;
407 u32 savePIPEA_DP_LINK_N
;
408 u32 savePIPEB_DP_LINK_N
;
419 u32 savePCH_DREF_CONTROL
;
420 u32 saveDISP_ARB_CTL
;
421 u32 savePIPEA_DATA_M1
;
422 u32 savePIPEA_DATA_N1
;
423 u32 savePIPEA_LINK_M1
;
424 u32 savePIPEA_LINK_N1
;
425 u32 savePIPEB_DATA_M1
;
426 u32 savePIPEB_DATA_N1
;
427 u32 savePIPEB_LINK_M1
;
428 u32 savePIPEB_LINK_N1
;
431 struct drm_mm gtt_space
;
433 struct io_mapping
*gtt_mapping
;
437 * Membership on list of all loaded devices, used to evict
438 * inactive buffers under memory pressure.
440 * Modifications should only be done whilst holding the
441 * shrink_list_lock spinlock.
443 struct list_head shrink_list
;
446 * List of objects currently involved in rendering from the
449 * Includes buffers having the contents of their GPU caches
450 * flushed, not necessarily primitives. last_rendering_seqno
451 * represents when the rendering involved will be completed.
453 * A reference is held on the buffer while on this list.
455 spinlock_t active_list_lock
;
456 struct list_head active_list
;
459 * List of objects which are not in the ringbuffer but which
460 * still have a write_domain which needs to be flushed before
463 * last_rendering_seqno is 0 while an object is in this list.
465 * A reference is held on the buffer while on this list.
467 struct list_head flushing_list
;
470 * LRU list of objects which are not in the ringbuffer and
471 * are ready to unbind, but are still in the GTT.
473 * last_rendering_seqno is 0 while an object is in this list.
475 * A reference is not held on the buffer while on this list,
476 * as merely being GTT-bound shouldn't prevent its being
477 * freed, and we'll pull it off the list in the free path.
479 struct list_head inactive_list
;
481 /** LRU list of objects with fence regs on them. */
482 struct list_head fence_list
;
485 * List of breadcrumbs associated with GPU requests currently
488 struct list_head request_list
;
491 * We leave the user IRQ off as much as possible,
492 * but this means that requests will finish and never
493 * be retired once the system goes idle. Set a timer to
494 * fire periodically while the ring is running. When it
495 * fires, go retire requests.
497 struct delayed_work retire_work
;
499 uint32_t next_gem_seqno
;
502 * Waiting sequence number, if any
504 uint32_t waiting_gem_seqno
;
507 * Last seq seen at irq time
509 uint32_t irq_gem_seqno
;
512 * Flag if the X Server, and thus DRM, is not currently in
513 * control of the device.
515 * This is set between LeaveVT and EnterVT. It needs to be
516 * replaced with a semaphore. It also needs to be
517 * transitioned away from for kernel modesetting.
522 * Flag if the hardware appears to be wedged.
524 * This is set when attempts to idle the device timeout.
525 * It prevents command submission from occuring and makes
526 * every pending request fail
530 /** Bit 6 swizzling required for X tiling */
531 uint32_t bit_6_swizzle_x
;
532 /** Bit 6 swizzling required for Y tiling */
533 uint32_t bit_6_swizzle_y
;
535 /* storage for physical objects */
536 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
538 struct sdvo_device_mapping sdvo_mappings
[2];
539 /* indicate whether the LVDS_BORDER should be enabled or not */
540 unsigned int lvds_border_bits
;
542 /* Reclocking support */
543 bool render_reclock_avail
;
544 bool lvds_downclock_avail
;
545 struct work_struct idle_work
;
546 struct timer_list idle_timer
;
549 } drm_i915_private_t
;
551 /** driver private structure attached to each drm_gem_object */
552 struct drm_i915_gem_object
{
553 struct drm_gem_object
*obj
;
555 /** Current space allocated to this object in the GTT, if any. */
556 struct drm_mm_node
*gtt_space
;
558 /** This object's place on the active/flushing/inactive lists */
559 struct list_head list
;
561 /** This object's place on the fenced object LRU */
562 struct list_head fence_list
;
565 * This is set if the object is on the active or flushing lists
566 * (has pending rendering), and is not set if it's on inactive (ready
572 * This is set if the object has been written to since last bound
577 /** AGP memory structure for our GTT binding. */
578 DRM_AGP_MEM
*agp_mem
;
584 * Current offset of the object in GTT space.
586 * This is the same as gtt_space->start
591 * Fake offset for use by mmap(2)
593 uint64_t mmap_offset
;
596 * Fence register bits (if any) for this object. Will be set
597 * as needed when mapped into the GTT.
598 * Protected by dev->struct_mutex.
602 /** How many users have pinned this object in GTT space */
605 /** Breadcrumb of last rendering to the buffer. */
606 uint32_t last_rendering_seqno
;
608 /** Current tiling mode for the object. */
609 uint32_t tiling_mode
;
612 /** Record of address bit 17 of each page at last unbind. */
615 /** AGP mapping type (AGP_USER_MEMORY or AGP_USER_CACHED_MEMORY */
619 * If present, while GEM_DOMAIN_CPU is in the read domain this array
620 * flags which individual pages are valid.
622 uint8_t *page_cpu_valid
;
624 /** User space pin count and filp owning the pin */
625 uint32_t user_pin_count
;
626 struct drm_file
*pin_filp
;
628 /** for phy allocated objects */
629 struct drm_i915_gem_phys_object
*phys_obj
;
632 * Used for checking the object doesn't appear more than once
633 * in an execbuffer object list.
638 * Advice: are the backing pages purgeable?
644 * Request queue structure.
646 * The request queue allows us to note sequence numbers that have been emitted
647 * and may be associated with active buffers to be retired.
649 * By keeping this list, we can avoid having to do questionable
650 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
651 * an emission time with seqnos for tracking how far ahead of the GPU we are.
653 struct drm_i915_gem_request
{
654 /** GEM sequence number associated with this request. */
657 /** Time at which this request was emitted, in jiffies. */
658 unsigned long emitted_jiffies
;
660 /** global list entry for this request */
661 struct list_head list
;
663 /** file_priv list entry for this request */
664 struct list_head client_list
;
667 struct drm_i915_file_private
{
669 struct list_head request_list
;
673 enum intel_chip_family
{
680 extern struct drm_ioctl_desc i915_ioctls
[];
681 extern int i915_max_ioctl
;
682 extern unsigned int i915_fbpercrtc
;
683 extern unsigned int i915_powersave
;
685 extern void i915_save_display(struct drm_device
*dev
);
686 extern void i915_restore_display(struct drm_device
*dev
);
687 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
688 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
691 extern void i915_kernel_lost_context(struct drm_device
* dev
);
692 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
693 extern int i915_driver_unload(struct drm_device
*);
694 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
695 extern void i915_driver_lastclose(struct drm_device
* dev
);
696 extern void i915_driver_preclose(struct drm_device
*dev
,
697 struct drm_file
*file_priv
);
698 extern void i915_driver_postclose(struct drm_device
*dev
,
699 struct drm_file
*file_priv
);
700 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
701 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
703 extern int i915_emit_box(struct drm_device
*dev
,
704 struct drm_clip_rect
*boxes
,
705 int i
, int DR1
, int DR4
);
706 extern int i965_reset(struct drm_device
*dev
, u8 flags
);
709 void i915_hangcheck_elapsed(unsigned long data
);
710 extern int i915_irq_emit(struct drm_device
*dev
, void *data
,
711 struct drm_file
*file_priv
);
712 extern int i915_irq_wait(struct drm_device
*dev
, void *data
,
713 struct drm_file
*file_priv
);
714 void i915_user_irq_get(struct drm_device
*dev
);
715 void i915_trace_irq_get(struct drm_device
*dev
, u32 seqno
);
716 void i915_user_irq_put(struct drm_device
*dev
);
717 extern void i915_enable_interrupt (struct drm_device
*dev
);
719 extern irqreturn_t
i915_driver_irq_handler(DRM_IRQ_ARGS
);
720 extern void i915_driver_irq_preinstall(struct drm_device
* dev
);
721 extern int i915_driver_irq_postinstall(struct drm_device
*dev
);
722 extern void i915_driver_irq_uninstall(struct drm_device
* dev
);
723 extern int i915_vblank_pipe_set(struct drm_device
*dev
, void *data
,
724 struct drm_file
*file_priv
);
725 extern int i915_vblank_pipe_get(struct drm_device
*dev
, void *data
,
726 struct drm_file
*file_priv
);
727 extern int i915_enable_vblank(struct drm_device
*dev
, int crtc
);
728 extern void i915_disable_vblank(struct drm_device
*dev
, int crtc
);
729 extern u32
i915_get_vblank_counter(struct drm_device
*dev
, int crtc
);
730 extern u32
gm45_get_vblank_counter(struct drm_device
*dev
, int crtc
);
731 extern int i915_vblank_swap(struct drm_device
*dev
, void *data
,
732 struct drm_file
*file_priv
);
733 extern void i915_enable_irq(drm_i915_private_t
*dev_priv
, u32 mask
);
736 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
739 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
743 extern int i915_mem_alloc(struct drm_device
*dev
, void *data
,
744 struct drm_file
*file_priv
);
745 extern int i915_mem_free(struct drm_device
*dev
, void *data
,
746 struct drm_file
*file_priv
);
747 extern int i915_mem_init_heap(struct drm_device
*dev
, void *data
,
748 struct drm_file
*file_priv
);
749 extern int i915_mem_destroy_heap(struct drm_device
*dev
, void *data
,
750 struct drm_file
*file_priv
);
751 extern void i915_mem_takedown(struct mem_block
**heap
);
752 extern void i915_mem_release(struct drm_device
* dev
,
753 struct drm_file
*file_priv
, struct mem_block
*heap
);
755 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
756 struct drm_file
*file_priv
);
757 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
758 struct drm_file
*file_priv
);
759 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
760 struct drm_file
*file_priv
);
761 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
762 struct drm_file
*file_priv
);
763 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
764 struct drm_file
*file_priv
);
765 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
766 struct drm_file
*file_priv
);
767 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
768 struct drm_file
*file_priv
);
769 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
770 struct drm_file
*file_priv
);
771 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
772 struct drm_file
*file_priv
);
773 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
774 struct drm_file
*file_priv
);
775 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
776 struct drm_file
*file_priv
);
777 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
778 struct drm_file
*file_priv
);
779 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
780 struct drm_file
*file_priv
);
781 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
782 struct drm_file
*file_priv
);
783 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
784 struct drm_file
*file_priv
);
785 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
786 struct drm_file
*file_priv
);
787 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
788 struct drm_file
*file_priv
);
789 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
790 struct drm_file
*file_priv
);
791 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
792 struct drm_file
*file_priv
);
793 void i915_gem_load(struct drm_device
*dev
);
794 int i915_gem_init_object(struct drm_gem_object
*obj
);
795 void i915_gem_free_object(struct drm_gem_object
*obj
);
796 int i915_gem_object_pin(struct drm_gem_object
*obj
, uint32_t alignment
);
797 void i915_gem_object_unpin(struct drm_gem_object
*obj
);
798 int i915_gem_object_unbind(struct drm_gem_object
*obj
);
799 void i915_gem_release_mmap(struct drm_gem_object
*obj
);
800 void i915_gem_lastclose(struct drm_device
*dev
);
801 uint32_t i915_get_gem_seqno(struct drm_device
*dev
);
802 bool i915_seqno_passed(uint32_t seq1
, uint32_t seq2
);
803 int i915_gem_object_get_fence_reg(struct drm_gem_object
*obj
);
804 int i915_gem_object_put_fence_reg(struct drm_gem_object
*obj
);
805 void i915_gem_retire_requests(struct drm_device
*dev
);
806 void i915_gem_retire_work_handler(struct work_struct
*work
);
807 void i915_gem_clflush_object(struct drm_gem_object
*obj
);
808 int i915_gem_object_set_domain(struct drm_gem_object
*obj
,
809 uint32_t read_domains
,
810 uint32_t write_domain
);
811 int i915_gem_init_ringbuffer(struct drm_device
*dev
);
812 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
813 int i915_gem_do_init(struct drm_device
*dev
, unsigned long start
,
815 int i915_gem_idle(struct drm_device
*dev
);
816 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
817 int i915_gem_object_set_to_gtt_domain(struct drm_gem_object
*obj
,
819 int i915_gem_attach_phys_object(struct drm_device
*dev
,
820 struct drm_gem_object
*obj
, int id
);
821 void i915_gem_detach_phys_object(struct drm_device
*dev
,
822 struct drm_gem_object
*obj
);
823 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
824 int i915_gem_object_get_pages(struct drm_gem_object
*obj
);
825 void i915_gem_object_put_pages(struct drm_gem_object
*obj
);
826 void i915_gem_release(struct drm_device
* dev
, struct drm_file
*file_priv
);
828 void i915_gem_shrinker_init(void);
829 void i915_gem_shrinker_exit(void);
831 /* i915_gem_tiling.c */
832 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
833 void i915_gem_object_do_bit_17_swizzle(struct drm_gem_object
*obj
);
834 void i915_gem_object_save_bit_17_swizzle(struct drm_gem_object
*obj
);
836 /* i915_gem_debug.c */
837 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
838 const char *where
, uint32_t mark
);
840 void i915_verify_inactive(struct drm_device
*dev
, char *file
, int line
);
842 #define i915_verify_inactive(dev, file, line)
844 void i915_gem_object_check_coherency(struct drm_gem_object
*obj
, int handle
);
845 void i915_gem_dump_object(struct drm_gem_object
*obj
, int len
,
846 const char *where
, uint32_t mark
);
847 void i915_dump_lru(struct drm_device
*dev
, const char *where
);
850 int i915_debugfs_init(struct drm_minor
*minor
);
851 void i915_debugfs_cleanup(struct drm_minor
*minor
);
854 extern int i915_save_state(struct drm_device
*dev
);
855 extern int i915_restore_state(struct drm_device
*dev
);
858 extern int i915_save_state(struct drm_device
*dev
);
859 extern int i915_restore_state(struct drm_device
*dev
);
862 /* i915_opregion.c */
863 extern int intel_opregion_init(struct drm_device
*dev
, int resume
);
864 extern void intel_opregion_free(struct drm_device
*dev
, int suspend
);
865 extern void opregion_asle_intr(struct drm_device
*dev
);
866 extern void opregion_enable_asle(struct drm_device
*dev
);
868 static inline int intel_opregion_init(struct drm_device
*dev
, int resume
) { return 0; }
869 static inline void intel_opregion_free(struct drm_device
*dev
, int suspend
) { return; }
870 static inline void opregion_asle_intr(struct drm_device
*dev
) { return; }
871 static inline void opregion_enable_asle(struct drm_device
*dev
) { return; }
875 extern void intel_modeset_init(struct drm_device
*dev
);
876 extern void intel_modeset_cleanup(struct drm_device
*dev
);
877 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
878 extern void i8xx_disable_fbc(struct drm_device
*dev
);
879 extern void g4x_disable_fbc(struct drm_device
*dev
);
882 * Lock test for when it's just for synchronization of ring access.
884 * In that case, we don't need to do it when GEM is initialized as nobody else
885 * has access to the ring.
887 #define RING_LOCK_TEST_WITH_RETURN(dev, file_priv) do { \
888 if (((drm_i915_private_t *)dev->dev_private)->ring.ring_obj == NULL) \
889 LOCK_TEST_WITH_RETURN(dev, file_priv); \
892 #define I915_READ(reg) readl(dev_priv->regs + (reg))
893 #define I915_WRITE(reg, val) writel(val, dev_priv->regs + (reg))
894 #define I915_READ16(reg) readw(dev_priv->regs + (reg))
895 #define I915_WRITE16(reg, val) writel(val, dev_priv->regs + (reg))
896 #define I915_READ8(reg) readb(dev_priv->regs + (reg))
897 #define I915_WRITE8(reg, val) writeb(val, dev_priv->regs + (reg))
898 #define I915_WRITE64(reg, val) writeq(val, dev_priv->regs + (reg))
899 #define I915_READ64(reg) readq(dev_priv->regs + (reg))
900 #define POSTING_READ(reg) (void)I915_READ(reg)
902 #define I915_VERBOSE 0
904 #define RING_LOCALS volatile unsigned int *ring_virt__;
906 #define BEGIN_LP_RING(n) do { \
907 int bytes__ = 4*(n); \
908 if (I915_VERBOSE) DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \
909 /* a wrap must occur between instructions so pad beforehand */ \
910 if (unlikely (dev_priv->ring.tail + bytes__ > dev_priv->ring.Size)) \
911 i915_wrap_ring(dev); \
912 if (unlikely (dev_priv->ring.space < bytes__)) \
913 i915_wait_ring(dev, bytes__, __func__); \
914 ring_virt__ = (unsigned int *) \
915 (dev_priv->ring.virtual_start + dev_priv->ring.tail); \
916 dev_priv->ring.tail += bytes__; \
917 dev_priv->ring.tail &= dev_priv->ring.Size - 1; \
918 dev_priv->ring.space -= bytes__; \
921 #define OUT_RING(n) do { \
922 if (I915_VERBOSE) DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \
923 *ring_virt__++ = (n); \
926 #define ADVANCE_LP_RING() do { \
928 DRM_DEBUG("ADVANCE_LP_RING %x\n", dev_priv->ring.tail); \
929 I915_WRITE(PRB0_TAIL, dev_priv->ring.tail); \
933 * Reads a dword out of the status page, which is written to from the command
934 * queue by automatic updates, MI_REPORT_HEAD, MI_STORE_DATA_INDEX, or
937 * The following dwords have a reserved meaning:
938 * 0x00: ISR copy, updated when an ISR bit not set in the HWSTAM changes.
939 * 0x04: ring 0 head pointer
940 * 0x05: ring 1 head pointer (915-class)
941 * 0x06: ring 2 head pointer (915-class)
942 * 0x10-0x1b: Context status DWords (GM45)
943 * 0x1f: Last written status offset. (GM45)
945 * The area from dword 0x20 to 0x3ff is available for driver usage.
947 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg])
948 #define READ_BREADCRUMB(dev_priv) READ_HWSP(dev_priv, I915_BREADCRUMB_INDEX)
949 #define I915_GEM_HWS_INDEX 0x20
950 #define I915_BREADCRUMB_INDEX 0x21
952 extern int i915_wrap_ring(struct drm_device
* dev
);
953 extern int i915_wait_ring(struct drm_device
* dev
, int n
, const char *caller
);
955 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
956 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
957 #define IS_I85X(dev) ((dev)->pci_device == 0x3582)
958 #define IS_I855(dev) ((dev)->pci_device == 0x3582)
959 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
961 #define IS_I915G(dev) ((dev)->pci_device == 0x2582 || (dev)->pci_device == 0x258a)
962 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
963 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
964 #define IS_I945GM(dev) ((dev)->pci_device == 0x27A2 ||\
965 (dev)->pci_device == 0x27AE)
966 #define IS_I965G(dev) ((dev)->pci_device == 0x2972 || \
967 (dev)->pci_device == 0x2982 || \
968 (dev)->pci_device == 0x2992 || \
969 (dev)->pci_device == 0x29A2 || \
970 (dev)->pci_device == 0x2A02 || \
971 (dev)->pci_device == 0x2A12 || \
972 (dev)->pci_device == 0x2A42 || \
973 (dev)->pci_device == 0x2E02 || \
974 (dev)->pci_device == 0x2E12 || \
975 (dev)->pci_device == 0x2E22 || \
976 (dev)->pci_device == 0x2E32 || \
977 (dev)->pci_device == 0x2E42 || \
978 (dev)->pci_device == 0x0042 || \
979 (dev)->pci_device == 0x0046)
981 #define IS_I965GM(dev) ((dev)->pci_device == 0x2A02 || \
982 (dev)->pci_device == 0x2A12)
984 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
986 #define IS_G4X(dev) ((dev)->pci_device == 0x2E02 || \
987 (dev)->pci_device == 0x2E12 || \
988 (dev)->pci_device == 0x2E22 || \
989 (dev)->pci_device == 0x2E32 || \
990 (dev)->pci_device == 0x2E42 || \
993 #define IS_IGDG(dev) ((dev)->pci_device == 0xa001)
994 #define IS_IGDGM(dev) ((dev)->pci_device == 0xa011)
995 #define IS_IGD(dev) (IS_IGDG(dev) || IS_IGDGM(dev))
997 #define IS_G33(dev) ((dev)->pci_device == 0x29C2 || \
998 (dev)->pci_device == 0x29B2 || \
999 (dev)->pci_device == 0x29D2 || \
1002 #define IS_IGDNG_D(dev) ((dev)->pci_device == 0x0042)
1003 #define IS_IGDNG_M(dev) ((dev)->pci_device == 0x0046)
1004 #define IS_IGDNG(dev) (IS_IGDNG_D(dev) || IS_IGDNG_M(dev))
1006 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \
1007 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev) || \
1010 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \
1011 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev) || \
1012 IS_IGD(dev) || IS_IGDNG_M(dev))
1014 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev) || \
1016 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1017 * rows, which changed the alignment requirements and fence programming.
1019 #define HAS_128_BYTE_Y_TILING(dev) (IS_I9XX(dev) && !(IS_I915G(dev) || \
1021 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1022 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1023 #define SUPPORTS_EDP(dev) (IS_IGDNG_M(dev))
1024 #define I915_HAS_HOTPLUG(dev) (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev) || IS_I965G(dev))
1025 /* dsparb controlled by hw only */
1026 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1028 #define HAS_FW_BLC(dev) (IS_I9XX(dev) || IS_G4X(dev) || IS_IGDNG(dev))
1029 #define HAS_PIPE_CXSR(dev) (IS_G4X(dev) || IS_IGDNG(dev))
1030 #define I915_HAS_FBC(dev) (IS_MOBILE(dev) && \
1031 (IS_I9XX(dev) || IS_GM45(dev)) && \
1035 #define PRIMARY_RINGBUFFER_SIZE (128*1024)