1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
= POWER_DOMAIN_TRANSCODER_A
+ 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
112 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct drm_i915_private
;
138 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
143 #define I915_NUM_PLLS 2
145 struct intel_dpll_hw_state
{
152 struct intel_shared_dpll
{
153 int refcount
; /* count of number of CRTCs sharing this PLL */
154 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on
; /* is the PLL actually active? Disabled during modeset */
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id
;
159 struct intel_dpll_hw_state hw_state
;
160 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
161 struct intel_shared_dpll
*pll
);
162 void (*enable
)(struct drm_i915_private
*dev_priv
,
163 struct intel_shared_dpll
*pll
);
164 void (*disable
)(struct drm_i915_private
*dev_priv
,
165 struct intel_shared_dpll
*pll
);
166 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
167 struct intel_shared_dpll
*pll
,
168 struct intel_dpll_hw_state
*hw_state
);
171 /* Used by dp and fdi links */
172 struct intel_link_m_n
{
180 void intel_link_compute_m_n(int bpp
, int nlanes
,
181 int pixel_clock
, int link_clock
,
182 struct intel_link_m_n
*m_n
);
184 struct intel_ddi_plls
{
190 /* Interface history:
193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
195 * 1.4: Fix cmdbuffer path, add heap destroy
196 * 1.5: Add vblank pipe configuration
197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
200 #define DRIVER_MAJOR 1
201 #define DRIVER_MINOR 6
202 #define DRIVER_PATCHLEVEL 0
204 #define WATCH_LISTS 0
207 #define I915_GEM_PHYS_CURSOR_0 1
208 #define I915_GEM_PHYS_CURSOR_1 2
209 #define I915_GEM_PHYS_OVERLAY_REGS 3
210 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
212 struct drm_i915_gem_phys_object
{
214 struct page
**page_list
;
215 drm_dma_handle_t
*handle
;
216 struct drm_i915_gem_object
*cur_obj
;
219 struct opregion_header
;
220 struct opregion_acpi
;
221 struct opregion_swsci
;
222 struct opregion_asle
;
224 struct intel_opregion
{
225 struct opregion_header __iomem
*header
;
226 struct opregion_acpi __iomem
*acpi
;
227 struct opregion_swsci __iomem
*swsci
;
228 struct opregion_asle __iomem
*asle
;
230 u32 __iomem
*lid_state
;
232 #define OPREGION_SIZE (8*1024)
234 struct intel_overlay
;
235 struct intel_overlay_error_state
;
237 struct drm_i915_master_private
{
238 drm_local_map_t
*sarea
;
239 struct _drm_i915_sarea
*sarea_priv
;
241 #define I915_FENCE_REG_NONE -1
242 #define I915_MAX_NUM_FENCES 32
243 /* 32 fences + sign bit for FENCE_REG_NONE */
244 #define I915_MAX_NUM_FENCE_BITS 6
246 struct drm_i915_fence_reg
{
247 struct list_head lru_list
;
248 struct drm_i915_gem_object
*obj
;
252 struct sdvo_device_mapping
{
261 struct intel_display_error_state
;
263 struct drm_i915_error_state
{
271 bool waiting
[I915_NUM_RINGS
];
272 u32 pipestat
[I915_MAX_PIPES
];
273 u32 tail
[I915_NUM_RINGS
];
274 u32 head
[I915_NUM_RINGS
];
275 u32 ctl
[I915_NUM_RINGS
];
276 u32 ipeir
[I915_NUM_RINGS
];
277 u32 ipehr
[I915_NUM_RINGS
];
278 u32 instdone
[I915_NUM_RINGS
];
279 u32 acthd
[I915_NUM_RINGS
];
280 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
281 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
282 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
283 /* our own tracking of ring head and tail */
284 u32 cpu_ring_head
[I915_NUM_RINGS
];
285 u32 cpu_ring_tail
[I915_NUM_RINGS
];
286 u32 error
; /* gen6+ */
287 u32 err_int
; /* gen7 */
288 u32 instpm
[I915_NUM_RINGS
];
289 u32 instps
[I915_NUM_RINGS
];
290 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
291 u32 seqno
[I915_NUM_RINGS
];
293 u32 fault_reg
[I915_NUM_RINGS
];
295 u32 faddr
[I915_NUM_RINGS
];
296 u64 fence
[I915_MAX_NUM_FENCES
];
298 struct drm_i915_error_ring
{
299 struct drm_i915_error_object
{
303 } *ringbuffer
, *batchbuffer
, *ctx
;
304 struct drm_i915_error_request
{
310 } ring
[I915_NUM_RINGS
];
311 struct drm_i915_error_buffer
{
318 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
325 } **active_bo
, **pinned_bo
;
326 u32
*active_bo_count
, *pinned_bo_count
;
327 struct intel_overlay_error_state
*overlay
;
328 struct intel_display_error_state
*display
;
331 struct intel_crtc_config
;
336 struct drm_i915_display_funcs
{
337 bool (*fbc_enabled
)(struct drm_device
*dev
);
338 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
339 void (*disable_fbc
)(struct drm_device
*dev
);
340 int (*get_display_clock_speed
)(struct drm_device
*dev
);
341 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
343 * find_dpll() - Find the best values for the PLL
344 * @limit: limits for the PLL
345 * @crtc: current CRTC
346 * @target: target frequency in kHz
347 * @refclk: reference clock frequency in kHz
348 * @match_clock: if provided, @best_clock P divider must
349 * match the P divider from @match_clock
350 * used for LVDS downclocking
351 * @best_clock: best PLL values found
353 * Returns true on success, false on failure.
355 bool (*find_dpll
)(const struct intel_limit
*limit
,
356 struct drm_crtc
*crtc
,
357 int target
, int refclk
,
358 struct dpll
*match_clock
,
359 struct dpll
*best_clock
);
360 void (*update_wm
)(struct drm_device
*dev
);
361 void (*update_sprite_wm
)(struct drm_plane
*plane
,
362 struct drm_crtc
*crtc
,
363 uint32_t sprite_width
, int pixel_size
,
364 bool enable
, bool scaled
);
365 void (*modeset_global_resources
)(struct drm_device
*dev
);
366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config
)(struct intel_crtc
*,
369 struct intel_crtc_config
*);
370 void (*get_clock
)(struct intel_crtc
*, struct intel_crtc_config
*);
371 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
373 struct drm_framebuffer
*old_fb
);
374 void (*crtc_enable
)(struct drm_crtc
*crtc
);
375 void (*crtc_disable
)(struct drm_crtc
*crtc
);
376 void (*off
)(struct drm_crtc
*crtc
);
377 void (*write_eld
)(struct drm_connector
*connector
,
378 struct drm_crtc
*crtc
);
379 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
380 void (*init_clock_gating
)(struct drm_device
*dev
);
381 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
382 struct drm_framebuffer
*fb
,
383 struct drm_i915_gem_object
*obj
);
384 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
386 void (*hpd_irq_setup
)(struct drm_device
*dev
);
387 /* clock updates for mode set */
389 /* render clock increase/decrease */
390 /* display clock increase/decrease */
391 /* pll clock increase/decrease */
394 struct intel_uncore_funcs
{
395 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
396 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
399 struct intel_uncore
{
400 spinlock_t lock
; /** lock is also taken in irq contexts. */
402 struct intel_uncore_funcs funcs
;
405 unsigned forcewake_count
;
408 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
409 func(is_mobile) sep \
412 func(is_i945gm) sep \
414 func(need_gfx_hws) sep \
416 func(is_pineview) sep \
417 func(is_broadwater) sep \
418 func(is_crestline) sep \
419 func(is_ivybridge) sep \
420 func(is_valleyview) sep \
421 func(is_haswell) sep \
422 func(has_force_wake) sep \
424 func(has_pipe_cxsr) sep \
425 func(has_hotplug) sep \
426 func(cursor_needs_physical) sep \
427 func(has_overlay) sep \
428 func(overlay_needs_physical) sep \
429 func(supports_tv) sep \
430 func(has_bsd_ring) sep \
431 func(has_blt_ring) sep \
432 func(has_vebox_ring) sep \
437 #define DEFINE_FLAG(name) u8 name:1
438 #define SEP_SEMICOLON ;
440 struct intel_device_info
{
441 u32 display_mmio_offset
;
444 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
450 enum i915_cache_level
{
452 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
453 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
454 caches, eg sampler/render caches, and the
455 large Last-Level-Cache. LLC is coherent with
456 the CPU, but L3 is only visible to the GPU. */
457 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
460 typedef uint32_t gen6_gtt_pte_t
;
462 struct i915_address_space
{
464 struct drm_device
*dev
;
465 struct list_head global_link
;
466 unsigned long start
; /* Start offset always 0 for dri2 */
467 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
475 * List of objects currently involved in rendering.
477 * Includes buffers having the contents of their GPU caches
478 * flushed, not necessarily primitives. last_rendering_seqno
479 * represents when the rendering involved will be completed.
481 * A reference is held on the buffer while on this list.
483 struct list_head active_list
;
486 * LRU list of objects which are not in the ringbuffer and
487 * are ready to unbind, but are still in the GTT.
489 * last_rendering_seqno is 0 while an object is in this list.
491 * A reference is not held on the buffer while on this list,
492 * as merely being GTT-bound shouldn't prevent its being
493 * freed, and we'll pull it off the list in the free path.
495 struct list_head inactive_list
;
497 /* FIXME: Need a more generic return type */
498 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
499 enum i915_cache_level level
);
500 void (*clear_range
)(struct i915_address_space
*vm
,
501 unsigned int first_entry
,
502 unsigned int num_entries
);
503 void (*insert_entries
)(struct i915_address_space
*vm
,
505 unsigned int first_entry
,
506 enum i915_cache_level cache_level
);
507 void (*cleanup
)(struct i915_address_space
*vm
);
510 /* The Graphics Translation Table is the way in which GEN hardware translates a
511 * Graphics Virtual Address into a Physical Address. In addition to the normal
512 * collateral associated with any va->pa translations GEN hardware also has a
513 * portion of the GTT which can be mapped by the CPU and remain both coherent
514 * and correct (in cases like swizzling). That region is referred to as GMADR in
518 struct i915_address_space base
;
519 size_t stolen_size
; /* Total size of stolen memory */
521 unsigned long mappable_end
; /* End offset that we can CPU map */
522 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
523 phys_addr_t mappable_base
; /* PA of our GMADR */
525 /** "Graphics Stolen Memory" holds the global PTEs */
533 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
534 size_t *stolen
, phys_addr_t
*mappable_base
,
535 unsigned long *mappable_end
);
537 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
539 struct i915_hw_ppgtt
{
540 struct i915_address_space base
;
541 unsigned num_pd_entries
;
542 struct page
**pt_pages
;
544 dma_addr_t
*pt_dma_addr
;
546 int (*enable
)(struct drm_device
*dev
);
550 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
551 * VMA's presence cannot be guaranteed before binding, or after unbinding the
552 * object into/from the address space.
554 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
555 * will always be <= an objects lifetime. So object refcounting should cover us.
558 struct drm_mm_node node
;
559 struct drm_i915_gem_object
*obj
;
560 struct i915_address_space
*vm
;
562 /** This object's place on the active/inactive lists */
563 struct list_head mm_list
;
565 struct list_head vma_link
; /* Link in the object's VMA list */
567 /** This vma's place in the batchbuffer or on the eviction list */
568 struct list_head exec_list
;
572 struct i915_ctx_hang_stats
{
573 /* This context had batch pending when hang was declared */
574 unsigned batch_pending
;
576 /* This context had batch active when hang was declared */
577 unsigned batch_active
;
580 /* This must match up with the value previously used for execbuf2.rsvd1. */
581 #define DEFAULT_CONTEXT_ID 0
582 struct i915_hw_context
{
586 struct drm_i915_file_private
*file_priv
;
587 struct intel_ring_buffer
*ring
;
588 struct drm_i915_gem_object
*obj
;
589 struct i915_ctx_hang_stats hang_stats
;
598 struct drm_mm_node
*compressed_fb
;
599 struct drm_mm_node
*compressed_llb
;
601 struct intel_fbc_work
{
602 struct delayed_work work
;
603 struct drm_crtc
*crtc
;
604 struct drm_framebuffer
*fb
;
609 FBC_OK
, /* FBC is enabled */
610 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
611 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
612 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
613 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
614 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
615 FBC_BAD_PLANE
, /* fbc not supported on plane */
616 FBC_NOT_TILED
, /* buffer not tiled */
617 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
619 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
624 PSR_NO_SOURCE
, /* Not supported on platform */
625 PSR_NO_SINK
, /* Not supported by panel */
628 PSR_PWR_WELL_ENABLED
,
632 PSR_INTERLACED_ENABLED
,
637 PCH_NONE
= 0, /* No PCH present */
638 PCH_IBX
, /* Ibexpeak PCH */
639 PCH_CPT
, /* Cougarpoint PCH */
640 PCH_LPT
, /* Lynxpoint PCH */
644 enum intel_sbi_destination
{
649 #define QUIRK_PIPEA_FORCE (1<<0)
650 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
651 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
652 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
655 struct intel_fbc_work
;
658 struct i2c_adapter adapter
;
662 struct i2c_algo_bit_data bit_algo
;
663 struct drm_i915_private
*dev_priv
;
666 struct i915_suspend_saved_registers
{
687 u32 saveTRANS_HTOTAL_A
;
688 u32 saveTRANS_HBLANK_A
;
689 u32 saveTRANS_HSYNC_A
;
690 u32 saveTRANS_VTOTAL_A
;
691 u32 saveTRANS_VBLANK_A
;
692 u32 saveTRANS_VSYNC_A
;
700 u32 savePFIT_PGM_RATIOS
;
701 u32 saveBLC_HIST_CTL
;
703 u32 saveBLC_PWM_CTL2
;
704 u32 saveBLC_CPU_PWM_CTL
;
705 u32 saveBLC_CPU_PWM_CTL2
;
718 u32 saveTRANS_HTOTAL_B
;
719 u32 saveTRANS_HBLANK_B
;
720 u32 saveTRANS_HSYNC_B
;
721 u32 saveTRANS_VTOTAL_B
;
722 u32 saveTRANS_VBLANK_B
;
723 u32 saveTRANS_VSYNC_B
;
737 u32 savePP_ON_DELAYS
;
738 u32 savePP_OFF_DELAYS
;
746 u32 savePFIT_CONTROL
;
747 u32 save_palette_a
[256];
748 u32 save_palette_b
[256];
749 u32 saveDPFC_CB_BASE
;
750 u32 saveFBC_CFB_BASE
;
753 u32 saveFBC_CONTROL2
;
763 u32 saveCACHE_MODE_0
;
764 u32 saveMI_ARB_STATE
;
775 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
786 u32 savePIPEA_GMCH_DATA_M
;
787 u32 savePIPEB_GMCH_DATA_M
;
788 u32 savePIPEA_GMCH_DATA_N
;
789 u32 savePIPEB_GMCH_DATA_N
;
790 u32 savePIPEA_DP_LINK_M
;
791 u32 savePIPEB_DP_LINK_M
;
792 u32 savePIPEA_DP_LINK_N
;
793 u32 savePIPEB_DP_LINK_N
;
804 u32 savePCH_DREF_CONTROL
;
805 u32 saveDISP_ARB_CTL
;
806 u32 savePIPEA_DATA_M1
;
807 u32 savePIPEA_DATA_N1
;
808 u32 savePIPEA_LINK_M1
;
809 u32 savePIPEA_LINK_N1
;
810 u32 savePIPEB_DATA_M1
;
811 u32 savePIPEB_DATA_N1
;
812 u32 savePIPEB_LINK_M1
;
813 u32 savePIPEB_LINK_N1
;
814 u32 saveMCHBAR_RENDER_STANDBY
;
815 u32 savePCH_PORT_HOTPLUG
;
818 struct intel_gen6_power_mgmt
{
819 /* work and pm_iir are protected by dev_priv->irq_lock */
820 struct work_struct work
;
823 /* On vlv we need to manually drop to Vmin with a delayed work. */
824 struct delayed_work vlv_work
;
826 /* The below variables an all the rps hw state are protected by
827 * dev->struct mutext. */
834 struct delayed_work delayed_resume_work
;
837 * Protects RPS/RC6 register access and PCU communication.
838 * Must be taken after struct_mutex if nested.
840 struct mutex hw_lock
;
843 /* defined intel_pm.c */
844 extern spinlock_t mchdev_lock
;
846 struct intel_ilk_power_mgmt
{
854 unsigned long last_time1
;
855 unsigned long chipset_power
;
857 struct timespec last_time2
;
858 unsigned long gfx_power
;
864 struct drm_i915_gem_object
*pwrctx
;
865 struct drm_i915_gem_object
*renderctx
;
868 /* Power well structure for haswell */
869 struct i915_power_well
{
870 struct drm_device
*device
;
872 /* power well enable/disable usage count */
877 struct i915_dri1_state
{
878 unsigned allow_batchbuffer
: 1;
879 u32 __iomem
*gfx_hws_cpu_addr
;
890 struct i915_ums_state
{
892 * Flag if the X Server, and thus DRM, is not currently in
893 * control of the device.
895 * This is set between LeaveVT and EnterVT. It needs to be
896 * replaced with a semaphore. It also needs to be
897 * transitioned away from for kernel modesetting.
902 struct intel_l3_parity
{
904 struct work_struct error_work
;
908 /** Memory allocator for GTT stolen memory */
909 struct drm_mm stolen
;
910 /** List of all objects in gtt_space. Used to restore gtt
911 * mappings on resume */
912 struct list_head bound_list
;
914 * List of objects which are not bound to the GTT (thus
915 * are idle and not used by the GPU) but still have
916 * (presumably uncached) pages still attached.
918 struct list_head unbound_list
;
920 /** Usable portion of the GTT for GEM */
921 unsigned long stolen_base
; /* limited to low memory (32-bit) */
923 /** PPGTT used for aliasing the PPGTT with the GTT */
924 struct i915_hw_ppgtt
*aliasing_ppgtt
;
926 struct shrinker inactive_shrinker
;
927 bool shrinker_no_lock_stealing
;
929 /** LRU list of objects with fence regs on them. */
930 struct list_head fence_list
;
933 * We leave the user IRQ off as much as possible,
934 * but this means that requests will finish and never
935 * be retired once the system goes idle. Set a timer to
936 * fire periodically while the ring is running. When it
937 * fires, go retire requests.
939 struct delayed_work retire_work
;
942 * Are we in a non-interruptible section of code like
947 /** Bit 6 swizzling required for X tiling */
948 uint32_t bit_6_swizzle_x
;
949 /** Bit 6 swizzling required for Y tiling */
950 uint32_t bit_6_swizzle_y
;
952 /* storage for physical objects */
953 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
955 /* accounting, useful for userland debugging */
956 spinlock_t object_stat_lock
;
957 size_t object_memory
;
961 struct drm_i915_error_state_buf
{
970 struct i915_error_state_file_priv
{
971 struct drm_device
*dev
;
972 struct drm_i915_error_state
*error
;
975 struct i915_gpu_error
{
976 /* For hangcheck timer */
977 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
978 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
979 struct timer_list hangcheck_timer
;
981 /* For reset and error_state handling. */
983 /* Protected by the above dev->gpu_error.lock. */
984 struct drm_i915_error_state
*first_error
;
985 struct work_struct work
;
987 unsigned long last_reset
;
990 * State variable and reset counter controlling the reset flow
992 * Upper bits are for the reset counter. This counter is used by the
993 * wait_seqno code to race-free noticed that a reset event happened and
994 * that it needs to restart the entire ioctl (since most likely the
995 * seqno it waited for won't ever signal anytime soon).
997 * This is important for lock-free wait paths, where no contended lock
998 * naturally enforces the correct ordering between the bail-out of the
999 * waiter and the gpu reset work code.
1001 * Lowest bit controls the reset state machine: Set means a reset is in
1002 * progress. This state will (presuming we don't have any bugs) decay
1003 * into either unset (successful reset) or the special WEDGED value (hw
1004 * terminally sour). All waiters on the reset_queue will be woken when
1007 atomic_t reset_counter
;
1010 * Special values/flags for reset_counter
1012 * Note that the code relies on
1013 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1016 #define I915_RESET_IN_PROGRESS_FLAG 1
1017 #define I915_WEDGED 0xffffffff
1020 * Waitqueue to signal when the reset has completed. Used by clients
1021 * that wait for dev_priv->mm.wedged to settle.
1023 wait_queue_head_t reset_queue
;
1025 /* For gpu hang simulation. */
1026 unsigned int stop_rings
;
1029 enum modeset_restore
{
1030 MODESET_ON_LID_OPEN
,
1035 struct intel_vbt_data
{
1036 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1037 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1040 unsigned int int_tv_support
:1;
1041 unsigned int lvds_dither
:1;
1042 unsigned int lvds_vbt
:1;
1043 unsigned int int_crt_support
:1;
1044 unsigned int lvds_use_ssc
:1;
1045 unsigned int display_clock_mode
:1;
1046 unsigned int fdi_rx_polarity_inverted
:1;
1048 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1053 int edp_preemphasis
;
1055 bool edp_initialized
;
1058 struct edp_power_seq edp_pps
;
1063 struct child_device_config
*child_dev
;
1066 enum intel_ddb_partitioning
{
1068 INTEL_DDB_PART_5_6
, /* IVB+ */
1071 struct intel_wm_level
{
1079 typedef struct drm_i915_private
{
1080 struct drm_device
*dev
;
1081 struct kmem_cache
*slab
;
1083 const struct intel_device_info
*info
;
1085 int relative_constants_mode
;
1089 struct intel_uncore uncore
;
1091 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1094 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1095 * controller on different i2c buses. */
1096 struct mutex gmbus_mutex
;
1099 * Base address of the gmbus and gpio block.
1101 uint32_t gpio_mmio_base
;
1103 wait_queue_head_t gmbus_wait_queue
;
1105 struct pci_dev
*bridge_dev
;
1106 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1107 uint32_t last_seqno
, next_seqno
;
1109 drm_dma_handle_t
*status_page_dmah
;
1110 struct resource mch_res
;
1112 atomic_t irq_received
;
1114 /* protects the irq masks */
1115 spinlock_t irq_lock
;
1117 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1118 struct pm_qos_request pm_qos
;
1120 /* DPIO indirect register protection */
1121 struct mutex dpio_lock
;
1123 /** Cached value of IMR to avoid reads in updating the bitfield */
1127 struct work_struct hotplug_work
;
1128 bool enable_hotplug_processing
;
1130 unsigned long hpd_last_jiffies
;
1135 HPD_MARK_DISABLED
= 2
1137 } hpd_stats
[HPD_NUM_PINS
];
1139 struct timer_list hotplug_reenable_timer
;
1143 struct i915_fbc fbc
;
1144 struct intel_opregion opregion
;
1145 struct intel_vbt_data vbt
;
1148 struct intel_overlay
*overlay
;
1149 unsigned int sprite_scaling_enabled
;
1155 spinlock_t lock
; /* bl registers and the above bl fields */
1156 struct backlight_device
*device
;
1160 bool no_aux_handshake
;
1162 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1163 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1164 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1166 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1168 struct workqueue_struct
*wq
;
1170 /* Display functions */
1171 struct drm_i915_display_funcs display
;
1173 /* PCH chipset type */
1174 enum intel_pch pch_type
;
1175 unsigned short pch_id
;
1177 unsigned long quirks
;
1179 enum modeset_restore modeset_restore
;
1180 struct mutex modeset_restore_lock
;
1182 struct list_head vm_list
; /* Global list of all address spaces */
1183 struct i915_gtt gtt
; /* VMA representing the global address space */
1185 struct i915_gem_mm mm
;
1187 /* Kernel Modesetting */
1189 struct sdvo_device_mapping sdvo_mappings
[2];
1191 struct drm_crtc
*plane_to_crtc_mapping
[3];
1192 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1193 wait_queue_head_t pending_flip_queue
;
1195 int num_shared_dpll
;
1196 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1197 struct intel_ddi_plls ddi_plls
;
1199 /* Reclocking support */
1200 bool render_reclock_avail
;
1201 bool lvds_downclock_avail
;
1202 /* indicates the reduced downclock for LVDS*/
1206 bool mchbar_need_disable
;
1208 struct intel_l3_parity l3_parity
;
1210 /* Cannot be determined by PCIID. You must always read a register. */
1213 /* gen6+ rps state */
1214 struct intel_gen6_power_mgmt rps
;
1216 /* ilk-only ips/rps state. Everything in here is protected by the global
1217 * mchdev_lock in intel_pm.c */
1218 struct intel_ilk_power_mgmt ips
;
1220 /* Haswell power well */
1221 struct i915_power_well power_well
;
1223 enum no_psr_reason no_psr_reason
;
1225 struct i915_gpu_error gpu_error
;
1227 struct drm_i915_gem_object
*vlv_pctx
;
1229 /* list of fbdev register on this device */
1230 struct intel_fbdev
*fbdev
;
1233 * The console may be contended at resume, but we don't
1234 * want it to block on it.
1236 struct work_struct console_resume_work
;
1238 struct drm_property
*broadcast_rgb_property
;
1239 struct drm_property
*force_audio_property
;
1241 bool hw_contexts_disabled
;
1242 uint32_t hw_context_size
;
1246 struct i915_suspend_saved_registers regfile
;
1250 * Raw watermark latency values:
1251 * in 0.1us units for WM0,
1252 * in 0.5us units for WM1+.
1255 uint16_t pri_latency
[5];
1257 uint16_t spr_latency
[5];
1259 uint16_t cur_latency
[5];
1262 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1264 struct i915_dri1_state dri1
;
1265 /* Old ums support infrastructure, same warning applies. */
1266 struct i915_ums_state ums
;
1267 } drm_i915_private_t
;
1269 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1271 return dev
->dev_private
;
1274 /* Iterate over initialised rings */
1275 #define for_each_ring(ring__, dev_priv__, i__) \
1276 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1277 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1279 enum hdmi_force_audio
{
1280 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1281 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1282 HDMI_AUDIO_AUTO
, /* trust EDID */
1283 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1286 #define I915_GTT_OFFSET_NONE ((u32)-1)
1288 struct drm_i915_gem_object_ops
{
1289 /* Interface between the GEM object and its backing storage.
1290 * get_pages() is called once prior to the use of the associated set
1291 * of pages before to binding them into the GTT, and put_pages() is
1292 * called after we no longer need them. As we expect there to be
1293 * associated cost with migrating pages between the backing storage
1294 * and making them available for the GPU (e.g. clflush), we may hold
1295 * onto the pages after they are no longer referenced by the GPU
1296 * in case they may be used again shortly (for example migrating the
1297 * pages to a different memory domain within the GTT). put_pages()
1298 * will therefore most likely be called when the object itself is
1299 * being released or under memory pressure (where we attempt to
1300 * reap pages for the shrinker).
1302 int (*get_pages
)(struct drm_i915_gem_object
*);
1303 void (*put_pages
)(struct drm_i915_gem_object
*);
1306 struct drm_i915_gem_object
{
1307 struct drm_gem_object base
;
1309 const struct drm_i915_gem_object_ops
*ops
;
1311 /** List of VMAs backed by this object */
1312 struct list_head vma_list
;
1314 /** Stolen memory for this object, instead of being backed by shmem. */
1315 struct drm_mm_node
*stolen
;
1316 struct list_head global_list
;
1318 struct list_head ring_list
;
1319 /** Used in execbuf to temporarily hold a ref */
1320 struct list_head obj_exec_link
;
1321 /** This object's place in the batchbuffer or on the eviction list */
1322 struct list_head exec_list
;
1325 * This is set if the object is on the active lists (has pending
1326 * rendering and so a non-zero seqno), and is not set if it i s on
1327 * inactive (ready to be unbound) list.
1329 unsigned int active
:1;
1332 * This is set if the object has been written to since last bound
1335 unsigned int dirty
:1;
1338 * Fence register bits (if any) for this object. Will be set
1339 * as needed when mapped into the GTT.
1340 * Protected by dev->struct_mutex.
1342 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1345 * Advice: are the backing pages purgeable?
1347 unsigned int madv
:2;
1350 * Current tiling mode for the object.
1352 unsigned int tiling_mode
:2;
1354 * Whether the tiling parameters for the currently associated fence
1355 * register have changed. Note that for the purposes of tracking
1356 * tiling changes we also treat the unfenced register, the register
1357 * slot that the object occupies whilst it executes a fenced
1358 * command (such as BLT on gen2/3), as a "fence".
1360 unsigned int fence_dirty
:1;
1362 /** How many users have pinned this object in GTT space. The following
1363 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1364 * (via user_pin_count), execbuffer (objects are not allowed multiple
1365 * times for the same batchbuffer), and the framebuffer code. When
1366 * switching/pageflipping, the framebuffer code has at most two buffers
1369 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1370 * bits with absolutely no headroom. So use 4 bits. */
1371 unsigned int pin_count
:4;
1372 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1375 * Is the object at the current location in the gtt mappable and
1376 * fenceable? Used to avoid costly recalculations.
1378 unsigned int map_and_fenceable
:1;
1381 * Whether the current gtt mapping needs to be mappable (and isn't just
1382 * mappable by accident). Track pin and fault separate for a more
1383 * accurate mappable working set.
1385 unsigned int fault_mappable
:1;
1386 unsigned int pin_mappable
:1;
1387 unsigned int pin_display
:1;
1390 * Is the GPU currently using a fence to access this buffer,
1392 unsigned int pending_fenced_gpu_access
:1;
1393 unsigned int fenced_gpu_access
:1;
1395 unsigned int cache_level
:3;
1397 unsigned int has_aliasing_ppgtt_mapping
:1;
1398 unsigned int has_global_gtt_mapping
:1;
1399 unsigned int has_dma_mapping
:1;
1401 struct sg_table
*pages
;
1402 int pages_pin_count
;
1404 /* prime dma-buf support */
1405 void *dma_buf_vmapping
;
1409 * Used for performing relocations during execbuffer insertion.
1411 struct hlist_node exec_node
;
1412 unsigned long exec_handle
;
1413 struct drm_i915_gem_exec_object2
*exec_entry
;
1415 struct intel_ring_buffer
*ring
;
1417 /** Breadcrumb of last rendering to the buffer. */
1418 uint32_t last_read_seqno
;
1419 uint32_t last_write_seqno
;
1420 /** Breadcrumb of last fenced GPU access to the buffer. */
1421 uint32_t last_fenced_seqno
;
1423 /** Current tiling stride for the object, if it's tiled. */
1426 /** Record of address bit 17 of each page at last unbind. */
1427 unsigned long *bit_17
;
1429 /** User space pin count and filp owning the pin */
1430 uint32_t user_pin_count
;
1431 struct drm_file
*pin_filp
;
1433 /** for phy allocated objects */
1434 struct drm_i915_gem_phys_object
*phys_obj
;
1436 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1438 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1441 * Request queue structure.
1443 * The request queue allows us to note sequence numbers that have been emitted
1444 * and may be associated with active buffers to be retired.
1446 * By keeping this list, we can avoid having to do questionable
1447 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1448 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1450 struct drm_i915_gem_request
{
1451 /** On Which ring this request was generated */
1452 struct intel_ring_buffer
*ring
;
1454 /** GEM sequence number associated with this request. */
1457 /** Position in the ringbuffer of the start of the request */
1460 /** Position in the ringbuffer of the end of the request */
1463 /** Context related to this request */
1464 struct i915_hw_context
*ctx
;
1466 /** Batch buffer related to this request if any */
1467 struct drm_i915_gem_object
*batch_obj
;
1469 /** Time at which this request was emitted, in jiffies. */
1470 unsigned long emitted_jiffies
;
1472 /** global list entry for this request */
1473 struct list_head list
;
1475 struct drm_i915_file_private
*file_priv
;
1476 /** file_priv list entry for this request */
1477 struct list_head client_list
;
1480 struct drm_i915_file_private
{
1483 struct list_head request_list
;
1485 struct idr context_idr
;
1487 struct i915_ctx_hang_stats hang_stats
;
1490 #define INTEL_INFO(dev) (to_i915(dev)->info)
1492 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1493 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1494 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1495 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1496 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1497 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1498 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1499 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1500 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1501 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1502 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1503 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1504 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1505 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1506 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1507 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1508 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1509 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1510 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1511 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1512 (dev)->pci_device == 0x0152 || \
1513 (dev)->pci_device == 0x015a)
1514 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1515 (dev)->pci_device == 0x0106 || \
1516 (dev)->pci_device == 0x010A)
1517 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1518 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1519 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1520 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1521 ((dev)->pci_device & 0xFF00) == 0x0C00)
1522 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1523 ((dev)->pci_device & 0xFF00) == 0x0A00)
1526 * The genX designation typically refers to the render engine, so render
1527 * capability related checks should use IS_GEN, while display and other checks
1528 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1531 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1532 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1533 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1534 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1535 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1536 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1538 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1539 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1540 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1541 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1542 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1543 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1545 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1546 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1548 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1549 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1551 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1552 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1554 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1555 * rows, which changed the alignment requirements and fence programming.
1557 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1559 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1560 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1561 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1562 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1563 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1564 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1565 /* dsparb controlled by hw only */
1566 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1568 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1569 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1570 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1572 #define HAS_IPS(dev) (IS_ULT(dev))
1574 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1576 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1577 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1578 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1580 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1581 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1582 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1583 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1584 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1585 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1587 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1588 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1589 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1590 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1591 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1592 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1594 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1596 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1598 #define GT_FREQUENCY_MULTIPLIER 50
1600 #include "i915_trace.h"
1603 * RC6 is a special power stage which allows the GPU to enter an very
1604 * low-voltage mode when idle, using down to 0V while at this stage. This
1605 * stage is entered automatically when the GPU is idle when RC6 support is
1606 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1608 * There are different RC6 modes available in Intel GPU, which differentiate
1609 * among each other with the latency required to enter and leave RC6 and
1610 * voltage consumed by the GPU in different states.
1612 * The combination of the following flags define which states GPU is allowed
1613 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1614 * RC6pp is deepest RC6. Their support by hardware varies according to the
1615 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1616 * which brings the most power savings; deeper states save more power, but
1617 * require higher latency to switch to and wake up.
1619 #define INTEL_RC6_ENABLE (1<<0)
1620 #define INTEL_RC6p_ENABLE (1<<1)
1621 #define INTEL_RC6pp_ENABLE (1<<2)
1623 extern struct drm_ioctl_desc i915_ioctls
[];
1624 extern int i915_max_ioctl
;
1625 extern unsigned int i915_fbpercrtc __always_unused
;
1626 extern int i915_panel_ignore_lid __read_mostly
;
1627 extern unsigned int i915_powersave __read_mostly
;
1628 extern int i915_semaphores __read_mostly
;
1629 extern unsigned int i915_lvds_downclock __read_mostly
;
1630 extern int i915_lvds_channel_mode __read_mostly
;
1631 extern int i915_panel_use_ssc __read_mostly
;
1632 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1633 extern int i915_enable_rc6 __read_mostly
;
1634 extern int i915_enable_fbc __read_mostly
;
1635 extern bool i915_enable_hangcheck __read_mostly
;
1636 extern int i915_enable_ppgtt __read_mostly
;
1637 extern int i915_enable_psr __read_mostly
;
1638 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1639 extern int i915_disable_power_well __read_mostly
;
1640 extern int i915_enable_ips __read_mostly
;
1641 extern bool i915_fastboot __read_mostly
;
1642 extern bool i915_prefault_disable __read_mostly
;
1644 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1645 extern int i915_resume(struct drm_device
*dev
);
1646 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1647 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1650 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1651 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1652 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1653 extern int i915_driver_unload(struct drm_device
*);
1654 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1655 extern void i915_driver_lastclose(struct drm_device
* dev
);
1656 extern void i915_driver_preclose(struct drm_device
*dev
,
1657 struct drm_file
*file_priv
);
1658 extern void i915_driver_postclose(struct drm_device
*dev
,
1659 struct drm_file
*file_priv
);
1660 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1661 #ifdef CONFIG_COMPAT
1662 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1665 extern int i915_emit_box(struct drm_device
*dev
,
1666 struct drm_clip_rect
*box
,
1668 extern int intel_gpu_reset(struct drm_device
*dev
);
1669 extern int i915_reset(struct drm_device
*dev
);
1670 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1671 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1672 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1673 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1675 extern void intel_console_resume(struct work_struct
*work
);
1678 void i915_queue_hangcheck(struct drm_device
*dev
);
1679 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1681 extern void intel_irq_init(struct drm_device
*dev
);
1682 extern void intel_hpd_init(struct drm_device
*dev
);
1683 extern void intel_pm_init(struct drm_device
*dev
);
1685 extern void intel_uncore_sanitize(struct drm_device
*dev
);
1686 extern void intel_uncore_early_sanitize(struct drm_device
*dev
);
1687 extern void intel_uncore_init(struct drm_device
*dev
);
1688 extern void intel_uncore_clear_errors(struct drm_device
*dev
);
1689 extern void intel_uncore_check_errors(struct drm_device
*dev
);
1692 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1695 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1698 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1699 struct drm_file
*file_priv
);
1700 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1701 struct drm_file
*file_priv
);
1702 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1703 struct drm_file
*file_priv
);
1704 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1705 struct drm_file
*file_priv
);
1706 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1707 struct drm_file
*file_priv
);
1708 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1709 struct drm_file
*file_priv
);
1710 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1711 struct drm_file
*file_priv
);
1712 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1713 struct drm_file
*file_priv
);
1714 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1715 struct drm_file
*file_priv
);
1716 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1717 struct drm_file
*file_priv
);
1718 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1719 struct drm_file
*file_priv
);
1720 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1721 struct drm_file
*file_priv
);
1722 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1723 struct drm_file
*file_priv
);
1724 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1725 struct drm_file
*file
);
1726 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1727 struct drm_file
*file
);
1728 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1729 struct drm_file
*file_priv
);
1730 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1731 struct drm_file
*file_priv
);
1732 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1733 struct drm_file
*file_priv
);
1734 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1735 struct drm_file
*file_priv
);
1736 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1737 struct drm_file
*file_priv
);
1738 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1739 struct drm_file
*file_priv
);
1740 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1741 struct drm_file
*file_priv
);
1742 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1743 struct drm_file
*file_priv
);
1744 void i915_gem_load(struct drm_device
*dev
);
1745 void *i915_gem_object_alloc(struct drm_device
*dev
);
1746 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1747 int i915_gem_init_object(struct drm_gem_object
*obj
);
1748 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1749 const struct drm_i915_gem_object_ops
*ops
);
1750 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1752 void i915_gem_free_object(struct drm_gem_object
*obj
);
1753 struct i915_vma
*i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
1754 struct i915_address_space
*vm
);
1755 void i915_gem_vma_destroy(struct i915_vma
*vma
);
1757 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1758 struct i915_address_space
*vm
,
1760 bool map_and_fenceable
,
1762 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1763 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
1764 int __must_check
i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
);
1765 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1766 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1767 void i915_gem_lastclose(struct drm_device
*dev
);
1769 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1770 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1772 struct sg_page_iter sg_iter
;
1774 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1775 return sg_page_iter_page(&sg_iter
);
1779 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1781 BUG_ON(obj
->pages
== NULL
);
1782 obj
->pages_pin_count
++;
1784 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1786 BUG_ON(obj
->pages_pin_count
== 0);
1787 obj
->pages_pin_count
--;
1790 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1791 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1792 struct intel_ring_buffer
*to
);
1793 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1794 struct intel_ring_buffer
*ring
);
1796 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1797 struct drm_device
*dev
,
1798 struct drm_mode_create_dumb
*args
);
1799 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1800 uint32_t handle
, uint64_t *offset
);
1801 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1804 * Returns true if seq1 is later than seq2.
1807 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1809 return (int32_t)(seq1
- seq2
) >= 0;
1812 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1813 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1814 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1815 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1818 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1820 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1821 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1822 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1829 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1831 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1832 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1833 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
1834 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1838 void i915_gem_retire_requests(struct drm_device
*dev
);
1839 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1840 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1841 bool interruptible
);
1842 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1844 return unlikely(atomic_read(&error
->reset_counter
)
1845 & I915_RESET_IN_PROGRESS_FLAG
);
1848 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1850 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1853 void i915_gem_reset(struct drm_device
*dev
);
1854 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
1855 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1856 int __must_check
i915_gem_init(struct drm_device
*dev
);
1857 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1858 void i915_gem_l3_remap(struct drm_device
*dev
);
1859 void i915_gem_init_swizzling(struct drm_device
*dev
);
1860 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1861 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1862 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1863 int __i915_add_request(struct intel_ring_buffer
*ring
,
1864 struct drm_file
*file
,
1865 struct drm_i915_gem_object
*batch_obj
,
1867 #define i915_add_request(ring, seqno) \
1868 __i915_add_request(ring, NULL, NULL, seqno)
1869 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1871 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1873 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1876 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1878 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1880 struct intel_ring_buffer
*pipelined
);
1881 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
1882 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1883 struct drm_i915_gem_object
*obj
,
1886 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1887 struct drm_i915_gem_object
*obj
);
1888 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1889 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1892 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
1894 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1895 int tiling_mode
, bool fenced
);
1897 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1898 enum i915_cache_level cache_level
);
1900 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1901 struct dma_buf
*dma_buf
);
1903 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1904 struct drm_gem_object
*gem_obj
, int flags
);
1906 void i915_gem_restore_fences(struct drm_device
*dev
);
1908 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
1909 struct i915_address_space
*vm
);
1910 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
1911 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
1912 struct i915_address_space
*vm
);
1913 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
1914 struct i915_address_space
*vm
);
1915 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
1916 struct i915_address_space
*vm
);
1917 /* Some GGTT VM helpers */
1918 #define obj_to_ggtt(obj) \
1919 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
1920 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
1922 struct i915_address_space
*ggtt
=
1923 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
1927 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
1929 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
1932 static inline unsigned long
1933 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
1935 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
1938 static inline unsigned long
1939 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
1941 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
1944 static inline int __must_check
1945 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
1947 bool map_and_fenceable
,
1950 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
,
1951 map_and_fenceable
, nonblocking
);
1955 /* i915_gem_context.c */
1956 void i915_gem_context_init(struct drm_device
*dev
);
1957 void i915_gem_context_fini(struct drm_device
*dev
);
1958 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1959 int i915_switch_context(struct intel_ring_buffer
*ring
,
1960 struct drm_file
*file
, int to_id
);
1961 void i915_gem_context_free(struct kref
*ctx_ref
);
1962 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
1964 kref_get(&ctx
->ref
);
1967 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
1969 kref_put(&ctx
->ref
, i915_gem_context_free
);
1972 struct i915_ctx_hang_stats
* __must_check
1973 i915_gem_context_get_hang_stats(struct drm_device
*dev
,
1974 struct drm_file
*file
,
1976 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1977 struct drm_file
*file
);
1978 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1979 struct drm_file
*file
);
1981 /* i915_gem_gtt.c */
1982 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1983 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1984 struct drm_i915_gem_object
*obj
,
1985 enum i915_cache_level cache_level
);
1986 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1987 struct drm_i915_gem_object
*obj
);
1989 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1990 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1991 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1992 enum i915_cache_level cache_level
);
1993 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1994 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1995 void i915_gem_init_global_gtt(struct drm_device
*dev
);
1996 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
1997 unsigned long mappable_end
, unsigned long end
);
1998 int i915_gem_gtt_init(struct drm_device
*dev
);
1999 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2001 if (INTEL_INFO(dev
)->gen
< 6)
2002 intel_gtt_chipset_flush();
2006 /* i915_gem_evict.c */
2007 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2008 struct i915_address_space
*vm
,
2011 unsigned cache_level
,
2014 int i915_gem_evict_everything(struct drm_device
*dev
);
2016 /* i915_gem_stolen.c */
2017 int i915_gem_init_stolen(struct drm_device
*dev
);
2018 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
2019 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2020 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2021 struct drm_i915_gem_object
*
2022 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2023 struct drm_i915_gem_object
*
2024 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2028 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
2030 /* i915_gem_tiling.c */
2031 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2033 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2035 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2036 obj
->tiling_mode
!= I915_TILING_NONE
;
2039 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2040 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2041 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2043 /* i915_gem_debug.c */
2045 int i915_verify_lists(struct drm_device
*dev
);
2047 #define i915_verify_lists(dev) 0
2050 /* i915_debugfs.c */
2051 int i915_debugfs_init(struct drm_minor
*minor
);
2052 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2054 /* i915_gpu_error.c */
2056 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2057 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2058 const struct i915_error_state_file_priv
*error
);
2059 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2060 size_t count
, loff_t pos
);
2061 static inline void i915_error_state_buf_release(
2062 struct drm_i915_error_state_buf
*eb
)
2066 void i915_capture_error_state(struct drm_device
*dev
);
2067 void i915_error_state_get(struct drm_device
*dev
,
2068 struct i915_error_state_file_priv
*error_priv
);
2069 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2070 void i915_destroy_error_state(struct drm_device
*dev
);
2072 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2073 const char *i915_cache_level_str(int type
);
2075 /* i915_suspend.c */
2076 extern int i915_save_state(struct drm_device
*dev
);
2077 extern int i915_restore_state(struct drm_device
*dev
);
2080 void i915_save_display_reg(struct drm_device
*dev
);
2081 void i915_restore_display_reg(struct drm_device
*dev
);
2084 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2085 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2088 extern int intel_setup_gmbus(struct drm_device
*dev
);
2089 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2090 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2092 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2095 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2096 struct drm_i915_private
*dev_priv
, unsigned port
);
2097 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2098 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2099 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2101 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2103 extern void intel_i2c_reset(struct drm_device
*dev
);
2105 /* intel_opregion.c */
2106 extern int intel_opregion_setup(struct drm_device
*dev
);
2108 extern void intel_opregion_init(struct drm_device
*dev
);
2109 extern void intel_opregion_fini(struct drm_device
*dev
);
2110 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2112 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2113 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2114 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2119 extern void intel_register_dsm_handler(void);
2120 extern void intel_unregister_dsm_handler(void);
2122 static inline void intel_register_dsm_handler(void) { return; }
2123 static inline void intel_unregister_dsm_handler(void) { return; }
2124 #endif /* CONFIG_ACPI */
2127 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2128 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2129 extern void intel_modeset_init(struct drm_device
*dev
);
2130 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2131 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2132 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2133 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2134 bool force_restore
);
2135 extern void i915_redisable_vga(struct drm_device
*dev
);
2136 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2137 extern void intel_disable_fbc(struct drm_device
*dev
);
2138 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2139 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2140 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2141 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2142 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2143 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2144 extern void intel_detect_pch(struct drm_device
*dev
);
2145 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2146 extern int intel_enable_rc6(const struct drm_device
*dev
);
2148 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2149 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2150 struct drm_file
*file
);
2153 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2154 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2155 struct intel_overlay_error_state
*error
);
2157 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2158 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2159 struct drm_device
*dev
,
2160 struct intel_display_error_state
*error
);
2162 /* On SNB platform, before reading ring registers forcewake bit
2163 * must be set to prevent GT core from power down and stale values being
2166 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
2167 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
2169 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2170 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2172 /* intel_sideband.c */
2173 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2174 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2175 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2176 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, int reg
);
2177 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, int reg
, u32 val
);
2178 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2179 enum intel_sbi_destination destination
);
2180 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2181 enum intel_sbi_destination destination
);
2183 int vlv_gpu_freq(int ddr_freq
, int val
);
2184 int vlv_freq_opcode(int ddr_freq
, int val
);
2186 #define __i915_read(x) \
2187 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
2194 #define __i915_write(x) \
2195 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace);
2202 #define I915_READ8(reg) i915_read8(dev_priv, (reg), true)
2203 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true)
2205 #define I915_READ16(reg) i915_read16(dev_priv, (reg), true)
2206 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true)
2207 #define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false)
2208 #define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false)
2210 #define I915_READ(reg) i915_read32(dev_priv, (reg), true)
2211 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true)
2212 #define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false)
2213 #define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false)
2215 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true)
2216 #define I915_READ64(reg) i915_read64(dev_priv, (reg), true)
2218 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2219 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2221 /* "Broadcast RGB" property */
2222 #define INTEL_BROADCAST_RGB_AUTO 0
2223 #define INTEL_BROADCAST_RGB_FULL 1
2224 #define INTEL_BROADCAST_RGB_LIMITED 2
2226 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2228 if (HAS_PCH_SPLIT(dev
))
2229 return CPU_VGACNTRL
;
2230 else if (IS_VALLEYVIEW(dev
))
2231 return VLV_VGACNTRL
;
2236 static inline void __user
*to_user_ptr(u64 address
)
2238 return (void __user
*)(uintptr_t)address
;
2241 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2243 unsigned long j
= msecs_to_jiffies(m
);
2245 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2248 static inline unsigned long
2249 timespec_to_jiffies_timeout(const struct timespec
*value
)
2251 unsigned long j
= timespec_to_jiffies(value
);
2253 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);