drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include <uapi/drm/i915_drm.h>
  34
  35 #include "i915_reg.h"
  36 #include "intel_bios.h"
  37 #include "intel_ringbuffer.h"
  38 #include "i915_gem_gtt.h"
  39 #include <linux/io-mapping.h>
  40 #include <linux/i2c.h>
  41 #include <linux/i2c-algo-bit.h>
  42 #include <drm/intel-gtt.h>
  43 #include <linux/backlight.h>
  44 #include <linux/hashtable.h>
  45 #include <linux/intel-iommu.h>
  46 #include <linux/kref.h>
  47 #include <linux/pm_qos.h>
  48
  49 /* General customization:
  50  */
  51
  52 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  53
  54 #define DRIVER_NAME             "i915"
  55 #define DRIVER_DESC             "Intel Graphics"
  56 #define DRIVER_DATE             "20080730"
  57
  58 enum pipe {
  59         INVALID_PIPE = -1,
  60         PIPE_A = 0,
  61         PIPE_B,
  62         PIPE_C,
  63         _PIPE_EDP,
  64         I915_MAX_PIPES = _PIPE_EDP
  65 };
  66 #define pipe_name(p) ((p) + 'A')
  67
  68 enum transcoder {
  69         TRANSCODER_A = 0,
  70         TRANSCODER_B,
  71         TRANSCODER_C,
  72         TRANSCODER_EDP,
  73         I915_MAX_TRANSCODERS
  74 };
  75 #define transcoder_name(t) ((t) + 'A')
  76
  77 enum plane {
  78         PLANE_A = 0,
  79         PLANE_B,
  80         PLANE_C,
  81 };
  82 #define plane_name(p) ((p) + 'A')
  83
  84 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
  85
  86 enum port {
  87         PORT_A = 0,
  88         PORT_B,
  89         PORT_C,
  90         PORT_D,
  91         PORT_E,
  92         I915_MAX_PORTS
  93 };
  94 #define port_name(p) ((p) + 'A')
  95
  96 #define I915_NUM_PHYS_VLV 2
  97
  98 enum dpio_channel {
  99         DPIO_CH0,
 100         DPIO_CH1
 101 };
 102
 103 enum dpio_phy {
 104         DPIO_PHY0,
 105         DPIO_PHY1
 106 };
 107
 108 enum intel_display_power_domain {
 109         POWER_DOMAIN_PIPE_A,
 110         POWER_DOMAIN_PIPE_B,
 111         POWER_DOMAIN_PIPE_C,
 112         POWER_DOMAIN_PIPE_A_PANEL_FITTER,
 113         POWER_DOMAIN_PIPE_B_PANEL_FITTER,
 114         POWER_DOMAIN_PIPE_C_PANEL_FITTER,
 115         POWER_DOMAIN_TRANSCODER_A,
 116         POWER_DOMAIN_TRANSCODER_B,
 117         POWER_DOMAIN_TRANSCODER_C,
 118         POWER_DOMAIN_TRANSCODER_EDP,
 119         POWER_DOMAIN_PORT_DDI_A_2_LANES,
 120         POWER_DOMAIN_PORT_DDI_A_4_LANES,
 121         POWER_DOMAIN_PORT_DDI_B_2_LANES,
 122         POWER_DOMAIN_PORT_DDI_B_4_LANES,
 123         POWER_DOMAIN_PORT_DDI_C_2_LANES,
 124         POWER_DOMAIN_PORT_DDI_C_4_LANES,
 125         POWER_DOMAIN_PORT_DDI_D_2_LANES,
 126         POWER_DOMAIN_PORT_DDI_D_4_LANES,
 127         POWER_DOMAIN_PORT_DSI,
 128         POWER_DOMAIN_PORT_CRT,
 129         POWER_DOMAIN_PORT_OTHER,
 130         POWER_DOMAIN_VGA,
 131         POWER_DOMAIN_AUDIO,
 132         POWER_DOMAIN_INIT,
 133
 134         POWER_DOMAIN_NUM,
 135 };
 136
 137 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 138 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 139                 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
 140 #define POWER_DOMAIN_TRANSCODER(tran) \
 141         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 142          (tran) + POWER_DOMAIN_TRANSCODER_A)
 143
 144 enum hpd_pin {
 145         HPD_NONE = 0,
 146         HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
 147         HPD_TV = HPD_NONE,     /* TV is known to be unreliable */
 148         HPD_CRT,
 149         HPD_SDVO_B,
 150         HPD_SDVO_C,
 151         HPD_PORT_B,
 152         HPD_PORT_C,
 153         HPD_PORT_D,
 154         HPD_NUM_PINS
 155 };
 156
 157 #define I915_GEM_GPU_DOMAINS \
 158         (I915_GEM_DOMAIN_RENDER | \
 159          I915_GEM_DOMAIN_SAMPLER | \
 160          I915_GEM_DOMAIN_COMMAND | \
 161          I915_GEM_DOMAIN_INSTRUCTION | \
 162          I915_GEM_DOMAIN_VERTEX)
 163
 164 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
 165 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
 166
 167 #define for_each_crtc(dev, crtc) \
 168         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
 169
 170 #define for_each_intel_crtc(dev, intel_crtc) \
 171         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
 172
 173 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
 174         list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
 175                 if ((intel_encoder)->base.crtc == (__crtc))
 176
 177 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
 178         list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
 179                 if ((intel_connector)->base.encoder == (__encoder))
 180
 181 struct drm_i915_private;
 182 struct i915_mmu_object;
 183
 184 enum intel_dpll_id {
 185         DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
 186         /* real shared dpll ids must be >= 0 */
 187         DPLL_ID_PCH_PLL_A,
 188         DPLL_ID_PCH_PLL_B,
 189 };
 190 #define I915_NUM_PLLS 2
 191
 192 struct intel_dpll_hw_state {
 193         uint32_t dpll;
 194         uint32_t dpll_md;
 195         uint32_t fp0;
 196         uint32_t fp1;
 197 };
 198
 199 struct intel_shared_dpll {
 200         int refcount; /* count of number of CRTCs sharing this PLL */
 201         int active; /* count of number of active CRTCs (i.e. DPMS on) */
 202         bool on; /* is the PLL actually active? Disabled during modeset */
 203         const char *name;
 204         /* should match the index in the dev_priv->shared_dplls array */
 205         enum intel_dpll_id id;
 206         struct intel_dpll_hw_state hw_state;
 207         void (*mode_set)(struct drm_i915_private *dev_priv,
 208                          struct intel_shared_dpll *pll);
 209         void (*enable)(struct drm_i915_private *dev_priv,
 210                        struct intel_shared_dpll *pll);
 211         void (*disable)(struct drm_i915_private *dev_priv,
 212                         struct intel_shared_dpll *pll);
 213         bool (*get_hw_state)(struct drm_i915_private *dev_priv,
 214                              struct intel_shared_dpll *pll,
 215                              struct intel_dpll_hw_state *hw_state);
 216 };
 217
 218 /* Used by dp and fdi links */
 219 struct intel_link_m_n {
 220         uint32_t        tu;
 221         uint32_t        gmch_m;
 222         uint32_t        gmch_n;
 223         uint32_t        link_m;
 224         uint32_t        link_n;
 225 };
 226
 227 void intel_link_compute_m_n(int bpp, int nlanes,
 228                             int pixel_clock, int link_clock,
 229                             struct intel_link_m_n *m_n);
 230
 231 struct intel_ddi_plls {
 232         int spll_refcount;
 233         int wrpll1_refcount;
 234         int wrpll2_refcount;
 235 };
 236
 237 /* Interface history:
 238  *
 239  * 1.1: Original.
 240  * 1.2: Add Power Management
 241  * 1.3: Add vblank support
 242  * 1.4: Fix cmdbuffer path, add heap destroy
 243  * 1.5: Add vblank pipe configuration
 244  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
 245  *      - Support vertical blank on secondary display pipe
 246  */
 247 #define DRIVER_MAJOR            1
 248 #define DRIVER_MINOR            6
 249 #define DRIVER_PATCHLEVEL       0
 250
 251 #define WATCH_LISTS     0
 252 #define WATCH_GTT       0
 253
 254 #define I915_GEM_PHYS_CURSOR_0 1
 255 #define I915_GEM_PHYS_CURSOR_1 2
 256 #define I915_GEM_PHYS_OVERLAY_REGS 3
 257 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
 258
 259 struct drm_i915_gem_phys_object {
 260         int id;
 261         struct page **page_list;
 262         drm_dma_handle_t *handle;
 263         struct drm_i915_gem_object *cur_obj;
 264 };
 265
 266 struct opregion_header;
 267 struct opregion_acpi;
 268 struct opregion_swsci;
 269 struct opregion_asle;
 270
 271 struct intel_opregion {
 272         struct opregion_header __iomem *header;
 273         struct opregion_acpi __iomem *acpi;
 274         struct opregion_swsci __iomem *swsci;
 275         u32 swsci_gbda_sub_functions;
 276         u32 swsci_sbcb_sub_functions;
 277         struct opregion_asle __iomem *asle;
 278         void __iomem *vbt;
 279         u32 __iomem *lid_state;
 280         struct work_struct asle_work;
 281 };
 282 #define OPREGION_SIZE            (8*1024)
 283
 284 struct intel_overlay;
 285 struct intel_overlay_error_state;
 286
 287 struct drm_i915_master_private {
 288         drm_local_map_t *sarea;
 289         struct _drm_i915_sarea *sarea_priv;
 290 };
 291 #define I915_FENCE_REG_NONE -1
 292 #define I915_MAX_NUM_FENCES 32
 293 /* 32 fences + sign bit for FENCE_REG_NONE */
 294 #define I915_MAX_NUM_FENCE_BITS 6
 295
 296 struct drm_i915_fence_reg {
 297         struct list_head lru_list;
 298         struct drm_i915_gem_object *obj;
 299         int pin_count;
 300 };
 301
 302 struct sdvo_device_mapping {
 303         u8 initialized;
 304         u8 dvo_port;
 305         u8 slave_addr;
 306         u8 dvo_wiring;
 307         u8 i2c_pin;
 308         u8 ddc_pin;
 309 };
 310
 311 struct intel_display_error_state;
 312
 313 struct drm_i915_error_state {
 314         struct kref ref;
 315         struct timeval time;
 316
 317         char error_msg[128];
 318         u32 reset_count;
 319         u32 suspend_count;
 320
 321         /* Generic register state */
 322         u32 eir;
 323         u32 pgtbl_er;
 324         u32 ier;
 325         u32 ccid;
 326         u32 derrmr;
 327         u32 forcewake;
 328         u32 error; /* gen6+ */
 329         u32 err_int; /* gen7 */
 330         u32 done_reg;
 331         u32 gac_eco;
 332         u32 gam_ecochk;
 333         u32 gab_ctl;
 334         u32 gfx_mode;
 335         u32 extra_instdone[I915_NUM_INSTDONE_REG];
 336         u64 fence[I915_MAX_NUM_FENCES];
 337         struct intel_overlay_error_state *overlay;
 338         struct intel_display_error_state *display;
 339
 340         struct drm_i915_error_ring {
 341                 bool valid;
 342                 /* Software tracked state */
 343                 bool waiting;
 344                 int hangcheck_score;
 345                 enum intel_ring_hangcheck_action hangcheck_action;
 346                 int num_requests;
 347
 348                 /* our own tracking of ring head and tail */
 349                 u32 cpu_ring_head;
 350                 u32 cpu_ring_tail;
 351
 352                 u32 semaphore_seqno[I915_NUM_RINGS - 1];
 353
 354                 /* Register state */
 355                 u32 tail;
 356                 u32 head;
 357                 u32 ctl;
 358                 u32 hws;
 359                 u32 ipeir;
 360                 u32 ipehr;
 361                 u32 instdone;
 362                 u32 bbstate;
 363                 u32 instpm;
 364                 u32 instps;
 365                 u32 seqno;
 366                 u64 bbaddr;
 367                 u64 acthd;
 368                 u32 fault_reg;
 369                 u64 faddr;
 370                 u32 rc_psmi; /* sleep state */
 371                 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
 372
 373                 struct drm_i915_error_object {
 374                         int page_count;
 375                         u32 gtt_offset;
 376                         u32 *pages[0];
 377                 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
 378
 379                 struct drm_i915_error_request {
 380                         long jiffies;
 381                         u32 seqno;
 382                         u32 tail;
 383                 } *requests;
 384
 385                 struct {
 386                         u32 gfx_mode;
 387                         union {
 388                                 u64 pdp[4];
 389                                 u32 pp_dir_base;
 390                         };
 391                 } vm_info;
 392
 393                 pid_t pid;
 394                 char comm[TASK_COMM_LEN];
 395         } ring[I915_NUM_RINGS];
 396         struct drm_i915_error_buffer {
 397                 u32 size;
 398                 u32 name;
 399                 u32 rseqno, wseqno;
 400                 u32 gtt_offset;
 401                 u32 read_domains;
 402                 u32 write_domain;
 403                 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
 404                 s32 pinned:2;
 405                 u32 tiling:2;
 406                 u32 dirty:1;
 407                 u32 purgeable:1;
 408                 u32 userptr:1;
 409                 s32 ring:4;
 410                 u32 cache_level:3;
 411         } **active_bo, **pinned_bo;
 412
 413         u32 *active_bo_count, *pinned_bo_count;
 414 };
 415
 416 struct intel_connector;
 417 struct intel_crtc_config;
 418 struct intel_plane_config;
 419 struct intel_crtc;
 420 struct intel_limit;
 421 struct dpll;
 422
 423 struct drm_i915_display_funcs {
 424         bool (*fbc_enabled)(struct drm_device *dev);
 425         void (*enable_fbc)(struct drm_crtc *crtc);
 426         void (*disable_fbc)(struct drm_device *dev);
 427         int (*get_display_clock_speed)(struct drm_device *dev);
 428         int (*get_fifo_size)(struct drm_device *dev, int plane);
 429         /**
 430          * find_dpll() - Find the best values for the PLL
 431          * @limit: limits for the PLL
 432          * @crtc: current CRTC
 433          * @target: target frequency in kHz
 434          * @refclk: reference clock frequency in kHz
 435          * @match_clock: if provided, @best_clock P divider must
 436          *               match the P divider from @match_clock
 437          *               used for LVDS downclocking
 438          * @best_clock: best PLL values found
 439          *
 440          * Returns true on success, false on failure.
 441          */
 442         bool (*find_dpll)(const struct intel_limit *limit,
 443                           struct drm_crtc *crtc,
 444                           int target, int refclk,
 445                           struct dpll *match_clock,
 446                           struct dpll *best_clock);
 447         void (*update_wm)(struct drm_crtc *crtc);
 448         void (*update_sprite_wm)(struct drm_plane *plane,
 449                                  struct drm_crtc *crtc,
 450                                  uint32_t sprite_width, int pixel_size,
 451                                  bool enable, bool scaled);
 452         void (*modeset_global_resources)(struct drm_device *dev);
 453         /* Returns the active state of the crtc, and if the crtc is active,
 454          * fills out the pipe-config with the hw state. */
 455         bool (*get_pipe_config)(struct intel_crtc *,
 456                                 struct intel_crtc_config *);
 457         void (*get_plane_config)(struct intel_crtc *,
 458                                  struct intel_plane_config *);
 459         int (*crtc_mode_set)(struct drm_crtc *crtc,
 460                              int x, int y,
 461                              struct drm_framebuffer *old_fb);
 462         void (*crtc_enable)(struct drm_crtc *crtc);
 463         void (*crtc_disable)(struct drm_crtc *crtc);
 464         void (*off)(struct drm_crtc *crtc);
 465         void (*write_eld)(struct drm_connector *connector,
 466                           struct drm_crtc *crtc,
 467                           struct drm_display_mode *mode);
 468         void (*fdi_link_train)(struct drm_crtc *crtc);
 469         void (*init_clock_gating)(struct drm_device *dev);
 470         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 471                           struct drm_framebuffer *fb,
 472                           struct drm_i915_gem_object *obj,
 473                           struct intel_ring_buffer *ring,
 474                           uint32_t flags);
 475         void (*update_primary_plane)(struct drm_crtc *crtc,
 476                                      struct drm_framebuffer *fb,
 477                                      int x, int y);
 478         void (*hpd_irq_setup)(struct drm_device *dev);
 479         /* clock updates for mode set */
 480         /* cursor updates */
 481         /* render clock increase/decrease */
 482         /* display clock increase/decrease */
 483         /* pll clock increase/decrease */
 484
 485         int (*setup_backlight)(struct intel_connector *connector);
 486         uint32_t (*get_backlight)(struct intel_connector *connector);
 487         void (*set_backlight)(struct intel_connector *connector,
 488                               uint32_t level);
 489         void (*disable_backlight)(struct intel_connector *connector);
 490         void (*enable_backlight)(struct intel_connector *connector);
 491 };
 492
 493 struct intel_uncore_funcs {
 494         void (*force_wake_get)(struct drm_i915_private *dev_priv,
 495                                                         int fw_engine);
 496         void (*force_wake_put)(struct drm_i915_private *dev_priv,
 497                                                         int fw_engine);
 498
 499         uint8_t  (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 500         uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 501         uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 502         uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
 503
 504         void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
 505                                 uint8_t val, bool trace);
 506         void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
 507                                 uint16_t val, bool trace);
 508         void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
 509                                 uint32_t val, bool trace);
 510         void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
 511                                 uint64_t val, bool trace);
 512 };
 513
 514 struct intel_uncore {
 515         spinlock_t lock; /** lock is also taken in irq contexts. */
 516
 517         struct intel_uncore_funcs funcs;
 518
 519         unsigned fifo_count;
 520         unsigned forcewake_count;
 521
 522         unsigned fw_rendercount;
 523         unsigned fw_mediacount;
 524
 525         struct timer_list force_wake_timer;
 526 };
 527
 528 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
 529         func(is_mobile) sep \
 530         func(is_i85x) sep \
 531         func(is_i915g) sep \
 532         func(is_i945gm) sep \
 533         func(is_g33) sep \
 534         func(need_gfx_hws) sep \
 535         func(is_g4x) sep \
 536         func(is_pineview) sep \
 537         func(is_broadwater) sep \
 538         func(is_crestline) sep \
 539         func(is_ivybridge) sep \
 540         func(is_valleyview) sep \
 541         func(is_haswell) sep \
 542         func(is_preliminary) sep \
 543         func(has_fbc) sep \
 544         func(has_pipe_cxsr) sep \
 545         func(has_hotplug) sep \
 546         func(cursor_needs_physical) sep \
 547         func(has_overlay) sep \
 548         func(overlay_needs_physical) sep \
 549         func(supports_tv) sep \
 550         func(has_llc) sep \
 551         func(has_ddi) sep \
 552         func(has_fpga_dbg)
 553
 554 #define DEFINE_FLAG(name) u8 name:1
 555 #define SEP_SEMICOLON ;
 556
 557 struct intel_device_info {
 558         u32 display_mmio_offset;
 559         u8 num_pipes:3;
 560         u8 num_sprites[I915_MAX_PIPES];
 561         u8 gen;
 562         u8 ring_mask; /* Rings supported by the HW */
 563         DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
 564         /* Register offsets for the various display pipes and transcoders */
 565         int pipe_offsets[I915_MAX_TRANSCODERS];
 566         int trans_offsets[I915_MAX_TRANSCODERS];
 567         int dpll_offsets[I915_MAX_PIPES];
 568         int dpll_md_offsets[I915_MAX_PIPES];
 569         int palette_offsets[I915_MAX_PIPES];
 570         int cursor_offsets[I915_MAX_PIPES];
 571 };
 572
 573 #undef DEFINE_FLAG
 574 #undef SEP_SEMICOLON
 575
 576 enum i915_cache_level {
 577         I915_CACHE_NONE = 0,
 578         I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
 579         I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
 580                               caches, eg sampler/render caches, and the
 581                               large Last-Level-Cache. LLC is coherent with
 582                               the CPU, but L3 is only visible to the GPU. */
 583         I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
 584 };
 585
 586 struct i915_ctx_hang_stats {
 587         /* This context had batch pending when hang was declared */
 588         unsigned batch_pending;
 589
 590         /* This context had batch active when hang was declared */
 591         unsigned batch_active;
 592
 593         /* Time when this context was last blamed for a GPU reset */
 594         unsigned long guilty_ts;
 595
 596         /* This context is banned to submit more work */
 597         bool banned;
 598 };
 599
 600 /* This must match up with the value previously used for execbuf2.rsvd1. */
 601 #define DEFAULT_CONTEXT_ID 0
 602 struct i915_hw_context {
 603         struct kref ref;
 604         int id;
 605         bool is_initialized;
 606         uint8_t remap_slice;
 607         struct drm_i915_file_private *file_priv;
 608         struct intel_ring_buffer *last_ring;
 609         struct drm_i915_gem_object *obj;
 610         struct i915_ctx_hang_stats hang_stats;
 611         struct i915_address_space *vm;
 612
 613         struct list_head link;
 614 };
 615
 616 struct i915_fbc {
 617         unsigned long size;
 618         unsigned int fb_id;
 619         enum plane plane;
 620         int y;
 621
 622         struct drm_mm_node *compressed_fb;
 623         struct drm_mm_node *compressed_llb;
 624
 625         struct intel_fbc_work {
 626                 struct delayed_work work;
 627                 struct drm_crtc *crtc;
 628                 struct drm_framebuffer *fb;
 629         } *fbc_work;
 630
 631         enum no_fbc_reason {
 632                 FBC_OK, /* FBC is enabled */
 633                 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
 634                 FBC_NO_OUTPUT, /* no outputs enabled to compress */
 635                 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
 636                 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 637                 FBC_MODE_TOO_LARGE, /* mode too large for compression */
 638                 FBC_BAD_PLANE, /* fbc not supported on plane */
 639                 FBC_NOT_TILED, /* buffer not tiled */
 640                 FBC_MULTIPLE_PIPES, /* more than one pipe active */
 641                 FBC_MODULE_PARAM,
 642                 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
 643         } no_fbc_reason;
 644 };
 645
 646 struct i915_drrs {
 647         struct intel_connector *connector;
 648 };
 649
 650 struct i915_psr {
 651         bool sink_support;
 652         bool source_ok;
 653 };
 654
 655 enum intel_pch {
 656         PCH_NONE = 0,   /* No PCH present */
 657         PCH_IBX,        /* Ibexpeak PCH */
 658         PCH_CPT,        /* Cougarpoint PCH */
 659         PCH_LPT,        /* Lynxpoint PCH */
 660         PCH_NOP,
 661 };
 662
 663 enum intel_sbi_destination {
 664         SBI_ICLK,
 665         SBI_MPHY,
 666 };
 667
 668 #define QUIRK_PIPEA_FORCE (1<<0)
 669 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 670 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
 671
 672 struct intel_fbdev;
 673 struct intel_fbc_work;
 674
 675 struct intel_gmbus {
 676         struct i2c_adapter adapter;
 677         u32 force_bit;
 678         u32 reg0;
 679         u32 gpio_reg;
 680         struct i2c_algo_bit_data bit_algo;
 681         struct drm_i915_private *dev_priv;
 682 };
 683
 684 struct i915_suspend_saved_registers {
 685         u8 saveLBB;
 686         u32 saveDSPACNTR;
 687         u32 saveDSPBCNTR;
 688         u32 saveDSPARB;
 689         u32 savePIPEACONF;
 690         u32 savePIPEBCONF;
 691         u32 savePIPEASRC;
 692         u32 savePIPEBSRC;
 693         u32 saveFPA0;
 694         u32 saveFPA1;
 695         u32 saveDPLL_A;
 696         u32 saveDPLL_A_MD;
 697         u32 saveHTOTAL_A;
 698         u32 saveHBLANK_A;
 699         u32 saveHSYNC_A;
 700         u32 saveVTOTAL_A;
 701         u32 saveVBLANK_A;
 702         u32 saveVSYNC_A;
 703         u32 saveBCLRPAT_A;
 704         u32 saveTRANSACONF;
 705         u32 saveTRANS_HTOTAL_A;
 706         u32 saveTRANS_HBLANK_A;
 707         u32 saveTRANS_HSYNC_A;
 708         u32 saveTRANS_VTOTAL_A;
 709         u32 saveTRANS_VBLANK_A;
 710         u32 saveTRANS_VSYNC_A;
 711         u32 savePIPEASTAT;
 712         u32 saveDSPASTRIDE;
 713         u32 saveDSPASIZE;
 714         u32 saveDSPAPOS;
 715         u32 saveDSPAADDR;
 716         u32 saveDSPASURF;
 717         u32 saveDSPATILEOFF;
 718         u32 savePFIT_PGM_RATIOS;
 719         u32 saveBLC_HIST_CTL;
 720         u32 saveBLC_PWM_CTL;
 721         u32 saveBLC_PWM_CTL2;
 722         u32 saveBLC_HIST_CTL_B;
 723         u32 saveBLC_CPU_PWM_CTL;
 724         u32 saveBLC_CPU_PWM_CTL2;
 725         u32 saveFPB0;
 726         u32 saveFPB1;
 727         u32 saveDPLL_B;
 728         u32 saveDPLL_B_MD;
 729         u32 saveHTOTAL_B;
 730         u32 saveHBLANK_B;
 731         u32 saveHSYNC_B;
 732         u32 saveVTOTAL_B;
 733         u32 saveVBLANK_B;
 734         u32 saveVSYNC_B;
 735         u32 saveBCLRPAT_B;
 736         u32 saveTRANSBCONF;
 737         u32 saveTRANS_HTOTAL_B;
 738         u32 saveTRANS_HBLANK_B;
 739         u32 saveTRANS_HSYNC_B;
 740         u32 saveTRANS_VTOTAL_B;
 741         u32 saveTRANS_VBLANK_B;
 742         u32 saveTRANS_VSYNC_B;
 743         u32 savePIPEBSTAT;
 744         u32 saveDSPBSTRIDE;
 745         u32 saveDSPBSIZE;
 746         u32 saveDSPBPOS;
 747         u32 saveDSPBADDR;
 748         u32 saveDSPBSURF;
 749         u32 saveDSPBTILEOFF;
 750         u32 saveVGA0;
 751         u32 saveVGA1;
 752         u32 saveVGA_PD;
 753         u32 saveVGACNTRL;
 754         u32 saveADPA;
 755         u32 saveLVDS;
 756         u32 savePP_ON_DELAYS;
 757         u32 savePP_OFF_DELAYS;
 758         u32 saveDVOA;
 759         u32 saveDVOB;
 760         u32 saveDVOC;
 761         u32 savePP_ON;
 762         u32 savePP_OFF;
 763         u32 savePP_CONTROL;
 764         u32 savePP_DIVISOR;
 765         u32 savePFIT_CONTROL;
 766         u32 save_palette_a[256];
 767         u32 save_palette_b[256];
 768         u32 saveFBC_CONTROL;
 769         u32 saveIER;
 770         u32 saveIIR;
 771         u32 saveIMR;
 772         u32 saveDEIER;
 773         u32 saveDEIMR;
 774         u32 saveGTIER;
 775         u32 saveGTIMR;
 776         u32 saveFDI_RXA_IMR;
 777         u32 saveFDI_RXB_IMR;
 778         u32 saveCACHE_MODE_0;
 779         u32 saveMI_ARB_STATE;
 780         u32 saveSWF0[16];
 781         u32 saveSWF1[16];
 782         u32 saveSWF2[3];
 783         u8 saveMSR;
 784         u8 saveSR[8];
 785         u8 saveGR[25];
 786         u8 saveAR_INDEX;
 787         u8 saveAR[21];
 788         u8 saveDACMASK;
 789         u8 saveCR[37];
 790         uint64_t saveFENCE[I915_MAX_NUM_FENCES];
 791         u32 saveCURACNTR;
 792         u32 saveCURAPOS;
 793         u32 saveCURABASE;
 794         u32 saveCURBCNTR;
 795         u32 saveCURBPOS;
 796         u32 saveCURBBASE;
 797         u32 saveCURSIZE;
 798         u32 saveDP_B;
 799         u32 saveDP_C;
 800         u32 saveDP_D;
 801         u32 savePIPEA_GMCH_DATA_M;
 802         u32 savePIPEB_GMCH_DATA_M;
 803         u32 savePIPEA_GMCH_DATA_N;
 804         u32 savePIPEB_GMCH_DATA_N;
 805         u32 savePIPEA_DP_LINK_M;
 806         u32 savePIPEB_DP_LINK_M;
 807         u32 savePIPEA_DP_LINK_N;
 808         u32 savePIPEB_DP_LINK_N;
 809         u32 saveFDI_RXA_CTL;
 810         u32 saveFDI_TXA_CTL;
 811         u32 saveFDI_RXB_CTL;
 812         u32 saveFDI_TXB_CTL;
 813         u32 savePFA_CTL_1;
 814         u32 savePFB_CTL_1;
 815         u32 savePFA_WIN_SZ;
 816         u32 savePFB_WIN_SZ;
 817         u32 savePFA_WIN_POS;
 818         u32 savePFB_WIN_POS;
 819         u32 savePCH_DREF_CONTROL;
 820         u32 saveDISP_ARB_CTL;
 821         u32 savePIPEA_DATA_M1;
 822         u32 savePIPEA_DATA_N1;
 823         u32 savePIPEA_LINK_M1;
 824         u32 savePIPEA_LINK_N1;
 825         u32 savePIPEB_DATA_M1;
 826         u32 savePIPEB_DATA_N1;
 827         u32 savePIPEB_LINK_M1;
 828         u32 savePIPEB_LINK_N1;
 829         u32 saveMCHBAR_RENDER_STANDBY;
 830         u32 savePCH_PORT_HOTPLUG;
 831 };
 832
 833 struct vlv_s0ix_state {
 834         /* GAM */
 835         u32 wr_watermark;
 836         u32 gfx_prio_ctrl;
 837         u32 arb_mode;
 838         u32 gfx_pend_tlb0;
 839         u32 gfx_pend_tlb1;
 840         u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
 841         u32 media_max_req_count;
 842         u32 gfx_max_req_count;
 843         u32 render_hwsp;
 844         u32 ecochk;
 845         u32 bsd_hwsp;
 846         u32 blt_hwsp;
 847         u32 tlb_rd_addr;
 848
 849         /* MBC */
 850         u32 g3dctl;
 851         u32 gsckgctl;
 852         u32 mbctl;
 853
 854         /* GCP */
 855         u32 ucgctl1;
 856         u32 ucgctl3;
 857         u32 rcgctl1;
 858         u32 rcgctl2;
 859         u32 rstctl;
 860         u32 misccpctl;
 861
 862         /* GPM */
 863         u32 gfxpause;
 864         u32 rpdeuhwtc;
 865         u32 rpdeuc;
 866         u32 ecobus;
 867         u32 pwrdwnupctl;
 868         u32 rp_down_timeout;
 869         u32 rp_deucsw;
 870         u32 rcubmabdtmr;
 871         u32 rcedata;
 872         u32 spare2gh;
 873
 874         /* Display 1 CZ domain */
 875         u32 gt_imr;
 876         u32 gt_ier;
 877         u32 pm_imr;
 878         u32 pm_ier;
 879         u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
 880
 881         /* GT SA CZ domain */
 882         u32 tilectl;
 883         u32 gt_fifoctl;
 884         u32 gtlc_wake_ctrl;
 885         u32 gtlc_survive;
 886         u32 pmwgicz;
 887
 888         /* Display 2 CZ domain */
 889         u32 gu_ctl0;
 890         u32 gu_ctl1;
 891         u32 clock_gate_dis2;
 892 };
 893
 894 struct intel_gen6_power_mgmt {
 895         /* work and pm_iir are protected by dev_priv->irq_lock */
 896         struct work_struct work;
 897         u32 pm_iir;
 898
 899         /* Frequencies are stored in potentially platform dependent multiples.
 900          * In other words, *_freq needs to be multiplied by X to be interesting.
 901          * Soft limits are those which are used for the dynamic reclocking done
 902          * by the driver (raise frequencies under heavy loads, and lower for
 903          * lighter loads). Hard limits are those imposed by the hardware.
 904          *
 905          * A distinction is made for overclocking, which is never enabled by
 906          * default, and is considered to be above the hard limit if it's
 907          * possible at all.
 908          */
 909         u8 cur_freq;            /* Current frequency (cached, may not == HW) */
 910         u8 min_freq_softlimit;  /* Minimum frequency permitted by the driver */
 911         u8 max_freq_softlimit;  /* Max frequency permitted by the driver */
 912         u8 max_freq;            /* Maximum frequency, RP0 if not overclocking */
 913         u8 min_freq;            /* AKA RPn. Minimum frequency */
 914         u8 efficient_freq;      /* AKA RPe. Pre-determined balanced frequency */
 915         u8 rp1_freq;            /* "less than" RP0 power/freqency */
 916         u8 rp0_freq;            /* Non-overclocked max frequency. */
 917
 918         int last_adj;
 919         enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
 920
 921         bool enabled;
 922         struct delayed_work delayed_resume_work;
 923
 924         /*
 925          * Protects RPS/RC6 register access and PCU communication.
 926          * Must be taken after struct_mutex if nested.
 927          */
 928         struct mutex hw_lock;
 929 };
 930
 931 /* defined intel_pm.c */
 932 extern spinlock_t mchdev_lock;
 933
 934 struct intel_ilk_power_mgmt {
 935         u8 cur_delay;
 936         u8 min_delay;
 937         u8 max_delay;
 938         u8 fmax;
 939         u8 fstart;
 940
 941         u64 last_count1;
 942         unsigned long last_time1;
 943         unsigned long chipset_power;
 944         u64 last_count2;
 945         struct timespec last_time2;
 946         unsigned long gfx_power;
 947         u8 corr;
 948
 949         int c_m;
 950         int r_t;
 951
 952         struct drm_i915_gem_object *pwrctx;
 953         struct drm_i915_gem_object *renderctx;
 954 };
 955
 956 struct drm_i915_private;
 957 struct i915_power_well;
 958
 959 struct i915_power_well_ops {
 960         /*
 961          * Synchronize the well's hw state to match the current sw state, for
 962          * example enable/disable it based on the current refcount. Called
 963          * during driver init and resume time, possibly after first calling
 964          * the enable/disable handlers.
 965          */
 966         void (*sync_hw)(struct drm_i915_private *dev_priv,
 967                         struct i915_power_well *power_well);
 968         /*
 969          * Enable the well and resources that depend on it (for example
 970          * interrupts located on the well). Called after the 0->1 refcount
 971          * transition.
 972          */
 973         void (*enable)(struct drm_i915_private *dev_priv,
 974                        struct i915_power_well *power_well);
 975         /*
 976          * Disable the well and resources that depend on it. Called after
 977          * the 1->0 refcount transition.
 978          */
 979         void (*disable)(struct drm_i915_private *dev_priv,
 980                         struct i915_power_well *power_well);
 981         /* Returns the hw enabled state. */
 982         bool (*is_enabled)(struct drm_i915_private *dev_priv,
 983                            struct i915_power_well *power_well);
 984 };
 985
 986 /* Power well structure for haswell */
 987 struct i915_power_well {
 988         const char *name;
 989         bool always_on;
 990         /* power well enable/disable usage count */
 991         int count;
 992         unsigned long domains;
 993         unsigned long data;
 994         const struct i915_power_well_ops *ops;
 995 };
 996
 997 struct i915_power_domains {
 998         /*
 999          * Power wells needed for initialization at driver init and suspend
1000          * time are on. They are kept on until after the first modeset.
1001          */
1002         bool init_power_on;
1003         bool initializing;
1004         int power_well_count;
1005
1006         struct mutex lock;
1007         int domain_use_count[POWER_DOMAIN_NUM];
1008         struct i915_power_well *power_wells;
1009 };
1010
1011 struct i915_dri1_state {
1012         unsigned allow_batchbuffer : 1;
1013         u32 __iomem *gfx_hws_cpu_addr;
1014
1015         unsigned int cpp;
1016         int back_offset;
1017         int front_offset;
1018         int current_page;
1019         int page_flipping;
1020
1021         uint32_t counter;
1022 };
1023
1024 struct i915_ums_state {
1025         /**
1026          * Flag if the X Server, and thus DRM, is not currently in
1027          * control of the device.
1028          *
1029          * This is set between LeaveVT and EnterVT.  It needs to be
1030          * replaced with a semaphore.  It also needs to be
1031          * transitioned away from for kernel modesetting.
1032          */
1033         int mm_suspended;
1034 };
1035
1036 #define MAX_L3_SLICES 2
1037 struct intel_l3_parity {
1038         u32 *remap_info[MAX_L3_SLICES];
1039         struct work_struct error_work;
1040         int which_slice;
1041 };
1042
1043 struct i915_gem_mm {
1044         /** Memory allocator for GTT stolen memory */
1045         struct drm_mm stolen;
1046         /** List of all objects in gtt_space. Used to restore gtt
1047          * mappings on resume */
1048         struct list_head bound_list;
1049         /**
1050          * List of objects which are not bound to the GTT (thus
1051          * are idle and not used by the GPU) but still have
1052          * (presumably uncached) pages still attached.
1053          */
1054         struct list_head unbound_list;
1055
1056         /** Usable portion of the GTT for GEM */
1057         unsigned long stolen_base; /* limited to low memory (32-bit) */
1058
1059         /** PPGTT used for aliasing the PPGTT with the GTT */
1060         struct i915_hw_ppgtt *aliasing_ppgtt;
1061
1062         struct notifier_block oom_notifier;
1063         struct shrinker shrinker;
1064         bool shrinker_no_lock_stealing;
1065
1066         /** LRU list of objects with fence regs on them. */
1067         struct list_head fence_list;
1068
1069         /**
1070          * We leave the user IRQ off as much as possible,
1071          * but this means that requests will finish and never
1072          * be retired once the system goes idle. Set a timer to
1073          * fire periodically while the ring is running. When it
1074          * fires, go retire requests.
1075          */
1076         struct delayed_work retire_work;
1077
1078         /**
1079          * When we detect an idle GPU, we want to turn on
1080          * powersaving features. So once we see that there
1081          * are no more requests outstanding and no more
1082          * arrive within a small period of time, we fire
1083          * off the idle_work.
1084          */
1085         struct delayed_work idle_work;
1086
1087         /**
1088          * Are we in a non-interruptible section of code like
1089          * modesetting?
1090          */
1091         bool interruptible;
1092
1093         /**
1094          * Is the GPU currently considered idle, or busy executing userspace
1095          * requests?  Whilst idle, we attempt to power down the hardware and
1096          * display clocks. In order to reduce the effect on performance, there
1097          * is a slight delay before we do so.
1098          */
1099         bool busy;
1100
1101         /** Bit 6 swizzling required for X tiling */
1102         uint32_t bit_6_swizzle_x;
1103         /** Bit 6 swizzling required for Y tiling */
1104         uint32_t bit_6_swizzle_y;
1105
1106         /* storage for physical objects */
1107         struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1108
1109         /* accounting, useful for userland debugging */
1110         spinlock_t object_stat_lock;
1111         size_t object_memory;
1112         u32 object_count;
1113 };
1114
1115 struct drm_i915_error_state_buf {
1116         unsigned bytes;
1117         unsigned size;
1118         int err;
1119         u8 *buf;
1120         loff_t start;
1121         loff_t pos;
1122 };
1123
1124 struct i915_error_state_file_priv {
1125         struct drm_device *dev;
1126         struct drm_i915_error_state *error;
1127 };
1128
1129 struct i915_gpu_error {
1130         /* For hangcheck timer */
1131 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1132 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1133         /* Hang gpu twice in this window and your context gets banned */
1134 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1135
1136         struct timer_list hangcheck_timer;
1137
1138         /* For reset and error_state handling. */
1139         spinlock_t lock;
1140         /* Protected by the above dev->gpu_error.lock. */
1141         struct drm_i915_error_state *first_error;
1142         struct work_struct work;
1143
1144
1145         unsigned long missed_irq_rings;
1146
1147         /**
1148          * State variable controlling the reset flow and count
1149          *
1150          * This is a counter which gets incremented when reset is triggered,
1151          * and again when reset has been handled. So odd values (lowest bit set)
1152          * means that reset is in progress and even values that
1153          * (reset_counter >> 1):th reset was successfully completed.
1154          *
1155          * If reset is not completed succesfully, the I915_WEDGE bit is
1156          * set meaning that hardware is terminally sour and there is no
1157          * recovery. All waiters on the reset_queue will be woken when
1158          * that happens.
1159          *
1160          * This counter is used by the wait_seqno code to notice that reset
1161          * event happened and it needs to restart the entire ioctl (since most
1162          * likely the seqno it waited for won't ever signal anytime soon).
1163          *
1164          * This is important for lock-free wait paths, where no contended lock
1165          * naturally enforces the correct ordering between the bail-out of the
1166          * waiter and the gpu reset work code.
1167          */
1168         atomic_t reset_counter;
1169
1170 #define I915_RESET_IN_PROGRESS_FLAG     1
1171 #define I915_WEDGED                     (1 << 31)
1172
1173         /**
1174          * Waitqueue to signal when the reset has completed. Used by clients
1175          * that wait for dev_priv->mm.wedged to settle.
1176          */
1177         wait_queue_head_t reset_queue;
1178
1179         /* Userspace knobs for gpu hang simulation;
1180          * combines both a ring mask, and extra flags
1181          */
1182         u32 stop_rings;
1183 #define I915_STOP_RING_ALLOW_BAN       (1 << 31)
1184 #define I915_STOP_RING_ALLOW_WARN      (1 << 30)
1185
1186         /* For missed irq/seqno simulation. */
1187         unsigned int test_irq_rings;
1188 };
1189
1190 enum modeset_restore {
1191         MODESET_ON_LID_OPEN,
1192         MODESET_DONE,
1193         MODESET_SUSPENDED,
1194 };
1195
1196 struct ddi_vbt_port_info {
1197         uint8_t hdmi_level_shift;
1198
1199         uint8_t supports_dvi:1;
1200         uint8_t supports_hdmi:1;
1201         uint8_t supports_dp:1;
1202 };
1203
1204 enum drrs_support_type {
1205         DRRS_NOT_SUPPORTED = 0,
1206         STATIC_DRRS_SUPPORT = 1,
1207         SEAMLESS_DRRS_SUPPORT = 2
1208 };
1209
1210 struct intel_vbt_data {
1211         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1212         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1213
1214         /* Feature bits */
1215         unsigned int int_tv_support:1;
1216         unsigned int lvds_dither:1;
1217         unsigned int lvds_vbt:1;
1218         unsigned int int_crt_support:1;
1219         unsigned int lvds_use_ssc:1;
1220         unsigned int display_clock_mode:1;
1221         unsigned int fdi_rx_polarity_inverted:1;
1222         int lvds_ssc_freq;
1223         unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1224
1225         enum drrs_support_type drrs_type;
1226
1227         /* eDP */
1228         int edp_rate;
1229         int edp_lanes;
1230         int edp_preemphasis;
1231         int edp_vswing;
1232         bool edp_initialized;
1233         bool edp_support;
1234         int edp_bpp;
1235         struct edp_power_seq edp_pps;
1236
1237         struct {
1238                 u16 pwm_freq_hz;
1239                 bool present;
1240                 bool active_low_pwm;
1241         } backlight;
1242
1243         /* MIPI DSI */
1244         struct {
1245                 u16 panel_id;
1246                 struct mipi_config *config;
1247                 struct mipi_pps_data *pps;
1248                 u8 seq_version;
1249                 u32 size;
1250                 u8 *data;
1251                 u8 *sequence[MIPI_SEQ_MAX];
1252         } dsi;
1253
1254         int crt_ddc_pin;
1255
1256         int child_dev_num;
1257         union child_device_config *child_dev;
1258
1259         struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1260 };
1261
1262 enum intel_ddb_partitioning {
1263         INTEL_DDB_PART_1_2,
1264         INTEL_DDB_PART_5_6, /* IVB+ */
1265 };
1266
1267 struct intel_wm_level {
1268         bool enable;
1269         uint32_t pri_val;
1270         uint32_t spr_val;
1271         uint32_t cur_val;
1272         uint32_t fbc_val;
1273 };
1274
1275 struct ilk_wm_values {
1276         uint32_t wm_pipe[3];
1277         uint32_t wm_lp[3];
1278         uint32_t wm_lp_spr[3];
1279         uint32_t wm_linetime[3];
1280         bool enable_fbc_wm;
1281         enum intel_ddb_partitioning partitioning;
1282 };
1283
1284 /*
1285  * This struct helps tracking the state needed for runtime PM, which puts the
1286  * device in PCI D3 state. Notice that when this happens, nothing on the
1287  * graphics device works, even register access, so we don't get interrupts nor
1288  * anything else.
1289  *
1290  * Every piece of our code that needs to actually touch the hardware needs to
1291  * either call intel_runtime_pm_get or call intel_display_power_get with the
1292  * appropriate power domain.
1293  *
1294  * Our driver uses the autosuspend delay feature, which means we'll only really
1295  * suspend if we stay with zero refcount for a certain amount of time. The
1296  * default value is currently very conservative (see intel_init_runtime_pm), but
1297  * it can be changed with the standard runtime PM files from sysfs.
1298  *
1299  * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1300  * goes back to false exactly before we reenable the IRQs. We use this variable
1301  * to check if someone is trying to enable/disable IRQs while they're supposed
1302  * to be disabled. This shouldn't happen and we'll print some error messages in
1303  * case it happens.
1304  *
1305  * For more, read the Documentation/power/runtime_pm.txt.
1306  */
1307 struct i915_runtime_pm {
1308         bool suspended;
1309         bool irqs_disabled;
1310 };
1311
1312 enum intel_pipe_crc_source {
1313         INTEL_PIPE_CRC_SOURCE_NONE,
1314         INTEL_PIPE_CRC_SOURCE_PLANE1,
1315         INTEL_PIPE_CRC_SOURCE_PLANE2,
1316         INTEL_PIPE_CRC_SOURCE_PF,
1317         INTEL_PIPE_CRC_SOURCE_PIPE,
1318         /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1319         INTEL_PIPE_CRC_SOURCE_TV,
1320         INTEL_PIPE_CRC_SOURCE_DP_B,
1321         INTEL_PIPE_CRC_SOURCE_DP_C,
1322         INTEL_PIPE_CRC_SOURCE_DP_D,
1323         INTEL_PIPE_CRC_SOURCE_AUTO,
1324         INTEL_PIPE_CRC_SOURCE_MAX,
1325 };
1326
1327 struct intel_pipe_crc_entry {
1328         uint32_t frame;
1329         uint32_t crc[5];
1330 };
1331
1332 #define INTEL_PIPE_CRC_ENTRIES_NR       128
1333 struct intel_pipe_crc {
1334         spinlock_t lock;
1335         bool opened;            /* exclusive access to the result file */
1336         struct intel_pipe_crc_entry *entries;
1337         enum intel_pipe_crc_source source;
1338         int head, tail;
1339         wait_queue_head_t wq;
1340 };
1341
1342 struct drm_i915_private {
1343         struct drm_device *dev;
1344         struct kmem_cache *slab;
1345
1346         const struct intel_device_info info;
1347
1348         int relative_constants_mode;
1349
1350         void __iomem *regs;
1351
1352         struct intel_uncore uncore;
1353
1354         struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1355
1356
1357         /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1358          * controller on different i2c buses. */
1359         struct mutex gmbus_mutex;
1360
1361         /**
1362          * Base address of the gmbus and gpio block.
1363          */
1364         uint32_t gpio_mmio_base;
1365
1366         /* MMIO base address for MIPI regs */
1367         uint32_t mipi_mmio_base;
1368
1369         wait_queue_head_t gmbus_wait_queue;
1370
1371         struct pci_dev *bridge_dev;
1372         struct intel_ring_buffer ring[I915_NUM_RINGS];
1373         uint32_t last_seqno, next_seqno;
1374
1375         drm_dma_handle_t *status_page_dmah;
1376         struct resource mch_res;
1377
1378         /* protects the irq masks */
1379         spinlock_t irq_lock;
1380
1381         bool display_irqs_enabled;
1382
1383         /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1384         struct pm_qos_request pm_qos;
1385
1386         /* DPIO indirect register protection */
1387         struct mutex dpio_lock;
1388
1389         /** Cached value of IMR to avoid reads in updating the bitfield */
1390         union {
1391                 u32 irq_mask;
1392                 u32 de_irq_mask[I915_MAX_PIPES];
1393         };
1394         u32 gt_irq_mask;
1395         u32 pm_irq_mask;
1396         u32 pm_rps_events;
1397         u32 pipestat_irq_mask[I915_MAX_PIPES];
1398
1399         struct work_struct hotplug_work;
1400         bool enable_hotplug_processing;
1401         struct {
1402                 unsigned long hpd_last_jiffies;
1403                 int hpd_cnt;
1404                 enum {
1405                         HPD_ENABLED = 0,
1406                         HPD_DISABLED = 1,
1407                         HPD_MARK_DISABLED = 2
1408                 } hpd_mark;
1409         } hpd_stats[HPD_NUM_PINS];
1410         u32 hpd_event_bits;
1411         struct timer_list hotplug_reenable_timer;
1412
1413         struct i915_fbc fbc;
1414         struct i915_drrs drrs;
1415         struct intel_opregion opregion;
1416         struct intel_vbt_data vbt;
1417
1418         /* overlay */
1419         struct intel_overlay *overlay;
1420
1421         /* backlight registers and fields in struct intel_panel */
1422         spinlock_t backlight_lock;
1423
1424         /* LVDS info */
1425         bool no_aux_handshake;
1426
1427         struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1428         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1429         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1430
1431         unsigned int fsb_freq, mem_freq, is_ddr3;
1432         unsigned int vlv_cdclk_freq;
1433
1434         /**
1435          * wq - Driver workqueue for GEM.
1436          *
1437          * NOTE: Work items scheduled here are not allowed to grab any modeset
1438          * locks, for otherwise the flushing done in the pageflip code will
1439          * result in deadlocks.
1440          */
1441         struct workqueue_struct *wq;
1442
1443         /* Display functions */
1444         struct drm_i915_display_funcs display;
1445
1446         /* PCH chipset type */
1447         enum intel_pch pch_type;
1448         unsigned short pch_id;
1449
1450         unsigned long quirks;
1451
1452         enum modeset_restore modeset_restore;
1453         struct mutex modeset_restore_lock;
1454
1455         struct list_head vm_list; /* Global list of all address spaces */
1456         struct i915_gtt gtt; /* VM representing the global address space */
1457
1458         struct i915_gem_mm mm;
1459 #if defined(CONFIG_MMU_NOTIFIER)
1460         DECLARE_HASHTABLE(mmu_notifiers, 7);
1461 #endif
1462
1463         /* Kernel Modesetting */
1464
1465         struct sdvo_device_mapping sdvo_mappings[2];
1466
1467         struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1468         struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1469         wait_queue_head_t pending_flip_queue;
1470
1471 #ifdef CONFIG_DEBUG_FS
1472         struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1473 #endif
1474
1475         int num_shared_dpll;
1476         struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1477         struct intel_ddi_plls ddi_plls;
1478         int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1479
1480         /* Reclocking support */
1481         bool render_reclock_avail;
1482         bool lvds_downclock_avail;
1483         /* indicates the reduced downclock for LVDS*/
1484         int lvds_downclock;
1485         u16 orig_clock;
1486
1487         bool mchbar_need_disable;
1488
1489         struct intel_l3_parity l3_parity;
1490
1491         /* Cannot be determined by PCIID. You must always read a register. */
1492         size_t ellc_size;
1493
1494         /* gen6+ rps state */
1495         struct intel_gen6_power_mgmt rps;
1496
1497         /* ilk-only ips/rps state. Everything in here is protected by the global
1498          * mchdev_lock in intel_pm.c */
1499         struct intel_ilk_power_mgmt ips;
1500
1501         struct i915_power_domains power_domains;
1502
1503         struct i915_psr psr;
1504
1505         struct i915_gpu_error gpu_error;
1506
1507         struct drm_i915_gem_object *vlv_pctx;
1508
1509 #ifdef CONFIG_DRM_I915_FBDEV
1510         /* list of fbdev register on this device */
1511         struct intel_fbdev *fbdev;
1512 #endif
1513
1514         /*
1515          * The console may be contended at resume, but we don't
1516          * want it to block on it.
1517          */
1518         struct work_struct console_resume_work;
1519
1520         struct drm_property *broadcast_rgb_property;
1521         struct drm_property *force_audio_property;
1522
1523         uint32_t hw_context_size;
1524         struct list_head context_list;
1525
1526         u32 fdi_rx_config;
1527
1528         u32 suspend_count;
1529         struct i915_suspend_saved_registers regfile;
1530         struct vlv_s0ix_state vlv_s0ix_state;
1531
1532         struct {
1533                 /*
1534                  * Raw watermark latency values:
1535                  * in 0.1us units for WM0,
1536                  * in 0.5us units for WM1+.
1537                  */
1538                 /* primary */
1539                 uint16_t pri_latency[5];
1540                 /* sprite */
1541                 uint16_t spr_latency[5];
1542                 /* cursor */
1543                 uint16_t cur_latency[5];
1544
1545                 /* current hardware state */
1546                 struct ilk_wm_values hw;
1547         } wm;
1548
1549         struct i915_runtime_pm pm;
1550
1551         /* Old dri1 support infrastructure, beware the dragons ya fools entering
1552          * here! */
1553         struct i915_dri1_state dri1;
1554         /* Old ums support infrastructure, same warning applies. */
1555         struct i915_ums_state ums;
1556         /* the indicator for dispatch video commands on two BSD rings */
1557         int ring_index;
1558 };
1559
1560 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1561 {
1562         return dev->dev_private;
1563 }
1564
1565 /* Iterate over initialised rings */
1566 #define for_each_ring(ring__, dev_priv__, i__) \
1567         for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1568                 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1569
1570 enum hdmi_force_audio {
1571         HDMI_AUDIO_OFF_DVI = -2,        /* no aux data for HDMI-DVI converter */
1572         HDMI_AUDIO_OFF,                 /* force turn off HDMI audio */
1573         HDMI_AUDIO_AUTO,                /* trust EDID */
1574         HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
1575 };
1576
1577 #define I915_GTT_OFFSET_NONE ((u32)-1)
1578
1579 struct drm_i915_gem_object_ops {
1580         /* Interface between the GEM object and its backing storage.
1581          * get_pages() is called once prior to the use of the associated set
1582          * of pages before to binding them into the GTT, and put_pages() is
1583          * called after we no longer need them. As we expect there to be
1584          * associated cost with migrating pages between the backing storage
1585          * and making them available for the GPU (e.g. clflush), we may hold
1586          * onto the pages after they are no longer referenced by the GPU
1587          * in case they may be used again shortly (for example migrating the
1588          * pages to a different memory domain within the GTT). put_pages()
1589          * will therefore most likely be called when the object itself is
1590          * being released or under memory pressure (where we attempt to
1591          * reap pages for the shrinker).
1592          */
1593         int (*get_pages)(struct drm_i915_gem_object *);
1594         void (*put_pages)(struct drm_i915_gem_object *);
1595         int (*dmabuf_export)(struct drm_i915_gem_object *);
1596         void (*release)(struct drm_i915_gem_object *);
1597 };
1598
1599 struct drm_i915_gem_object {
1600         struct drm_gem_object base;
1601
1602         const struct drm_i915_gem_object_ops *ops;
1603
1604         /** List of VMAs backed by this object */
1605         struct list_head vma_list;
1606
1607         /** Stolen memory for this object, instead of being backed by shmem. */
1608         struct drm_mm_node *stolen;
1609         struct list_head global_list;
1610
1611         struct list_head ring_list;
1612         /** Used in execbuf to temporarily hold a ref */
1613         struct list_head obj_exec_link;
1614
1615         /**
1616          * This is set if the object is on the active lists (has pending
1617          * rendering and so a non-zero seqno), and is not set if it i s on
1618          * inactive (ready to be unbound) list.
1619          */
1620         unsigned int active:1;
1621
1622         /**
1623          * This is set if the object has been written to since last bound
1624          * to the GTT
1625          */
1626         unsigned int dirty:1;
1627
1628         /**
1629          * Fence register bits (if any) for this object.  Will be set
1630          * as needed when mapped into the GTT.
1631          * Protected by dev->struct_mutex.
1632          */
1633         signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1634
1635         /**
1636          * Advice: are the backing pages purgeable?
1637          */
1638         unsigned int madv:2;
1639
1640         /**
1641          * Current tiling mode for the object.
1642          */
1643         unsigned int tiling_mode:2;
1644         /**
1645          * Whether the tiling parameters for the currently associated fence
1646          * register have changed. Note that for the purposes of tracking
1647          * tiling changes we also treat the unfenced register, the register
1648          * slot that the object occupies whilst it executes a fenced
1649          * command (such as BLT on gen2/3), as a "fence".
1650          */
1651         unsigned int fence_dirty:1;
1652
1653         /**
1654          * Is the object at the current location in the gtt mappable and
1655          * fenceable? Used to avoid costly recalculations.
1656          */
1657         unsigned int map_and_fenceable:1;
1658
1659         /**
1660          * Whether the current gtt mapping needs to be mappable (and isn't just
1661          * mappable by accident). Track pin and fault separate for a more
1662          * accurate mappable working set.
1663          */
1664         unsigned int fault_mappable:1;
1665         unsigned int pin_mappable:1;
1666         unsigned int pin_display:1;
1667
1668         /*
1669          * Is the GPU currently using a fence to access this buffer,
1670          */
1671         unsigned int pending_fenced_gpu_access:1;
1672         unsigned int fenced_gpu_access:1;
1673
1674         unsigned int cache_level:3;
1675
1676         unsigned int has_aliasing_ppgtt_mapping:1;
1677         unsigned int has_global_gtt_mapping:1;
1678         unsigned int has_dma_mapping:1;
1679
1680         struct sg_table *pages;
1681         int pages_pin_count;
1682
1683         /* prime dma-buf support */
1684         void *dma_buf_vmapping;
1685         int vmapping_count;
1686
1687         struct intel_ring_buffer *ring;
1688
1689         /** Breadcrumb of last rendering to the buffer. */
1690         uint32_t last_read_seqno;
1691         uint32_t last_write_seqno;
1692         /** Breadcrumb of last fenced GPU access to the buffer. */
1693         uint32_t last_fenced_seqno;
1694
1695         /** Current tiling stride for the object, if it's tiled. */
1696         uint32_t stride;
1697
1698         /** References from framebuffers, locks out tiling changes. */
1699         unsigned long framebuffer_references;
1700
1701         /** Record of address bit 17 of each page at last unbind. */
1702         unsigned long *bit_17;
1703
1704         /** User space pin count and filp owning the pin */
1705         unsigned long user_pin_count;
1706         struct drm_file *pin_filp;
1707
1708         /** for phy allocated objects */
1709         struct drm_i915_gem_phys_object *phys_obj;
1710
1711         union {
1712                 struct i915_gem_userptr {
1713                         uintptr_t ptr;
1714                         unsigned read_only :1;
1715                         unsigned workers :4;
1716 #define I915_GEM_USERPTR_MAX_WORKERS 15
1717
1718                         struct mm_struct *mm;
1719                         struct i915_mmu_object *mn;
1720                         struct work_struct *work;
1721                 } userptr;
1722         };
1723 };
1724 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1725
1726 /**
1727  * Request queue structure.
1728  *
1729  * The request queue allows us to note sequence numbers that have been emitted
1730  * and may be associated with active buffers to be retired.
1731  *
1732  * By keeping this list, we can avoid having to do questionable
1733  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1734  * an emission time with seqnos for tracking how far ahead of the GPU we are.
1735  */
1736 struct drm_i915_gem_request {
1737         /** On Which ring this request was generated */
1738         struct intel_ring_buffer *ring;
1739
1740         /** GEM sequence number associated with this request. */
1741         uint32_t seqno;
1742
1743         /** Position in the ringbuffer of the start of the request */
1744         u32 head;
1745
1746         /** Position in the ringbuffer of the end of the request */
1747         u32 tail;
1748
1749         /** Context related to this request */
1750         struct i915_hw_context *ctx;
1751
1752         /** Batch buffer related to this request if any */
1753         struct drm_i915_gem_object *batch_obj;
1754
1755         /** Time at which this request was emitted, in jiffies. */
1756         unsigned long emitted_jiffies;
1757
1758         /** global list entry for this request */
1759         struct list_head list;
1760
1761         struct drm_i915_file_private *file_priv;
1762         /** file_priv list entry for this request */
1763         struct list_head client_list;
1764 };
1765
1766 struct drm_i915_file_private {
1767         struct drm_i915_private *dev_priv;
1768         struct drm_file *file;
1769
1770         struct {
1771                 spinlock_t lock;
1772                 struct list_head request_list;
1773                 struct delayed_work idle_work;
1774         } mm;
1775         struct idr context_idr;
1776
1777         struct i915_hw_context *private_default_ctx;
1778         atomic_t rps_wait_boost;
1779         struct  intel_ring_buffer *bsd_ring;
1780 };
1781
1782 /*
1783  * A command that requires special handling by the command parser.
1784  */
1785 struct drm_i915_cmd_descriptor {
1786         /*
1787          * Flags describing how the command parser processes the command.
1788          *
1789          * CMD_DESC_FIXED: The command has a fixed length if this is set,
1790          *                 a length mask if not set
1791          * CMD_DESC_SKIP: The command is allowed but does not follow the
1792          *                standard length encoding for the opcode range in
1793          *                which it falls
1794          * CMD_DESC_REJECT: The command is never allowed
1795          * CMD_DESC_REGISTER: The command should be checked against the
1796          *                    register whitelist for the appropriate ring
1797          * CMD_DESC_MASTER: The command is allowed if the submitting process
1798          *                  is the DRM master
1799          */
1800         u32 flags;
1801 #define CMD_DESC_FIXED    (1<<0)
1802 #define CMD_DESC_SKIP     (1<<1)
1803 #define CMD_DESC_REJECT   (1<<2)
1804 #define CMD_DESC_REGISTER (1<<3)
1805 #define CMD_DESC_BITMASK  (1<<4)
1806 #define CMD_DESC_MASTER   (1<<5)
1807
1808         /*
1809          * The command's unique identification bits and the bitmask to get them.
1810          * This isn't strictly the opcode field as defined in the spec and may
1811          * also include type, subtype, and/or subop fields.
1812          */
1813         struct {
1814                 u32 value;
1815                 u32 mask;
1816         } cmd;
1817
1818         /*
1819          * The command's length. The command is either fixed length (i.e. does
1820          * not include a length field) or has a length field mask. The flag
1821          * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1822          * a length mask. All command entries in a command table must include
1823          * length information.
1824          */
1825         union {
1826                 u32 fixed;
1827                 u32 mask;
1828         } length;
1829
1830         /*
1831          * Describes where to find a register address in the command to check
1832          * against the ring's register whitelist. Only valid if flags has the
1833          * CMD_DESC_REGISTER bit set.
1834          */
1835         struct {
1836                 u32 offset;
1837                 u32 mask;
1838         } reg;
1839
1840 #define MAX_CMD_DESC_BITMASKS 3
1841         /*
1842          * Describes command checks where a particular dword is masked and
1843          * compared against an expected value. If the command does not match
1844          * the expected value, the parser rejects it. Only valid if flags has
1845          * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1846          * are valid.
1847          *
1848          * If the check specifies a non-zero condition_mask then the parser
1849          * only performs the check when the bits specified by condition_mask
1850          * are non-zero.
1851          */
1852         struct {
1853                 u32 offset;
1854                 u32 mask;
1855                 u32 expected;
1856                 u32 condition_offset;
1857                 u32 condition_mask;
1858         } bits[MAX_CMD_DESC_BITMASKS];
1859 };
1860
1861 /*
1862  * A table of commands requiring special handling by the command parser.
1863  *
1864  * Each ring has an array of tables. Each table consists of an array of command
1865  * descriptors, which must be sorted with command opcodes in ascending order.
1866  */
1867 struct drm_i915_cmd_table {
1868         const struct drm_i915_cmd_descriptor *table;
1869         int count;
1870 };
1871
1872 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1873
1874 #define IS_I830(dev)            ((dev)->pdev->device == 0x3577)
1875 #define IS_845G(dev)            ((dev)->pdev->device == 0x2562)
1876 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
1877 #define IS_I865G(dev)           ((dev)->pdev->device == 0x2572)
1878 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
1879 #define IS_I915GM(dev)          ((dev)->pdev->device == 0x2592)
1880 #define IS_I945G(dev)           ((dev)->pdev->device == 0x2772)
1881 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
1882 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
1883 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
1884 #define IS_GM45(dev)            ((dev)->pdev->device == 0x2A42)
1885 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
1886 #define IS_PINEVIEW_G(dev)      ((dev)->pdev->device == 0xa001)
1887 #define IS_PINEVIEW_M(dev)      ((dev)->pdev->device == 0xa011)
1888 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
1889 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
1890 #define IS_IRONLAKE_M(dev)      ((dev)->pdev->device == 0x0046)
1891 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
1892 #define IS_IVB_GT1(dev)         ((dev)->pdev->device == 0x0156 || \
1893                                  (dev)->pdev->device == 0x0152 || \
1894                                  (dev)->pdev->device == 0x015a)
1895 #define IS_SNB_GT1(dev)         ((dev)->pdev->device == 0x0102 || \
1896                                  (dev)->pdev->device == 0x0106 || \
1897                                  (dev)->pdev->device == 0x010A)
1898 #define IS_VALLEYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview)
1899 #define IS_CHERRYVIEW(dev)      (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1900 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1901 #define IS_BROADWELL(dev)       (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1902 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
1903 #define IS_HSW_EARLY_SDV(dev)   (IS_HASWELL(dev) && \
1904                                  ((dev)->pdev->device & 0xFF00) == 0x0C00)
1905 #define IS_BDW_ULT(dev)         (IS_BROADWELL(dev) && \
1906                                  (((dev)->pdev->device & 0xf) == 0x2  || \
1907                                  ((dev)->pdev->device & 0xf) == 0x6 || \
1908                                  ((dev)->pdev->device & 0xf) == 0xe))
1909 #define IS_HSW_ULT(dev)         (IS_HASWELL(dev) && \
1910                                  ((dev)->pdev->device & 0xFF00) == 0x0A00)
1911 #define IS_ULT(dev)             (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1912 #define IS_HSW_GT3(dev)         (IS_HASWELL(dev) && \
1913                                  ((dev)->pdev->device & 0x00F0) == 0x0020)
1914 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1915
1916 /*
1917  * The genX designation typically refers to the render engine, so render
1918  * capability related checks should use IS_GEN, while display and other checks
1919  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1920  * chips, etc.).
1921  */
1922 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
1923 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
1924 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
1925 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
1926 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
1927 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
1928 #define IS_GEN8(dev)    (INTEL_INFO(dev)->gen == 8)
1929
1930 #define RENDER_RING             (1<<RCS)
1931 #define BSD_RING                (1<<VCS)
1932 #define BLT_RING                (1<<BCS)
1933 #define VEBOX_RING              (1<<VECS)
1934 #define BSD2_RING               (1<<VCS2)
1935 #define HAS_BSD(dev)            (INTEL_INFO(dev)->ring_mask & BSD_RING)
1936 #define HAS_BSD2(dev)           (INTEL_INFO(dev)->ring_mask & BSD2_RING)
1937 #define HAS_BLT(dev)            (INTEL_INFO(dev)->ring_mask & BLT_RING)
1938 #define HAS_VEBOX(dev)          (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1939 #define HAS_LLC(dev)            (INTEL_INFO(dev)->has_llc)
1940 #define HAS_WT(dev)             ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
1941                                  to_i915(dev)->ellc_size)
1942 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
1943
1944 #define HAS_HW_CONTEXTS(dev)    (INTEL_INFO(dev)->gen >= 6)
1945 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && \
1946                                  (!IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)))
1947 #define HAS_PPGTT(dev)          (INTEL_INFO(dev)->gen >= 7 \
1948                                  && !IS_GEN8(dev))
1949 #define USES_PPGTT(dev)         intel_enable_ppgtt(dev, false)
1950 #define USES_FULL_PPGTT(dev)    intel_enable_ppgtt(dev, true)
1951
1952 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
1953 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
1954
1955 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1956 #define HAS_BROKEN_CS_TLB(dev)          (IS_I830(dev) || IS_845G(dev))
1957 /*
1958  * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1959  * even when in MSI mode. This results in spurious interrupt warnings if the
1960  * legacy irq no. is shared with another device. The kernel then disables that
1961  * interrupt source and so prevents the other device from working properly.
1962  */
1963 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1964 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1965
1966 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1967  * rows, which changed the alignment requirements and fence programming.
1968  */
1969 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1970                                                       IS_I915GM(dev)))
1971 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1972 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
1973 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
1974 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
1975 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
1976
1977 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1978 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1979 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1980
1981 #define HAS_IPS(dev)            (IS_ULT(dev) || IS_BROADWELL(dev))
1982
1983 #define HAS_DDI(dev)            (INTEL_INFO(dev)->has_ddi)
1984 #define HAS_FPGA_DBG_UNCLAIMED(dev)     (INTEL_INFO(dev)->has_fpga_dbg)
1985 #define HAS_PSR(dev)            (IS_HASWELL(dev) || IS_BROADWELL(dev))
1986 #define HAS_RUNTIME_PM(dev)     (IS_GEN6(dev) || IS_HASWELL(dev) || \
1987                                  IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
1988
1989 #define INTEL_PCH_DEVICE_ID_MASK                0xff00
1990 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
1991 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
1992 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
1993 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
1994 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
1995
1996 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1997 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1998 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1999 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2000 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2001 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2002
2003 /* DPF == dynamic parity feature */
2004 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2005 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2006
2007 #define GT_FREQUENCY_MULTIPLIER 50
2008
2009 #include "i915_trace.h"
2010
2011 extern const struct drm_ioctl_desc i915_ioctls[];
2012 extern int i915_max_ioctl;
2013
2014 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
2015 extern int i915_resume(struct drm_device *dev);
2016 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2017 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2018
2019 /* i915_params.c */
2020 struct i915_params {
2021         int modeset;
2022         int panel_ignore_lid;
2023         unsigned int powersave;
2024         int semaphores;
2025         unsigned int lvds_downclock;
2026         int lvds_channel_mode;
2027         int panel_use_ssc;
2028         int vbt_sdvo_panel_type;
2029         int enable_rc6;
2030         int enable_fbc;
2031         int enable_ppgtt;
2032         int enable_psr;
2033         unsigned int preliminary_hw_support;
2034         int disable_power_well;
2035         int enable_ips;
2036         int invert_brightness;
2037         int enable_cmd_parser;
2038         /* leave bools at the end to not create holes */
2039         bool enable_hangcheck;
2040         bool fastboot;
2041         bool prefault_disable;
2042         bool reset;
2043         bool disable_display;
2044         bool disable_vtd_wa;
2045 };
2046 extern struct i915_params i915 __read_mostly;
2047
2048                                 /* i915_dma.c */
2049 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2050 extern void i915_kernel_lost_context(struct drm_device * dev);
2051 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2052 extern int i915_driver_unload(struct drm_device *);
2053 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
2054 extern void i915_driver_lastclose(struct drm_device * dev);
2055 extern void i915_driver_preclose(struct drm_device *dev,
2056                                  struct drm_file *file_priv);
2057 extern void i915_driver_postclose(struct drm_device *dev,
2058                                   struct drm_file *file_priv);
2059 extern int i915_driver_device_is_agp(struct drm_device * dev);
2060 #ifdef CONFIG_COMPAT
2061 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2062                               unsigned long arg);
2063 #endif
2064 extern int i915_emit_box(struct drm_device *dev,
2065                          struct drm_clip_rect *box,
2066                          int DR1, int DR4);
2067 extern int intel_gpu_reset(struct drm_device *dev);
2068 extern int i915_reset(struct drm_device *dev);
2069 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2070 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2071 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2072 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2073 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2074
2075 extern void intel_console_resume(struct work_struct *work);
2076
2077 /* i915_irq.c */
2078 void i915_queue_hangcheck(struct drm_device *dev);
2079 __printf(3, 4)
2080 void i915_handle_error(struct drm_device *dev, bool wedged,
2081                        const char *fmt, ...);
2082
2083 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2084                                                         int new_delay);
2085 extern void intel_irq_init(struct drm_device *dev);
2086 extern void intel_hpd_init(struct drm_device *dev);
2087
2088 extern void intel_uncore_sanitize(struct drm_device *dev);
2089 extern void intel_uncore_early_sanitize(struct drm_device *dev);
2090 extern void intel_uncore_init(struct drm_device *dev);
2091 extern void intel_uncore_check_errors(struct drm_device *dev);
2092 extern void intel_uncore_fini(struct drm_device *dev);
2093
2094 void
2095 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2096                      u32 status_mask);
2097
2098 void
2099 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2100                       u32 status_mask);
2101
2102 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2103 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2104
2105 /* i915_gem.c */
2106 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2107                         struct drm_file *file_priv);
2108 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2109                           struct drm_file *file_priv);
2110 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2111                          struct drm_file *file_priv);
2112 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2113                           struct drm_file *file_priv);
2114 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2115                         struct drm_file *file_priv);
2116 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2117                         struct drm_file *file_priv);
2118 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2119                               struct drm_file *file_priv);
2120 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2121                              struct drm_file *file_priv);
2122 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2123                         struct drm_file *file_priv);
2124 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2125                          struct drm_file *file_priv);
2126 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2127                        struct drm_file *file_priv);
2128 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2129                          struct drm_file *file_priv);
2130 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2131                         struct drm_file *file_priv);
2132 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2133                                struct drm_file *file);
2134 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2135                                struct drm_file *file);
2136 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2137                             struct drm_file *file_priv);
2138 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2139                            struct drm_file *file_priv);
2140 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2141                            struct drm_file *file_priv);
2142 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2143                            struct drm_file *file_priv);
2144 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2145                         struct drm_file *file_priv);
2146 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2147                         struct drm_file *file_priv);
2148 int i915_gem_init_userptr(struct drm_device *dev);
2149 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2150                            struct drm_file *file);
2151 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2152                                 struct drm_file *file_priv);
2153 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2154                         struct drm_file *file_priv);
2155 void i915_gem_load(struct drm_device *dev);
2156 void *i915_gem_object_alloc(struct drm_device *dev);
2157 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2158 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2159                          const struct drm_i915_gem_object_ops *ops);
2160 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2161                                                   size_t size);
2162 void i915_init_vm(struct drm_i915_private *dev_priv,
2163                   struct i915_address_space *vm);
2164 void i915_gem_free_object(struct drm_gem_object *obj);
2165 void i915_gem_vma_destroy(struct i915_vma *vma);
2166
2167 #define PIN_MAPPABLE 0x1
2168 #define PIN_NONBLOCK 0x2
2169 #define PIN_GLOBAL 0x4
2170 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2171                                      struct i915_address_space *vm,
2172                                      uint32_t alignment,
2173                                      unsigned flags);
2174 int __must_check i915_vma_unbind(struct i915_vma *vma);
2175 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2176 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2177 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2178 void i915_gem_lastclose(struct drm_device *dev);
2179
2180 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2181                                     int *needs_clflush);
2182
2183 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2184 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2185 {
2186         struct sg_page_iter sg_iter;
2187
2188         for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2189                 return sg_page_iter_page(&sg_iter);
2190
2191         return NULL;
2192 }
2193 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2194 {
2195         BUG_ON(obj->pages == NULL);
2196         obj->pages_pin_count++;
2197 }
2198 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2199 {
2200         BUG_ON(obj->pages_pin_count == 0);
2201         obj->pages_pin_count--;
2202 }
2203
2204 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2205 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2206                          struct intel_ring_buffer *to);
2207 void i915_vma_move_to_active(struct i915_vma *vma,
2208                              struct intel_ring_buffer *ring);
2209 int i915_gem_dumb_create(struct drm_file *file_priv,
2210                          struct drm_device *dev,
2211                          struct drm_mode_create_dumb *args);
2212 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2213                       uint32_t handle, uint64_t *offset);
2214 /**
2215  * Returns true if seq1 is later than seq2.
2216  */
2217 static inline bool
2218 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2219 {
2220         return (int32_t)(seq1 - seq2) >= 0;
2221 }
2222
2223 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2224 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2225 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2226 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2227
2228 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2229 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2230
2231 struct drm_i915_gem_request *
2232 i915_gem_find_active_request(struct intel_ring_buffer *ring);
2233
2234 bool i915_gem_retire_requests(struct drm_device *dev);
2235 void i915_gem_retire_requests_ring(struct intel_ring_buffer *ring);
2236 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2237                                       bool interruptible);
2238 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2239 {
2240         return unlikely(atomic_read(&error->reset_counter)
2241                         & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2242 }
2243
2244 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2245 {
2246         return atomic_read(&error->reset_counter) & I915_WEDGED;
2247 }
2248
2249 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2250 {
2251         return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2252 }
2253
2254 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2255 {
2256         return dev_priv->gpu_error.stop_rings == 0 ||
2257                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2258 }
2259
2260 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2261 {
2262         return dev_priv->gpu_error.stop_rings == 0 ||
2263                 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2264 }
2265
2266 void i915_gem_reset(struct drm_device *dev);
2267 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2268 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2269 int __must_check i915_gem_init(struct drm_device *dev);
2270 int __must_check i915_gem_init_hw(struct drm_device *dev);
2271 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2272 void i915_gem_init_swizzling(struct drm_device *dev);
2273 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2274 int __must_check i915_gpu_idle(struct drm_device *dev);
2275 int __must_check i915_gem_suspend(struct drm_device *dev);
2276 int __i915_add_request(struct intel_ring_buffer *ring,
2277                        struct drm_file *file,
2278                        struct drm_i915_gem_object *batch_obj,
2279                        u32 *seqno);
2280 #define i915_add_request(ring, seqno) \
2281         __i915_add_request(ring, NULL, NULL, seqno)
2282 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2283                                  uint32_t seqno);
2284 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2285 int __must_check
2286 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2287                                   bool write);
2288 int __must_check
2289 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2290 int __must_check
2291 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2292                                      u32 alignment,
2293                                      struct intel_ring_buffer *pipelined);
2294 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2295 int i915_gem_attach_phys_object(struct drm_device *dev,
2296                                 struct drm_i915_gem_object *obj,
2297                                 int id,
2298                                 int align);
2299 void i915_gem_detach_phys_object(struct drm_device *dev,
2300                                  struct drm_i915_gem_object *obj);
2301 void i915_gem_free_all_phys_object(struct drm_device *dev);
2302 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2303 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2304
2305 uint32_t
2306 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2307 uint32_t
2308 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2309                             int tiling_mode, bool fenced);
2310
2311 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2312                                     enum i915_cache_level cache_level);
2313
2314 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2315                                 struct dma_buf *dma_buf);
2316
2317 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2318                                 struct drm_gem_object *gem_obj, int flags);
2319
2320 void i915_gem_restore_fences(struct drm_device *dev);
2321
2322 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2323                                   struct i915_address_space *vm);
2324 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2325 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2326                         struct i915_address_space *vm);
2327 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2328                                 struct i915_address_space *vm);
2329 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2330                                      struct i915_address_space *vm);
2331 struct i915_vma *
2332 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2333                                   struct i915_address_space *vm);
2334
2335 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2336 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2337         struct i915_vma *vma;
2338         list_for_each_entry(vma, &obj->vma_list, vma_link)
2339                 if (vma->pin_count > 0)
2340                         return true;
2341         return false;
2342 }
2343
2344 /* Some GGTT VM helpers */
2345 #define obj_to_ggtt(obj) \
2346         (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2347 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2348 {
2349         struct i915_address_space *ggtt =
2350                 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2351         return vm == ggtt;
2352 }
2353
2354 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2355 {
2356         return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2357 }
2358
2359 static inline unsigned long
2360 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2361 {
2362         return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2363 }
2364
2365 static inline unsigned long
2366 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2367 {
2368         return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2369 }
2370
2371 static inline int __must_check
2372 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2373                       uint32_t alignment,
2374                       unsigned flags)
2375 {
2376         return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2377 }
2378
2379 static inline int
2380 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2381 {
2382         return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2383 }
2384
2385 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2386
2387 /* i915_gem_context.c */
2388 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2389 int __must_check i915_gem_context_init(struct drm_device *dev);
2390 void i915_gem_context_fini(struct drm_device *dev);
2391 void i915_gem_context_reset(struct drm_device *dev);
2392 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2393 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2394 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2395 int i915_switch_context(struct intel_ring_buffer *ring,
2396                         struct i915_hw_context *to);
2397 struct i915_hw_context *
2398 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2399 void i915_gem_context_free(struct kref *ctx_ref);
2400 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2401 {
2402         kref_get(&ctx->ref);
2403 }
2404
2405 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2406 {
2407         kref_put(&ctx->ref, i915_gem_context_free);
2408 }
2409
2410 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2411 {
2412         return c->id == DEFAULT_CONTEXT_ID;
2413 }
2414
2415 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2416                                   struct drm_file *file);
2417 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2418                                    struct drm_file *file);
2419
2420 /* i915_gem_render_state.c */
2421 int i915_gem_render_state_init(struct intel_ring_buffer *ring);
2422 /* i915_gem_evict.c */
2423 int __must_check i915_gem_evict_something(struct drm_device *dev,
2424                                           struct i915_address_space *vm,
2425                                           int min_size,
2426                                           unsigned alignment,
2427                                           unsigned cache_level,
2428                                           unsigned flags);
2429 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2430 int i915_gem_evict_everything(struct drm_device *dev);
2431
2432 /* belongs in i915_gem_gtt.h */
2433 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2434 {
2435         if (INTEL_INFO(dev)->gen < 6)
2436                 intel_gtt_chipset_flush();
2437 }
2438
2439 /* i915_gem_stolen.c */
2440 int i915_gem_init_stolen(struct drm_device *dev);
2441 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2442 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2443 void i915_gem_cleanup_stolen(struct drm_device *dev);
2444 struct drm_i915_gem_object *
2445 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2446 struct drm_i915_gem_object *
2447 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2448                                                u32 stolen_offset,
2449                                                u32 gtt_offset,
2450                                                u32 size);
2451 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2452
2453 /* i915_gem_tiling.c */
2454 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2455 {
2456         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2457
2458         return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2459                 obj->tiling_mode != I915_TILING_NONE;
2460 }
2461
2462 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2463 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2464 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2465
2466 /* i915_gem_debug.c */
2467 #if WATCH_LISTS
2468 int i915_verify_lists(struct drm_device *dev);
2469 #else
2470 #define i915_verify_lists(dev) 0
2471 #endif
2472
2473 /* i915_debugfs.c */
2474 int i915_debugfs_init(struct drm_minor *minor);
2475 void i915_debugfs_cleanup(struct drm_minor *minor);
2476 #ifdef CONFIG_DEBUG_FS
2477 void intel_display_crc_init(struct drm_device *dev);
2478 #else
2479 static inline void intel_display_crc_init(struct drm_device *dev) {}
2480 #endif
2481
2482 /* i915_gpu_error.c */
2483 __printf(2, 3)
2484 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2485 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2486                             const struct i915_error_state_file_priv *error);
2487 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2488                               size_t count, loff_t pos);
2489 static inline void i915_error_state_buf_release(
2490         struct drm_i915_error_state_buf *eb)
2491 {
2492         kfree(eb->buf);
2493 }
2494 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2495                               const char *error_msg);
2496 void i915_error_state_get(struct drm_device *dev,
2497                           struct i915_error_state_file_priv *error_priv);
2498 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2499 void i915_destroy_error_state(struct drm_device *dev);
2500
2501 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2502 const char *i915_cache_level_str(int type);
2503
2504 /* i915_cmd_parser.c */
2505 int i915_cmd_parser_get_version(void);
2506 int i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2507 void i915_cmd_parser_fini_ring(struct intel_ring_buffer *ring);
2508 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2509 int i915_parse_cmds(struct intel_ring_buffer *ring,
2510                     struct drm_i915_gem_object *batch_obj,
2511                     u32 batch_start_offset,
2512                     bool is_master);
2513
2514 /* i915_suspend.c */
2515 extern int i915_save_state(struct drm_device *dev);
2516 extern int i915_restore_state(struct drm_device *dev);
2517
2518 /* i915_ums.c */
2519 void i915_save_display_reg(struct drm_device *dev);
2520 void i915_restore_display_reg(struct drm_device *dev);
2521
2522 /* i915_sysfs.c */
2523 void i915_setup_sysfs(struct drm_device *dev_priv);
2524 void i915_teardown_sysfs(struct drm_device *dev_priv);
2525
2526 /* intel_i2c.c */
2527 extern int intel_setup_gmbus(struct drm_device *dev);
2528 extern void intel_teardown_gmbus(struct drm_device *dev);
2529 static inline bool intel_gmbus_is_port_valid(unsigned port)
2530 {
2531         return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2532 }
2533
2534 extern struct i2c_adapter *intel_gmbus_get_adapter(
2535                 struct drm_i915_private *dev_priv, unsigned port);
2536 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2537 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2538 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2539 {
2540         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2541 }
2542 extern void intel_i2c_reset(struct drm_device *dev);
2543
2544 /* intel_opregion.c */
2545 struct intel_encoder;
2546 #ifdef CONFIG_ACPI
2547 extern int intel_opregion_setup(struct drm_device *dev);
2548 extern void intel_opregion_init(struct drm_device *dev);
2549 extern void intel_opregion_fini(struct drm_device *dev);
2550 extern void intel_opregion_asle_intr(struct drm_device *dev);
2551 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2552                                          bool enable);
2553 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2554                                          pci_power_t state);
2555 #else
2556 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2557 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2558 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2559 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2560 static inline int
2561 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2562 {
2563         return 0;
2564 }
2565 static inline int
2566 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2567 {
2568         return 0;
2569 }
2570 #endif
2571
2572 /* intel_acpi.c */
2573 #ifdef CONFIG_ACPI
2574 extern void intel_register_dsm_handler(void);
2575 extern void intel_unregister_dsm_handler(void);
2576 #else
2577 static inline void intel_register_dsm_handler(void) { return; }
2578 static inline void intel_unregister_dsm_handler(void) { return; }
2579 #endif /* CONFIG_ACPI */
2580
2581 /* modesetting */
2582 extern void intel_modeset_init_hw(struct drm_device *dev);
2583 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2584 extern void intel_modeset_init(struct drm_device *dev);
2585 extern void intel_modeset_gem_init(struct drm_device *dev);
2586 extern void intel_modeset_cleanup(struct drm_device *dev);
2587 extern void intel_connector_unregister(struct intel_connector *);
2588 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2589 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2590                                          bool force_restore);
2591 extern void i915_redisable_vga(struct drm_device *dev);
2592 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2593 extern bool intel_fbc_enabled(struct drm_device *dev);
2594 extern void intel_disable_fbc(struct drm_device *dev);
2595 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2596 extern void intel_init_pch_refclk(struct drm_device *dev);
2597 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2598 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2599 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2600 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2601 extern void intel_detect_pch(struct drm_device *dev);
2602 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2603 extern int intel_enable_rc6(const struct drm_device *dev);
2604
2605 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2606 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2607                         struct drm_file *file);
2608 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2609                                struct drm_file *file);
2610
2611 /* overlay */
2612 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2613 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2614                                             struct intel_overlay_error_state *error);
2615
2616 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2617 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2618                                             struct drm_device *dev,
2619                                             struct intel_display_error_state *error);
2620
2621 /* On SNB platform, before reading ring registers forcewake bit
2622  * must be set to prevent GT core from power down and stale values being
2623  * returned.
2624  */
2625 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2626 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2627 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2628
2629 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2630 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2631
2632 /* intel_sideband.c */
2633 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2634 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2635 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2636 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2637 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2638 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2639 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2640 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2641 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2642 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2643 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2644 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2645 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2646 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2647 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2648 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2649                    enum intel_sbi_destination destination);
2650 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2651                      enum intel_sbi_destination destination);
2652 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2653 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2654
2655 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2656 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2657
2658 #define FORCEWAKE_RENDER        (1 << 0)
2659 #define FORCEWAKE_MEDIA         (1 << 1)
2660 #define FORCEWAKE_ALL           (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2661
2662
2663 #define I915_READ8(reg)         dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2664 #define I915_WRITE8(reg, val)   dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2665
2666 #define I915_READ16(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2667 #define I915_WRITE16(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2668 #define I915_READ16_NOTRACE(reg)        dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2669 #define I915_WRITE16_NOTRACE(reg, val)  dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2670
2671 #define I915_READ(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2672 #define I915_WRITE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2673 #define I915_READ_NOTRACE(reg)          dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2674 #define I915_WRITE_NOTRACE(reg, val)    dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2675
2676 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2677  * will be implemented using 2 32-bit writes in an arbitrary order with
2678  * an arbitrary delay between them. This can cause the hardware to
2679  * act upon the intermediate value, possibly leading to corruption and
2680  * machine death. You have been warned.
2681  */
2682 #define I915_WRITE64(reg, val)  dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2683 #define I915_READ64(reg)        dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2684
2685 #define I915_READ64_2x32(lower_reg, upper_reg) ({                       \
2686                 u32 upper = I915_READ(upper_reg);                       \
2687                 u32 lower = I915_READ(lower_reg);                       \
2688                 u32 tmp = I915_READ(upper_reg);                         \
2689                 if (upper != tmp) {                                     \
2690                         upper = tmp;                                    \
2691                         lower = I915_READ(lower_reg);                   \
2692                         WARN_ON(I915_READ(upper_reg) != upper);         \
2693                 }                                                       \
2694                 (u64)upper << 32 | lower; })
2695
2696 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
2697 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
2698
2699 /* "Broadcast RGB" property */
2700 #define INTEL_BROADCAST_RGB_AUTO 0
2701 #define INTEL_BROADCAST_RGB_FULL 1
2702 #define INTEL_BROADCAST_RGB_LIMITED 2
2703
2704 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2705 {
2706         if (HAS_PCH_SPLIT(dev))
2707                 return CPU_VGACNTRL;
2708         else if (IS_VALLEYVIEW(dev))
2709                 return VLV_VGACNTRL;
2710         else
2711                 return VGACNTRL;
2712 }
2713
2714 static inline void __user *to_user_ptr(u64 address)
2715 {
2716         return (void __user *)(uintptr_t)address;
2717 }
2718
2719 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2720 {
2721         unsigned long j = msecs_to_jiffies(m);
2722
2723         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2724 }
2725
2726 static inline unsigned long
2727 timespec_to_jiffies_timeout(const struct timespec *value)
2728 {
2729         unsigned long j = timespec_to_jiffies(value);
2730
2731         return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2732 }
2733
2734 /*
2735  * If you need to wait X milliseconds between events A and B, but event B
2736  * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2737  * when event A happened, then just before event B you call this function and
2738  * pass the timestamp as the first argument, and X as the second argument.
2739  */
2740 static inline void
2741 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2742 {
2743         unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2744
2745         /*
2746          * Don't re-read the value of "jiffies" every time since it may change
2747          * behind our back and break the math.
2748          */
2749         tmp_jiffies = jiffies;
2750         target_jiffies = timestamp_jiffies +
2751                          msecs_to_jiffies_timeout(to_wait_ms);
2752
2753         if (time_after(target_jiffies, tmp_jiffies)) {
2754                 remaining_jiffies = target_jiffies - tmp_jiffies;
2755                 while (remaining_jiffies)
2756                         remaining_jiffies =
2757                             schedule_timeout_uninterruptible(remaining_jiffies);
2758         }
2759 }
2760
2761 #endif