1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <linux/i2c-algo-bit.h>
39 #include <linux/backlight.h>
40 #include <linux/hashtable.h>
41 #include <linux/intel-iommu.h>
42 #include <linux/kref.h>
43 #include <linux/pm_qos.h>
44 #include <linux/shmem_fs.h>
47 #include <drm/intel-gtt.h>
48 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
49 #include <drm/drm_gem.h>
50 #include <drm/drm_auth.h>
52 #include "i915_params.h"
55 #include "intel_bios.h"
56 #include "intel_dpll_mgr.h"
57 #include "intel_guc.h"
58 #include "intel_lrc.h"
59 #include "intel_ringbuffer.h"
62 #include "i915_gem_gtt.h"
63 #include "i915_gem_render_state.h"
64 #include "i915_gem_request.h"
66 #include "intel_gvt.h"
68 /* General customization:
71 #define DRIVER_NAME "i915"
72 #define DRIVER_DESC "Intel Graphics"
73 #define DRIVER_DATE "20160808"
76 /* Many gcc seem to no see through this and fall over :( */
78 #define WARN_ON(x) ({ \
79 bool __i915_warn_cond = (x); \
80 if (__builtin_constant_p(__i915_warn_cond)) \
81 BUILD_BUG_ON(__i915_warn_cond); \
82 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
84 #define WARN_ON(x) WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
88 #define WARN_ON_ONCE(x) WARN_ONCE((x), "%s", "WARN_ON_ONCE(" __stringify(x) ")")
90 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
91 (long) (x), __func__);
93 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
94 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
95 * which may not necessarily be a user visible problem. This will either
96 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
97 * enable distros and users to tailor their preferred amount of i915 abrt
100 #define I915_STATE_WARN(condition, format...) ({ \
101 int __ret_warn_on = !!(condition); \
102 if (unlikely(__ret_warn_on)) \
103 if (!WARN(i915.verbose_state_checks, format)) \
105 unlikely(__ret_warn_on); \
108 #define I915_STATE_WARN_ON(x) \
109 I915_STATE_WARN((x), "%s", "WARN_ON(" __stringify(x) ")")
111 bool __i915_inject_load_failure(const char *func
, int line
);
112 #define i915_inject_load_failure() \
113 __i915_inject_load_failure(__func__, __LINE__)
115 static inline const char *yesno(bool v
)
117 return v
? "yes" : "no";
120 static inline const char *onoff(bool v
)
122 return v
? "on" : "off";
131 I915_MAX_PIPES
= _PIPE_EDP
133 #define pipe_name(p) ((p) + 'A')
145 static inline const char *transcoder_name(enum transcoder transcoder
)
147 switch (transcoder
) {
156 case TRANSCODER_DSI_A
:
158 case TRANSCODER_DSI_C
:
165 static inline bool transcoder_is_dsi(enum transcoder transcoder
)
167 return transcoder
== TRANSCODER_DSI_A
|| transcoder
== TRANSCODER_DSI_C
;
171 * I915_MAX_PLANES in the enum below is the maximum (across all platforms)
172 * number of planes per CRTC. Not all platforms really have this many planes,
173 * which means some arrays of size I915_MAX_PLANES may have unused entries
174 * between the topmost sprite plane and the cursor plane.
183 #define plane_name(p) ((p) + 'A')
185 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
195 #define port_name(p) ((p) + 'A')
197 #define I915_NUM_PHYS_VLV 2
209 enum intel_display_power_domain
{
213 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
214 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
215 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
216 POWER_DOMAIN_TRANSCODER_A
,
217 POWER_DOMAIN_TRANSCODER_B
,
218 POWER_DOMAIN_TRANSCODER_C
,
219 POWER_DOMAIN_TRANSCODER_EDP
,
220 POWER_DOMAIN_TRANSCODER_DSI_A
,
221 POWER_DOMAIN_TRANSCODER_DSI_C
,
222 POWER_DOMAIN_PORT_DDI_A_LANES
,
223 POWER_DOMAIN_PORT_DDI_B_LANES
,
224 POWER_DOMAIN_PORT_DDI_C_LANES
,
225 POWER_DOMAIN_PORT_DDI_D_LANES
,
226 POWER_DOMAIN_PORT_DDI_E_LANES
,
227 POWER_DOMAIN_PORT_DSI
,
228 POWER_DOMAIN_PORT_CRT
,
229 POWER_DOMAIN_PORT_OTHER
,
238 POWER_DOMAIN_MODESET
,
244 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
245 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
246 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
247 #define POWER_DOMAIN_TRANSCODER(tran) \
248 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
249 (tran) + POWER_DOMAIN_TRANSCODER_A)
253 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
265 #define for_each_hpd_pin(__pin) \
266 for ((__pin) = (HPD_NONE + 1); (__pin) < HPD_NUM_PINS; (__pin)++)
268 struct i915_hotplug
{
269 struct work_struct hotplug_work
;
272 unsigned long last_jiffies
;
277 HPD_MARK_DISABLED
= 2
279 } stats
[HPD_NUM_PINS
];
281 struct delayed_work reenable_work
;
283 struct intel_digital_port
*irq_port
[I915_MAX_PORTS
];
286 struct work_struct dig_port_work
;
288 struct work_struct poll_init_work
;
292 * if we get a HPD irq from DP and a HPD irq from non-DP
293 * the non-DP HPD could block the workqueue on a mode config
294 * mutex getting, that userspace may have taken. However
295 * userspace is waiting on the DP workqueue to run which is
296 * blocked behind the non-DP one.
298 struct workqueue_struct
*dp_wq
;
301 #define I915_GEM_GPU_DOMAINS \
302 (I915_GEM_DOMAIN_RENDER | \
303 I915_GEM_DOMAIN_SAMPLER | \
304 I915_GEM_DOMAIN_COMMAND | \
305 I915_GEM_DOMAIN_INSTRUCTION | \
306 I915_GEM_DOMAIN_VERTEX)
308 #define for_each_pipe(__dev_priv, __p) \
309 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
310 #define for_each_pipe_masked(__dev_priv, __p, __mask) \
311 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++) \
312 for_each_if ((__mask) & (1 << (__p)))
313 #define for_each_plane(__dev_priv, __pipe, __p) \
315 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
317 #define for_each_sprite(__dev_priv, __p, __s) \
319 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
322 #define for_each_port_masked(__port, __ports_mask) \
323 for ((__port) = PORT_A; (__port) < I915_MAX_PORTS; (__port)++) \
324 for_each_if ((__ports_mask) & (1 << (__port)))
326 #define for_each_crtc(dev, crtc) \
327 list_for_each_entry(crtc, &(dev)->mode_config.crtc_list, head)
329 #define for_each_intel_plane(dev, intel_plane) \
330 list_for_each_entry(intel_plane, \
331 &(dev)->mode_config.plane_list, \
334 #define for_each_intel_plane_mask(dev, intel_plane, plane_mask) \
335 list_for_each_entry(intel_plane, \
336 &(dev)->mode_config.plane_list, \
338 for_each_if ((plane_mask) & \
339 (1 << drm_plane_index(&intel_plane->base)))
341 #define for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) \
342 list_for_each_entry(intel_plane, \
343 &(dev)->mode_config.plane_list, \
345 for_each_if ((intel_plane)->pipe == (intel_crtc)->pipe)
347 #define for_each_intel_crtc(dev, intel_crtc) \
348 list_for_each_entry(intel_crtc, \
349 &(dev)->mode_config.crtc_list, \
352 #define for_each_intel_crtc_mask(dev, intel_crtc, crtc_mask) \
353 list_for_each_entry(intel_crtc, \
354 &(dev)->mode_config.crtc_list, \
356 for_each_if ((crtc_mask) & (1 << drm_crtc_index(&intel_crtc->base)))
358 #define for_each_intel_encoder(dev, intel_encoder) \
359 list_for_each_entry(intel_encoder, \
360 &(dev)->mode_config.encoder_list, \
363 #define for_each_intel_connector(dev, intel_connector) \
364 list_for_each_entry(intel_connector, \
365 &(dev)->mode_config.connector_list, \
368 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
369 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
370 for_each_if ((intel_encoder)->base.crtc == (__crtc))
372 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
373 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
374 for_each_if ((intel_connector)->base.encoder == (__encoder))
376 #define for_each_power_domain(domain, mask) \
377 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
378 for_each_if ((1 << (domain)) & (mask))
380 struct drm_i915_private
;
381 struct i915_mm_struct
;
382 struct i915_mmu_object
;
384 struct drm_i915_file_private
{
385 struct drm_i915_private
*dev_priv
;
386 struct drm_file
*file
;
390 struct list_head request_list
;
391 /* 20ms is a fairly arbitrary limit (greater than the average frame time)
392 * chosen to prevent the CPU getting more than a frame ahead of the GPU
393 * (when using lax throttling for the frontbuffer). We also use it to
394 * offer free GPU waitboosts for severely congested workloads.
396 #define DRM_I915_THROTTLE_JIFFIES msecs_to_jiffies(20)
398 struct idr context_idr
;
400 struct intel_rps_client
{
401 struct list_head link
;
405 unsigned int bsd_engine
;
408 /* Used by dp and fdi links */
409 struct intel_link_m_n
{
417 void intel_link_compute_m_n(int bpp
, int nlanes
,
418 int pixel_clock
, int link_clock
,
419 struct intel_link_m_n
*m_n
);
421 /* Interface history:
424 * 1.2: Add Power Management
425 * 1.3: Add vblank support
426 * 1.4: Fix cmdbuffer path, add heap destroy
427 * 1.5: Add vblank pipe configuration
428 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
429 * - Support vertical blank on secondary display pipe
431 #define DRIVER_MAJOR 1
432 #define DRIVER_MINOR 6
433 #define DRIVER_PATCHLEVEL 0
435 struct opregion_header
;
436 struct opregion_acpi
;
437 struct opregion_swsci
;
438 struct opregion_asle
;
440 struct intel_opregion
{
441 struct opregion_header
*header
;
442 struct opregion_acpi
*acpi
;
443 struct opregion_swsci
*swsci
;
444 u32 swsci_gbda_sub_functions
;
445 u32 swsci_sbcb_sub_functions
;
446 struct opregion_asle
*asle
;
451 struct work_struct asle_work
;
453 #define OPREGION_SIZE (8*1024)
455 struct intel_overlay
;
456 struct intel_overlay_error_state
;
458 #define I915_FENCE_REG_NONE -1
459 #define I915_MAX_NUM_FENCES 32
460 /* 32 fences + sign bit for FENCE_REG_NONE */
461 #define I915_MAX_NUM_FENCE_BITS 6
463 struct drm_i915_fence_reg
{
464 struct list_head lru_list
;
465 struct drm_i915_gem_object
*obj
;
469 struct sdvo_device_mapping
{
478 struct intel_connector
;
479 struct intel_encoder
;
480 struct intel_crtc_state
;
481 struct intel_initial_plane_config
;
486 struct drm_i915_display_funcs
{
487 int (*get_display_clock_speed
)(struct drm_device
*dev
);
488 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
489 int (*compute_pipe_wm
)(struct intel_crtc_state
*cstate
);
490 int (*compute_intermediate_wm
)(struct drm_device
*dev
,
491 struct intel_crtc
*intel_crtc
,
492 struct intel_crtc_state
*newstate
);
493 void (*initial_watermarks
)(struct intel_crtc_state
*cstate
);
494 void (*optimize_watermarks
)(struct intel_crtc_state
*cstate
);
495 int (*compute_global_watermarks
)(struct drm_atomic_state
*state
);
496 void (*update_wm
)(struct drm_crtc
*crtc
);
497 int (*modeset_calc_cdclk
)(struct drm_atomic_state
*state
);
498 void (*modeset_commit_cdclk
)(struct drm_atomic_state
*state
);
499 /* Returns the active state of the crtc, and if the crtc is active,
500 * fills out the pipe-config with the hw state. */
501 bool (*get_pipe_config
)(struct intel_crtc
*,
502 struct intel_crtc_state
*);
503 void (*get_initial_plane_config
)(struct intel_crtc
*,
504 struct intel_initial_plane_config
*);
505 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
506 struct intel_crtc_state
*crtc_state
);
507 void (*crtc_enable
)(struct drm_crtc
*crtc
);
508 void (*crtc_disable
)(struct drm_crtc
*crtc
);
509 void (*audio_codec_enable
)(struct drm_connector
*connector
,
510 struct intel_encoder
*encoder
,
511 const struct drm_display_mode
*adjusted_mode
);
512 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
513 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
514 void (*init_clock_gating
)(struct drm_device
*dev
);
515 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
516 struct drm_framebuffer
*fb
,
517 struct drm_i915_gem_object
*obj
,
518 struct drm_i915_gem_request
*req
,
520 void (*hpd_irq_setup
)(struct drm_i915_private
*dev_priv
);
521 /* clock updates for mode set */
523 /* render clock increase/decrease */
524 /* display clock increase/decrease */
525 /* pll clock increase/decrease */
527 void (*load_csc_matrix
)(struct drm_crtc_state
*crtc_state
);
528 void (*load_luts
)(struct drm_crtc_state
*crtc_state
);
531 enum forcewake_domain_id
{
532 FW_DOMAIN_ID_RENDER
= 0,
533 FW_DOMAIN_ID_BLITTER
,
539 enum forcewake_domains
{
540 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
541 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
542 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
543 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
548 #define FW_REG_READ (1)
549 #define FW_REG_WRITE (2)
551 enum forcewake_domains
552 intel_uncore_forcewake_for_reg(struct drm_i915_private
*dev_priv
,
553 i915_reg_t reg
, unsigned int op
);
555 struct intel_uncore_funcs
{
556 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
557 enum forcewake_domains domains
);
558 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
559 enum forcewake_domains domains
);
561 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
562 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
563 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
564 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
, bool trace
);
566 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
567 uint8_t val
, bool trace
);
568 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
569 uint16_t val
, bool trace
);
570 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
571 uint32_t val
, bool trace
);
572 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, i915_reg_t r
,
573 uint64_t val
, bool trace
);
576 struct intel_uncore
{
577 spinlock_t lock
; /** lock is also taken in irq contexts. */
579 struct intel_uncore_funcs funcs
;
582 enum forcewake_domains fw_domains
;
584 struct intel_uncore_forcewake_domain
{
585 struct drm_i915_private
*i915
;
586 enum forcewake_domain_id id
;
587 enum forcewake_domains mask
;
589 struct hrtimer timer
;
596 } fw_domain
[FW_DOMAIN_ID_COUNT
];
598 int unclaimed_mmio_check
;
601 /* Iterate over initialised fw domains */
602 #define for_each_fw_domain_masked(domain__, mask__, dev_priv__) \
603 for ((domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
604 (domain__) < &(dev_priv__)->uncore.fw_domain[FW_DOMAIN_ID_COUNT]; \
606 for_each_if ((mask__) & (domain__)->mask)
608 #define for_each_fw_domain(domain__, dev_priv__) \
609 for_each_fw_domain_masked(domain__, FORCEWAKE_ALL, dev_priv__)
611 #define CSR_VERSION(major, minor) ((major) << 16 | (minor))
612 #define CSR_VERSION_MAJOR(version) ((version) >> 16)
613 #define CSR_VERSION_MINOR(version) ((version) & 0xffff)
616 struct work_struct work
;
618 uint32_t *dmc_payload
;
619 uint32_t dmc_fw_size
;
622 i915_reg_t mmioaddr
[8];
623 uint32_t mmiodata
[8];
625 uint32_t allowed_dc_mask
;
628 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
629 func(is_mobile) sep \
632 func(is_i945gm) sep \
634 func(need_gfx_hws) sep \
636 func(is_pineview) sep \
637 func(is_broadwater) sep \
638 func(is_crestline) sep \
639 func(is_ivybridge) sep \
640 func(is_valleyview) sep \
641 func(is_cherryview) sep \
642 func(is_haswell) sep \
643 func(is_broadwell) sep \
644 func(is_skylake) sep \
645 func(is_broxton) sep \
646 func(is_kabylake) sep \
647 func(is_preliminary) sep \
649 func(has_pipe_cxsr) sep \
650 func(has_hotplug) sep \
651 func(cursor_needs_physical) sep \
652 func(has_overlay) sep \
653 func(overlay_needs_physical) sep \
654 func(supports_tv) sep \
656 func(has_snoop) sep \
658 func(has_fpga_dbg) sep \
661 #define DEFINE_FLAG(name) u8 name:1
662 #define SEP_SEMICOLON ;
664 struct intel_device_info
{
665 u32 display_mmio_offset
;
668 u8 num_sprites
[I915_MAX_PIPES
];
671 u8 ring_mask
; /* Rings supported by the HW */
673 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
674 /* Register offsets for the various display pipes and transcoders */
675 int pipe_offsets
[I915_MAX_TRANSCODERS
];
676 int trans_offsets
[I915_MAX_TRANSCODERS
];
677 int palette_offsets
[I915_MAX_PIPES
];
678 int cursor_offsets
[I915_MAX_PIPES
];
680 /* Slice/subslice/EU info */
683 u8 subslice_per_slice
;
687 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
690 u8 has_subslice_pg
:1;
694 u16 degamma_lut_size
;
702 struct intel_display_error_state
;
704 struct drm_i915_error_state
{
713 struct intel_device_info device_info
;
715 /* Generic register state */
723 u32 error
; /* gen6+ */
724 u32 err_int
; /* gen7 */
725 u32 fault_data0
; /* gen8, gen9 */
726 u32 fault_data1
; /* gen8, gen9 */
732 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
733 u64 fence
[I915_MAX_NUM_FENCES
];
734 struct intel_overlay_error_state
*overlay
;
735 struct intel_display_error_state
*display
;
736 struct drm_i915_error_object
*semaphore
;
738 struct drm_i915_error_engine
{
740 /* Software tracked state */
744 enum intel_engine_hangcheck_action hangcheck_action
;
745 struct i915_address_space
*vm
;
748 /* our own tracking of ring head and tail */
753 u32 semaphore_seqno
[I915_NUM_ENGINES
- 1];
772 u32 rc_psmi
; /* sleep state */
773 u32 semaphore_mboxes
[I915_NUM_ENGINES
- 1];
775 struct drm_i915_error_object
{
779 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
781 struct drm_i915_error_object
*wa_ctx
;
783 struct drm_i915_error_request
{
790 struct drm_i915_error_waiter
{
791 char comm
[TASK_COMM_LEN
];
805 char comm
[TASK_COMM_LEN
];
806 } engine
[I915_NUM_ENGINES
];
808 struct drm_i915_error_buffer
{
811 u32 rseqno
[I915_NUM_ENGINES
], wseqno
;
815 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
822 } *active_bo
[I915_NUM_ENGINES
], *pinned_bo
;
823 u32 active_bo_count
[I915_NUM_ENGINES
], pinned_bo_count
;
824 struct i915_address_space
*active_vm
[I915_NUM_ENGINES
];
827 enum i915_cache_level
{
829 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
830 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
831 caches, eg sampler/render caches, and the
832 large Last-Level-Cache. LLC is coherent with
833 the CPU, but L3 is only visible to the GPU. */
834 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
837 struct i915_ctx_hang_stats
{
838 /* This context had batch pending when hang was declared */
839 unsigned batch_pending
;
841 /* This context had batch active when hang was declared */
842 unsigned batch_active
;
844 /* Time when this context was last blamed for a GPU reset */
845 unsigned long guilty_ts
;
847 /* If the contexts causes a second GPU hang within this time,
848 * it is permanently banned from submitting any more work.
850 unsigned long ban_period_seconds
;
852 /* This context is banned to submit more work */
856 /* This must match up with the value previously used for execbuf2.rsvd1. */
857 #define DEFAULT_CONTEXT_HANDLE 0
860 * struct i915_gem_context - as the name implies, represents a context.
861 * @ref: reference count.
862 * @user_handle: userspace tracking identity for this context.
863 * @remap_slice: l3 row remapping information.
864 * @flags: context specific flags:
865 * CONTEXT_NO_ZEROMAP: do not allow mapping things to page 0.
866 * @file_priv: filp associated with this context (NULL for global default
868 * @hang_stats: information about the role of this context in possible GPU
870 * @ppgtt: virtual memory space used by this context.
871 * @legacy_hw_ctx: render context backing object and whether it is correctly
872 * initialized (legacy ring submission mechanism only).
873 * @link: link in the global list of contexts.
875 * Contexts are memory images used by the hardware to store copies of their
878 struct i915_gem_context
{
880 struct drm_i915_private
*i915
;
881 struct drm_i915_file_private
*file_priv
;
882 struct i915_hw_ppgtt
*ppgtt
;
884 struct i915_ctx_hang_stats hang_stats
;
886 /* Unique identifier for this context, used by the hw for tracking */
888 #define CONTEXT_NO_ZEROMAP BIT(0)
889 #define CONTEXT_NO_ERROR_CAPTURE BIT(1)
895 struct intel_context
{
896 struct i915_vma
*state
;
897 struct intel_ring
*ring
;
898 uint32_t *lrc_reg_state
;
902 } engine
[I915_NUM_ENGINES
];
905 struct atomic_notifier_head status_notifier
;
906 bool execlists_force_single_submission
;
908 struct list_head link
;
923 /* This is always the inner lock when overlapping with struct_mutex and
924 * it's the outer lock when overlapping with stolen_lock. */
927 unsigned int possible_framebuffer_bits
;
928 unsigned int busy_bits
;
929 unsigned int visible_pipes_mask
;
930 struct intel_crtc
*crtc
;
932 struct drm_mm_node compressed_fb
;
933 struct drm_mm_node
*compressed_llb
;
940 struct intel_fbc_state_cache
{
942 unsigned int mode_flags
;
943 uint32_t hsw_bdw_pixel_rate
;
947 unsigned int rotation
;
955 uint32_t pixel_format
;
958 unsigned int tiling_mode
;
962 struct intel_fbc_reg_params
{
966 unsigned int fence_y_offset
;
971 uint32_t pixel_format
;
979 struct intel_fbc_work
{
981 u32 scheduled_vblank
;
982 struct work_struct work
;
985 const char *no_fbc_reason
;
989 * HIGH_RR is the highest eDP panel refresh rate read from EDID
990 * LOW_RR is the lowest eDP panel refresh rate found from EDID
991 * parsing for same resolution.
993 enum drrs_refresh_rate_type
{
996 DRRS_MAX_RR
, /* RR count */
999 enum drrs_support_type
{
1000 DRRS_NOT_SUPPORTED
= 0,
1001 STATIC_DRRS_SUPPORT
= 1,
1002 SEAMLESS_DRRS_SUPPORT
= 2
1008 struct delayed_work work
;
1009 struct intel_dp
*dp
;
1010 unsigned busy_frontbuffer_bits
;
1011 enum drrs_refresh_rate_type refresh_rate_type
;
1012 enum drrs_support_type type
;
1019 struct intel_dp
*enabled
;
1021 struct delayed_work work
;
1022 unsigned busy_frontbuffer_bits
;
1024 bool aux_frame_sync
;
1029 PCH_NONE
= 0, /* No PCH present */
1030 PCH_IBX
, /* Ibexpeak PCH */
1031 PCH_CPT
, /* Cougarpoint PCH */
1032 PCH_LPT
, /* Lynxpoint PCH */
1033 PCH_SPT
, /* Sunrisepoint PCH */
1034 PCH_KBP
, /* Kabypoint PCH */
1038 enum intel_sbi_destination
{
1043 #define QUIRK_PIPEA_FORCE (1<<0)
1044 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
1045 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
1046 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
1047 #define QUIRK_PIPEB_FORCE (1<<4)
1048 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
1051 struct intel_fbc_work
;
1053 struct intel_gmbus
{
1054 struct i2c_adapter adapter
;
1055 #define GMBUS_FORCE_BIT_RETRY (1U << 31)
1058 i915_reg_t gpio_reg
;
1059 struct i2c_algo_bit_data bit_algo
;
1060 struct drm_i915_private
*dev_priv
;
1063 struct i915_suspend_saved_registers
{
1065 u32 saveFBC_CONTROL
;
1066 u32 saveCACHE_MODE_0
;
1067 u32 saveMI_ARB_STATE
;
1071 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
1072 u32 savePCH_PORT_HOTPLUG
;
1076 struct vlv_s0ix_state
{
1083 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
1084 u32 media_max_req_count
;
1085 u32 gfx_max_req_count
;
1111 u32 rp_down_timeout
;
1117 /* Display 1 CZ domain */
1122 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1124 /* GT SA CZ domain */
1131 /* Display 2 CZ domain */
1135 u32 clock_gate_dis2
;
1138 struct intel_rps_ei
{
1144 struct intel_gen6_power_mgmt
{
1146 * work, interrupts_enabled and pm_iir are protected by
1147 * dev_priv->irq_lock
1149 struct work_struct work
;
1150 bool interrupts_enabled
;
1155 /* Frequencies are stored in potentially platform dependent multiples.
1156 * In other words, *_freq needs to be multiplied by X to be interesting.
1157 * Soft limits are those which are used for the dynamic reclocking done
1158 * by the driver (raise frequencies under heavy loads, and lower for
1159 * lighter loads). Hard limits are those imposed by the hardware.
1161 * A distinction is made for overclocking, which is never enabled by
1162 * default, and is considered to be above the hard limit if it's
1165 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1166 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1167 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1168 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1169 u8 min_freq
; /* AKA RPn. Minimum frequency */
1170 u8 boost_freq
; /* Frequency to request when wait boosting */
1171 u8 idle_freq
; /* Frequency to request when we are idle */
1172 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1173 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1174 u8 rp0_freq
; /* Non-overclocked max frequency. */
1175 u16 gpll_ref_freq
; /* vlv/chv GPLL reference frequency */
1177 u8 up_threshold
; /* Current %busy required to uplock */
1178 u8 down_threshold
; /* Current %busy required to downclock */
1181 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1183 spinlock_t client_lock
;
1184 struct list_head clients
;
1188 struct delayed_work autoenable_work
;
1191 /* manual wa residency calculations */
1192 struct intel_rps_ei up_ei
, down_ei
;
1195 * Protects RPS/RC6 register access and PCU communication.
1196 * Must be taken after struct_mutex if nested. Note that
1197 * this lock may be held for long periods of time when
1198 * talking to hw - so only take it when talking to hw!
1200 struct mutex hw_lock
;
1203 /* defined intel_pm.c */
1204 extern spinlock_t mchdev_lock
;
1206 struct intel_ilk_power_mgmt
{
1214 unsigned long last_time1
;
1215 unsigned long chipset_power
;
1218 unsigned long gfx_power
;
1225 struct drm_i915_private
;
1226 struct i915_power_well
;
1228 struct i915_power_well_ops
{
1230 * Synchronize the well's hw state to match the current sw state, for
1231 * example enable/disable it based on the current refcount. Called
1232 * during driver init and resume time, possibly after first calling
1233 * the enable/disable handlers.
1235 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1236 struct i915_power_well
*power_well
);
1238 * Enable the well and resources that depend on it (for example
1239 * interrupts located on the well). Called after the 0->1 refcount
1242 void (*enable
)(struct drm_i915_private
*dev_priv
,
1243 struct i915_power_well
*power_well
);
1245 * Disable the well and resources that depend on it. Called after
1246 * the 1->0 refcount transition.
1248 void (*disable
)(struct drm_i915_private
*dev_priv
,
1249 struct i915_power_well
*power_well
);
1250 /* Returns the hw enabled state. */
1251 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1252 struct i915_power_well
*power_well
);
1255 /* Power well structure for haswell */
1256 struct i915_power_well
{
1259 /* power well enable/disable usage count */
1261 /* cached hw enabled state */
1263 unsigned long domains
;
1265 const struct i915_power_well_ops
*ops
;
1268 struct i915_power_domains
{
1270 * Power wells needed for initialization at driver init and suspend
1271 * time are on. They are kept on until after the first modeset.
1275 int power_well_count
;
1278 int domain_use_count
[POWER_DOMAIN_NUM
];
1279 struct i915_power_well
*power_wells
;
1282 #define MAX_L3_SLICES 2
1283 struct intel_l3_parity
{
1284 u32
*remap_info
[MAX_L3_SLICES
];
1285 struct work_struct error_work
;
1289 struct i915_gem_mm
{
1290 /** Memory allocator for GTT stolen memory */
1291 struct drm_mm stolen
;
1292 /** Protects the usage of the GTT stolen memory allocator. This is
1293 * always the inner lock when overlapping with struct_mutex. */
1294 struct mutex stolen_lock
;
1296 /** List of all objects in gtt_space. Used to restore gtt
1297 * mappings on resume */
1298 struct list_head bound_list
;
1300 * List of objects which are not bound to the GTT (thus
1301 * are idle and not used by the GPU) but still have
1302 * (presumably uncached) pages still attached.
1304 struct list_head unbound_list
;
1306 /** Usable portion of the GTT for GEM */
1307 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1309 /** PPGTT used for aliasing the PPGTT with the GTT */
1310 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1312 struct notifier_block oom_notifier
;
1313 struct notifier_block vmap_notifier
;
1314 struct shrinker shrinker
;
1316 /** LRU list of objects with fence regs on them. */
1317 struct list_head fence_list
;
1320 * Are we in a non-interruptible section of code like
1325 /* the indicator for dispatch video commands on two BSD rings */
1326 unsigned int bsd_engine_dispatch_index
;
1328 /** Bit 6 swizzling required for X tiling */
1329 uint32_t bit_6_swizzle_x
;
1330 /** Bit 6 swizzling required for Y tiling */
1331 uint32_t bit_6_swizzle_y
;
1333 /* accounting, useful for userland debugging */
1334 spinlock_t object_stat_lock
;
1335 size_t object_memory
;
1339 struct drm_i915_error_state_buf
{
1340 struct drm_i915_private
*i915
;
1349 struct i915_error_state_file_priv
{
1350 struct drm_device
*dev
;
1351 struct drm_i915_error_state
*error
;
1354 struct i915_gpu_error
{
1355 /* For hangcheck timer */
1356 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1357 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1358 /* Hang gpu twice in this window and your context gets banned */
1359 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1361 struct delayed_work hangcheck_work
;
1363 /* For reset and error_state handling. */
1365 /* Protected by the above dev->gpu_error.lock. */
1366 struct drm_i915_error_state
*first_error
;
1368 unsigned long missed_irq_rings
;
1371 * State variable controlling the reset flow and count
1373 * This is a counter which gets incremented when reset is triggered,
1374 * and again when reset has been handled. So odd values (lowest bit set)
1375 * means that reset is in progress and even values that
1376 * (reset_counter >> 1):th reset was successfully completed.
1378 * If reset is not completed succesfully, the I915_WEDGE bit is
1379 * set meaning that hardware is terminally sour and there is no
1380 * recovery. All waiters on the reset_queue will be woken when
1383 * This counter is used by the wait_seqno code to notice that reset
1384 * event happened and it needs to restart the entire ioctl (since most
1385 * likely the seqno it waited for won't ever signal anytime soon).
1387 * This is important for lock-free wait paths, where no contended lock
1388 * naturally enforces the correct ordering between the bail-out of the
1389 * waiter and the gpu reset work code.
1391 atomic_t reset_counter
;
1393 #define I915_RESET_IN_PROGRESS_FLAG 1
1394 #define I915_WEDGED (1 << 31)
1397 * Waitqueue to signal when a hang is detected. Used to for waiters
1398 * to release the struct_mutex for the reset to procede.
1400 wait_queue_head_t wait_queue
;
1403 * Waitqueue to signal when the reset has completed. Used by clients
1404 * that wait for dev_priv->mm.wedged to settle.
1406 wait_queue_head_t reset_queue
;
1408 /* For missed irq/seqno simulation. */
1409 unsigned long test_irq_rings
;
1412 enum modeset_restore
{
1413 MODESET_ON_LID_OPEN
,
1418 #define DP_AUX_A 0x40
1419 #define DP_AUX_B 0x10
1420 #define DP_AUX_C 0x20
1421 #define DP_AUX_D 0x30
1423 #define DDC_PIN_B 0x05
1424 #define DDC_PIN_C 0x04
1425 #define DDC_PIN_D 0x06
1427 struct ddi_vbt_port_info
{
1429 * This is an index in the HDMI/DVI DDI buffer translation table.
1430 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1431 * populate this field.
1433 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1434 uint8_t hdmi_level_shift
;
1436 uint8_t supports_dvi
:1;
1437 uint8_t supports_hdmi
:1;
1438 uint8_t supports_dp
:1;
1440 uint8_t alternate_aux_channel
;
1441 uint8_t alternate_ddc_pin
;
1443 uint8_t dp_boost_level
;
1444 uint8_t hdmi_boost_level
;
1447 enum psr_lines_to_wait
{
1448 PSR_0_LINES_TO_WAIT
= 0,
1450 PSR_4_LINES_TO_WAIT
,
1454 struct intel_vbt_data
{
1455 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1456 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1459 unsigned int int_tv_support
:1;
1460 unsigned int lvds_dither
:1;
1461 unsigned int lvds_vbt
:1;
1462 unsigned int int_crt_support
:1;
1463 unsigned int lvds_use_ssc
:1;
1464 unsigned int display_clock_mode
:1;
1465 unsigned int fdi_rx_polarity_inverted
:1;
1466 unsigned int panel_type
:4;
1468 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1470 enum drrs_support_type drrs_type
;
1481 struct edp_power_seq pps
;
1486 bool require_aux_wakeup
;
1488 enum psr_lines_to_wait lines_to_wait
;
1489 int tp1_wakeup_time
;
1490 int tp2_tp3_wakeup_time
;
1496 bool active_low_pwm
;
1497 u8 min_brightness
; /* min_brightness/255 of max */
1498 enum intel_backlight_type type
;
1504 struct mipi_config
*config
;
1505 struct mipi_pps_data
*pps
;
1509 const u8
*sequence
[MIPI_SEQ_MAX
];
1515 union child_device_config
*child_dev
;
1517 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1518 struct sdvo_device_mapping sdvo_mappings
[2];
1521 enum intel_ddb_partitioning
{
1523 INTEL_DDB_PART_5_6
, /* IVB+ */
1526 struct intel_wm_level
{
1534 struct ilk_wm_values
{
1535 uint32_t wm_pipe
[3];
1537 uint32_t wm_lp_spr
[3];
1538 uint32_t wm_linetime
[3];
1540 enum intel_ddb_partitioning partitioning
;
1543 struct vlv_pipe_wm
{
1554 struct vlv_wm_values
{
1555 struct vlv_pipe_wm pipe
[3];
1556 struct vlv_sr_wm sr
;
1566 struct skl_ddb_entry
{
1567 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1570 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1572 return entry
->end
- entry
->start
;
1575 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1576 const struct skl_ddb_entry
*e2
)
1578 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1584 struct skl_ddb_allocation
{
1585 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1586 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
]; /* packed/uv */
1587 struct skl_ddb_entry y_plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1590 struct skl_wm_values
{
1591 unsigned dirty_pipes
;
1592 struct skl_ddb_allocation ddb
;
1593 uint32_t wm_linetime
[I915_MAX_PIPES
];
1594 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1595 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1598 struct skl_wm_level
{
1599 bool plane_en
[I915_MAX_PLANES
];
1600 uint16_t plane_res_b
[I915_MAX_PLANES
];
1601 uint8_t plane_res_l
[I915_MAX_PLANES
];
1605 * This struct helps tracking the state needed for runtime PM, which puts the
1606 * device in PCI D3 state. Notice that when this happens, nothing on the
1607 * graphics device works, even register access, so we don't get interrupts nor
1610 * Every piece of our code that needs to actually touch the hardware needs to
1611 * either call intel_runtime_pm_get or call intel_display_power_get with the
1612 * appropriate power domain.
1614 * Our driver uses the autosuspend delay feature, which means we'll only really
1615 * suspend if we stay with zero refcount for a certain amount of time. The
1616 * default value is currently very conservative (see intel_runtime_pm_enable), but
1617 * it can be changed with the standard runtime PM files from sysfs.
1619 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1620 * goes back to false exactly before we reenable the IRQs. We use this variable
1621 * to check if someone is trying to enable/disable IRQs while they're supposed
1622 * to be disabled. This shouldn't happen and we'll print some error messages in
1625 * For more, read the Documentation/power/runtime_pm.txt.
1627 struct i915_runtime_pm
{
1628 atomic_t wakeref_count
;
1629 atomic_t atomic_seq
;
1634 enum intel_pipe_crc_source
{
1635 INTEL_PIPE_CRC_SOURCE_NONE
,
1636 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1637 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1638 INTEL_PIPE_CRC_SOURCE_PF
,
1639 INTEL_PIPE_CRC_SOURCE_PIPE
,
1640 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1641 INTEL_PIPE_CRC_SOURCE_TV
,
1642 INTEL_PIPE_CRC_SOURCE_DP_B
,
1643 INTEL_PIPE_CRC_SOURCE_DP_C
,
1644 INTEL_PIPE_CRC_SOURCE_DP_D
,
1645 INTEL_PIPE_CRC_SOURCE_AUTO
,
1646 INTEL_PIPE_CRC_SOURCE_MAX
,
1649 struct intel_pipe_crc_entry
{
1654 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1655 struct intel_pipe_crc
{
1657 bool opened
; /* exclusive access to the result file */
1658 struct intel_pipe_crc_entry
*entries
;
1659 enum intel_pipe_crc_source source
;
1661 wait_queue_head_t wq
;
1664 struct i915_frontbuffer_tracking
{
1668 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1675 struct i915_wa_reg
{
1678 /* bitmask representing WA bits */
1683 * RING_MAX_NONPRIV_SLOTS is per-engine but at this point we are only
1684 * allowing it for RCS as we don't foresee any requirement of having
1685 * a whitelist for other engines. When it is really required for
1686 * other engines then the limit need to be increased.
1688 #define I915_MAX_WA_REGS (16 + RING_MAX_NONPRIV_SLOTS)
1690 struct i915_workarounds
{
1691 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1693 u32 hw_whitelist_count
[I915_NUM_ENGINES
];
1696 struct i915_virtual_gpu
{
1700 /* used in computing the new watermarks state */
1701 struct intel_wm_config
{
1702 unsigned int num_pipes_active
;
1703 bool sprites_enabled
;
1704 bool sprites_scaled
;
1707 struct drm_i915_private
{
1708 struct drm_device drm
;
1710 struct kmem_cache
*objects
;
1711 struct kmem_cache
*vmas
;
1712 struct kmem_cache
*requests
;
1714 const struct intel_device_info info
;
1716 int relative_constants_mode
;
1720 struct intel_uncore uncore
;
1722 struct i915_virtual_gpu vgpu
;
1724 struct intel_gvt gvt
;
1726 struct intel_guc guc
;
1728 struct intel_csr csr
;
1730 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1732 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1733 * controller on different i2c buses. */
1734 struct mutex gmbus_mutex
;
1737 * Base address of the gmbus and gpio block.
1739 uint32_t gpio_mmio_base
;
1741 /* MMIO base address for MIPI regs */
1742 uint32_t mipi_mmio_base
;
1744 uint32_t psr_mmio_base
;
1746 uint32_t pps_mmio_base
;
1748 wait_queue_head_t gmbus_wait_queue
;
1750 struct pci_dev
*bridge_dev
;
1751 struct i915_gem_context
*kernel_context
;
1752 struct intel_engine_cs engine
[I915_NUM_ENGINES
];
1753 struct i915_vma
*semaphore
;
1756 struct drm_dma_handle
*status_page_dmah
;
1757 struct resource mch_res
;
1759 /* protects the irq masks */
1760 spinlock_t irq_lock
;
1762 /* protects the mmio flip data */
1763 spinlock_t mmio_flip_lock
;
1765 bool display_irqs_enabled
;
1767 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1768 struct pm_qos_request pm_qos
;
1770 /* Sideband mailbox protection */
1771 struct mutex sb_lock
;
1773 /** Cached value of IMR to avoid reads in updating the bitfield */
1776 u32 de_irq_mask
[I915_MAX_PIPES
];
1781 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1783 struct i915_hotplug hotplug
;
1784 struct intel_fbc fbc
;
1785 struct i915_drrs drrs
;
1786 struct intel_opregion opregion
;
1787 struct intel_vbt_data vbt
;
1789 bool preserve_bios_swizzle
;
1792 struct intel_overlay
*overlay
;
1794 /* backlight registers and fields in struct intel_panel */
1795 struct mutex backlight_lock
;
1798 bool no_aux_handshake
;
1800 /* protects panel power sequencer state */
1801 struct mutex pps_mutex
;
1803 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1804 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1806 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1807 unsigned int skl_preferred_vco_freq
;
1808 unsigned int cdclk_freq
, max_cdclk_freq
, atomic_cdclk_freq
;
1809 unsigned int max_dotclk_freq
;
1810 unsigned int rawclk_freq
;
1811 unsigned int hpll_freq
;
1812 unsigned int czclk_freq
;
1815 unsigned int vco
, ref
;
1819 * wq - Driver workqueue for GEM.
1821 * NOTE: Work items scheduled here are not allowed to grab any modeset
1822 * locks, for otherwise the flushing done in the pageflip code will
1823 * result in deadlocks.
1825 struct workqueue_struct
*wq
;
1827 /* Display functions */
1828 struct drm_i915_display_funcs display
;
1830 /* PCH chipset type */
1831 enum intel_pch pch_type
;
1832 unsigned short pch_id
;
1834 unsigned long quirks
;
1836 enum modeset_restore modeset_restore
;
1837 struct mutex modeset_restore_lock
;
1838 struct drm_atomic_state
*modeset_restore_state
;
1839 struct drm_modeset_acquire_ctx reset_ctx
;
1841 struct list_head vm_list
; /* Global list of all address spaces */
1842 struct i915_ggtt ggtt
; /* VM representing the global address space */
1844 struct i915_gem_mm mm
;
1845 DECLARE_HASHTABLE(mm_structs
, 7);
1846 struct mutex mm_lock
;
1848 /* The hw wants to have a stable context identifier for the lifetime
1849 * of the context (for OA, PASID, faults, etc). This is limited
1850 * in execlists to 21 bits.
1852 struct ida context_hw_ida
;
1853 #define MAX_CONTEXT_HW_ID (1<<21) /* exclusive */
1855 /* Kernel Modesetting */
1857 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1858 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1859 wait_queue_head_t pending_flip_queue
;
1861 #ifdef CONFIG_DEBUG_FS
1862 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1865 /* dpll and cdclk state is protected by connection_mutex */
1866 int num_shared_dpll
;
1867 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1868 const struct intel_dpll_mgr
*dpll_mgr
;
1871 * dpll_lock serializes intel_{prepare,enable,disable}_shared_dpll.
1872 * Must be global rather than per dpll, because on some platforms
1873 * plls share registers.
1875 struct mutex dpll_lock
;
1877 unsigned int active_crtcs
;
1878 unsigned int min_pixclk
[I915_MAX_PIPES
];
1880 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1882 struct i915_workarounds workarounds
;
1884 struct i915_frontbuffer_tracking fb_tracking
;
1888 bool mchbar_need_disable
;
1890 struct intel_l3_parity l3_parity
;
1892 /* Cannot be determined by PCIID. You must always read a register. */
1895 /* gen6+ rps state */
1896 struct intel_gen6_power_mgmt rps
;
1898 /* ilk-only ips/rps state. Everything in here is protected by the global
1899 * mchdev_lock in intel_pm.c */
1900 struct intel_ilk_power_mgmt ips
;
1902 struct i915_power_domains power_domains
;
1904 struct i915_psr psr
;
1906 struct i915_gpu_error gpu_error
;
1908 struct drm_i915_gem_object
*vlv_pctx
;
1910 #ifdef CONFIG_DRM_FBDEV_EMULATION
1911 /* list of fbdev register on this device */
1912 struct intel_fbdev
*fbdev
;
1913 struct work_struct fbdev_suspend_work
;
1916 struct drm_property
*broadcast_rgb_property
;
1917 struct drm_property
*force_audio_property
;
1919 /* hda/i915 audio component */
1920 struct i915_audio_component
*audio_component
;
1921 bool audio_component_registered
;
1923 * av_mutex - mutex for audio/video sync
1926 struct mutex av_mutex
;
1928 uint32_t hw_context_size
;
1929 struct list_head context_list
;
1933 /* Shadow for DISPLAY_PHY_CONTROL which can't be safely read */
1934 u32 chv_phy_control
;
1936 * Shadows for CHV DPLL_MD regs to keep the state
1937 * checker somewhat working in the presence hardware
1938 * crappiness (can't read out DPLL_MD for pipes B & C).
1940 u32 chv_dpll_md
[I915_MAX_PIPES
];
1944 bool suspended_to_idle
;
1945 struct i915_suspend_saved_registers regfile
;
1946 struct vlv_s0ix_state vlv_s0ix_state
;
1950 * Raw watermark latency values:
1951 * in 0.1us units for WM0,
1952 * in 0.5us units for WM1+.
1955 uint16_t pri_latency
[5];
1957 uint16_t spr_latency
[5];
1959 uint16_t cur_latency
[5];
1961 * Raw watermark memory latency values
1962 * for SKL for all 8 levels
1965 uint16_t skl_latency
[8];
1968 * The skl_wm_values structure is a bit too big for stack
1969 * allocation, so we keep the staging struct where we store
1970 * intermediate results here instead.
1972 struct skl_wm_values skl_results
;
1974 /* current hardware state */
1976 struct ilk_wm_values hw
;
1977 struct skl_wm_values skl_hw
;
1978 struct vlv_wm_values vlv
;
1984 * Should be held around atomic WM register writing; also
1985 * protects * intel_crtc->wm.active and
1986 * cstate->wm.need_postvbl_update.
1988 struct mutex wm_mutex
;
1991 * Set during HW readout of watermarks/DDB. Some platforms
1992 * need to know when we're still using BIOS-provided values
1993 * (which we don't fully trust).
1995 bool distrust_bios_wm
;
1998 struct i915_runtime_pm pm
;
2000 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
2002 void (*cleanup_engine
)(struct intel_engine_cs
*engine
);
2005 * Is the GPU currently considered idle, or busy executing
2006 * userspace requests? Whilst idle, we allow runtime power
2007 * management to power down the hardware and display clocks.
2008 * In order to reduce the effect on performance, there
2009 * is a slight delay before we do so.
2011 unsigned int active_engines
;
2015 * We leave the user IRQ off as much as possible,
2016 * but this means that requests will finish and never
2017 * be retired once the system goes idle. Set a timer to
2018 * fire periodically while the ring is running. When it
2019 * fires, go retire requests.
2021 struct delayed_work retire_work
;
2024 * When we detect an idle GPU, we want to turn on
2025 * powersaving features. So once we see that there
2026 * are no more requests outstanding and no more
2027 * arrive within a small period of time, we fire
2028 * off the idle_work.
2030 struct delayed_work idle_work
;
2033 /* perform PHY state sanity checks? */
2034 bool chv_phy_assert
[2];
2036 struct intel_encoder
*dig_port_map
[I915_MAX_PORTS
];
2039 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
2040 * will be rejected. Instead look for a better place.
2044 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
2046 return container_of(dev
, struct drm_i915_private
, drm
);
2049 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
2051 return to_i915(dev_get_drvdata(dev
));
2054 static inline struct drm_i915_private
*guc_to_i915(struct intel_guc
*guc
)
2056 return container_of(guc
, struct drm_i915_private
, guc
);
2059 /* Simple iterator over all initialised engines */
2060 #define for_each_engine(engine__, dev_priv__) \
2061 for ((engine__) = &(dev_priv__)->engine[0]; \
2062 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2064 for_each_if (intel_engine_initialized(engine__))
2066 /* Iterator with engine_id */
2067 #define for_each_engine_id(engine__, dev_priv__, id__) \
2068 for ((engine__) = &(dev_priv__)->engine[0], (id__) = 0; \
2069 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2071 for_each_if (((id__) = (engine__)->id, \
2072 intel_engine_initialized(engine__)))
2074 /* Iterator over subset of engines selected by mask */
2075 #define for_each_engine_masked(engine__, dev_priv__, mask__) \
2076 for ((engine__) = &(dev_priv__)->engine[0]; \
2077 (engine__) < &(dev_priv__)->engine[I915_NUM_ENGINES]; \
2079 for_each_if (((mask__) & intel_engine_flag(engine__)) && \
2080 intel_engine_initialized(engine__))
2082 enum hdmi_force_audio
{
2083 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
2084 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
2085 HDMI_AUDIO_AUTO
, /* trust EDID */
2086 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
2089 #define I915_GTT_OFFSET_NONE ((u32)-1)
2091 struct drm_i915_gem_object_ops
{
2093 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
2095 /* Interface between the GEM object and its backing storage.
2096 * get_pages() is called once prior to the use of the associated set
2097 * of pages before to binding them into the GTT, and put_pages() is
2098 * called after we no longer need them. As we expect there to be
2099 * associated cost with migrating pages between the backing storage
2100 * and making them available for the GPU (e.g. clflush), we may hold
2101 * onto the pages after they are no longer referenced by the GPU
2102 * in case they may be used again shortly (for example migrating the
2103 * pages to a different memory domain within the GTT). put_pages()
2104 * will therefore most likely be called when the object itself is
2105 * being released or under memory pressure (where we attempt to
2106 * reap pages for the shrinker).
2108 int (*get_pages
)(struct drm_i915_gem_object
*);
2109 void (*put_pages
)(struct drm_i915_gem_object
*);
2111 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
2112 void (*release
)(struct drm_i915_gem_object
*);
2116 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
2117 * considered to be the frontbuffer for the given plane interface-wise. This
2118 * doesn't mean that the hw necessarily already scans it out, but that any
2119 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
2121 * We have one bit per pipe and per scanout plane type.
2123 #define INTEL_MAX_SPRITE_BITS_PER_PIPE 5
2124 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 8
2125 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
2126 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2127 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
2128 (1 << (1 + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2129 #define INTEL_FRONTBUFFER_SPRITE(pipe, plane) \
2130 (1 << (2 + plane + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2131 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
2132 (1 << (2 + INTEL_MAX_SPRITE_BITS_PER_PIPE + (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
2133 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
2134 (0xff << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
2136 struct drm_i915_gem_object
{
2137 struct drm_gem_object base
;
2139 const struct drm_i915_gem_object_ops
*ops
;
2141 /** List of VMAs backed by this object */
2142 struct list_head vma_list
;
2144 /** Stolen memory for this object, instead of being backed by shmem. */
2145 struct drm_mm_node
*stolen
;
2146 struct list_head global_list
;
2148 /** Used in execbuf to temporarily hold a ref */
2149 struct list_head obj_exec_link
;
2151 struct list_head batch_pool_link
;
2153 unsigned long flags
;
2155 * This is set if the object is on the active lists (has pending
2156 * rendering and so a non-zero seqno), and is not set if it i s on
2157 * inactive (ready to be unbound) list.
2159 #define I915_BO_ACTIVE_SHIFT 0
2160 #define I915_BO_ACTIVE_MASK ((1 << I915_NUM_ENGINES) - 1)
2161 #define __I915_BO_ACTIVE(bo) \
2162 ((READ_ONCE((bo)->flags) >> I915_BO_ACTIVE_SHIFT) & I915_BO_ACTIVE_MASK)
2165 * This is set if the object has been written to since last bound
2168 unsigned int dirty
:1;
2171 * Fence register bits (if any) for this object. Will be set
2172 * as needed when mapped into the GTT.
2173 * Protected by dev->struct_mutex.
2175 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
2178 * Advice: are the backing pages purgeable?
2180 unsigned int madv
:2;
2183 * Whether the tiling parameters for the currently associated fence
2184 * register have changed. Note that for the purposes of tracking
2185 * tiling changes we also treat the unfenced register, the register
2186 * slot that the object occupies whilst it executes a fenced
2187 * command (such as BLT on gen2/3), as a "fence".
2189 unsigned int fence_dirty
:1;
2192 * Is the object at the current location in the gtt mappable and
2193 * fenceable? Used to avoid costly recalculations.
2195 unsigned int map_and_fenceable
:1;
2198 * Whether the current gtt mapping needs to be mappable (and isn't just
2199 * mappable by accident). Track pin and fault separate for a more
2200 * accurate mappable working set.
2202 unsigned int fault_mappable
:1;
2205 * Is the object to be mapped as read-only to the GPU
2206 * Only honoured if hardware has relevant pte bit
2208 unsigned long gt_ro
:1;
2209 unsigned int cache_level
:3;
2210 unsigned int cache_dirty
:1;
2212 atomic_t frontbuffer_bits
;
2214 /** Current tiling stride for the object, if it's tiled. */
2215 unsigned int tiling_and_stride
;
2216 #define FENCE_MINIMUM_STRIDE 128 /* See i915_tiling_ok() */
2217 #define TILING_MASK (FENCE_MINIMUM_STRIDE-1)
2218 #define STRIDE_MASK (~TILING_MASK)
2220 unsigned int has_wc_mmap
;
2221 /** Count of VMA actually bound by this object */
2222 unsigned int bind_count
;
2223 unsigned int pin_display
;
2225 struct sg_table
*pages
;
2226 int pages_pin_count
;
2228 struct scatterlist
*sg
;
2233 /** Breadcrumb of last rendering to the buffer.
2234 * There can only be one writer, but we allow for multiple readers.
2235 * If there is a writer that necessarily implies that all other
2236 * read requests are complete - but we may only be lazily clearing
2237 * the read requests. A read request is naturally the most recent
2238 * request on a ring, so we may have two different write and read
2239 * requests on one ring where the write request is older than the
2240 * read request. This allows for the CPU to read from an active
2241 * buffer by only waiting for the write to complete.
2243 struct i915_gem_active last_read
[I915_NUM_ENGINES
];
2244 struct i915_gem_active last_write
;
2245 struct i915_gem_active last_fence
;
2247 /** References from framebuffers, locks out tiling changes. */
2248 unsigned long framebuffer_references
;
2250 /** Record of address bit 17 of each page at last unbind. */
2251 unsigned long *bit_17
;
2254 /** for phy allocated objects */
2255 struct drm_dma_handle
*phys_handle
;
2257 struct i915_gem_userptr
{
2259 unsigned read_only
:1;
2260 unsigned workers
:4;
2261 #define I915_GEM_USERPTR_MAX_WORKERS 15
2263 struct i915_mm_struct
*mm
;
2264 struct i915_mmu_object
*mmu_object
;
2265 struct work_struct
*work
;
2270 static inline struct drm_i915_gem_object
*
2271 to_intel_bo(struct drm_gem_object
*gem
)
2273 /* Assert that to_intel_bo(NULL) == NULL */
2274 BUILD_BUG_ON(offsetof(struct drm_i915_gem_object
, base
));
2276 return container_of(gem
, struct drm_i915_gem_object
, base
);
2279 static inline struct drm_i915_gem_object
*
2280 i915_gem_object_lookup(struct drm_file
*file
, u32 handle
)
2282 return to_intel_bo(drm_gem_object_lookup(file
, handle
));
2286 extern struct drm_gem_object
*
2287 drm_gem_object_lookup(struct drm_file
*file
, u32 handle
);
2289 __attribute__((nonnull
))
2290 static inline struct drm_i915_gem_object
*
2291 i915_gem_object_get(struct drm_i915_gem_object
*obj
)
2293 drm_gem_object_reference(&obj
->base
);
2298 extern void drm_gem_object_reference(struct drm_gem_object
*);
2300 __attribute__((nonnull
))
2302 i915_gem_object_put(struct drm_i915_gem_object
*obj
)
2304 drm_gem_object_unreference(&obj
->base
);
2308 extern void drm_gem_object_unreference(struct drm_gem_object
*);
2310 __attribute__((nonnull
))
2312 i915_gem_object_put_unlocked(struct drm_i915_gem_object
*obj
)
2314 drm_gem_object_unreference_unlocked(&obj
->base
);
2318 extern void drm_gem_object_unreference_unlocked(struct drm_gem_object
*);
2321 i915_gem_object_has_struct_page(const struct drm_i915_gem_object
*obj
)
2323 return obj
->ops
->flags
& I915_GEM_OBJECT_HAS_STRUCT_PAGE
;
2326 static inline unsigned long
2327 i915_gem_object_get_active(const struct drm_i915_gem_object
*obj
)
2329 return (obj
->flags
>> I915_BO_ACTIVE_SHIFT
) & I915_BO_ACTIVE_MASK
;
2333 i915_gem_object_is_active(const struct drm_i915_gem_object
*obj
)
2335 return i915_gem_object_get_active(obj
);
2339 i915_gem_object_set_active(struct drm_i915_gem_object
*obj
, int engine
)
2341 obj
->flags
|= BIT(engine
+ I915_BO_ACTIVE_SHIFT
);
2345 i915_gem_object_clear_active(struct drm_i915_gem_object
*obj
, int engine
)
2347 obj
->flags
&= ~BIT(engine
+ I915_BO_ACTIVE_SHIFT
);
2351 i915_gem_object_has_active_engine(const struct drm_i915_gem_object
*obj
,
2354 return obj
->flags
& BIT(engine
+ I915_BO_ACTIVE_SHIFT
);
2357 static inline unsigned int
2358 i915_gem_object_get_tiling(struct drm_i915_gem_object
*obj
)
2360 return obj
->tiling_and_stride
& TILING_MASK
;
2364 i915_gem_object_is_tiled(struct drm_i915_gem_object
*obj
)
2366 return i915_gem_object_get_tiling(obj
) != I915_TILING_NONE
;
2369 static inline unsigned int
2370 i915_gem_object_get_stride(struct drm_i915_gem_object
*obj
)
2372 return obj
->tiling_and_stride
& STRIDE_MASK
;
2375 static inline struct i915_vma
*i915_vma_get(struct i915_vma
*vma
)
2377 i915_gem_object_get(vma
->obj
);
2381 static inline void i915_vma_put(struct i915_vma
*vma
)
2383 lockdep_assert_held(&vma
->vm
->dev
->struct_mutex
);
2384 i915_gem_object_put(vma
->obj
);
2388 * Optimised SGL iterator for GEM objects
2390 static __always_inline
struct sgt_iter
{
2391 struct scatterlist
*sgp
;
2398 } __sgt_iter(struct scatterlist
*sgl
, bool dma
) {
2399 struct sgt_iter s
= { .sgp
= sgl
};
2402 s
.max
= s
.curr
= s
.sgp
->offset
;
2403 s
.max
+= s
.sgp
->length
;
2405 s
.dma
= sg_dma_address(s
.sgp
);
2407 s
.pfn
= page_to_pfn(sg_page(s
.sgp
));
2414 * __sg_next - return the next scatterlist entry in a list
2415 * @sg: The current sg entry
2418 * If the entry is the last, return NULL; otherwise, step to the next
2419 * element in the array (@sg@+1). If that's a chain pointer, follow it;
2420 * otherwise just return the pointer to the current element.
2422 static inline struct scatterlist
*__sg_next(struct scatterlist
*sg
)
2424 #ifdef CONFIG_DEBUG_SG
2425 BUG_ON(sg
->sg_magic
!= SG_MAGIC
);
2427 return sg_is_last(sg
) ? NULL
:
2428 likely(!sg_is_chain(++sg
)) ? sg
:
2433 * for_each_sgt_dma - iterate over the DMA addresses of the given sg_table
2434 * @__dmap: DMA address (output)
2435 * @__iter: 'struct sgt_iter' (iterator state, internal)
2436 * @__sgt: sg_table to iterate over (input)
2438 #define for_each_sgt_dma(__dmap, __iter, __sgt) \
2439 for ((__iter) = __sgt_iter((__sgt)->sgl, true); \
2440 ((__dmap) = (__iter).dma + (__iter).curr); \
2441 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2442 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), true), 0))
2445 * for_each_sgt_page - iterate over the pages of the given sg_table
2446 * @__pp: page pointer (output)
2447 * @__iter: 'struct sgt_iter' (iterator state, internal)
2448 * @__sgt: sg_table to iterate over (input)
2450 #define for_each_sgt_page(__pp, __iter, __sgt) \
2451 for ((__iter) = __sgt_iter((__sgt)->sgl, false); \
2452 ((__pp) = (__iter).pfn == 0 ? NULL : \
2453 pfn_to_page((__iter).pfn + ((__iter).curr >> PAGE_SHIFT))); \
2454 (((__iter).curr += PAGE_SIZE) < (__iter).max) || \
2455 ((__iter) = __sgt_iter(__sg_next((__iter).sgp), false), 0))
2458 * A command that requires special handling by the command parser.
2460 struct drm_i915_cmd_descriptor
{
2462 * Flags describing how the command parser processes the command.
2464 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2465 * a length mask if not set
2466 * CMD_DESC_SKIP: The command is allowed but does not follow the
2467 * standard length encoding for the opcode range in
2469 * CMD_DESC_REJECT: The command is never allowed
2470 * CMD_DESC_REGISTER: The command should be checked against the
2471 * register whitelist for the appropriate ring
2472 * CMD_DESC_MASTER: The command is allowed if the submitting process
2476 #define CMD_DESC_FIXED (1<<0)
2477 #define CMD_DESC_SKIP (1<<1)
2478 #define CMD_DESC_REJECT (1<<2)
2479 #define CMD_DESC_REGISTER (1<<3)
2480 #define CMD_DESC_BITMASK (1<<4)
2481 #define CMD_DESC_MASTER (1<<5)
2484 * The command's unique identification bits and the bitmask to get them.
2485 * This isn't strictly the opcode field as defined in the spec and may
2486 * also include type, subtype, and/or subop fields.
2494 * The command's length. The command is either fixed length (i.e. does
2495 * not include a length field) or has a length field mask. The flag
2496 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2497 * a length mask. All command entries in a command table must include
2498 * length information.
2506 * Describes where to find a register address in the command to check
2507 * against the ring's register whitelist. Only valid if flags has the
2508 * CMD_DESC_REGISTER bit set.
2510 * A non-zero step value implies that the command may access multiple
2511 * registers in sequence (e.g. LRI), in that case step gives the
2512 * distance in dwords between individual offset fields.
2520 #define MAX_CMD_DESC_BITMASKS 3
2522 * Describes command checks where a particular dword is masked and
2523 * compared against an expected value. If the command does not match
2524 * the expected value, the parser rejects it. Only valid if flags has
2525 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2528 * If the check specifies a non-zero condition_mask then the parser
2529 * only performs the check when the bits specified by condition_mask
2536 u32 condition_offset
;
2538 } bits
[MAX_CMD_DESC_BITMASKS
];
2542 * A table of commands requiring special handling by the command parser.
2544 * Each engine has an array of tables. Each table consists of an array of
2545 * command descriptors, which must be sorted with command opcodes in
2548 struct drm_i915_cmd_table
{
2549 const struct drm_i915_cmd_descriptor
*table
;
2553 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2554 #define __I915__(p) ({ \
2555 struct drm_i915_private *__p; \
2556 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2557 __p = (struct drm_i915_private *)p; \
2558 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2559 __p = to_i915((struct drm_device *)p); \
2564 #define INTEL_INFO(p) (&__I915__(p)->info)
2565 #define INTEL_GEN(p) (INTEL_INFO(p)->gen)
2566 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2568 #define REVID_FOREVER 0xff
2569 #define INTEL_REVID(p) (__I915__(p)->drm.pdev->revision)
2571 #define GEN_FOREVER (0)
2573 * Returns true if Gen is in inclusive range [Start, End].
2575 * Use GEN_FOREVER for unbound start and or end.
2577 #define IS_GEN(p, s, e) ({ \
2578 unsigned int __s = (s), __e = (e); \
2579 BUILD_BUG_ON(!__builtin_constant_p(s)); \
2580 BUILD_BUG_ON(!__builtin_constant_p(e)); \
2581 if ((__s) != GEN_FOREVER) \
2583 if ((__e) == GEN_FOREVER) \
2584 __e = BITS_PER_LONG - 1; \
2587 !!(INTEL_INFO(p)->gen_mask & GENMASK((__e), (__s))); \
2591 * Return true if revision is in range [since,until] inclusive.
2593 * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
2595 #define IS_REVID(p, since, until) \
2596 (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
2598 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2599 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2600 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2601 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2602 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2603 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2604 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2605 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2606 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2607 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2608 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2609 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2610 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2611 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2612 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2613 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2614 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2615 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2616 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2617 INTEL_DEVID(dev) == 0x0152 || \
2618 INTEL_DEVID(dev) == 0x015a)
2619 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2620 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_cherryview)
2621 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2622 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->is_broadwell)
2623 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2624 #define IS_BROXTON(dev) (INTEL_INFO(dev)->is_broxton)
2625 #define IS_KABYLAKE(dev) (INTEL_INFO(dev)->is_kabylake)
2626 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2627 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2628 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2629 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2630 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2631 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2632 (INTEL_DEVID(dev) & 0xf) == 0xe))
2633 /* ULX machines are also considered ULT. */
2634 #define IS_BDW_ULX(dev) (IS_BROADWELL(dev) && \
2635 (INTEL_DEVID(dev) & 0xf) == 0xe)
2636 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2637 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2638 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2639 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2640 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2641 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2642 /* ULX machines are also considered ULT. */
2643 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2644 INTEL_DEVID(dev) == 0x0A1E)
2645 #define IS_SKL_ULT(dev) (INTEL_DEVID(dev) == 0x1906 || \
2646 INTEL_DEVID(dev) == 0x1913 || \
2647 INTEL_DEVID(dev) == 0x1916 || \
2648 INTEL_DEVID(dev) == 0x1921 || \
2649 INTEL_DEVID(dev) == 0x1926)
2650 #define IS_SKL_ULX(dev) (INTEL_DEVID(dev) == 0x190E || \
2651 INTEL_DEVID(dev) == 0x1915 || \
2652 INTEL_DEVID(dev) == 0x191E)
2653 #define IS_KBL_ULT(dev) (INTEL_DEVID(dev) == 0x5906 || \
2654 INTEL_DEVID(dev) == 0x5913 || \
2655 INTEL_DEVID(dev) == 0x5916 || \
2656 INTEL_DEVID(dev) == 0x5921 || \
2657 INTEL_DEVID(dev) == 0x5926)
2658 #define IS_KBL_ULX(dev) (INTEL_DEVID(dev) == 0x590E || \
2659 INTEL_DEVID(dev) == 0x5915 || \
2660 INTEL_DEVID(dev) == 0x591E)
2661 #define IS_SKL_GT3(dev) (IS_SKYLAKE(dev) && \
2662 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2663 #define IS_SKL_GT4(dev) (IS_SKYLAKE(dev) && \
2664 (INTEL_DEVID(dev) & 0x00F0) == 0x0030)
2666 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2668 #define SKL_REVID_A0 0x0
2669 #define SKL_REVID_B0 0x1
2670 #define SKL_REVID_C0 0x2
2671 #define SKL_REVID_D0 0x3
2672 #define SKL_REVID_E0 0x4
2673 #define SKL_REVID_F0 0x5
2674 #define SKL_REVID_G0 0x6
2675 #define SKL_REVID_H0 0x7
2677 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
2679 #define BXT_REVID_A0 0x0
2680 #define BXT_REVID_A1 0x1
2681 #define BXT_REVID_B0 0x3
2682 #define BXT_REVID_C0 0x9
2684 #define IS_BXT_REVID(p, since, until) (IS_BROXTON(p) && IS_REVID(p, since, until))
2686 #define KBL_REVID_A0 0x0
2687 #define KBL_REVID_B0 0x1
2688 #define KBL_REVID_C0 0x2
2689 #define KBL_REVID_D0 0x3
2690 #define KBL_REVID_E0 0x4
2692 #define IS_KBL_REVID(p, since, until) \
2693 (IS_KABYLAKE(p) && IS_REVID(p, since, until))
2696 * The genX designation typically refers to the render engine, so render
2697 * capability related checks should use IS_GEN, while display and other checks
2698 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2701 #define IS_GEN2(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(1)))
2702 #define IS_GEN3(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(2)))
2703 #define IS_GEN4(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(3)))
2704 #define IS_GEN5(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(4)))
2705 #define IS_GEN6(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(5)))
2706 #define IS_GEN7(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(6)))
2707 #define IS_GEN8(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(7)))
2708 #define IS_GEN9(dev) (!!(INTEL_INFO(dev)->gen_mask & BIT(8)))
2710 #define ENGINE_MASK(id) BIT(id)
2711 #define RENDER_RING ENGINE_MASK(RCS)
2712 #define BSD_RING ENGINE_MASK(VCS)
2713 #define BLT_RING ENGINE_MASK(BCS)
2714 #define VEBOX_RING ENGINE_MASK(VECS)
2715 #define BSD2_RING ENGINE_MASK(VCS2)
2716 #define ALL_ENGINES (~0)
2718 #define HAS_ENGINE(dev_priv, id) \
2719 (!!(INTEL_INFO(dev_priv)->ring_mask & ENGINE_MASK(id)))
2721 #define HAS_BSD(dev_priv) HAS_ENGINE(dev_priv, VCS)
2722 #define HAS_BSD2(dev_priv) HAS_ENGINE(dev_priv, VCS2)
2723 #define HAS_BLT(dev_priv) HAS_ENGINE(dev_priv, BCS)
2724 #define HAS_VEBOX(dev_priv) HAS_ENGINE(dev_priv, VECS)
2726 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2727 #define HAS_SNOOP(dev) (INTEL_INFO(dev)->has_snoop)
2728 #define HAS_EDRAM(dev) (!!(__I915__(dev)->edram_cap & EDRAM_ENABLED))
2729 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2731 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2733 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2734 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2735 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2736 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt >= 2)
2737 #define USES_FULL_48BIT_PPGTT(dev) (i915.enable_ppgtt == 3)
2739 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2740 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2742 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2743 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2745 /* WaRsDisableCoarsePowerGating:skl,bxt */
2746 #define NEEDS_WaRsDisableCoarsePowerGating(dev_priv) \
2747 (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1) || \
2748 IS_SKL_GT3(dev_priv) || \
2749 IS_SKL_GT4(dev_priv))
2752 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2753 * even when in MSI mode. This results in spurious interrupt warnings if the
2754 * legacy irq no. is shared with another device. The kernel then disables that
2755 * interrupt source and so prevents the other device from working properly.
2757 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2758 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2760 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2761 * rows, which changed the alignment requirements and fence programming.
2763 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2765 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2766 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2768 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2769 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2770 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2772 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2774 #define HAS_DP_MST(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2775 INTEL_INFO(dev)->gen >= 9)
2777 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2778 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2779 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2780 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2781 IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
2782 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2783 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2784 IS_CHERRYVIEW(dev) || IS_SKYLAKE(dev) || \
2785 IS_KABYLAKE(dev) || IS_BROXTON(dev))
2786 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2787 #define HAS_RC6p(dev) (IS_GEN6(dev) || IS_IVYBRIDGE(dev))
2789 #define HAS_CSR(dev) (IS_GEN9(dev))
2792 * For now, anything with a GuC requires uCode loading, and then supports
2793 * command submission once loaded. But these are logically independent
2794 * properties, so we have separate macros to test them.
2796 #define HAS_GUC(dev) (IS_GEN9(dev))
2797 #define HAS_GUC_UCODE(dev) (HAS_GUC(dev))
2798 #define HAS_GUC_SCHED(dev) (HAS_GUC(dev))
2800 #define HAS_RESOURCE_STREAMER(dev) (IS_HASWELL(dev) || \
2801 INTEL_INFO(dev)->gen >= 8)
2803 #define HAS_CORE_RING_FREQ(dev) (INTEL_INFO(dev)->gen >= 6 && \
2804 !IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev) && \
2807 #define HAS_POOLED_EU(dev) (INTEL_INFO(dev)->has_pooled_eu)
2809 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2810 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2811 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2812 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2813 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2814 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2815 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2816 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2817 #define INTEL_PCH_KBP_DEVICE_ID_TYPE 0xA200
2818 #define INTEL_PCH_P2X_DEVICE_ID_TYPE 0x7100
2819 #define INTEL_PCH_P3X_DEVICE_ID_TYPE 0x7000
2820 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE 0x2900 /* qemu q35 has 2918 */
2822 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2823 #define HAS_PCH_KBP(dev) (INTEL_PCH_TYPE(dev) == PCH_KBP)
2824 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2825 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2826 #define HAS_PCH_LPT_LP(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
2827 #define HAS_PCH_LPT_H(dev) (__I915__(dev)->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
2828 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2829 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2830 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2831 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2833 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || \
2834 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2836 /* DPF == dynamic parity feature */
2837 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2838 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2840 #define GT_FREQUENCY_MULTIPLIER 50
2841 #define GEN9_FREQ_SCALER 3
2843 #include "i915_trace.h"
2845 static inline bool intel_scanout_needs_vtd_wa(struct drm_i915_private
*dev_priv
)
2847 #ifdef CONFIG_INTEL_IOMMU
2848 if (INTEL_GEN(dev_priv
) >= 6 && intel_iommu_gfx_mapped
)
2854 extern int i915_suspend_switcheroo(struct drm_device
*dev
, pm_message_t state
);
2855 extern int i915_resume_switcheroo(struct drm_device
*dev
);
2857 int intel_sanitize_enable_ppgtt(struct drm_i915_private
*dev_priv
,
2860 bool intel_sanitize_semaphores(struct drm_i915_private
*dev_priv
, int value
);
2864 __i915_printk(struct drm_i915_private
*dev_priv
, const char *level
,
2865 const char *fmt
, ...);
2867 #define i915_report_error(dev_priv, fmt, ...) \
2868 __i915_printk(dev_priv, KERN_ERR, fmt, ##__VA_ARGS__)
2870 #ifdef CONFIG_COMPAT
2871 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2874 extern int intel_gpu_reset(struct drm_i915_private
*dev_priv
, u32 engine_mask
);
2875 extern bool intel_has_gpu_reset(struct drm_i915_private
*dev_priv
);
2876 extern int i915_reset(struct drm_i915_private
*dev_priv
);
2877 extern int intel_guc_reset(struct drm_i915_private
*dev_priv
);
2878 extern void intel_engine_init_hangcheck(struct intel_engine_cs
*engine
);
2879 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2880 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2881 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2882 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2883 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2885 /* intel_hotplug.c */
2886 void intel_hpd_irq_handler(struct drm_i915_private
*dev_priv
,
2887 u32 pin_mask
, u32 long_mask
);
2888 void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2889 void intel_hpd_init_work(struct drm_i915_private
*dev_priv
);
2890 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2891 bool intel_hpd_pin_to_port(enum hpd_pin pin
, enum port
*port
);
2892 bool intel_hpd_disable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2893 void intel_hpd_enable(struct drm_i915_private
*dev_priv
, enum hpd_pin pin
);
2896 static inline void i915_queue_hangcheck(struct drm_i915_private
*dev_priv
)
2898 unsigned long delay
;
2900 if (unlikely(!i915
.enable_hangcheck
))
2903 /* Don't continually defer the hangcheck so that it is always run at
2904 * least once after work has been scheduled on any ring. Otherwise,
2905 * we will ignore a hung ring if a second ring is kept busy.
2908 delay
= round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES
);
2909 queue_delayed_work(system_long_wq
,
2910 &dev_priv
->gpu_error
.hangcheck_work
, delay
);
2914 void i915_handle_error(struct drm_i915_private
*dev_priv
,
2916 const char *fmt
, ...);
2918 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2919 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2920 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2922 extern void intel_uncore_sanitize(struct drm_i915_private
*dev_priv
);
2923 extern void intel_uncore_early_sanitize(struct drm_i915_private
*dev_priv
,
2924 bool restore_forcewake
);
2925 extern void intel_uncore_init(struct drm_i915_private
*dev_priv
);
2926 extern bool intel_uncore_unclaimed_mmio(struct drm_i915_private
*dev_priv
);
2927 extern bool intel_uncore_arm_unclaimed_mmio_detection(struct drm_i915_private
*dev_priv
);
2928 extern void intel_uncore_fini(struct drm_i915_private
*dev_priv
);
2929 extern void intel_uncore_forcewake_reset(struct drm_i915_private
*dev_priv
,
2931 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2932 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2933 enum forcewake_domains domains
);
2934 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2935 enum forcewake_domains domains
);
2936 /* Like above but the caller must manage the uncore.lock itself.
2937 * Must be used with I915_READ_FW and friends.
2939 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2940 enum forcewake_domains domains
);
2941 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2942 enum forcewake_domains domains
);
2943 u64
intel_uncore_edram_size(struct drm_i915_private
*dev_priv
);
2945 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2947 int intel_wait_for_register(struct drm_i915_private
*dev_priv
,
2951 const unsigned long timeout_ms
);
2952 int intel_wait_for_register_fw(struct drm_i915_private
*dev_priv
,
2956 const unsigned long timeout_ms
);
2958 static inline bool intel_gvt_active(struct drm_i915_private
*dev_priv
)
2960 return dev_priv
->gvt
.initialized
;
2963 static inline bool intel_vgpu_active(struct drm_i915_private
*dev_priv
)
2965 return dev_priv
->vgpu
.active
;
2969 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2973 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2976 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2977 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2978 void i915_hotplug_interrupt_update(struct drm_i915_private
*dev_priv
,
2981 void ilk_update_display_irq(struct drm_i915_private
*dev_priv
,
2982 uint32_t interrupt_mask
,
2983 uint32_t enabled_irq_mask
);
2985 ilk_enable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2987 ilk_update_display_irq(dev_priv
, bits
, bits
);
2990 ilk_disable_display_irq(struct drm_i915_private
*dev_priv
, uint32_t bits
)
2992 ilk_update_display_irq(dev_priv
, bits
, 0);
2994 void bdw_update_pipe_irq(struct drm_i915_private
*dev_priv
,
2996 uint32_t interrupt_mask
,
2997 uint32_t enabled_irq_mask
);
2998 static inline void bdw_enable_pipe_irq(struct drm_i915_private
*dev_priv
,
2999 enum pipe pipe
, uint32_t bits
)
3001 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, bits
);
3003 static inline void bdw_disable_pipe_irq(struct drm_i915_private
*dev_priv
,
3004 enum pipe pipe
, uint32_t bits
)
3006 bdw_update_pipe_irq(dev_priv
, pipe
, bits
, 0);
3008 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
3009 uint32_t interrupt_mask
,
3010 uint32_t enabled_irq_mask
);
3012 ibx_enable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3014 ibx_display_interrupt_update(dev_priv
, bits
, bits
);
3017 ibx_disable_display_interrupt(struct drm_i915_private
*dev_priv
, uint32_t bits
)
3019 ibx_display_interrupt_update(dev_priv
, bits
, 0);
3023 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
3024 struct drm_file
*file_priv
);
3025 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
3026 struct drm_file
*file_priv
);
3027 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
3028 struct drm_file
*file_priv
);
3029 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
3030 struct drm_file
*file_priv
);
3031 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
3032 struct drm_file
*file_priv
);
3033 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
3034 struct drm_file
*file_priv
);
3035 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
3036 struct drm_file
*file_priv
);
3037 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
3038 struct drm_file
*file_priv
);
3039 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
3040 struct drm_file
*file_priv
);
3041 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
3042 struct drm_file
*file_priv
);
3043 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
3044 struct drm_file
*file
);
3045 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
3046 struct drm_file
*file
);
3047 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
3048 struct drm_file
*file_priv
);
3049 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
3050 struct drm_file
*file_priv
);
3051 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
3052 struct drm_file
*file_priv
);
3053 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
3054 struct drm_file
*file_priv
);
3055 void i915_gem_init_userptr(struct drm_i915_private
*dev_priv
);
3056 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
3057 struct drm_file
*file
);
3058 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
3059 struct drm_file
*file_priv
);
3060 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
3061 struct drm_file
*file_priv
);
3062 void i915_gem_load_init(struct drm_device
*dev
);
3063 void i915_gem_load_cleanup(struct drm_device
*dev
);
3064 void i915_gem_load_init_fences(struct drm_i915_private
*dev_priv
);
3065 int i915_gem_freeze_late(struct drm_i915_private
*dev_priv
);
3067 void *i915_gem_object_alloc(struct drm_device
*dev
);
3068 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
3069 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
3070 const struct drm_i915_gem_object_ops
*ops
);
3071 struct drm_i915_gem_object
*i915_gem_object_create(struct drm_device
*dev
,
3073 struct drm_i915_gem_object
*i915_gem_object_create_from_data(
3074 struct drm_device
*dev
, const void *data
, size_t size
);
3075 void i915_gem_close_object(struct drm_gem_object
*gem
, struct drm_file
*file
);
3076 void i915_gem_free_object(struct drm_gem_object
*obj
);
3078 struct i915_vma
* __must_check
3079 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
3080 const struct i915_ggtt_view
*view
,
3085 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
3087 void __i915_vma_set_map_and_fenceable(struct i915_vma
*vma
);
3088 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
3089 void i915_vma_close(struct i915_vma
*vma
);
3090 void i915_vma_destroy(struct i915_vma
*vma
);
3092 int i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
3093 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
3094 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
3095 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
3097 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
3098 int *needs_clflush
);
3100 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
3102 static inline int __sg_page_count(struct scatterlist
*sg
)
3104 return sg
->length
>> PAGE_SHIFT
;
3108 i915_gem_object_get_dirty_page(struct drm_i915_gem_object
*obj
, int n
);
3110 static inline dma_addr_t
3111 i915_gem_object_get_dma_address(struct drm_i915_gem_object
*obj
, int n
)
3113 if (n
< obj
->get_page
.last
) {
3114 obj
->get_page
.sg
= obj
->pages
->sgl
;
3115 obj
->get_page
.last
= 0;
3118 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3119 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3120 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3121 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3124 return sg_dma_address(obj
->get_page
.sg
) + ((n
- obj
->get_page
.last
) << PAGE_SHIFT
);
3127 static inline struct page
*
3128 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
3130 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
3133 if (n
< obj
->get_page
.last
) {
3134 obj
->get_page
.sg
= obj
->pages
->sgl
;
3135 obj
->get_page
.last
= 0;
3138 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
3139 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
3140 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
3141 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
3144 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
3147 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
3149 BUG_ON(obj
->pages
== NULL
);
3150 obj
->pages_pin_count
++;
3153 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
3155 BUG_ON(obj
->pages_pin_count
== 0);
3156 obj
->pages_pin_count
--;
3159 enum i915_map_type
{
3165 * i915_gem_object_pin_map - return a contiguous mapping of the entire object
3166 * @obj - the object to map into kernel address space
3167 * @type - the type of mapping, used to select pgprot_t
3169 * Calls i915_gem_object_pin_pages() to prevent reaping of the object's
3170 * pages and then returns a contiguous mapping of the backing storage into
3171 * the kernel address space. Based on the @type of mapping, the PTE will be
3172 * set to either WriteBack or WriteCombine (via pgprot_t).
3174 * The caller must hold the struct_mutex, and is responsible for calling
3175 * i915_gem_object_unpin_map() when the mapping is no longer required.
3177 * Returns the pointer through which to access the mapped object, or an
3178 * ERR_PTR() on error.
3180 void *__must_check
i915_gem_object_pin_map(struct drm_i915_gem_object
*obj
,
3181 enum i915_map_type type
);
3184 * i915_gem_object_unpin_map - releases an earlier mapping
3185 * @obj - the object to unmap
3187 * After pinning the object and mapping its pages, once you are finished
3188 * with your access, call i915_gem_object_unpin_map() to release the pin
3189 * upon the mapping. Once the pin count reaches zero, that mapping may be
3192 * The caller must hold the struct_mutex.
3194 static inline void i915_gem_object_unpin_map(struct drm_i915_gem_object
*obj
)
3196 lockdep_assert_held(&obj
->base
.dev
->struct_mutex
);
3197 i915_gem_object_unpin_pages(obj
);
3200 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
3201 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
3202 struct drm_i915_gem_request
*to
);
3203 void i915_vma_move_to_active(struct i915_vma
*vma
,
3204 struct drm_i915_gem_request
*req
,
3205 unsigned int flags
);
3206 int i915_gem_dumb_create(struct drm_file
*file_priv
,
3207 struct drm_device
*dev
,
3208 struct drm_mode_create_dumb
*args
);
3209 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
3210 uint32_t handle
, uint64_t *offset
);
3212 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
3213 struct drm_i915_gem_object
*new,
3214 unsigned frontbuffer_bits
);
3216 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
3218 struct drm_i915_gem_request
*
3219 i915_gem_find_active_request(struct intel_engine_cs
*engine
);
3221 void i915_gem_retire_requests(struct drm_i915_private
*dev_priv
);
3223 static inline u32
i915_reset_counter(struct i915_gpu_error
*error
)
3225 return atomic_read(&error
->reset_counter
);
3228 static inline bool __i915_reset_in_progress(u32 reset
)
3230 return unlikely(reset
& I915_RESET_IN_PROGRESS_FLAG
);
3233 static inline bool __i915_reset_in_progress_or_wedged(u32 reset
)
3235 return unlikely(reset
& (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
3238 static inline bool __i915_terminally_wedged(u32 reset
)
3240 return unlikely(reset
& I915_WEDGED
);
3243 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
3245 return __i915_reset_in_progress(i915_reset_counter(error
));
3248 static inline bool i915_reset_in_progress_or_wedged(struct i915_gpu_error
*error
)
3250 return __i915_reset_in_progress_or_wedged(i915_reset_counter(error
));
3253 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
3255 return __i915_terminally_wedged(i915_reset_counter(error
));
3258 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
3260 return ((i915_reset_counter(error
) & ~I915_WEDGED
) + 1) / 2;
3263 void i915_gem_reset(struct drm_device
*dev
);
3264 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
3265 int __must_check
i915_gem_init(struct drm_device
*dev
);
3266 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
3267 void i915_gem_init_swizzling(struct drm_device
*dev
);
3268 void i915_gem_cleanup_engines(struct drm_device
*dev
);
3269 int __must_check
i915_gem_wait_for_idle(struct drm_i915_private
*dev_priv
,
3270 bool interruptible
);
3271 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
3272 void i915_gem_resume(struct drm_device
*dev
);
3273 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
3275 i915_gem_object_wait_rendering(struct drm_i915_gem_object
*obj
,
3278 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
3281 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
3282 struct i915_vma
* __must_check
3283 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
3285 const struct i915_ggtt_view
*view
);
3286 void i915_gem_object_unpin_from_display_plane(struct i915_vma
*vma
);
3287 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
3289 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
3290 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
3292 u64
i915_gem_get_ggtt_size(struct drm_i915_private
*dev_priv
, u64 size
,
3294 u64
i915_gem_get_ggtt_alignment(struct drm_i915_private
*dev_priv
, u64 size
,
3295 int tiling_mode
, bool fenced
);
3297 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
3298 enum i915_cache_level cache_level
);
3300 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
3301 struct dma_buf
*dma_buf
);
3303 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
3304 struct drm_gem_object
*gem_obj
, int flags
);
3307 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
3308 struct i915_address_space
*vm
,
3309 const struct i915_ggtt_view
*view
);
3312 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
3313 struct i915_address_space
*vm
,
3314 const struct i915_ggtt_view
*view
);
3316 static inline struct i915_hw_ppgtt
*
3317 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
3319 return container_of(vm
, struct i915_hw_ppgtt
, base
);
3322 static inline struct i915_vma
*
3323 i915_gem_object_to_ggtt(struct drm_i915_gem_object
*obj
,
3324 const struct i915_ggtt_view
*view
)
3326 return i915_gem_obj_to_vma(obj
, &to_i915(obj
->base
.dev
)->ggtt
.base
, view
);
3329 static inline unsigned long
3330 i915_gem_object_ggtt_offset(struct drm_i915_gem_object
*o
,
3331 const struct i915_ggtt_view
*view
)
3333 return i915_gem_object_to_ggtt(o
, view
)->node
.start
;
3336 /* i915_gem_fence.c */
3337 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
3338 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
3340 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
3341 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
3343 void i915_gem_restore_fences(struct drm_device
*dev
);
3345 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3346 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3347 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3349 /* i915_gem_context.c */
3350 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
3351 void i915_gem_context_lost(struct drm_i915_private
*dev_priv
);
3352 void i915_gem_context_fini(struct drm_device
*dev
);
3353 void i915_gem_context_reset(struct drm_device
*dev
);
3354 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
3355 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
3356 int i915_switch_context(struct drm_i915_gem_request
*req
);
3357 int i915_gem_switch_to_kernel_context(struct drm_i915_private
*dev_priv
);
3358 void i915_gem_context_free(struct kref
*ctx_ref
);
3359 struct drm_i915_gem_object
*
3360 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
3361 struct i915_gem_context
*
3362 i915_gem_context_create_gvt(struct drm_device
*dev
);
3364 static inline struct i915_gem_context
*
3365 i915_gem_context_lookup(struct drm_i915_file_private
*file_priv
, u32 id
)
3367 struct i915_gem_context
*ctx
;
3369 lockdep_assert_held(&file_priv
->dev_priv
->drm
.struct_mutex
);
3371 ctx
= idr_find(&file_priv
->context_idr
, id
);
3373 return ERR_PTR(-ENOENT
);
3378 static inline struct i915_gem_context
*
3379 i915_gem_context_get(struct i915_gem_context
*ctx
)
3381 kref_get(&ctx
->ref
);
3385 static inline void i915_gem_context_put(struct i915_gem_context
*ctx
)
3387 lockdep_assert_held(&ctx
->i915
->drm
.struct_mutex
);
3388 kref_put(&ctx
->ref
, i915_gem_context_free
);
3391 static inline bool i915_gem_context_is_default(const struct i915_gem_context
*c
)
3393 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3396 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3397 struct drm_file
*file
);
3398 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3399 struct drm_file
*file
);
3400 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3401 struct drm_file
*file_priv
);
3402 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3403 struct drm_file
*file_priv
);
3404 int i915_gem_context_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3405 struct drm_file
*file
);
3407 /* i915_gem_evict.c */
3408 int __must_check
i915_gem_evict_something(struct i915_address_space
*vm
,
3409 u64 min_size
, u64 alignment
,
3410 unsigned cache_level
,
3413 int __must_check
i915_gem_evict_for_vma(struct i915_vma
*target
);
3414 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3416 /* belongs in i915_gem_gtt.h */
3417 static inline void i915_gem_chipset_flush(struct drm_i915_private
*dev_priv
)
3419 if (INTEL_GEN(dev_priv
) < 6)
3420 intel_gtt_chipset_flush();
3423 /* i915_gem_stolen.c */
3424 int i915_gem_stolen_insert_node(struct drm_i915_private
*dev_priv
,
3425 struct drm_mm_node
*node
, u64 size
,
3426 unsigned alignment
);
3427 int i915_gem_stolen_insert_node_in_range(struct drm_i915_private
*dev_priv
,
3428 struct drm_mm_node
*node
, u64 size
,
3429 unsigned alignment
, u64 start
,
3431 void i915_gem_stolen_remove_node(struct drm_i915_private
*dev_priv
,
3432 struct drm_mm_node
*node
);
3433 int i915_gem_init_stolen(struct drm_device
*dev
);
3434 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3435 struct drm_i915_gem_object
*
3436 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3437 struct drm_i915_gem_object
*
3438 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3443 /* i915_gem_shrinker.c */
3444 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3445 unsigned long target
,
3447 #define I915_SHRINK_PURGEABLE 0x1
3448 #define I915_SHRINK_UNBOUND 0x2
3449 #define I915_SHRINK_BOUND 0x4
3450 #define I915_SHRINK_ACTIVE 0x8
3451 #define I915_SHRINK_VMAPS 0x10
3452 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3453 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3454 void i915_gem_shrinker_cleanup(struct drm_i915_private
*dev_priv
);
3457 /* i915_gem_tiling.c */
3458 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3460 struct drm_i915_private
*dev_priv
= to_i915(obj
->base
.dev
);
3462 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3463 i915_gem_object_is_tiled(obj
);
3466 /* i915_debugfs.c */
3467 #ifdef CONFIG_DEBUG_FS
3468 int i915_debugfs_register(struct drm_i915_private
*dev_priv
);
3469 void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
);
3470 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3471 void intel_display_crc_init(struct drm_device
*dev
);
3473 static inline int i915_debugfs_register(struct drm_i915_private
*dev_priv
) {return 0;}
3474 static inline void i915_debugfs_unregister(struct drm_i915_private
*dev_priv
) {}
3475 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
)
3477 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3480 /* i915_gpu_error.c */
3482 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3483 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3484 const struct i915_error_state_file_priv
*error
);
3485 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3486 struct drm_i915_private
*i915
,
3487 size_t count
, loff_t pos
);
3488 static inline void i915_error_state_buf_release(
3489 struct drm_i915_error_state_buf
*eb
)
3493 void i915_capture_error_state(struct drm_i915_private
*dev_priv
,
3495 const char *error_msg
);
3496 void i915_error_state_get(struct drm_device
*dev
,
3497 struct i915_error_state_file_priv
*error_priv
);
3498 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3499 void i915_destroy_error_state(struct drm_device
*dev
);
3501 void i915_get_extra_instdone(struct drm_i915_private
*dev_priv
, uint32_t *instdone
);
3502 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3504 /* i915_cmd_parser.c */
3505 int i915_cmd_parser_get_version(struct drm_i915_private
*dev_priv
);
3506 int intel_engine_init_cmd_parser(struct intel_engine_cs
*engine
);
3507 void intel_engine_cleanup_cmd_parser(struct intel_engine_cs
*engine
);
3508 bool intel_engine_needs_cmd_parser(struct intel_engine_cs
*engine
);
3509 int intel_engine_cmd_parser(struct intel_engine_cs
*engine
,
3510 struct drm_i915_gem_object
*batch_obj
,
3511 struct drm_i915_gem_object
*shadow_batch_obj
,
3512 u32 batch_start_offset
,
3516 /* i915_suspend.c */
3517 extern int i915_save_state(struct drm_device
*dev
);
3518 extern int i915_restore_state(struct drm_device
*dev
);
3521 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3522 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3525 extern int intel_setup_gmbus(struct drm_device
*dev
);
3526 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3527 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3530 extern struct i2c_adapter
*
3531 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3532 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3533 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3534 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3536 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3538 extern void intel_i2c_reset(struct drm_device
*dev
);
3541 int intel_bios_init(struct drm_i915_private
*dev_priv
);
3542 bool intel_bios_is_valid_vbt(const void *buf
, size_t size
);
3543 bool intel_bios_is_tv_present(struct drm_i915_private
*dev_priv
);
3544 bool intel_bios_is_lvds_present(struct drm_i915_private
*dev_priv
, u8
*i2c_pin
);
3545 bool intel_bios_is_port_present(struct drm_i915_private
*dev_priv
, enum port port
);
3546 bool intel_bios_is_port_edp(struct drm_i915_private
*dev_priv
, enum port port
);
3547 bool intel_bios_is_port_dp_dual_mode(struct drm_i915_private
*dev_priv
, enum port port
);
3548 bool intel_bios_is_dsi_present(struct drm_i915_private
*dev_priv
, enum port
*port
);
3549 bool intel_bios_is_port_hpd_inverted(struct drm_i915_private
*dev_priv
,
3552 /* intel_opregion.c */
3554 extern int intel_opregion_setup(struct drm_i915_private
*dev_priv
);
3555 extern void intel_opregion_register(struct drm_i915_private
*dev_priv
);
3556 extern void intel_opregion_unregister(struct drm_i915_private
*dev_priv
);
3557 extern void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
);
3558 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3560 extern int intel_opregion_notify_adapter(struct drm_i915_private
*dev_priv
,
3562 extern int intel_opregion_get_panel_type(struct drm_i915_private
*dev_priv
);
3564 static inline int intel_opregion_setup(struct drm_i915_private
*dev
) { return 0; }
3565 static inline void intel_opregion_register(struct drm_i915_private
*dev_priv
) { }
3566 static inline void intel_opregion_unregister(struct drm_i915_private
*dev_priv
) { }
3567 static inline void intel_opregion_asle_intr(struct drm_i915_private
*dev_priv
)
3571 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3576 intel_opregion_notify_adapter(struct drm_i915_private
*dev
, pci_power_t state
)
3580 static inline int intel_opregion_get_panel_type(struct drm_i915_private
*dev
)
3588 extern void intel_register_dsm_handler(void);
3589 extern void intel_unregister_dsm_handler(void);
3591 static inline void intel_register_dsm_handler(void) { return; }
3592 static inline void intel_unregister_dsm_handler(void) { return; }
3593 #endif /* CONFIG_ACPI */
3595 /* intel_device_info.c */
3596 static inline struct intel_device_info
*
3597 mkwrite_device_info(struct drm_i915_private
*dev_priv
)
3599 return (struct intel_device_info
*)&dev_priv
->info
;
3602 void intel_device_info_runtime_init(struct drm_i915_private
*dev_priv
);
3603 void intel_device_info_dump(struct drm_i915_private
*dev_priv
);
3606 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3607 extern void intel_modeset_init(struct drm_device
*dev
);
3608 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3609 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3610 extern int intel_connector_register(struct drm_connector
*);
3611 extern void intel_connector_unregister(struct drm_connector
*);
3612 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3613 extern void intel_display_resume(struct drm_device
*dev
);
3614 extern void i915_redisable_vga(struct drm_device
*dev
);
3615 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3616 extern bool ironlake_set_drps(struct drm_i915_private
*dev_priv
, u8 val
);
3617 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3618 extern void intel_set_rps(struct drm_i915_private
*dev_priv
, u8 val
);
3619 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3622 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3623 struct drm_file
*file
);
3626 extern struct intel_overlay_error_state
*
3627 intel_overlay_capture_error_state(struct drm_i915_private
*dev_priv
);
3628 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3629 struct intel_overlay_error_state
*error
);
3631 extern struct intel_display_error_state
*
3632 intel_display_capture_error_state(struct drm_i915_private
*dev_priv
);
3633 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3634 struct drm_device
*dev
,
3635 struct intel_display_error_state
*error
);
3637 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3638 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3640 /* intel_sideband.c */
3641 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3642 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3643 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3644 u32
vlv_iosf_sb_read(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
);
3645 void vlv_iosf_sb_write(struct drm_i915_private
*dev_priv
, u8 port
, u32 reg
, u32 val
);
3646 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3647 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3648 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3649 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3650 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3651 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3652 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3653 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3654 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3655 enum intel_sbi_destination destination
);
3656 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3657 enum intel_sbi_destination destination
);
3658 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3659 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3661 /* intel_dpio_phy.c */
3662 void chv_set_phy_signal_level(struct intel_encoder
*encoder
,
3663 u32 deemph_reg_value
, u32 margin_reg_value
,
3664 bool uniq_trans_scale
);
3665 void chv_data_lane_soft_reset(struct intel_encoder
*encoder
,
3667 void chv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3668 void chv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3669 void chv_phy_release_cl2_override(struct intel_encoder
*encoder
);
3670 void chv_phy_post_pll_disable(struct intel_encoder
*encoder
);
3672 void vlv_set_phy_signal_level(struct intel_encoder
*encoder
,
3673 u32 demph_reg_value
, u32 preemph_reg_value
,
3674 u32 uniqtranscale_reg_value
, u32 tx3_demph
);
3675 void vlv_phy_pre_pll_enable(struct intel_encoder
*encoder
);
3676 void vlv_phy_pre_encoder_enable(struct intel_encoder
*encoder
);
3677 void vlv_phy_reset_lanes(struct intel_encoder
*encoder
);
3679 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3680 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3682 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3683 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3685 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3686 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3687 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3688 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3690 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3691 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3692 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3693 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3695 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3696 * will be implemented using 2 32-bit writes in an arbitrary order with
3697 * an arbitrary delay between them. This can cause the hardware to
3698 * act upon the intermediate value, possibly leading to corruption and
3699 * machine death. You have been warned.
3701 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3702 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3704 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3705 u32 upper, lower, old_upper, loop = 0; \
3706 upper = I915_READ(upper_reg); \
3708 old_upper = upper; \
3709 lower = I915_READ(lower_reg); \
3710 upper = I915_READ(upper_reg); \
3711 } while (upper != old_upper && loop++ < 2); \
3712 (u64)upper << 32 | lower; })
3714 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3715 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3717 #define __raw_read(x, s) \
3718 static inline uint##x##_t __raw_i915_read##x(struct drm_i915_private *dev_priv, \
3721 return read##s(dev_priv->regs + i915_mmio_reg_offset(reg)); \
3724 #define __raw_write(x, s) \
3725 static inline void __raw_i915_write##x(struct drm_i915_private *dev_priv, \
3726 i915_reg_t reg, uint##x##_t val) \
3728 write##s(val, dev_priv->regs + i915_mmio_reg_offset(reg)); \
3743 /* These are untraced mmio-accessors that are only valid to be used inside
3744 * criticial sections inside IRQ handlers where forcewake is explicitly
3746 * Think twice, and think again, before using these.
3747 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3748 * intel_uncore_forcewake_irqunlock().
3750 #define I915_READ_FW(reg__) __raw_i915_read32(dev_priv, (reg__))
3751 #define I915_WRITE_FW(reg__, val__) __raw_i915_write32(dev_priv, (reg__), (val__))
3752 #define I915_WRITE64_FW(reg__, val__) __raw_i915_write64(dev_priv, (reg__), (val__))
3753 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3755 /* "Broadcast RGB" property */
3756 #define INTEL_BROADCAST_RGB_AUTO 0
3757 #define INTEL_BROADCAST_RGB_FULL 1
3758 #define INTEL_BROADCAST_RGB_LIMITED 2
3760 static inline i915_reg_t
i915_vgacntrl_reg(struct drm_device
*dev
)
3762 if (IS_VALLEYVIEW(dev
) || IS_CHERRYVIEW(dev
))
3763 return VLV_VGACNTRL
;
3764 else if (INTEL_INFO(dev
)->gen
>= 5)
3765 return CPU_VGACNTRL
;
3770 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3772 unsigned long j
= msecs_to_jiffies(m
);
3774 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3777 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3779 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3782 static inline unsigned long
3783 timespec_to_jiffies_timeout(const struct timespec
*value
)
3785 unsigned long j
= timespec_to_jiffies(value
);
3787 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3791 * If you need to wait X milliseconds between events A and B, but event B
3792 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3793 * when event A happened, then just before event B you call this function and
3794 * pass the timestamp as the first argument, and X as the second argument.
3797 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3799 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3802 * Don't re-read the value of "jiffies" every time since it may change
3803 * behind our back and break the math.
3805 tmp_jiffies
= jiffies
;
3806 target_jiffies
= timestamp_jiffies
+
3807 msecs_to_jiffies_timeout(to_wait_ms
);
3809 if (time_after(target_jiffies
, tmp_jiffies
)) {
3810 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3811 while (remaining_jiffies
)
3813 schedule_timeout_uninterruptible(remaining_jiffies
);
3816 static inline bool __i915_request_irq_complete(struct drm_i915_gem_request
*req
)
3818 struct intel_engine_cs
*engine
= req
->engine
;
3820 /* Before we do the heavier coherent read of the seqno,
3821 * check the value (hopefully) in the CPU cacheline.
3823 if (i915_gem_request_completed(req
))
3826 /* Ensure our read of the seqno is coherent so that we
3827 * do not "miss an interrupt" (i.e. if this is the last
3828 * request and the seqno write from the GPU is not visible
3829 * by the time the interrupt fires, we will see that the
3830 * request is incomplete and go back to sleep awaiting
3831 * another interrupt that will never come.)
3833 * Strictly, we only need to do this once after an interrupt,
3834 * but it is easier and safer to do it every time the waiter
3837 if (engine
->irq_seqno_barrier
&&
3838 rcu_access_pointer(engine
->breadcrumbs
.irq_seqno_bh
) == current
&&
3839 cmpxchg_relaxed(&engine
->breadcrumbs
.irq_posted
, 1, 0)) {
3840 struct task_struct
*tsk
;
3842 /* The ordering of irq_posted versus applying the barrier
3843 * is crucial. The clearing of the current irq_posted must
3844 * be visible before we perform the barrier operation,
3845 * such that if a subsequent interrupt arrives, irq_posted
3846 * is reasserted and our task rewoken (which causes us to
3847 * do another __i915_request_irq_complete() immediately
3848 * and reapply the barrier). Conversely, if the clear
3849 * occurs after the barrier, then an interrupt that arrived
3850 * whilst we waited on the barrier would not trigger a
3851 * barrier on the next pass, and the read may not see the
3854 engine
->irq_seqno_barrier(engine
);
3856 /* If we consume the irq, but we are no longer the bottom-half,
3857 * the real bottom-half may not have serialised their own
3858 * seqno check with the irq-barrier (i.e. may have inspected
3859 * the seqno before we believe it coherent since they see
3860 * irq_posted == false but we are still running).
3863 tsk
= rcu_dereference(engine
->breadcrumbs
.irq_seqno_bh
);
3864 if (tsk
&& tsk
!= current
)
3865 /* Note that if the bottom-half is changed as we
3866 * are sending the wake-up, the new bottom-half will
3867 * be woken by whomever made the change. We only have
3868 * to worry about when we steal the irq-posted for
3871 wake_up_process(tsk
);
3874 if (i915_gem_request_completed(req
))
3878 /* We need to check whether any gpu reset happened in between
3879 * the request being submitted and now. If a reset has occurred,
3880 * the seqno will have been advance past ours and our request
3881 * is complete. If we are in the process of handling a reset,
3882 * the request is effectively complete as the rendering will
3883 * be discarded, but we need to return in order to drop the
3886 if (i915_reset_in_progress(&req
->i915
->gpu_error
))
3892 void i915_memcpy_init_early(struct drm_i915_private
*dev_priv
);
3893 bool i915_memcpy_from_wc(void *dst
, const void *src
, unsigned long len
);
3895 #define ptr_unpack_bits(ptr, bits) ({ \
3896 unsigned long __v = (unsigned long)(ptr); \
3897 (bits) = __v & ~PAGE_MASK; \
3898 (typeof(ptr))(__v & PAGE_MASK); \
3901 #define ptr_pack_bits(ptr, bits) \
3902 ((typeof(ptr))((unsigned long)(ptr) | (bits)))
3904 #define fetch_and_zero(ptr) ({ \
3905 typeof(*ptr) __T = *(ptr); \
3906 *(ptr) = (typeof(*ptr))0; \