1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
87 #define port_name(p) ((p) + 'A')
89 #define I915_GEM_GPU_DOMAINS \
90 (I915_GEM_DOMAIN_RENDER | \
91 I915_GEM_DOMAIN_SAMPLER | \
92 I915_GEM_DOMAIN_COMMAND | \
93 I915_GEM_DOMAIN_INSTRUCTION | \
94 I915_GEM_DOMAIN_VERTEX)
96 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
98 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
99 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
100 if ((intel_encoder)->base.crtc == (__crtc))
102 struct intel_pch_pll
{
103 int refcount
; /* count of number of CRTCs sharing this PLL */
104 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
105 bool on
; /* is the PLL actually active? Disabled during modeset */
110 #define I915_NUM_PLLS 2
112 /* Used by dp and fdi links */
113 struct intel_link_m_n
{
121 void intel_link_compute_m_n(int bpp
, int nlanes
,
122 int pixel_clock
, int link_clock
,
123 struct intel_link_m_n
*m_n
);
125 struct intel_ddi_plls
{
131 /* Interface history:
134 * 1.2: Add Power Management
135 * 1.3: Add vblank support
136 * 1.4: Fix cmdbuffer path, add heap destroy
137 * 1.5: Add vblank pipe configuration
138 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
139 * - Support vertical blank on secondary display pipe
141 #define DRIVER_MAJOR 1
142 #define DRIVER_MINOR 6
143 #define DRIVER_PATCHLEVEL 0
145 #define WATCH_COHERENCY 0
146 #define WATCH_LISTS 0
149 #define I915_GEM_PHYS_CURSOR_0 1
150 #define I915_GEM_PHYS_CURSOR_1 2
151 #define I915_GEM_PHYS_OVERLAY_REGS 3
152 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
154 struct drm_i915_gem_phys_object
{
156 struct page
**page_list
;
157 drm_dma_handle_t
*handle
;
158 struct drm_i915_gem_object
*cur_obj
;
161 struct opregion_header
;
162 struct opregion_acpi
;
163 struct opregion_swsci
;
164 struct opregion_asle
;
165 struct drm_i915_private
;
167 struct intel_opregion
{
168 struct opregion_header __iomem
*header
;
169 struct opregion_acpi __iomem
*acpi
;
170 struct opregion_swsci __iomem
*swsci
;
171 struct opregion_asle __iomem
*asle
;
173 u32 __iomem
*lid_state
;
175 #define OPREGION_SIZE (8*1024)
177 struct intel_overlay
;
178 struct intel_overlay_error_state
;
180 struct drm_i915_master_private
{
181 drm_local_map_t
*sarea
;
182 struct _drm_i915_sarea
*sarea_priv
;
184 #define I915_FENCE_REG_NONE -1
185 #define I915_MAX_NUM_FENCES 16
186 /* 16 fences + sign bit for FENCE_REG_NONE */
187 #define I915_MAX_NUM_FENCE_BITS 5
189 struct drm_i915_fence_reg
{
190 struct list_head lru_list
;
191 struct drm_i915_gem_object
*obj
;
195 struct sdvo_device_mapping
{
204 struct intel_display_error_state
;
206 struct drm_i915_error_state
{
212 bool waiting
[I915_NUM_RINGS
];
213 u32 pipestat
[I915_MAX_PIPES
];
214 u32 tail
[I915_NUM_RINGS
];
215 u32 head
[I915_NUM_RINGS
];
216 u32 ipeir
[I915_NUM_RINGS
];
217 u32 ipehr
[I915_NUM_RINGS
];
218 u32 instdone
[I915_NUM_RINGS
];
219 u32 acthd
[I915_NUM_RINGS
];
220 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
221 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
222 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
223 /* our own tracking of ring head and tail */
224 u32 cpu_ring_head
[I915_NUM_RINGS
];
225 u32 cpu_ring_tail
[I915_NUM_RINGS
];
226 u32 error
; /* gen6+ */
227 u32 err_int
; /* gen7 */
228 u32 instpm
[I915_NUM_RINGS
];
229 u32 instps
[I915_NUM_RINGS
];
230 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
231 u32 seqno
[I915_NUM_RINGS
];
233 u32 fault_reg
[I915_NUM_RINGS
];
235 u32 faddr
[I915_NUM_RINGS
];
236 u64 fence
[I915_MAX_NUM_FENCES
];
238 struct drm_i915_error_ring
{
239 struct drm_i915_error_object
{
243 } *ringbuffer
, *batchbuffer
;
244 struct drm_i915_error_request
{
250 } ring
[I915_NUM_RINGS
];
251 struct drm_i915_error_buffer
{
258 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
265 } *active_bo
, *pinned_bo
;
266 u32 active_bo_count
, pinned_bo_count
;
267 struct intel_overlay_error_state
*overlay
;
268 struct intel_display_error_state
*display
;
271 struct drm_i915_display_funcs
{
272 bool (*fbc_enabled
)(struct drm_device
*dev
);
273 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
274 void (*disable_fbc
)(struct drm_device
*dev
);
275 int (*get_display_clock_speed
)(struct drm_device
*dev
);
276 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
277 void (*update_wm
)(struct drm_device
*dev
);
278 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
279 uint32_t sprite_width
, int pixel_size
);
280 void (*update_linetime_wm
)(struct drm_device
*dev
, int pipe
,
281 struct drm_display_mode
*mode
);
282 void (*modeset_global_resources
)(struct drm_device
*dev
);
283 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
284 struct drm_display_mode
*mode
,
285 struct drm_display_mode
*adjusted_mode
,
287 struct drm_framebuffer
*old_fb
);
288 void (*crtc_enable
)(struct drm_crtc
*crtc
);
289 void (*crtc_disable
)(struct drm_crtc
*crtc
);
290 void (*off
)(struct drm_crtc
*crtc
);
291 void (*write_eld
)(struct drm_connector
*connector
,
292 struct drm_crtc
*crtc
);
293 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
294 void (*init_clock_gating
)(struct drm_device
*dev
);
295 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
296 struct drm_framebuffer
*fb
,
297 struct drm_i915_gem_object
*obj
);
298 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
300 void (*hpd_irq_setup
)(struct drm_device
*dev
);
301 /* clock updates for mode set */
303 /* render clock increase/decrease */
304 /* display clock increase/decrease */
305 /* pll clock increase/decrease */
308 struct drm_i915_gt_funcs
{
309 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
310 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
313 #define DEV_INFO_FLAGS \
314 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
315 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
316 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
317 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
318 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
319 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
320 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
321 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
322 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
323 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
324 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
325 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
326 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
327 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
328 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
329 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
330 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
331 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
332 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
333 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
334 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
335 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
336 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
337 DEV_INFO_FLAG(has_llc)
339 struct intel_device_info
{
358 u8 cursor_needs_physical
:1;
360 u8 overlay_needs_physical
:1;
367 /* The Graphics Translation Table is the way in which GEN hardware translates a
368 * Graphics Virtual Address into a Physical Address. In addition to the normal
369 * collateral associated with any va->pa translations GEN hardware also has a
370 * portion of the GTT which can be mapped by the CPU and remain both coherent
371 * and correct (in cases like swizzling). That region is referred to as GMADR in
375 unsigned long start
; /* Start offset of used GTT */
376 size_t total
; /* Total size GTT can map */
378 unsigned long mappable_end
; /* End offset that we can CPU map */
379 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
380 phys_addr_t mappable_base
; /* PA of our GMADR */
382 /** "Graphics Stolen Memory" holds the global PTEs */
386 dma_addr_t scratch_page_dma
;
387 struct page
*scratch_page
;
390 #define I915_PPGTT_PD_ENTRIES 512
391 #define I915_PPGTT_PT_ENTRIES 1024
392 struct i915_hw_ppgtt
{
393 struct drm_device
*dev
;
394 unsigned num_pd_entries
;
395 struct page
**pt_pages
;
397 dma_addr_t
*pt_dma_addr
;
398 dma_addr_t scratch_page_dma_addr
;
402 /* This must match up with the value previously used for execbuf2.rsvd1. */
403 #define DEFAULT_CONTEXT_ID 0
404 struct i915_hw_context
{
407 struct drm_i915_file_private
*file_priv
;
408 struct intel_ring_buffer
*ring
;
409 struct drm_i915_gem_object
*obj
;
413 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
414 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
415 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
416 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
417 FBC_BAD_PLANE
, /* fbc not supported on plane */
418 FBC_NOT_TILED
, /* buffer not tiled */
419 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
424 PCH_NONE
= 0, /* No PCH present */
425 PCH_IBX
, /* Ibexpeak PCH */
426 PCH_CPT
, /* Cougarpoint PCH */
427 PCH_LPT
, /* Lynxpoint PCH */
430 enum intel_sbi_destination
{
435 #define QUIRK_PIPEA_FORCE (1<<0)
436 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
437 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
440 struct intel_fbc_work
;
443 struct i2c_adapter adapter
;
447 struct i2c_algo_bit_data bit_algo
;
448 struct drm_i915_private
*dev_priv
;
451 struct i915_suspend_saved_registers
{
472 u32 saveTRANS_HTOTAL_A
;
473 u32 saveTRANS_HBLANK_A
;
474 u32 saveTRANS_HSYNC_A
;
475 u32 saveTRANS_VTOTAL_A
;
476 u32 saveTRANS_VBLANK_A
;
477 u32 saveTRANS_VSYNC_A
;
485 u32 savePFIT_PGM_RATIOS
;
486 u32 saveBLC_HIST_CTL
;
488 u32 saveBLC_PWM_CTL2
;
489 u32 saveBLC_CPU_PWM_CTL
;
490 u32 saveBLC_CPU_PWM_CTL2
;
503 u32 saveTRANS_HTOTAL_B
;
504 u32 saveTRANS_HBLANK_B
;
505 u32 saveTRANS_HSYNC_B
;
506 u32 saveTRANS_VTOTAL_B
;
507 u32 saveTRANS_VBLANK_B
;
508 u32 saveTRANS_VSYNC_B
;
522 u32 savePP_ON_DELAYS
;
523 u32 savePP_OFF_DELAYS
;
531 u32 savePFIT_CONTROL
;
532 u32 save_palette_a
[256];
533 u32 save_palette_b
[256];
534 u32 saveDPFC_CB_BASE
;
535 u32 saveFBC_CFB_BASE
;
538 u32 saveFBC_CONTROL2
;
548 u32 saveCACHE_MODE_0
;
549 u32 saveMI_ARB_STATE
;
560 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
571 u32 savePIPEA_GMCH_DATA_M
;
572 u32 savePIPEB_GMCH_DATA_M
;
573 u32 savePIPEA_GMCH_DATA_N
;
574 u32 savePIPEB_GMCH_DATA_N
;
575 u32 savePIPEA_DP_LINK_M
;
576 u32 savePIPEB_DP_LINK_M
;
577 u32 savePIPEA_DP_LINK_N
;
578 u32 savePIPEB_DP_LINK_N
;
589 u32 savePCH_DREF_CONTROL
;
590 u32 saveDISP_ARB_CTL
;
591 u32 savePIPEA_DATA_M1
;
592 u32 savePIPEA_DATA_N1
;
593 u32 savePIPEA_LINK_M1
;
594 u32 savePIPEA_LINK_N1
;
595 u32 savePIPEB_DATA_M1
;
596 u32 savePIPEB_DATA_N1
;
597 u32 savePIPEB_LINK_M1
;
598 u32 savePIPEB_LINK_N1
;
599 u32 saveMCHBAR_RENDER_STANDBY
;
600 u32 savePCH_PORT_HOTPLUG
;
603 struct intel_gen6_power_mgmt
{
604 struct work_struct work
;
606 /* lock - irqsave spinlock that protectects the work_struct and
610 /* The below variables an all the rps hw state are protected by
611 * dev->struct mutext. */
616 struct delayed_work delayed_resume_work
;
619 * Protects RPS/RC6 register access and PCU communication.
620 * Must be taken after struct_mutex if nested.
622 struct mutex hw_lock
;
625 /* defined intel_pm.c */
626 extern spinlock_t mchdev_lock
;
628 struct intel_ilk_power_mgmt
{
636 unsigned long last_time1
;
637 unsigned long chipset_power
;
639 struct timespec last_time2
;
640 unsigned long gfx_power
;
646 struct drm_i915_gem_object
*pwrctx
;
647 struct drm_i915_gem_object
*renderctx
;
650 struct i915_dri1_state
{
651 unsigned allow_batchbuffer
: 1;
652 u32 __iomem
*gfx_hws_cpu_addr
;
663 struct intel_l3_parity
{
665 struct work_struct error_work
;
669 /** Bridge to intel-gtt-ko */
670 struct intel_gtt
*gtt
;
671 /** Memory allocator for GTT stolen memory */
672 struct drm_mm stolen
;
673 /** Memory allocator for GTT */
674 struct drm_mm gtt_space
;
675 /** List of all objects in gtt_space. Used to restore gtt
676 * mappings on resume */
677 struct list_head bound_list
;
679 * List of objects which are not bound to the GTT (thus
680 * are idle and not used by the GPU) but still have
681 * (presumably uncached) pages still attached.
683 struct list_head unbound_list
;
685 /** Usable portion of the GTT for GEM */
686 unsigned long stolen_base
; /* limited to low memory (32-bit) */
690 /** PPGTT used for aliasing the PPGTT with the GTT */
691 struct i915_hw_ppgtt
*aliasing_ppgtt
;
693 struct shrinker inactive_shrinker
;
694 bool shrinker_no_lock_stealing
;
697 * List of objects currently involved in rendering.
699 * Includes buffers having the contents of their GPU caches
700 * flushed, not necessarily primitives. last_rendering_seqno
701 * represents when the rendering involved will be completed.
703 * A reference is held on the buffer while on this list.
705 struct list_head active_list
;
708 * LRU list of objects which are not in the ringbuffer and
709 * are ready to unbind, but are still in the GTT.
711 * last_rendering_seqno is 0 while an object is in this list.
713 * A reference is not held on the buffer while on this list,
714 * as merely being GTT-bound shouldn't prevent its being
715 * freed, and we'll pull it off the list in the free path.
717 struct list_head inactive_list
;
719 /** LRU list of objects with fence regs on them. */
720 struct list_head fence_list
;
723 * We leave the user IRQ off as much as possible,
724 * but this means that requests will finish and never
725 * be retired once the system goes idle. Set a timer to
726 * fire periodically while the ring is running. When it
727 * fires, go retire requests.
729 struct delayed_work retire_work
;
732 * Are we in a non-interruptible section of code like
738 * Flag if the X Server, and thus DRM, is not currently in
739 * control of the device.
741 * This is set between LeaveVT and EnterVT. It needs to be
742 * replaced with a semaphore. It also needs to be
743 * transitioned away from for kernel modesetting.
747 /** Bit 6 swizzling required for X tiling */
748 uint32_t bit_6_swizzle_x
;
749 /** Bit 6 swizzling required for Y tiling */
750 uint32_t bit_6_swizzle_y
;
752 /* storage for physical objects */
753 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
755 /* accounting, useful for userland debugging */
756 size_t object_memory
;
760 struct i915_gpu_error
{
761 /* For hangcheck timer */
762 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
763 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
764 struct timer_list hangcheck_timer
;
766 uint32_t last_acthd
[I915_NUM_RINGS
];
767 uint32_t prev_instdone
[I915_NUM_INSTDONE_REG
];
769 /* For reset and error_state handling. */
771 /* Protected by the above dev->gpu_error.lock. */
772 struct drm_i915_error_state
*first_error
;
773 struct work_struct work
;
775 unsigned long last_reset
;
778 * State variable controlling the reset flow
780 * Upper bits are for the reset counter.
782 * Lowest bit controls the reset state machine: Set means a reset is in
783 * progress. This state will (presuming we don't have any bugs) decay
784 * into either unset (successful reset) or the special WEDGED value (hw
785 * terminally sour). All waiters on the reset_queue will be woken when
788 atomic_t reset_counter
;
791 * Special values/flags for reset_counter
793 * Note that the code relies on
794 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
797 #define I915_RESET_IN_PROGRESS_FLAG 1
798 #define I915_WEDGED 0xffffffff
801 * Waitqueue to signal when the reset has completed. Used by clients
802 * that wait for dev_priv->mm.wedged to settle.
804 wait_queue_head_t reset_queue
;
806 /* For gpu hang simulation. */
807 unsigned int stop_rings
;
810 typedef struct drm_i915_private
{
811 struct drm_device
*dev
;
812 struct kmem_cache
*slab
;
814 const struct intel_device_info
*info
;
816 int relative_constants_mode
;
820 struct drm_i915_gt_funcs gt
;
821 /** gt_fifo_count and the subsequent register write are synchronized
822 * with dev->struct_mutex. */
823 unsigned gt_fifo_count
;
824 /** forcewake_count is protected by gt_lock */
825 unsigned forcewake_count
;
826 /** gt_lock is also taken in irq contexts. */
829 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
832 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
833 * controller on different i2c buses. */
834 struct mutex gmbus_mutex
;
837 * Base address of the gmbus and gpio block.
839 uint32_t gpio_mmio_base
;
841 wait_queue_head_t gmbus_wait_queue
;
843 struct pci_dev
*bridge_dev
;
844 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
845 uint32_t last_seqno
, next_seqno
;
847 drm_dma_handle_t
*status_page_dmah
;
848 struct resource mch_res
;
850 atomic_t irq_received
;
852 /* protects the irq masks */
855 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
856 struct pm_qos_request pm_qos
;
858 /* DPIO indirect register protection */
859 struct mutex dpio_lock
;
861 /** Cached value of IMR to avoid reads in updating the bitfield */
866 u32 hotplug_supported_mask
;
867 struct work_struct hotplug_work
;
868 bool enable_hotplug_processing
;
873 unsigned long cfb_size
;
875 enum plane cfb_plane
;
877 struct intel_fbc_work
*fbc_work
;
879 struct intel_opregion opregion
;
882 struct intel_overlay
*overlay
;
883 bool sprite_scaling_enabled
;
886 int backlight_level
; /* restore backlight to this value */
887 bool backlight_enabled
;
888 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
889 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
891 /* Feature bits from the VBIOS */
892 unsigned int int_tv_support
:1;
893 unsigned int lvds_dither
:1;
894 unsigned int lvds_vbt
:1;
895 unsigned int int_crt_support
:1;
896 unsigned int lvds_use_ssc
:1;
897 unsigned int display_clock_mode
:1;
899 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
909 struct edp_power_seq pps
;
911 bool no_aux_handshake
;
914 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
915 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
916 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
918 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
920 struct workqueue_struct
*wq
;
922 /* Display functions */
923 struct drm_i915_display_funcs display
;
925 /* PCH chipset type */
926 enum intel_pch pch_type
;
927 unsigned short pch_id
;
929 unsigned long quirks
;
936 struct i915_gem_mm mm
;
938 /* Kernel Modesetting */
940 struct sdvo_device_mapping sdvo_mappings
[2];
941 /* indicate whether the LVDS_BORDER should be enabled or not */
942 unsigned int lvds_border_bits
;
943 /* Panel fitter placement and size for Ironlake+ */
944 u32 pch_pf_pos
, pch_pf_size
;
946 struct drm_crtc
*plane_to_crtc_mapping
[3];
947 struct drm_crtc
*pipe_to_crtc_mapping
[3];
948 wait_queue_head_t pending_flip_queue
;
950 struct intel_pch_pll pch_plls
[I915_NUM_PLLS
];
951 struct intel_ddi_plls ddi_plls
;
953 /* Reclocking support */
954 bool render_reclock_avail
;
955 bool lvds_downclock_avail
;
956 /* indicates the reduced downclock for LVDS*/
960 struct child_device_config
*child_dev
;
962 bool mchbar_need_disable
;
964 struct intel_l3_parity l3_parity
;
966 /* gen6+ rps state */
967 struct intel_gen6_power_mgmt rps
;
969 /* ilk-only ips/rps state. Everything in here is protected by the global
970 * mchdev_lock in intel_pm.c */
971 struct intel_ilk_power_mgmt ips
;
973 enum no_fbc_reason no_fbc_reason
;
975 struct drm_mm_node
*compressed_fb
;
976 struct drm_mm_node
*compressed_llb
;
978 struct i915_gpu_error gpu_error
;
980 /* list of fbdev register on this device */
981 struct intel_fbdev
*fbdev
;
984 * The console may be contended at resume, but we don't
985 * want it to block on it.
987 struct work_struct console_resume_work
;
989 struct backlight_device
*backlight
;
991 struct drm_property
*broadcast_rgb_property
;
992 struct drm_property
*force_audio_property
;
994 bool hw_contexts_disabled
;
995 uint32_t hw_context_size
;
997 bool fdi_rx_polarity_reversed
;
999 struct i915_suspend_saved_registers regfile
;
1001 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1003 struct i915_dri1_state dri1
;
1004 } drm_i915_private_t
;
1006 /* Iterate over initialised rings */
1007 #define for_each_ring(ring__, dev_priv__, i__) \
1008 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1009 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1011 enum hdmi_force_audio
{
1012 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1013 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1014 HDMI_AUDIO_AUTO
, /* trust EDID */
1015 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1018 enum i915_cache_level
{
1019 I915_CACHE_NONE
= 0,
1021 I915_CACHE_LLC_MLC
, /* gen6+, in docs at least! */
1024 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1026 struct drm_i915_gem_object_ops
{
1027 /* Interface between the GEM object and its backing storage.
1028 * get_pages() is called once prior to the use of the associated set
1029 * of pages before to binding them into the GTT, and put_pages() is
1030 * called after we no longer need them. As we expect there to be
1031 * associated cost with migrating pages between the backing storage
1032 * and making them available for the GPU (e.g. clflush), we may hold
1033 * onto the pages after they are no longer referenced by the GPU
1034 * in case they may be used again shortly (for example migrating the
1035 * pages to a different memory domain within the GTT). put_pages()
1036 * will therefore most likely be called when the object itself is
1037 * being released or under memory pressure (where we attempt to
1038 * reap pages for the shrinker).
1040 int (*get_pages
)(struct drm_i915_gem_object
*);
1041 void (*put_pages
)(struct drm_i915_gem_object
*);
1044 struct drm_i915_gem_object
{
1045 struct drm_gem_object base
;
1047 const struct drm_i915_gem_object_ops
*ops
;
1049 /** Current space allocated to this object in the GTT, if any. */
1050 struct drm_mm_node
*gtt_space
;
1051 /** Stolen memory for this object, instead of being backed by shmem. */
1052 struct drm_mm_node
*stolen
;
1053 struct list_head gtt_list
;
1055 /** This object's place on the active/inactive lists */
1056 struct list_head ring_list
;
1057 struct list_head mm_list
;
1058 /** This object's place in the batchbuffer or on the eviction list */
1059 struct list_head exec_list
;
1062 * This is set if the object is on the active lists (has pending
1063 * rendering and so a non-zero seqno), and is not set if it i s on
1064 * inactive (ready to be unbound) list.
1066 unsigned int active
:1;
1069 * This is set if the object has been written to since last bound
1072 unsigned int dirty
:1;
1075 * Fence register bits (if any) for this object. Will be set
1076 * as needed when mapped into the GTT.
1077 * Protected by dev->struct_mutex.
1079 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1082 * Advice: are the backing pages purgeable?
1084 unsigned int madv
:2;
1087 * Current tiling mode for the object.
1089 unsigned int tiling_mode
:2;
1091 * Whether the tiling parameters for the currently associated fence
1092 * register have changed. Note that for the purposes of tracking
1093 * tiling changes we also treat the unfenced register, the register
1094 * slot that the object occupies whilst it executes a fenced
1095 * command (such as BLT on gen2/3), as a "fence".
1097 unsigned int fence_dirty
:1;
1099 /** How many users have pinned this object in GTT space. The following
1100 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1101 * (via user_pin_count), execbuffer (objects are not allowed multiple
1102 * times for the same batchbuffer), and the framebuffer code. When
1103 * switching/pageflipping, the framebuffer code has at most two buffers
1106 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1107 * bits with absolutely no headroom. So use 4 bits. */
1108 unsigned int pin_count
:4;
1109 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1112 * Is the object at the current location in the gtt mappable and
1113 * fenceable? Used to avoid costly recalculations.
1115 unsigned int map_and_fenceable
:1;
1118 * Whether the current gtt mapping needs to be mappable (and isn't just
1119 * mappable by accident). Track pin and fault separate for a more
1120 * accurate mappable working set.
1122 unsigned int fault_mappable
:1;
1123 unsigned int pin_mappable
:1;
1126 * Is the GPU currently using a fence to access this buffer,
1128 unsigned int pending_fenced_gpu_access
:1;
1129 unsigned int fenced_gpu_access
:1;
1131 unsigned int cache_level
:2;
1133 unsigned int has_aliasing_ppgtt_mapping
:1;
1134 unsigned int has_global_gtt_mapping
:1;
1135 unsigned int has_dma_mapping
:1;
1137 struct sg_table
*pages
;
1138 int pages_pin_count
;
1140 /* prime dma-buf support */
1141 void *dma_buf_vmapping
;
1145 * Used for performing relocations during execbuffer insertion.
1147 struct hlist_node exec_node
;
1148 unsigned long exec_handle
;
1149 struct drm_i915_gem_exec_object2
*exec_entry
;
1152 * Current offset of the object in GTT space.
1154 * This is the same as gtt_space->start
1156 uint32_t gtt_offset
;
1158 struct intel_ring_buffer
*ring
;
1160 /** Breadcrumb of last rendering to the buffer. */
1161 uint32_t last_read_seqno
;
1162 uint32_t last_write_seqno
;
1163 /** Breadcrumb of last fenced GPU access to the buffer. */
1164 uint32_t last_fenced_seqno
;
1166 /** Current tiling stride for the object, if it's tiled. */
1169 /** Record of address bit 17 of each page at last unbind. */
1170 unsigned long *bit_17
;
1172 /** User space pin count and filp owning the pin */
1173 uint32_t user_pin_count
;
1174 struct drm_file
*pin_filp
;
1176 /** for phy allocated objects */
1177 struct drm_i915_gem_phys_object
*phys_obj
;
1180 * Number of crtcs where this object is currently the fb, but
1181 * will be page flipped away on the next vblank. When it
1182 * reaches 0, dev_priv->pending_flip_queue will be woken up.
1184 atomic_t pending_flip
;
1186 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1188 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1191 * Request queue structure.
1193 * The request queue allows us to note sequence numbers that have been emitted
1194 * and may be associated with active buffers to be retired.
1196 * By keeping this list, we can avoid having to do questionable
1197 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1198 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1200 struct drm_i915_gem_request
{
1201 /** On Which ring this request was generated */
1202 struct intel_ring_buffer
*ring
;
1204 /** GEM sequence number associated with this request. */
1207 /** Postion in the ringbuffer of the end of the request */
1210 /** Time at which this request was emitted, in jiffies. */
1211 unsigned long emitted_jiffies
;
1213 /** global list entry for this request */
1214 struct list_head list
;
1216 struct drm_i915_file_private
*file_priv
;
1217 /** file_priv list entry for this request */
1218 struct list_head client_list
;
1221 struct drm_i915_file_private
{
1224 struct list_head request_list
;
1226 struct idr context_idr
;
1229 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1231 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1232 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1233 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1234 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1235 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1236 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1237 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1238 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1239 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1240 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1241 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1242 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1243 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1244 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1245 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1246 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1247 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1248 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1249 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1250 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1251 (dev)->pci_device == 0x0152 || \
1252 (dev)->pci_device == 0x015a)
1253 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1254 (dev)->pci_device == 0x0106 || \
1255 (dev)->pci_device == 0x010A)
1256 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1257 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1258 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1259 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1260 ((dev)->pci_device & 0xFF00) == 0x0A00)
1263 * The genX designation typically refers to the render engine, so render
1264 * capability related checks should use IS_GEN, while display and other checks
1265 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1268 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1269 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1270 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1271 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1272 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1273 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1275 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1276 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1277 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1278 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1280 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1281 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1283 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1284 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1286 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1287 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1289 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1290 * rows, which changed the alignment requirements and fence programming.
1292 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1294 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1295 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1296 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1297 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1298 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1299 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1300 /* dsparb controlled by hw only */
1301 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1303 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1304 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1305 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1307 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1309 #define HAS_DDI(dev) (IS_HASWELL(dev))
1311 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1312 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1313 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1314 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1315 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1316 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1318 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1319 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1320 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1321 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1322 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1324 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1326 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1328 #define GT_FREQUENCY_MULTIPLIER 50
1330 #include "i915_trace.h"
1333 * RC6 is a special power stage which allows the GPU to enter an very
1334 * low-voltage mode when idle, using down to 0V while at this stage. This
1335 * stage is entered automatically when the GPU is idle when RC6 support is
1336 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1338 * There are different RC6 modes available in Intel GPU, which differentiate
1339 * among each other with the latency required to enter and leave RC6 and
1340 * voltage consumed by the GPU in different states.
1342 * The combination of the following flags define which states GPU is allowed
1343 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1344 * RC6pp is deepest RC6. Their support by hardware varies according to the
1345 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1346 * which brings the most power savings; deeper states save more power, but
1347 * require higher latency to switch to and wake up.
1349 #define INTEL_RC6_ENABLE (1<<0)
1350 #define INTEL_RC6p_ENABLE (1<<1)
1351 #define INTEL_RC6pp_ENABLE (1<<2)
1353 extern struct drm_ioctl_desc i915_ioctls
[];
1354 extern int i915_max_ioctl
;
1355 extern unsigned int i915_fbpercrtc __always_unused
;
1356 extern int i915_panel_ignore_lid __read_mostly
;
1357 extern unsigned int i915_powersave __read_mostly
;
1358 extern int i915_semaphores __read_mostly
;
1359 extern unsigned int i915_lvds_downclock __read_mostly
;
1360 extern int i915_lvds_channel_mode __read_mostly
;
1361 extern int i915_panel_use_ssc __read_mostly
;
1362 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1363 extern int i915_enable_rc6 __read_mostly
;
1364 extern int i915_enable_fbc __read_mostly
;
1365 extern bool i915_enable_hangcheck __read_mostly
;
1366 extern int i915_enable_ppgtt __read_mostly
;
1367 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1369 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1370 extern int i915_resume(struct drm_device
*dev
);
1371 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1372 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1375 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1376 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1377 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1378 extern int i915_driver_unload(struct drm_device
*);
1379 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1380 extern void i915_driver_lastclose(struct drm_device
* dev
);
1381 extern void i915_driver_preclose(struct drm_device
*dev
,
1382 struct drm_file
*file_priv
);
1383 extern void i915_driver_postclose(struct drm_device
*dev
,
1384 struct drm_file
*file_priv
);
1385 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1386 #ifdef CONFIG_COMPAT
1387 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1390 extern int i915_emit_box(struct drm_device
*dev
,
1391 struct drm_clip_rect
*box
,
1393 extern int intel_gpu_reset(struct drm_device
*dev
);
1394 extern int i915_reset(struct drm_device
*dev
);
1395 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1396 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1397 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1398 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1400 extern void intel_console_resume(struct work_struct
*work
);
1403 void i915_hangcheck_elapsed(unsigned long data
);
1404 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1406 extern void intel_irq_init(struct drm_device
*dev
);
1407 extern void intel_hpd_init(struct drm_device
*dev
);
1408 extern void intel_gt_init(struct drm_device
*dev
);
1409 extern void intel_gt_reset(struct drm_device
*dev
);
1411 void i915_error_state_free(struct kref
*error_ref
);
1414 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1417 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1419 void intel_enable_asle(struct drm_device
*dev
);
1421 #ifdef CONFIG_DEBUG_FS
1422 extern void i915_destroy_error_state(struct drm_device
*dev
);
1424 #define i915_destroy_error_state(x)
1429 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1430 struct drm_file
*file_priv
);
1431 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1432 struct drm_file
*file_priv
);
1433 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1434 struct drm_file
*file_priv
);
1435 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1436 struct drm_file
*file_priv
);
1437 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1438 struct drm_file
*file_priv
);
1439 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1440 struct drm_file
*file_priv
);
1441 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1442 struct drm_file
*file_priv
);
1443 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1444 struct drm_file
*file_priv
);
1445 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1446 struct drm_file
*file_priv
);
1447 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1448 struct drm_file
*file_priv
);
1449 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1450 struct drm_file
*file_priv
);
1451 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1452 struct drm_file
*file_priv
);
1453 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1454 struct drm_file
*file_priv
);
1455 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1456 struct drm_file
*file
);
1457 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1458 struct drm_file
*file
);
1459 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1460 struct drm_file
*file_priv
);
1461 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1462 struct drm_file
*file_priv
);
1463 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1464 struct drm_file
*file_priv
);
1465 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1466 struct drm_file
*file_priv
);
1467 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1468 struct drm_file
*file_priv
);
1469 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1470 struct drm_file
*file_priv
);
1471 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1472 struct drm_file
*file_priv
);
1473 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1474 struct drm_file
*file_priv
);
1475 void i915_gem_load(struct drm_device
*dev
);
1476 void *i915_gem_object_alloc(struct drm_device
*dev
);
1477 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1478 int i915_gem_init_object(struct drm_gem_object
*obj
);
1479 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1480 const struct drm_i915_gem_object_ops
*ops
);
1481 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1483 void i915_gem_free_object(struct drm_gem_object
*obj
);
1485 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1487 bool map_and_fenceable
,
1489 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1490 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1491 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1492 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1493 void i915_gem_lastclose(struct drm_device
*dev
);
1495 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1496 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1498 struct scatterlist
*sg
= obj
->pages
->sgl
;
1499 int nents
= obj
->pages
->nents
;
1500 while (nents
> SG_MAX_SINGLE_ALLOC
) {
1501 if (n
< SG_MAX_SINGLE_ALLOC
- 1)
1504 sg
= sg_chain_ptr(sg
+ SG_MAX_SINGLE_ALLOC
- 1);
1505 n
-= SG_MAX_SINGLE_ALLOC
- 1;
1506 nents
-= SG_MAX_SINGLE_ALLOC
- 1;
1508 return sg_page(sg
+n
);
1510 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1512 BUG_ON(obj
->pages
== NULL
);
1513 obj
->pages_pin_count
++;
1515 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1517 BUG_ON(obj
->pages_pin_count
== 0);
1518 obj
->pages_pin_count
--;
1521 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1522 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1523 struct intel_ring_buffer
*to
);
1524 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1525 struct intel_ring_buffer
*ring
);
1527 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1528 struct drm_device
*dev
,
1529 struct drm_mode_create_dumb
*args
);
1530 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1531 uint32_t handle
, uint64_t *offset
);
1532 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1535 * Returns true if seq1 is later than seq2.
1538 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1540 return (int32_t)(seq1
- seq2
) >= 0;
1543 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1544 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1545 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1546 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1549 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1551 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1552 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1553 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1560 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1562 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1563 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1564 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1568 void i915_gem_retire_requests(struct drm_device
*dev
);
1569 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1570 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1571 bool interruptible
);
1572 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1574 return unlikely(atomic_read(&error
->reset_counter
)
1575 & I915_RESET_IN_PROGRESS_FLAG
);
1578 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1580 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1583 void i915_gem_reset(struct drm_device
*dev
);
1584 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1585 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1586 uint32_t read_domains
,
1587 uint32_t write_domain
);
1588 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1589 int __must_check
i915_gem_init(struct drm_device
*dev
);
1590 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1591 void i915_gem_l3_remap(struct drm_device
*dev
);
1592 void i915_gem_init_swizzling(struct drm_device
*dev
);
1593 void i915_gem_init_ppgtt(struct drm_device
*dev
);
1594 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1595 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1596 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1597 int i915_add_request(struct intel_ring_buffer
*ring
,
1598 struct drm_file
*file
,
1600 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1602 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1604 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1607 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1609 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1611 struct intel_ring_buffer
*pipelined
);
1612 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1613 struct drm_i915_gem_object
*obj
,
1616 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1617 struct drm_i915_gem_object
*obj
);
1618 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1619 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1622 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
1624 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1625 int tiling_mode
, bool fenced
);
1627 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1628 enum i915_cache_level cache_level
);
1630 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1631 struct dma_buf
*dma_buf
);
1633 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1634 struct drm_gem_object
*gem_obj
, int flags
);
1636 /* i915_gem_context.c */
1637 void i915_gem_context_init(struct drm_device
*dev
);
1638 void i915_gem_context_fini(struct drm_device
*dev
);
1639 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1640 int i915_switch_context(struct intel_ring_buffer
*ring
,
1641 struct drm_file
*file
, int to_id
);
1642 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1643 struct drm_file
*file
);
1644 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1645 struct drm_file
*file
);
1647 /* i915_gem_gtt.c */
1648 int __must_check
i915_gem_init_aliasing_ppgtt(struct drm_device
*dev
);
1649 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1650 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1651 struct drm_i915_gem_object
*obj
,
1652 enum i915_cache_level cache_level
);
1653 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1654 struct drm_i915_gem_object
*obj
);
1656 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1657 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1658 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1659 enum i915_cache_level cache_level
);
1660 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1661 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1662 void i915_gem_init_global_gtt(struct drm_device
*dev
);
1663 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
1664 unsigned long mappable_end
, unsigned long end
);
1665 int i915_gem_gtt_init(struct drm_device
*dev
);
1666 void i915_gem_gtt_fini(struct drm_device
*dev
);
1667 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
1669 if (INTEL_INFO(dev
)->gen
< 6)
1670 intel_gtt_chipset_flush();
1674 /* i915_gem_evict.c */
1675 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1677 unsigned cache_level
,
1680 int i915_gem_evict_everything(struct drm_device
*dev
);
1682 /* i915_gem_stolen.c */
1683 int i915_gem_init_stolen(struct drm_device
*dev
);
1684 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
1685 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
1686 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1687 struct drm_i915_gem_object
*
1688 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
1689 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
1691 /* i915_gem_tiling.c */
1692 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
1694 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
1696 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
1697 obj
->tiling_mode
!= I915_TILING_NONE
;
1700 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1701 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1702 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1704 /* i915_gem_debug.c */
1705 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1706 const char *where
, uint32_t mark
);
1708 int i915_verify_lists(struct drm_device
*dev
);
1710 #define i915_verify_lists(dev) 0
1712 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1714 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1715 const char *where
, uint32_t mark
);
1717 /* i915_debugfs.c */
1718 int i915_debugfs_init(struct drm_minor
*minor
);
1719 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1721 /* i915_suspend.c */
1722 extern int i915_save_state(struct drm_device
*dev
);
1723 extern int i915_restore_state(struct drm_device
*dev
);
1725 /* i915_suspend.c */
1726 extern int i915_save_state(struct drm_device
*dev
);
1727 extern int i915_restore_state(struct drm_device
*dev
);
1730 void i915_setup_sysfs(struct drm_device
*dev_priv
);
1731 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
1734 extern int intel_setup_gmbus(struct drm_device
*dev
);
1735 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1736 extern inline bool intel_gmbus_is_port_valid(unsigned port
)
1738 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
1741 extern struct i2c_adapter
*intel_gmbus_get_adapter(
1742 struct drm_i915_private
*dev_priv
, unsigned port
);
1743 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1744 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1745 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1747 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1749 extern void intel_i2c_reset(struct drm_device
*dev
);
1751 /* intel_opregion.c */
1752 extern int intel_opregion_setup(struct drm_device
*dev
);
1754 extern void intel_opregion_init(struct drm_device
*dev
);
1755 extern void intel_opregion_fini(struct drm_device
*dev
);
1756 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1757 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1758 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1760 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1761 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1762 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1763 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1764 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1769 extern void intel_register_dsm_handler(void);
1770 extern void intel_unregister_dsm_handler(void);
1772 static inline void intel_register_dsm_handler(void) { return; }
1773 static inline void intel_unregister_dsm_handler(void) { return; }
1774 #endif /* CONFIG_ACPI */
1777 extern void intel_modeset_init_hw(struct drm_device
*dev
);
1778 extern void intel_modeset_init(struct drm_device
*dev
);
1779 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1780 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1781 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1782 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
1783 bool force_restore
);
1784 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1785 extern void intel_disable_fbc(struct drm_device
*dev
);
1786 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1787 extern void intel_init_pch_refclk(struct drm_device
*dev
);
1788 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1789 extern void intel_detect_pch(struct drm_device
*dev
);
1790 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1791 extern int intel_enable_rc6(const struct drm_device
*dev
);
1793 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
1794 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
1795 struct drm_file
*file
);
1798 #ifdef CONFIG_DEBUG_FS
1799 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1800 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1802 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1803 extern void intel_display_print_error_state(struct seq_file
*m
,
1804 struct drm_device
*dev
,
1805 struct intel_display_error_state
*error
);
1808 /* On SNB platform, before reading ring registers forcewake bit
1809 * must be set to prevent GT core from power down and stale values being
1812 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1813 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1814 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1816 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
1817 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
1819 #define __i915_read(x, y) \
1820 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1828 #define __i915_write(x, y) \
1829 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1837 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1838 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1840 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1841 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1842 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1843 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1845 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1846 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1847 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1848 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1850 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1851 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1853 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1854 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1856 /* "Broadcast RGB" property */
1857 #define INTEL_BROADCAST_RGB_AUTO 0
1858 #define INTEL_BROADCAST_RGB_FULL 1
1859 #define INTEL_BROADCAST_RGB_LIMITED 2