1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150227"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
73 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
74 (long) (x), __func__);
76 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
77 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
78 * which may not necessarily be a user visible problem. This will either
79 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
80 * enable distros and users to tailor their preferred amount of i915 abrt
83 #define I915_STATE_WARN(condition, format...) ({ \
84 int __ret_warn_on = !!(condition); \
85 if (unlikely(__ret_warn_on)) { \
86 if (i915.verbose_state_checks) \
91 unlikely(__ret_warn_on); \
94 #define I915_STATE_WARN_ON(condition) ({ \
95 int __ret_warn_on = !!(condition); \
96 if (unlikely(__ret_warn_on)) { \
97 if (i915.verbose_state_checks) \
98 WARN(1, "WARN_ON(" #condition ")\n"); \
100 DRM_ERROR("WARN_ON(" #condition ")\n"); \
102 unlikely(__ret_warn_on); \
111 I915_MAX_PIPES
= _PIPE_EDP
113 #define pipe_name(p) ((p) + 'A')
122 #define transcoder_name(t) ((t) + 'A')
125 * This is the maximum (across all platforms) number of planes (primary +
126 * sprites) that can be active at the same time on one pipe.
128 * This value doesn't count the cursor plane.
130 #define I915_MAX_PLANES 3
137 #define plane_name(p) ((p) + 'A')
139 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
149 #define port_name(p) ((p) + 'A')
151 #define I915_NUM_PHYS_VLV 2
163 enum intel_display_power_domain
{
167 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
168 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
169 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
170 POWER_DOMAIN_TRANSCODER_A
,
171 POWER_DOMAIN_TRANSCODER_B
,
172 POWER_DOMAIN_TRANSCODER_C
,
173 POWER_DOMAIN_TRANSCODER_EDP
,
174 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
175 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
176 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
177 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
178 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
179 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
180 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
181 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
182 POWER_DOMAIN_PORT_DSI
,
183 POWER_DOMAIN_PORT_CRT
,
184 POWER_DOMAIN_PORT_OTHER
,
197 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
198 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
199 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
200 #define POWER_DOMAIN_TRANSCODER(tran) \
201 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
202 (tran) + POWER_DOMAIN_TRANSCODER_A)
206 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
207 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
217 #define I915_GEM_GPU_DOMAINS \
218 (I915_GEM_DOMAIN_RENDER | \
219 I915_GEM_DOMAIN_SAMPLER | \
220 I915_GEM_DOMAIN_COMMAND | \
221 I915_GEM_DOMAIN_INSTRUCTION | \
222 I915_GEM_DOMAIN_VERTEX)
224 #define for_each_pipe(__dev_priv, __p) \
225 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
226 #define for_each_plane(__dev_priv, __pipe, __p) \
228 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
230 #define for_each_sprite(__dev_priv, __p, __s) \
232 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
235 #define for_each_crtc(dev, crtc) \
236 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
238 #define for_each_intel_crtc(dev, intel_crtc) \
239 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
241 #define for_each_intel_encoder(dev, intel_encoder) \
242 list_for_each_entry(intel_encoder, \
243 &(dev)->mode_config.encoder_list, \
246 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
247 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
248 if ((intel_encoder)->base.crtc == (__crtc))
250 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
251 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
252 if ((intel_connector)->base.encoder == (__encoder))
254 #define for_each_power_domain(domain, mask) \
255 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
256 if ((1 << (domain)) & (mask))
258 struct drm_i915_private
;
259 struct i915_mm_struct
;
260 struct i915_mmu_object
;
263 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
264 /* real shared dpll ids must be >= 0 */
265 DPLL_ID_PCH_PLL_A
= 0,
266 DPLL_ID_PCH_PLL_B
= 1,
271 DPLL_ID_SKL_DPLL1
= 0,
272 DPLL_ID_SKL_DPLL2
= 1,
273 DPLL_ID_SKL_DPLL3
= 2,
275 #define I915_NUM_PLLS 3
277 struct intel_dpll_hw_state
{
289 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
290 * lower part of crtl1 and they get shifted into position when writing
291 * the register. This allows us to easily compare the state to share
295 /* HDMI only, 0 when used for DP */
296 uint32_t cfgcr1
, cfgcr2
;
299 struct intel_shared_dpll_config
{
300 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
301 struct intel_dpll_hw_state hw_state
;
304 struct intel_shared_dpll
{
305 struct intel_shared_dpll_config config
;
306 struct intel_shared_dpll_config
*new_config
;
308 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
309 bool on
; /* is the PLL actually active? Disabled during modeset */
311 /* should match the index in the dev_priv->shared_dplls array */
312 enum intel_dpll_id id
;
313 /* The mode_set hook is optional and should be used together with the
314 * intel_prepare_shared_dpll function. */
315 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
316 struct intel_shared_dpll
*pll
);
317 void (*enable
)(struct drm_i915_private
*dev_priv
,
318 struct intel_shared_dpll
*pll
);
319 void (*disable
)(struct drm_i915_private
*dev_priv
,
320 struct intel_shared_dpll
*pll
);
321 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
322 struct intel_shared_dpll
*pll
,
323 struct intel_dpll_hw_state
*hw_state
);
331 /* Used by dp and fdi links */
332 struct intel_link_m_n
{
340 void intel_link_compute_m_n(int bpp
, int nlanes
,
341 int pixel_clock
, int link_clock
,
342 struct intel_link_m_n
*m_n
);
344 /* Interface history:
347 * 1.2: Add Power Management
348 * 1.3: Add vblank support
349 * 1.4: Fix cmdbuffer path, add heap destroy
350 * 1.5: Add vblank pipe configuration
351 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
352 * - Support vertical blank on secondary display pipe
354 #define DRIVER_MAJOR 1
355 #define DRIVER_MINOR 6
356 #define DRIVER_PATCHLEVEL 0
358 #define WATCH_LISTS 0
360 struct opregion_header
;
361 struct opregion_acpi
;
362 struct opregion_swsci
;
363 struct opregion_asle
;
365 struct intel_opregion
{
366 struct opregion_header __iomem
*header
;
367 struct opregion_acpi __iomem
*acpi
;
368 struct opregion_swsci __iomem
*swsci
;
369 u32 swsci_gbda_sub_functions
;
370 u32 swsci_sbcb_sub_functions
;
371 struct opregion_asle __iomem
*asle
;
373 u32 __iomem
*lid_state
;
374 struct work_struct asle_work
;
376 #define OPREGION_SIZE (8*1024)
378 struct intel_overlay
;
379 struct intel_overlay_error_state
;
381 #define I915_FENCE_REG_NONE -1
382 #define I915_MAX_NUM_FENCES 32
383 /* 32 fences + sign bit for FENCE_REG_NONE */
384 #define I915_MAX_NUM_FENCE_BITS 6
386 struct drm_i915_fence_reg
{
387 struct list_head lru_list
;
388 struct drm_i915_gem_object
*obj
;
392 struct sdvo_device_mapping
{
401 struct intel_display_error_state
;
403 struct drm_i915_error_state
{
411 /* Generic register state */
419 u32 error
; /* gen6+ */
420 u32 err_int
; /* gen7 */
426 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
427 u64 fence
[I915_MAX_NUM_FENCES
];
428 struct intel_overlay_error_state
*overlay
;
429 struct intel_display_error_state
*display
;
430 struct drm_i915_error_object
*semaphore_obj
;
432 struct drm_i915_error_ring
{
434 /* Software tracked state */
437 enum intel_ring_hangcheck_action hangcheck_action
;
440 /* our own tracking of ring head and tail */
444 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
462 u32 rc_psmi
; /* sleep state */
463 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
465 struct drm_i915_error_object
{
469 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
471 struct drm_i915_error_request
{
486 char comm
[TASK_COMM_LEN
];
487 } ring
[I915_NUM_RINGS
];
489 struct drm_i915_error_buffer
{
496 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
504 } **active_bo
, **pinned_bo
;
506 u32
*active_bo_count
, *pinned_bo_count
;
510 struct intel_connector
;
511 struct intel_encoder
;
512 struct intel_crtc_state
;
513 struct intel_initial_plane_config
;
518 struct drm_i915_display_funcs
{
519 bool (*fbc_enabled
)(struct drm_device
*dev
);
520 void (*enable_fbc
)(struct drm_crtc
*crtc
);
521 void (*disable_fbc
)(struct drm_device
*dev
);
522 int (*get_display_clock_speed
)(struct drm_device
*dev
);
523 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
525 * find_dpll() - Find the best values for the PLL
526 * @limit: limits for the PLL
527 * @crtc: current CRTC
528 * @target: target frequency in kHz
529 * @refclk: reference clock frequency in kHz
530 * @match_clock: if provided, @best_clock P divider must
531 * match the P divider from @match_clock
532 * used for LVDS downclocking
533 * @best_clock: best PLL values found
535 * Returns true on success, false on failure.
537 bool (*find_dpll
)(const struct intel_limit
*limit
,
538 struct intel_crtc
*crtc
,
539 int target
, int refclk
,
540 struct dpll
*match_clock
,
541 struct dpll
*best_clock
);
542 void (*update_wm
)(struct drm_crtc
*crtc
);
543 void (*update_sprite_wm
)(struct drm_plane
*plane
,
544 struct drm_crtc
*crtc
,
545 uint32_t sprite_width
, uint32_t sprite_height
,
546 int pixel_size
, bool enable
, bool scaled
);
547 void (*modeset_global_resources
)(struct drm_device
*dev
);
548 /* Returns the active state of the crtc, and if the crtc is active,
549 * fills out the pipe-config with the hw state. */
550 bool (*get_pipe_config
)(struct intel_crtc
*,
551 struct intel_crtc_state
*);
552 void (*get_initial_plane_config
)(struct intel_crtc
*,
553 struct intel_initial_plane_config
*);
554 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
555 struct intel_crtc_state
*crtc_state
);
556 void (*crtc_enable
)(struct drm_crtc
*crtc
);
557 void (*crtc_disable
)(struct drm_crtc
*crtc
);
558 void (*off
)(struct drm_crtc
*crtc
);
559 void (*audio_codec_enable
)(struct drm_connector
*connector
,
560 struct intel_encoder
*encoder
,
561 struct drm_display_mode
*mode
);
562 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
563 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
564 void (*init_clock_gating
)(struct drm_device
*dev
);
565 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
566 struct drm_framebuffer
*fb
,
567 struct drm_i915_gem_object
*obj
,
568 struct intel_engine_cs
*ring
,
570 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
571 struct drm_framebuffer
*fb
,
573 void (*hpd_irq_setup
)(struct drm_device
*dev
);
574 /* clock updates for mode set */
576 /* render clock increase/decrease */
577 /* display clock increase/decrease */
578 /* pll clock increase/decrease */
580 int (*setup_backlight
)(struct intel_connector
*connector
, enum pipe pipe
);
581 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
582 void (*set_backlight
)(struct intel_connector
*connector
,
584 void (*disable_backlight
)(struct intel_connector
*connector
);
585 void (*enable_backlight
)(struct intel_connector
*connector
);
588 enum forcewake_domain_id
{
589 FW_DOMAIN_ID_RENDER
= 0,
590 FW_DOMAIN_ID_BLITTER
,
596 enum forcewake_domains
{
597 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
598 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
599 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
600 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
605 struct intel_uncore_funcs
{
606 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
607 enum forcewake_domains domains
);
608 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
609 enum forcewake_domains domains
);
611 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
612 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
613 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
614 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
616 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
617 uint8_t val
, bool trace
);
618 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
619 uint16_t val
, bool trace
);
620 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
621 uint32_t val
, bool trace
);
622 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
623 uint64_t val
, bool trace
);
626 struct intel_uncore
{
627 spinlock_t lock
; /** lock is also taken in irq contexts. */
629 struct intel_uncore_funcs funcs
;
632 enum forcewake_domains fw_domains
;
634 struct intel_uncore_forcewake_domain
{
635 struct drm_i915_private
*i915
;
636 enum forcewake_domain_id id
;
638 struct timer_list timer
;
645 } fw_domain
[FW_DOMAIN_ID_COUNT
];
648 /* Iterate over initialised fw domains */
649 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
650 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
651 (i__) < FW_DOMAIN_ID_COUNT; \
652 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
653 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
655 #define for_each_fw_domain(domain__, dev_priv__, i__) \
656 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
658 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
659 func(is_mobile) sep \
662 func(is_i945gm) sep \
664 func(need_gfx_hws) sep \
666 func(is_pineview) sep \
667 func(is_broadwater) sep \
668 func(is_crestline) sep \
669 func(is_ivybridge) sep \
670 func(is_valleyview) sep \
671 func(is_haswell) sep \
672 func(is_skylake) sep \
673 func(is_preliminary) sep \
675 func(has_pipe_cxsr) sep \
676 func(has_hotplug) sep \
677 func(cursor_needs_physical) sep \
678 func(has_overlay) sep \
679 func(overlay_needs_physical) sep \
680 func(supports_tv) sep \
685 #define DEFINE_FLAG(name) u8 name:1
686 #define SEP_SEMICOLON ;
688 struct intel_device_info
{
689 u32 display_mmio_offset
;
692 u8 num_sprites
[I915_MAX_PIPES
];
694 u8 ring_mask
; /* Rings supported by the HW */
695 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
696 /* Register offsets for the various display pipes and transcoders */
697 int pipe_offsets
[I915_MAX_TRANSCODERS
];
698 int trans_offsets
[I915_MAX_TRANSCODERS
];
699 int palette_offsets
[I915_MAX_PIPES
];
700 int cursor_offsets
[I915_MAX_PIPES
];
702 /* Slice/subslice/EU info */
705 u8 subslice_per_slice
;
708 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
711 u8 has_subslice_pg
:1;
718 enum i915_cache_level
{
720 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
721 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
722 caches, eg sampler/render caches, and the
723 large Last-Level-Cache. LLC is coherent with
724 the CPU, but L3 is only visible to the GPU. */
725 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
728 struct i915_ctx_hang_stats
{
729 /* This context had batch pending when hang was declared */
730 unsigned batch_pending
;
732 /* This context had batch active when hang was declared */
733 unsigned batch_active
;
735 /* Time when this context was last blamed for a GPU reset */
736 unsigned long guilty_ts
;
738 /* If the contexts causes a second GPU hang within this time,
739 * it is permanently banned from submitting any more work.
741 unsigned long ban_period_seconds
;
743 /* This context is banned to submit more work */
747 /* This must match up with the value previously used for execbuf2.rsvd1. */
748 #define DEFAULT_CONTEXT_HANDLE 0
750 * struct intel_context - as the name implies, represents a context.
751 * @ref: reference count.
752 * @user_handle: userspace tracking identity for this context.
753 * @remap_slice: l3 row remapping information.
754 * @file_priv: filp associated with this context (NULL for global default
756 * @hang_stats: information about the role of this context in possible GPU
758 * @vm: virtual memory space used by this context.
759 * @legacy_hw_ctx: render context backing object and whether it is correctly
760 * initialized (legacy ring submission mechanism only).
761 * @link: link in the global list of contexts.
763 * Contexts are memory images used by the hardware to store copies of their
766 struct intel_context
{
770 struct drm_i915_file_private
*file_priv
;
771 struct i915_ctx_hang_stats hang_stats
;
772 struct i915_hw_ppgtt
*ppgtt
;
774 /* Legacy ring buffer submission */
776 struct drm_i915_gem_object
*rcs_state
;
781 bool rcs_initialized
;
783 struct drm_i915_gem_object
*state
;
784 struct intel_ringbuffer
*ringbuf
;
786 } engine
[I915_NUM_RINGS
];
788 struct list_head link
;
799 unsigned long uncompressed_size
;
802 struct intel_crtc
*crtc
;
805 struct drm_mm_node compressed_fb
;
806 struct drm_mm_node
*compressed_llb
;
810 /* Tracks whether the HW is actually enabled, not whether the feature is
814 /* On gen8 some rings cannont perform fbc clean operation so for now
815 * we are doing this on SW with mmio.
816 * This variable works in the opposite information direction
817 * of ring->fbc_dirty telling software on frontbuffer tracking
818 * to perform the cache clean on sw side.
820 bool need_sw_cache_clean
;
822 struct intel_fbc_work
{
823 struct delayed_work work
;
824 struct drm_crtc
*crtc
;
825 struct drm_framebuffer
*fb
;
829 FBC_OK
, /* FBC is enabled */
830 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
831 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
832 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
833 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
834 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
835 FBC_BAD_PLANE
, /* fbc not supported on plane */
836 FBC_NOT_TILED
, /* buffer not tiled */
837 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
839 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
844 * HIGH_RR is the highest eDP panel refresh rate read from EDID
845 * LOW_RR is the lowest eDP panel refresh rate found from EDID
846 * parsing for same resolution.
848 enum drrs_refresh_rate_type
{
851 DRRS_MAX_RR
, /* RR count */
854 enum drrs_support_type
{
855 DRRS_NOT_SUPPORTED
= 0,
856 STATIC_DRRS_SUPPORT
= 1,
857 SEAMLESS_DRRS_SUPPORT
= 2
863 struct delayed_work work
;
865 unsigned busy_frontbuffer_bits
;
866 enum drrs_refresh_rate_type refresh_rate_type
;
867 enum drrs_support_type type
;
874 struct intel_dp
*enabled
;
876 struct delayed_work work
;
877 unsigned busy_frontbuffer_bits
;
882 PCH_NONE
= 0, /* No PCH present */
883 PCH_IBX
, /* Ibexpeak PCH */
884 PCH_CPT
, /* Cougarpoint PCH */
885 PCH_LPT
, /* Lynxpoint PCH */
886 PCH_SPT
, /* Sunrisepoint PCH */
890 enum intel_sbi_destination
{
895 #define QUIRK_PIPEA_FORCE (1<<0)
896 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
897 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
898 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
899 #define QUIRK_PIPEB_FORCE (1<<4)
900 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
903 struct intel_fbc_work
;
906 struct i2c_adapter adapter
;
910 struct i2c_algo_bit_data bit_algo
;
911 struct drm_i915_private
*dev_priv
;
914 struct i915_suspend_saved_registers
{
917 u32 savePP_ON_DELAYS
;
918 u32 savePP_OFF_DELAYS
;
924 u32 saveCACHE_MODE_0
;
925 u32 saveMI_ARB_STATE
;
929 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
930 u32 savePCH_PORT_HOTPLUG
;
934 struct vlv_s0ix_state
{
941 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
942 u32 media_max_req_count
;
943 u32 gfx_max_req_count
;
975 /* Display 1 CZ domain */
980 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
982 /* GT SA CZ domain */
989 /* Display 2 CZ domain */
995 struct intel_rps_ei
{
1001 struct intel_gen6_power_mgmt
{
1003 * work, interrupts_enabled and pm_iir are protected by
1004 * dev_priv->irq_lock
1006 struct work_struct work
;
1007 bool interrupts_enabled
;
1010 /* Frequencies are stored in potentially platform dependent multiples.
1011 * In other words, *_freq needs to be multiplied by X to be interesting.
1012 * Soft limits are those which are used for the dynamic reclocking done
1013 * by the driver (raise frequencies under heavy loads, and lower for
1014 * lighter loads). Hard limits are those imposed by the hardware.
1016 * A distinction is made for overclocking, which is never enabled by
1017 * default, and is considered to be above the hard limit if it's
1020 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1021 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1022 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1023 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1024 u8 min_freq
; /* AKA RPn. Minimum frequency */
1025 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1026 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1027 u8 rp0_freq
; /* Non-overclocked max frequency. */
1030 u32 ei_interrupt_count
;
1033 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1036 struct delayed_work delayed_resume_work
;
1038 /* manual wa residency calculations */
1039 struct intel_rps_ei up_ei
, down_ei
;
1042 * Protects RPS/RC6 register access and PCU communication.
1043 * Must be taken after struct_mutex if nested.
1045 struct mutex hw_lock
;
1048 /* defined intel_pm.c */
1049 extern spinlock_t mchdev_lock
;
1051 struct intel_ilk_power_mgmt
{
1059 unsigned long last_time1
;
1060 unsigned long chipset_power
;
1063 unsigned long gfx_power
;
1069 struct drm_i915_gem_object
*pwrctx
;
1070 struct drm_i915_gem_object
*renderctx
;
1073 struct drm_i915_private
;
1074 struct i915_power_well
;
1076 struct i915_power_well_ops
{
1078 * Synchronize the well's hw state to match the current sw state, for
1079 * example enable/disable it based on the current refcount. Called
1080 * during driver init and resume time, possibly after first calling
1081 * the enable/disable handlers.
1083 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1084 struct i915_power_well
*power_well
);
1086 * Enable the well and resources that depend on it (for example
1087 * interrupts located on the well). Called after the 0->1 refcount
1090 void (*enable
)(struct drm_i915_private
*dev_priv
,
1091 struct i915_power_well
*power_well
);
1093 * Disable the well and resources that depend on it. Called after
1094 * the 1->0 refcount transition.
1096 void (*disable
)(struct drm_i915_private
*dev_priv
,
1097 struct i915_power_well
*power_well
);
1098 /* Returns the hw enabled state. */
1099 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1100 struct i915_power_well
*power_well
);
1103 /* Power well structure for haswell */
1104 struct i915_power_well
{
1107 /* power well enable/disable usage count */
1109 /* cached hw enabled state */
1111 unsigned long domains
;
1113 const struct i915_power_well_ops
*ops
;
1116 struct i915_power_domains
{
1118 * Power wells needed for initialization at driver init and suspend
1119 * time are on. They are kept on until after the first modeset.
1123 int power_well_count
;
1126 int domain_use_count
[POWER_DOMAIN_NUM
];
1127 struct i915_power_well
*power_wells
;
1130 #define MAX_L3_SLICES 2
1131 struct intel_l3_parity
{
1132 u32
*remap_info
[MAX_L3_SLICES
];
1133 struct work_struct error_work
;
1137 struct i915_gem_batch_pool
{
1138 struct drm_device
*dev
;
1139 struct list_head cache_list
;
1142 struct i915_gem_mm
{
1143 /** Memory allocator for GTT stolen memory */
1144 struct drm_mm stolen
;
1145 /** List of all objects in gtt_space. Used to restore gtt
1146 * mappings on resume */
1147 struct list_head bound_list
;
1149 * List of objects which are not bound to the GTT (thus
1150 * are idle and not used by the GPU) but still have
1151 * (presumably uncached) pages still attached.
1153 struct list_head unbound_list
;
1156 * A pool of objects to use as shadow copies of client batch buffers
1157 * when the command parser is enabled. Prevents the client from
1158 * modifying the batch contents after software parsing.
1160 struct i915_gem_batch_pool batch_pool
;
1162 /** Usable portion of the GTT for GEM */
1163 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1165 /** PPGTT used for aliasing the PPGTT with the GTT */
1166 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1168 struct notifier_block oom_notifier
;
1169 struct shrinker shrinker
;
1170 bool shrinker_no_lock_stealing
;
1172 /** LRU list of objects with fence regs on them. */
1173 struct list_head fence_list
;
1176 * We leave the user IRQ off as much as possible,
1177 * but this means that requests will finish and never
1178 * be retired once the system goes idle. Set a timer to
1179 * fire periodically while the ring is running. When it
1180 * fires, go retire requests.
1182 struct delayed_work retire_work
;
1185 * When we detect an idle GPU, we want to turn on
1186 * powersaving features. So once we see that there
1187 * are no more requests outstanding and no more
1188 * arrive within a small period of time, we fire
1189 * off the idle_work.
1191 struct delayed_work idle_work
;
1194 * Are we in a non-interruptible section of code like
1200 * Is the GPU currently considered idle, or busy executing userspace
1201 * requests? Whilst idle, we attempt to power down the hardware and
1202 * display clocks. In order to reduce the effect on performance, there
1203 * is a slight delay before we do so.
1207 /* the indicator for dispatch video commands on two BSD rings */
1208 int bsd_ring_dispatch_index
;
1210 /** Bit 6 swizzling required for X tiling */
1211 uint32_t bit_6_swizzle_x
;
1212 /** Bit 6 swizzling required for Y tiling */
1213 uint32_t bit_6_swizzle_y
;
1215 /* accounting, useful for userland debugging */
1216 spinlock_t object_stat_lock
;
1217 size_t object_memory
;
1221 struct drm_i915_error_state_buf
{
1222 struct drm_i915_private
*i915
;
1231 struct i915_error_state_file_priv
{
1232 struct drm_device
*dev
;
1233 struct drm_i915_error_state
*error
;
1236 struct i915_gpu_error
{
1237 /* For hangcheck timer */
1238 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1239 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1240 /* Hang gpu twice in this window and your context gets banned */
1241 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1243 struct workqueue_struct
*hangcheck_wq
;
1244 struct delayed_work hangcheck_work
;
1246 /* For reset and error_state handling. */
1248 /* Protected by the above dev->gpu_error.lock. */
1249 struct drm_i915_error_state
*first_error
;
1251 unsigned long missed_irq_rings
;
1254 * State variable controlling the reset flow and count
1256 * This is a counter which gets incremented when reset is triggered,
1257 * and again when reset has been handled. So odd values (lowest bit set)
1258 * means that reset is in progress and even values that
1259 * (reset_counter >> 1):th reset was successfully completed.
1261 * If reset is not completed succesfully, the I915_WEDGE bit is
1262 * set meaning that hardware is terminally sour and there is no
1263 * recovery. All waiters on the reset_queue will be woken when
1266 * This counter is used by the wait_seqno code to notice that reset
1267 * event happened and it needs to restart the entire ioctl (since most
1268 * likely the seqno it waited for won't ever signal anytime soon).
1270 * This is important for lock-free wait paths, where no contended lock
1271 * naturally enforces the correct ordering between the bail-out of the
1272 * waiter and the gpu reset work code.
1274 atomic_t reset_counter
;
1276 #define I915_RESET_IN_PROGRESS_FLAG 1
1277 #define I915_WEDGED (1 << 31)
1280 * Waitqueue to signal when the reset has completed. Used by clients
1281 * that wait for dev_priv->mm.wedged to settle.
1283 wait_queue_head_t reset_queue
;
1285 /* Userspace knobs for gpu hang simulation;
1286 * combines both a ring mask, and extra flags
1289 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1290 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1292 /* For missed irq/seqno simulation. */
1293 unsigned int test_irq_rings
;
1295 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1296 bool reload_in_reset
;
1299 enum modeset_restore
{
1300 MODESET_ON_LID_OPEN
,
1305 struct ddi_vbt_port_info
{
1307 * This is an index in the HDMI/DVI DDI buffer translation table.
1308 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1309 * populate this field.
1311 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1312 uint8_t hdmi_level_shift
;
1314 uint8_t supports_dvi
:1;
1315 uint8_t supports_hdmi
:1;
1316 uint8_t supports_dp
:1;
1319 enum psr_lines_to_wait
{
1320 PSR_0_LINES_TO_WAIT
= 0,
1322 PSR_4_LINES_TO_WAIT
,
1326 struct intel_vbt_data
{
1327 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1328 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1331 unsigned int int_tv_support
:1;
1332 unsigned int lvds_dither
:1;
1333 unsigned int lvds_vbt
:1;
1334 unsigned int int_crt_support
:1;
1335 unsigned int lvds_use_ssc
:1;
1336 unsigned int display_clock_mode
:1;
1337 unsigned int fdi_rx_polarity_inverted
:1;
1338 unsigned int has_mipi
:1;
1340 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1342 enum drrs_support_type drrs_type
;
1347 int edp_preemphasis
;
1349 bool edp_initialized
;
1352 bool edp_low_vswing
;
1353 struct edp_power_seq edp_pps
;
1357 bool require_aux_wakeup
;
1359 enum psr_lines_to_wait lines_to_wait
;
1360 int tp1_wakeup_time
;
1361 int tp2_tp3_wakeup_time
;
1367 bool active_low_pwm
;
1368 u8 min_brightness
; /* min_brightness/255 of max */
1375 struct mipi_config
*config
;
1376 struct mipi_pps_data
*pps
;
1380 u8
*sequence
[MIPI_SEQ_MAX
];
1386 union child_device_config
*child_dev
;
1388 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1391 enum intel_ddb_partitioning
{
1393 INTEL_DDB_PART_5_6
, /* IVB+ */
1396 struct intel_wm_level
{
1404 struct ilk_wm_values
{
1405 uint32_t wm_pipe
[3];
1407 uint32_t wm_lp_spr
[3];
1408 uint32_t wm_linetime
[3];
1410 enum intel_ddb_partitioning partitioning
;
1413 struct skl_ddb_entry
{
1414 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1417 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1419 return entry
->end
- entry
->start
;
1422 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1423 const struct skl_ddb_entry
*e2
)
1425 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1431 struct skl_ddb_allocation
{
1432 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1433 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1434 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1437 struct skl_wm_values
{
1438 bool dirty
[I915_MAX_PIPES
];
1439 struct skl_ddb_allocation ddb
;
1440 uint32_t wm_linetime
[I915_MAX_PIPES
];
1441 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1442 uint32_t cursor
[I915_MAX_PIPES
][8];
1443 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1444 uint32_t cursor_trans
[I915_MAX_PIPES
];
1447 struct skl_wm_level
{
1448 bool plane_en
[I915_MAX_PLANES
];
1450 uint16_t plane_res_b
[I915_MAX_PLANES
];
1451 uint8_t plane_res_l
[I915_MAX_PLANES
];
1452 uint16_t cursor_res_b
;
1453 uint8_t cursor_res_l
;
1457 * This struct helps tracking the state needed for runtime PM, which puts the
1458 * device in PCI D3 state. Notice that when this happens, nothing on the
1459 * graphics device works, even register access, so we don't get interrupts nor
1462 * Every piece of our code that needs to actually touch the hardware needs to
1463 * either call intel_runtime_pm_get or call intel_display_power_get with the
1464 * appropriate power domain.
1466 * Our driver uses the autosuspend delay feature, which means we'll only really
1467 * suspend if we stay with zero refcount for a certain amount of time. The
1468 * default value is currently very conservative (see intel_runtime_pm_enable), but
1469 * it can be changed with the standard runtime PM files from sysfs.
1471 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1472 * goes back to false exactly before we reenable the IRQs. We use this variable
1473 * to check if someone is trying to enable/disable IRQs while they're supposed
1474 * to be disabled. This shouldn't happen and we'll print some error messages in
1477 * For more, read the Documentation/power/runtime_pm.txt.
1479 struct i915_runtime_pm
{
1484 enum intel_pipe_crc_source
{
1485 INTEL_PIPE_CRC_SOURCE_NONE
,
1486 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1487 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1488 INTEL_PIPE_CRC_SOURCE_PF
,
1489 INTEL_PIPE_CRC_SOURCE_PIPE
,
1490 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1491 INTEL_PIPE_CRC_SOURCE_TV
,
1492 INTEL_PIPE_CRC_SOURCE_DP_B
,
1493 INTEL_PIPE_CRC_SOURCE_DP_C
,
1494 INTEL_PIPE_CRC_SOURCE_DP_D
,
1495 INTEL_PIPE_CRC_SOURCE_AUTO
,
1496 INTEL_PIPE_CRC_SOURCE_MAX
,
1499 struct intel_pipe_crc_entry
{
1504 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1505 struct intel_pipe_crc
{
1507 bool opened
; /* exclusive access to the result file */
1508 struct intel_pipe_crc_entry
*entries
;
1509 enum intel_pipe_crc_source source
;
1511 wait_queue_head_t wq
;
1514 struct i915_frontbuffer_tracking
{
1518 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1525 struct i915_wa_reg
{
1528 /* bitmask representing WA bits */
1532 #define I915_MAX_WA_REGS 16
1534 struct i915_workarounds
{
1535 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1539 struct i915_virtual_gpu
{
1543 struct drm_i915_private
{
1544 struct drm_device
*dev
;
1545 struct kmem_cache
*slab
;
1547 const struct intel_device_info info
;
1549 int relative_constants_mode
;
1553 struct intel_uncore uncore
;
1555 struct i915_virtual_gpu vgpu
;
1557 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1560 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1561 * controller on different i2c buses. */
1562 struct mutex gmbus_mutex
;
1565 * Base address of the gmbus and gpio block.
1567 uint32_t gpio_mmio_base
;
1569 /* MMIO base address for MIPI regs */
1570 uint32_t mipi_mmio_base
;
1572 wait_queue_head_t gmbus_wait_queue
;
1574 struct pci_dev
*bridge_dev
;
1575 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1576 struct drm_i915_gem_object
*semaphore_obj
;
1577 uint32_t last_seqno
, next_seqno
;
1579 struct drm_dma_handle
*status_page_dmah
;
1580 struct resource mch_res
;
1582 /* protects the irq masks */
1583 spinlock_t irq_lock
;
1585 /* protects the mmio flip data */
1586 spinlock_t mmio_flip_lock
;
1588 bool display_irqs_enabled
;
1590 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1591 struct pm_qos_request pm_qos
;
1593 /* DPIO indirect register protection */
1594 struct mutex dpio_lock
;
1596 /** Cached value of IMR to avoid reads in updating the bitfield */
1599 u32 de_irq_mask
[I915_MAX_PIPES
];
1604 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1606 struct work_struct hotplug_work
;
1608 unsigned long hpd_last_jiffies
;
1613 HPD_MARK_DISABLED
= 2
1615 } hpd_stats
[HPD_NUM_PINS
];
1617 struct delayed_work hotplug_reenable_work
;
1619 struct i915_fbc fbc
;
1620 struct i915_drrs drrs
;
1621 struct intel_opregion opregion
;
1622 struct intel_vbt_data vbt
;
1624 bool preserve_bios_swizzle
;
1627 struct intel_overlay
*overlay
;
1629 /* backlight registers and fields in struct intel_panel */
1630 struct mutex backlight_lock
;
1633 bool no_aux_handshake
;
1635 /* protects panel power sequencer state */
1636 struct mutex pps_mutex
;
1638 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1639 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1640 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1642 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1643 unsigned int vlv_cdclk_freq
;
1644 unsigned int hpll_freq
;
1647 * wq - Driver workqueue for GEM.
1649 * NOTE: Work items scheduled here are not allowed to grab any modeset
1650 * locks, for otherwise the flushing done in the pageflip code will
1651 * result in deadlocks.
1653 struct workqueue_struct
*wq
;
1655 /* Display functions */
1656 struct drm_i915_display_funcs display
;
1658 /* PCH chipset type */
1659 enum intel_pch pch_type
;
1660 unsigned short pch_id
;
1662 unsigned long quirks
;
1664 enum modeset_restore modeset_restore
;
1665 struct mutex modeset_restore_lock
;
1667 struct list_head vm_list
; /* Global list of all address spaces */
1668 struct i915_gtt gtt
; /* VM representing the global address space */
1670 struct i915_gem_mm mm
;
1671 DECLARE_HASHTABLE(mm_structs
, 7);
1672 struct mutex mm_lock
;
1674 /* Kernel Modesetting */
1676 struct sdvo_device_mapping sdvo_mappings
[2];
1678 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1679 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1680 wait_queue_head_t pending_flip_queue
;
1682 #ifdef CONFIG_DEBUG_FS
1683 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1686 int num_shared_dpll
;
1687 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1688 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1690 struct i915_workarounds workarounds
;
1692 /* Reclocking support */
1693 bool render_reclock_avail
;
1694 bool lvds_downclock_avail
;
1695 /* indicates the reduced downclock for LVDS*/
1698 struct i915_frontbuffer_tracking fb_tracking
;
1702 bool mchbar_need_disable
;
1704 struct intel_l3_parity l3_parity
;
1706 /* Cannot be determined by PCIID. You must always read a register. */
1709 /* gen6+ rps state */
1710 struct intel_gen6_power_mgmt rps
;
1712 /* ilk-only ips/rps state. Everything in here is protected by the global
1713 * mchdev_lock in intel_pm.c */
1714 struct intel_ilk_power_mgmt ips
;
1716 struct i915_power_domains power_domains
;
1718 struct i915_psr psr
;
1720 struct i915_gpu_error gpu_error
;
1722 struct drm_i915_gem_object
*vlv_pctx
;
1724 #ifdef CONFIG_DRM_I915_FBDEV
1725 /* list of fbdev register on this device */
1726 struct intel_fbdev
*fbdev
;
1727 struct work_struct fbdev_suspend_work
;
1730 struct drm_property
*broadcast_rgb_property
;
1731 struct drm_property
*force_audio_property
;
1733 /* hda/i915 audio component */
1734 bool audio_component_registered
;
1736 uint32_t hw_context_size
;
1737 struct list_head context_list
;
1742 struct i915_suspend_saved_registers regfile
;
1743 struct vlv_s0ix_state vlv_s0ix_state
;
1747 * Raw watermark latency values:
1748 * in 0.1us units for WM0,
1749 * in 0.5us units for WM1+.
1752 uint16_t pri_latency
[5];
1754 uint16_t spr_latency
[5];
1756 uint16_t cur_latency
[5];
1758 * Raw watermark memory latency values
1759 * for SKL for all 8 levels
1762 uint16_t skl_latency
[8];
1765 * The skl_wm_values structure is a bit too big for stack
1766 * allocation, so we keep the staging struct where we store
1767 * intermediate results here instead.
1769 struct skl_wm_values skl_results
;
1771 /* current hardware state */
1773 struct ilk_wm_values hw
;
1774 struct skl_wm_values skl_hw
;
1778 struct i915_runtime_pm pm
;
1780 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1781 u32 long_hpd_port_mask
;
1782 u32 short_hpd_port_mask
;
1783 struct work_struct dig_port_work
;
1786 * if we get a HPD irq from DP and a HPD irq from non-DP
1787 * the non-DP HPD could block the workqueue on a mode config
1788 * mutex getting, that userspace may have taken. However
1789 * userspace is waiting on the DP workqueue to run which is
1790 * blocked behind the non-DP one.
1792 struct workqueue_struct
*dp_wq
;
1794 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1796 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1797 struct intel_engine_cs
*ring
,
1798 struct intel_context
*ctx
,
1799 struct drm_i915_gem_execbuffer2
*args
,
1800 struct list_head
*vmas
,
1801 struct drm_i915_gem_object
*batch_obj
,
1802 u64 exec_start
, u32 flags
);
1803 int (*init_rings
)(struct drm_device
*dev
);
1804 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1805 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1808 uint32_t request_uniq
;
1811 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1812 * will be rejected. Instead look for a better place.
1816 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1818 return dev
->dev_private
;
1821 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1823 return to_i915(dev_get_drvdata(dev
));
1826 /* Iterate over initialised rings */
1827 #define for_each_ring(ring__, dev_priv__, i__) \
1828 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1829 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1831 enum hdmi_force_audio
{
1832 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1833 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1834 HDMI_AUDIO_AUTO
, /* trust EDID */
1835 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1838 #define I915_GTT_OFFSET_NONE ((u32)-1)
1840 struct drm_i915_gem_object_ops
{
1841 /* Interface between the GEM object and its backing storage.
1842 * get_pages() is called once prior to the use of the associated set
1843 * of pages before to binding them into the GTT, and put_pages() is
1844 * called after we no longer need them. As we expect there to be
1845 * associated cost with migrating pages between the backing storage
1846 * and making them available for the GPU (e.g. clflush), we may hold
1847 * onto the pages after they are no longer referenced by the GPU
1848 * in case they may be used again shortly (for example migrating the
1849 * pages to a different memory domain within the GTT). put_pages()
1850 * will therefore most likely be called when the object itself is
1851 * being released or under memory pressure (where we attempt to
1852 * reap pages for the shrinker).
1854 int (*get_pages
)(struct drm_i915_gem_object
*);
1855 void (*put_pages
)(struct drm_i915_gem_object
*);
1856 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1857 void (*release
)(struct drm_i915_gem_object
*);
1861 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1862 * considered to be the frontbuffer for the given plane interface-vise. This
1863 * doesn't mean that the hw necessarily already scans it out, but that any
1864 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1866 * We have one bit per pipe and per scanout plane type.
1868 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1869 #define INTEL_FRONTBUFFER_BITS \
1870 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1871 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1872 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1873 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1874 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1875 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1876 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1877 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1878 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1879 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1880 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1882 struct drm_i915_gem_object
{
1883 struct drm_gem_object base
;
1885 const struct drm_i915_gem_object_ops
*ops
;
1887 /** List of VMAs backed by this object */
1888 struct list_head vma_list
;
1890 /** Stolen memory for this object, instead of being backed by shmem. */
1891 struct drm_mm_node
*stolen
;
1892 struct list_head global_list
;
1894 struct list_head ring_list
;
1895 /** Used in execbuf to temporarily hold a ref */
1896 struct list_head obj_exec_link
;
1898 struct list_head batch_pool_list
;
1901 * This is set if the object is on the active lists (has pending
1902 * rendering and so a non-zero seqno), and is not set if it i s on
1903 * inactive (ready to be unbound) list.
1905 unsigned int active
:1;
1908 * This is set if the object has been written to since last bound
1911 unsigned int dirty
:1;
1914 * Fence register bits (if any) for this object. Will be set
1915 * as needed when mapped into the GTT.
1916 * Protected by dev->struct_mutex.
1918 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1921 * Advice: are the backing pages purgeable?
1923 unsigned int madv
:2;
1926 * Current tiling mode for the object.
1928 unsigned int tiling_mode
:2;
1930 * Whether the tiling parameters for the currently associated fence
1931 * register have changed. Note that for the purposes of tracking
1932 * tiling changes we also treat the unfenced register, the register
1933 * slot that the object occupies whilst it executes a fenced
1934 * command (such as BLT on gen2/3), as a "fence".
1936 unsigned int fence_dirty
:1;
1939 * Is the object at the current location in the gtt mappable and
1940 * fenceable? Used to avoid costly recalculations.
1942 unsigned int map_and_fenceable
:1;
1945 * Whether the current gtt mapping needs to be mappable (and isn't just
1946 * mappable by accident). Track pin and fault separate for a more
1947 * accurate mappable working set.
1949 unsigned int fault_mappable
:1;
1950 unsigned int pin_mappable
:1;
1951 unsigned int pin_display
:1;
1954 * Is the object to be mapped as read-only to the GPU
1955 * Only honoured if hardware has relevant pte bit
1957 unsigned long gt_ro
:1;
1958 unsigned int cache_level
:3;
1959 unsigned int cache_dirty
:1;
1961 unsigned int has_dma_mapping
:1;
1963 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1965 struct sg_table
*pages
;
1966 int pages_pin_count
;
1968 /* prime dma-buf support */
1969 void *dma_buf_vmapping
;
1972 /** Breadcrumb of last rendering to the buffer. */
1973 struct drm_i915_gem_request
*last_read_req
;
1974 struct drm_i915_gem_request
*last_write_req
;
1975 /** Breadcrumb of last fenced GPU access to the buffer. */
1976 struct drm_i915_gem_request
*last_fenced_req
;
1978 /** Current tiling stride for the object, if it's tiled. */
1981 /** References from framebuffers, locks out tiling changes. */
1982 unsigned long framebuffer_references
;
1984 /** Record of address bit 17 of each page at last unbind. */
1985 unsigned long *bit_17
;
1988 /** for phy allocated objects */
1989 struct drm_dma_handle
*phys_handle
;
1991 struct i915_gem_userptr
{
1993 unsigned read_only
:1;
1994 unsigned workers
:4;
1995 #define I915_GEM_USERPTR_MAX_WORKERS 15
1997 struct i915_mm_struct
*mm
;
1998 struct i915_mmu_object
*mmu_object
;
1999 struct work_struct
*work
;
2003 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2005 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2006 struct drm_i915_gem_object
*new,
2007 unsigned frontbuffer_bits
);
2010 * Request queue structure.
2012 * The request queue allows us to note sequence numbers that have been emitted
2013 * and may be associated with active buffers to be retired.
2015 * By keeping this list, we can avoid having to do questionable sequence
2016 * number comparisons on buffer last_read|write_seqno. It also allows an
2017 * emission time to be associated with the request for tracking how far ahead
2018 * of the GPU the submission is.
2020 * The requests are reference counted, so upon creation they should have an
2021 * initial reference taken using kref_init
2023 struct drm_i915_gem_request
{
2026 /** On Which ring this request was generated */
2027 struct intel_engine_cs
*ring
;
2029 /** GEM sequence number associated with this request. */
2032 /** Position in the ringbuffer of the start of the request */
2036 * Position in the ringbuffer of the start of the postfix.
2037 * This is required to calculate the maximum available ringbuffer
2038 * space without overwriting the postfix.
2042 /** Position in the ringbuffer of the end of the whole request */
2046 * Context and ring buffer related to this request
2047 * Contexts are refcounted, so when this request is associated with a
2048 * context, we must increment the context's refcount, to guarantee that
2049 * it persists while any request is linked to it. Requests themselves
2050 * are also refcounted, so the request will only be freed when the last
2051 * reference to it is dismissed, and the code in
2052 * i915_gem_request_free() will then decrement the refcount on the
2055 struct intel_context
*ctx
;
2056 struct intel_ringbuffer
*ringbuf
;
2058 /** Batch buffer related to this request if any */
2059 struct drm_i915_gem_object
*batch_obj
;
2061 /** Time at which this request was emitted, in jiffies. */
2062 unsigned long emitted_jiffies
;
2064 /** global list entry for this request */
2065 struct list_head list
;
2067 struct drm_i915_file_private
*file_priv
;
2068 /** file_priv list entry for this request */
2069 struct list_head client_list
;
2071 /** process identifier submitting this request */
2077 * The ELSP only accepts two elements at a time, so we queue
2078 * context/tail pairs on a given queue (ring->execlist_queue) until the
2079 * hardware is available. The queue serves a double purpose: we also use
2080 * it to keep track of the up to 2 contexts currently in the hardware
2081 * (usually one in execution and the other queued up by the GPU): We
2082 * only remove elements from the head of the queue when the hardware
2083 * informs us that an element has been completed.
2085 * All accesses to the queue are mediated by a spinlock
2086 * (ring->execlist_lock).
2089 /** Execlist link in the submission queue.*/
2090 struct list_head execlist_link
;
2092 /** Execlists no. of times this request has been sent to the ELSP */
2097 void i915_gem_request_free(struct kref
*req_ref
);
2099 static inline uint32_t
2100 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2102 return req
? req
->seqno
: 0;
2105 static inline struct intel_engine_cs
*
2106 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2108 return req
? req
->ring
: NULL
;
2112 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2114 kref_get(&req
->ref
);
2118 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2120 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2121 kref_put(&req
->ref
, i915_gem_request_free
);
2124 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2125 struct drm_i915_gem_request
*src
)
2128 i915_gem_request_reference(src
);
2131 i915_gem_request_unreference(*pdst
);
2137 * XXX: i915_gem_request_completed should be here but currently needs the
2138 * definition of i915_seqno_passed() which is below. It will be moved in
2139 * a later patch when the call to i915_seqno_passed() is obsoleted...
2142 struct drm_i915_file_private
{
2143 struct drm_i915_private
*dev_priv
;
2144 struct drm_file
*file
;
2148 struct list_head request_list
;
2149 struct delayed_work idle_work
;
2151 struct idr context_idr
;
2153 atomic_t rps_wait_boost
;
2154 struct intel_engine_cs
*bsd_ring
;
2158 * A command that requires special handling by the command parser.
2160 struct drm_i915_cmd_descriptor
{
2162 * Flags describing how the command parser processes the command.
2164 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2165 * a length mask if not set
2166 * CMD_DESC_SKIP: The command is allowed but does not follow the
2167 * standard length encoding for the opcode range in
2169 * CMD_DESC_REJECT: The command is never allowed
2170 * CMD_DESC_REGISTER: The command should be checked against the
2171 * register whitelist for the appropriate ring
2172 * CMD_DESC_MASTER: The command is allowed if the submitting process
2176 #define CMD_DESC_FIXED (1<<0)
2177 #define CMD_DESC_SKIP (1<<1)
2178 #define CMD_DESC_REJECT (1<<2)
2179 #define CMD_DESC_REGISTER (1<<3)
2180 #define CMD_DESC_BITMASK (1<<4)
2181 #define CMD_DESC_MASTER (1<<5)
2184 * The command's unique identification bits and the bitmask to get them.
2185 * This isn't strictly the opcode field as defined in the spec and may
2186 * also include type, subtype, and/or subop fields.
2194 * The command's length. The command is either fixed length (i.e. does
2195 * not include a length field) or has a length field mask. The flag
2196 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2197 * a length mask. All command entries in a command table must include
2198 * length information.
2206 * Describes where to find a register address in the command to check
2207 * against the ring's register whitelist. Only valid if flags has the
2208 * CMD_DESC_REGISTER bit set.
2215 #define MAX_CMD_DESC_BITMASKS 3
2217 * Describes command checks where a particular dword is masked and
2218 * compared against an expected value. If the command does not match
2219 * the expected value, the parser rejects it. Only valid if flags has
2220 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2223 * If the check specifies a non-zero condition_mask then the parser
2224 * only performs the check when the bits specified by condition_mask
2231 u32 condition_offset
;
2233 } bits
[MAX_CMD_DESC_BITMASKS
];
2237 * A table of commands requiring special handling by the command parser.
2239 * Each ring has an array of tables. Each table consists of an array of command
2240 * descriptors, which must be sorted with command opcodes in ascending order.
2242 struct drm_i915_cmd_table
{
2243 const struct drm_i915_cmd_descriptor
*table
;
2247 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2248 #define __I915__(p) ({ \
2249 struct drm_i915_private *__p; \
2250 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2251 __p = (struct drm_i915_private *)p; \
2252 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2253 __p = to_i915((struct drm_device *)p); \
2258 #define INTEL_INFO(p) (&__I915__(p)->info)
2259 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2260 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2262 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2263 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2264 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2265 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2266 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2267 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2268 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2269 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2270 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2271 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2272 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2273 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2274 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2275 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2276 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2277 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2278 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2279 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2280 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2281 INTEL_DEVID(dev) == 0x0152 || \
2282 INTEL_DEVID(dev) == 0x015a)
2283 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2284 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2285 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2286 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2287 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2288 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2289 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2290 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2291 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2292 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2293 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2294 (INTEL_DEVID(dev) & 0xf) == 0xe))
2295 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2296 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2297 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2298 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2299 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2300 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2301 /* ULX machines are also considered ULT. */
2302 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2303 INTEL_DEVID(dev) == 0x0A1E)
2304 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2306 #define SKL_REVID_A0 (0x0)
2307 #define SKL_REVID_B0 (0x1)
2308 #define SKL_REVID_C0 (0x2)
2309 #define SKL_REVID_D0 (0x3)
2310 #define SKL_REVID_E0 (0x4)
2313 * The genX designation typically refers to the render engine, so render
2314 * capability related checks should use IS_GEN, while display and other checks
2315 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2318 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2319 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2320 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2321 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2322 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2323 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2324 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2325 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2327 #define RENDER_RING (1<<RCS)
2328 #define BSD_RING (1<<VCS)
2329 #define BLT_RING (1<<BCS)
2330 #define VEBOX_RING (1<<VECS)
2331 #define BSD2_RING (1<<VCS2)
2332 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2333 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2334 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2335 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2336 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2337 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2338 __I915__(dev)->ellc_size)
2339 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2341 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2342 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2343 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2344 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2346 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2347 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2349 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2350 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2352 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2353 * even when in MSI mode. This results in spurious interrupt warnings if the
2354 * legacy irq no. is shared with another device. The kernel then disables that
2355 * interrupt source and so prevents the other device from working properly.
2357 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2358 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2360 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2361 * rows, which changed the alignment requirements and fence programming.
2363 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2365 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2366 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2367 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2368 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2369 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2371 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2372 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2373 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2375 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2377 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2378 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2379 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2380 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2382 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2383 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2384 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2385 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2387 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2388 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2389 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2390 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2391 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2392 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2393 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2394 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2396 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2397 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2398 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2399 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2400 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2401 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2402 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2404 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2406 /* DPF == dynamic parity feature */
2407 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2408 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2410 #define GT_FREQUENCY_MULTIPLIER 50
2412 #include "i915_trace.h"
2414 extern const struct drm_ioctl_desc i915_ioctls
[];
2415 extern int i915_max_ioctl
;
2417 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2418 extern int i915_resume_legacy(struct drm_device
*dev
);
2421 struct i915_params
{
2423 int panel_ignore_lid
;
2424 unsigned int powersave
;
2426 unsigned int lvds_downclock
;
2427 int lvds_channel_mode
;
2429 int vbt_sdvo_panel_type
;
2433 int enable_execlists
;
2435 unsigned int preliminary_hw_support
;
2436 int disable_power_well
;
2438 int invert_brightness
;
2439 int enable_cmd_parser
;
2440 /* leave bools at the end to not create holes */
2441 bool enable_hangcheck
;
2443 bool prefault_disable
;
2445 bool disable_display
;
2446 bool disable_vtd_wa
;
2449 bool verbose_state_checks
;
2450 bool nuclear_pageflip
;
2452 extern struct i915_params i915 __read_mostly
;
2455 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2456 extern int i915_driver_unload(struct drm_device
*);
2457 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2458 extern void i915_driver_lastclose(struct drm_device
* dev
);
2459 extern void i915_driver_preclose(struct drm_device
*dev
,
2460 struct drm_file
*file
);
2461 extern void i915_driver_postclose(struct drm_device
*dev
,
2462 struct drm_file
*file
);
2463 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2464 #ifdef CONFIG_COMPAT
2465 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2468 extern int intel_gpu_reset(struct drm_device
*dev
);
2469 extern int i915_reset(struct drm_device
*dev
);
2470 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2471 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2472 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2473 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2474 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2475 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2478 void i915_queue_hangcheck(struct drm_device
*dev
);
2480 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2481 const char *fmt
, ...);
2483 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2484 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2485 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2486 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2488 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2489 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2490 bool restore_forcewake
);
2491 extern void intel_uncore_init(struct drm_device
*dev
);
2492 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2493 extern void intel_uncore_fini(struct drm_device
*dev
);
2494 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2495 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2496 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2497 enum forcewake_domains domains
);
2498 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2499 enum forcewake_domains domains
);
2500 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2501 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2503 return to_i915(dev
)->vgpu
.active
;
2507 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2511 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2514 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2515 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2517 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2519 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2520 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2521 uint32_t interrupt_mask
,
2522 uint32_t enabled_irq_mask
);
2523 #define ibx_enable_display_interrupt(dev_priv, bits) \
2524 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2525 #define ibx_disable_display_interrupt(dev_priv, bits) \
2526 ibx_display_interrupt_update((dev_priv), (bits), 0)
2529 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2530 struct drm_file
*file_priv
);
2531 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2532 struct drm_file
*file_priv
);
2533 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2534 struct drm_file
*file_priv
);
2535 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2536 struct drm_file
*file_priv
);
2537 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2538 struct drm_file
*file_priv
);
2539 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2540 struct drm_file
*file_priv
);
2541 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2542 struct drm_file
*file_priv
);
2543 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2544 struct intel_engine_cs
*ring
);
2545 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2546 struct drm_file
*file
,
2547 struct intel_engine_cs
*ring
,
2548 struct drm_i915_gem_object
*obj
);
2549 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2550 struct drm_file
*file
,
2551 struct intel_engine_cs
*ring
,
2552 struct intel_context
*ctx
,
2553 struct drm_i915_gem_execbuffer2
*args
,
2554 struct list_head
*vmas
,
2555 struct drm_i915_gem_object
*batch_obj
,
2556 u64 exec_start
, u32 flags
);
2557 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2558 struct drm_file
*file_priv
);
2559 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2560 struct drm_file
*file_priv
);
2561 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2562 struct drm_file
*file_priv
);
2563 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2564 struct drm_file
*file
);
2565 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2566 struct drm_file
*file
);
2567 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2568 struct drm_file
*file_priv
);
2569 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2570 struct drm_file
*file_priv
);
2571 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2572 struct drm_file
*file_priv
);
2573 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2574 struct drm_file
*file_priv
);
2575 int i915_gem_init_userptr(struct drm_device
*dev
);
2576 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2577 struct drm_file
*file
);
2578 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2579 struct drm_file
*file_priv
);
2580 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2581 struct drm_file
*file_priv
);
2582 void i915_gem_load(struct drm_device
*dev
);
2583 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2586 #define I915_SHRINK_PURGEABLE 0x1
2587 #define I915_SHRINK_UNBOUND 0x2
2588 #define I915_SHRINK_BOUND 0x4
2589 void *i915_gem_object_alloc(struct drm_device
*dev
);
2590 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2591 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2592 const struct drm_i915_gem_object_ops
*ops
);
2593 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2595 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2596 struct i915_address_space
*vm
);
2597 void i915_gem_free_object(struct drm_gem_object
*obj
);
2598 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2600 #define PIN_MAPPABLE 0x1
2601 #define PIN_NONBLOCK 0x2
2602 #define PIN_GLOBAL 0x4
2603 #define PIN_OFFSET_BIAS 0x8
2604 #define PIN_OFFSET_MASK (~4095)
2605 int __must_check
i915_gem_object_pin_view(struct drm_i915_gem_object
*obj
,
2606 struct i915_address_space
*vm
,
2609 const struct i915_ggtt_view
*view
);
2611 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2612 struct i915_address_space
*vm
,
2616 return i915_gem_object_pin_view(obj
, vm
, alignment
, flags
,
2617 &i915_ggtt_view_normal
);
2620 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2622 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2623 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2624 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2625 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2627 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2628 int *needs_clflush
);
2630 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2631 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2633 struct sg_page_iter sg_iter
;
2635 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2636 return sg_page_iter_page(&sg_iter
);
2640 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2642 BUG_ON(obj
->pages
== NULL
);
2643 obj
->pages_pin_count
++;
2645 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2647 BUG_ON(obj
->pages_pin_count
== 0);
2648 obj
->pages_pin_count
--;
2651 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2652 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2653 struct intel_engine_cs
*to
);
2654 void i915_vma_move_to_active(struct i915_vma
*vma
,
2655 struct intel_engine_cs
*ring
);
2656 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2657 struct drm_device
*dev
,
2658 struct drm_mode_create_dumb
*args
);
2659 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2660 uint32_t handle
, uint64_t *offset
);
2662 * Returns true if seq1 is later than seq2.
2665 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2667 return (int32_t)(seq1
- seq2
) >= 0;
2670 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2671 bool lazy_coherency
)
2675 BUG_ON(req
== NULL
);
2677 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2679 return i915_seqno_passed(seqno
, req
->seqno
);
2682 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2683 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2684 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2685 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2687 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2688 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2690 struct drm_i915_gem_request
*
2691 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2693 bool i915_gem_retire_requests(struct drm_device
*dev
);
2694 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2695 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2696 bool interruptible
);
2697 int __must_check
i915_gem_check_olr(struct drm_i915_gem_request
*req
);
2699 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2701 return unlikely(atomic_read(&error
->reset_counter
)
2702 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2705 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2707 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2710 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2712 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2715 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2717 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2718 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2721 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2723 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2724 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2727 void i915_gem_reset(struct drm_device
*dev
);
2728 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2729 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2730 int __must_check
i915_gem_init(struct drm_device
*dev
);
2731 int i915_gem_init_rings(struct drm_device
*dev
);
2732 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2733 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2734 void i915_gem_init_swizzling(struct drm_device
*dev
);
2735 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2736 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2737 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2738 int __i915_add_request(struct intel_engine_cs
*ring
,
2739 struct drm_file
*file
,
2740 struct drm_i915_gem_object
*batch_obj
);
2741 #define i915_add_request(ring) \
2742 __i915_add_request(ring, NULL, NULL)
2743 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2744 unsigned reset_counter
,
2747 struct drm_i915_file_private
*file_priv
);
2748 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2749 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2751 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2754 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2756 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2758 struct intel_engine_cs
*pipelined
);
2759 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2760 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2762 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2763 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2766 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2768 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2769 int tiling_mode
, bool fenced
);
2771 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2772 enum i915_cache_level cache_level
);
2774 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2775 struct dma_buf
*dma_buf
);
2777 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2778 struct drm_gem_object
*gem_obj
, int flags
);
2780 void i915_gem_restore_fences(struct drm_device
*dev
);
2782 unsigned long i915_gem_obj_offset_view(struct drm_i915_gem_object
*o
,
2783 struct i915_address_space
*vm
,
2784 enum i915_ggtt_view_type view
);
2786 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2787 struct i915_address_space
*vm
)
2789 return i915_gem_obj_offset_view(o
, vm
, I915_GGTT_VIEW_NORMAL
);
2791 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2792 bool i915_gem_obj_bound_view(struct drm_i915_gem_object
*o
,
2793 struct i915_address_space
*vm
,
2794 enum i915_ggtt_view_type view
);
2796 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2797 struct i915_address_space
*vm
)
2799 return i915_gem_obj_bound_view(o
, vm
, I915_GGTT_VIEW_NORMAL
);
2802 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2803 struct i915_address_space
*vm
);
2804 struct i915_vma
*i915_gem_obj_to_vma_view(struct drm_i915_gem_object
*obj
,
2805 struct i915_address_space
*vm
,
2806 const struct i915_ggtt_view
*view
);
2808 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2809 struct i915_address_space
*vm
)
2811 return i915_gem_obj_to_vma_view(obj
, vm
, &i915_ggtt_view_normal
);
2815 i915_gem_obj_lookup_or_create_vma_view(struct drm_i915_gem_object
*obj
,
2816 struct i915_address_space
*vm
,
2817 const struct i915_ggtt_view
*view
);
2821 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2822 struct i915_address_space
*vm
)
2824 return i915_gem_obj_lookup_or_create_vma_view(obj
, vm
,
2825 &i915_ggtt_view_normal
);
2828 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2829 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2830 struct i915_vma
*vma
;
2831 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2832 if (vma
->pin_count
> 0)
2837 /* Some GGTT VM helpers */
2838 #define i915_obj_to_ggtt(obj) \
2839 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2840 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2842 struct i915_address_space
*ggtt
=
2843 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2847 static inline struct i915_hw_ppgtt
*
2848 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2850 WARN_ON(i915_is_ggtt(vm
));
2852 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2856 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2858 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2861 static inline unsigned long
2862 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2864 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2867 static inline unsigned long
2868 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2870 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2873 static inline int __must_check
2874 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2878 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2879 alignment
, flags
| PIN_GLOBAL
);
2883 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2885 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2888 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2890 /* i915_gem_context.c */
2891 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2892 void i915_gem_context_fini(struct drm_device
*dev
);
2893 void i915_gem_context_reset(struct drm_device
*dev
);
2894 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2895 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2896 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2897 int i915_switch_context(struct intel_engine_cs
*ring
,
2898 struct intel_context
*to
);
2899 struct intel_context
*
2900 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2901 void i915_gem_context_free(struct kref
*ctx_ref
);
2902 struct drm_i915_gem_object
*
2903 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2904 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2906 kref_get(&ctx
->ref
);
2909 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2911 kref_put(&ctx
->ref
, i915_gem_context_free
);
2914 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2916 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2919 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2920 struct drm_file
*file
);
2921 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2922 struct drm_file
*file
);
2923 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
2924 struct drm_file
*file_priv
);
2925 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
2926 struct drm_file
*file_priv
);
2928 /* i915_gem_evict.c */
2929 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2930 struct i915_address_space
*vm
,
2933 unsigned cache_level
,
2934 unsigned long start
,
2937 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2938 int i915_gem_evict_everything(struct drm_device
*dev
);
2940 /* belongs in i915_gem_gtt.h */
2941 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2943 if (INTEL_INFO(dev
)->gen
< 6)
2944 intel_gtt_chipset_flush();
2947 /* i915_gem_stolen.c */
2948 int i915_gem_init_stolen(struct drm_device
*dev
);
2949 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2950 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2951 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2952 struct drm_i915_gem_object
*
2953 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2954 struct drm_i915_gem_object
*
2955 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2960 /* i915_gem_tiling.c */
2961 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2963 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2965 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2966 obj
->tiling_mode
!= I915_TILING_NONE
;
2969 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2970 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2971 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2973 /* i915_gem_debug.c */
2975 int i915_verify_lists(struct drm_device
*dev
);
2977 #define i915_verify_lists(dev) 0
2980 /* i915_debugfs.c */
2981 int i915_debugfs_init(struct drm_minor
*minor
);
2982 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2983 #ifdef CONFIG_DEBUG_FS
2984 void intel_display_crc_init(struct drm_device
*dev
);
2986 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2989 /* i915_gpu_error.c */
2991 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2992 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2993 const struct i915_error_state_file_priv
*error
);
2994 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2995 struct drm_i915_private
*i915
,
2996 size_t count
, loff_t pos
);
2997 static inline void i915_error_state_buf_release(
2998 struct drm_i915_error_state_buf
*eb
)
3002 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3003 const char *error_msg
);
3004 void i915_error_state_get(struct drm_device
*dev
,
3005 struct i915_error_state_file_priv
*error_priv
);
3006 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3007 void i915_destroy_error_state(struct drm_device
*dev
);
3009 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3010 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3012 /* i915_gem_batch_pool.c */
3013 void i915_gem_batch_pool_init(struct drm_device
*dev
,
3014 struct i915_gem_batch_pool
*pool
);
3015 void i915_gem_batch_pool_fini(struct i915_gem_batch_pool
*pool
);
3016 struct drm_i915_gem_object
*
3017 i915_gem_batch_pool_get(struct i915_gem_batch_pool
*pool
, size_t size
);
3019 /* i915_cmd_parser.c */
3020 int i915_cmd_parser_get_version(void);
3021 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3022 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3023 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3024 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3025 struct drm_i915_gem_object
*batch_obj
,
3026 struct drm_i915_gem_object
*shadow_batch_obj
,
3027 u32 batch_start_offset
,
3031 /* i915_suspend.c */
3032 extern int i915_save_state(struct drm_device
*dev
);
3033 extern int i915_restore_state(struct drm_device
*dev
);
3036 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3037 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3040 extern int intel_setup_gmbus(struct drm_device
*dev
);
3041 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3042 static inline bool intel_gmbus_is_port_valid(unsigned port
)
3044 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
3047 extern struct i2c_adapter
*intel_gmbus_get_adapter(
3048 struct drm_i915_private
*dev_priv
, unsigned port
);
3049 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3050 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3051 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3053 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3055 extern void intel_i2c_reset(struct drm_device
*dev
);
3057 /* intel_opregion.c */
3059 extern int intel_opregion_setup(struct drm_device
*dev
);
3060 extern void intel_opregion_init(struct drm_device
*dev
);
3061 extern void intel_opregion_fini(struct drm_device
*dev
);
3062 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3063 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3065 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3068 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3069 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3070 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3071 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3073 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3078 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3086 extern void intel_register_dsm_handler(void);
3087 extern void intel_unregister_dsm_handler(void);
3089 static inline void intel_register_dsm_handler(void) { return; }
3090 static inline void intel_unregister_dsm_handler(void) { return; }
3091 #endif /* CONFIG_ACPI */
3094 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3095 extern void intel_modeset_init(struct drm_device
*dev
);
3096 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3097 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3098 extern void intel_connector_unregister(struct intel_connector
*);
3099 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3100 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
3101 bool force_restore
);
3102 extern void i915_redisable_vga(struct drm_device
*dev
);
3103 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3104 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3105 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3106 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3107 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3109 extern void intel_detect_pch(struct drm_device
*dev
);
3110 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3111 extern int intel_enable_rc6(const struct drm_device
*dev
);
3113 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3114 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3115 struct drm_file
*file
);
3116 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3117 struct drm_file
*file
);
3120 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3121 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3122 struct intel_overlay_error_state
*error
);
3124 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3125 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3126 struct drm_device
*dev
,
3127 struct intel_display_error_state
*error
);
3129 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3130 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3132 /* intel_sideband.c */
3133 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3134 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3135 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3136 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3137 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3138 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3139 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3140 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3141 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3142 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3143 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3144 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3145 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3146 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3147 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3148 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3149 enum intel_sbi_destination destination
);
3150 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3151 enum intel_sbi_destination destination
);
3152 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3153 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3155 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3156 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3158 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3159 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3161 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3162 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3163 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3164 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3166 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3167 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3168 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3169 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3171 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3172 * will be implemented using 2 32-bit writes in an arbitrary order with
3173 * an arbitrary delay between them. This can cause the hardware to
3174 * act upon the intermediate value, possibly leading to corruption and
3175 * machine death. You have been warned.
3177 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3178 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3180 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3181 u32 upper = I915_READ(upper_reg); \
3182 u32 lower = I915_READ(lower_reg); \
3183 u32 tmp = I915_READ(upper_reg); \
3184 if (upper != tmp) { \
3186 lower = I915_READ(lower_reg); \
3187 WARN_ON(I915_READ(upper_reg) != upper); \
3189 (u64)upper << 32 | lower; })
3191 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3192 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3194 /* "Broadcast RGB" property */
3195 #define INTEL_BROADCAST_RGB_AUTO 0
3196 #define INTEL_BROADCAST_RGB_FULL 1
3197 #define INTEL_BROADCAST_RGB_LIMITED 2
3199 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3201 if (IS_VALLEYVIEW(dev
))
3202 return VLV_VGACNTRL
;
3203 else if (INTEL_INFO(dev
)->gen
>= 5)
3204 return CPU_VGACNTRL
;
3209 static inline void __user
*to_user_ptr(u64 address
)
3211 return (void __user
*)(uintptr_t)address
;
3214 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3216 unsigned long j
= msecs_to_jiffies(m
);
3218 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3221 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3223 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3226 static inline unsigned long
3227 timespec_to_jiffies_timeout(const struct timespec
*value
)
3229 unsigned long j
= timespec_to_jiffies(value
);
3231 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3235 * If you need to wait X milliseconds between events A and B, but event B
3236 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3237 * when event A happened, then just before event B you call this function and
3238 * pass the timestamp as the first argument, and X as the second argument.
3241 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3243 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3246 * Don't re-read the value of "jiffies" every time since it may change
3247 * behind our back and break the math.
3249 tmp_jiffies
= jiffies
;
3250 target_jiffies
= timestamp_jiffies
+
3251 msecs_to_jiffies_timeout(to_wait_ms
);
3253 if (time_after(target_jiffies
, tmp_jiffies
)) {
3254 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3255 while (remaining_jiffies
)
3257 schedule_timeout_uninterruptible(remaining_jiffies
);
3261 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3262 struct drm_i915_gem_request
*req
)
3264 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3265 i915_gem_request_assign(&ring
->trace_irq_req
, req
);