projects / deliverable / linux.git / blob
? search:


d2da91f9025284b917ca0c15806cde9cdf6bf51d
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include "i915_reg.h"
34 #include "intel_bios.h"
35 #include "intel_ringbuffer.h"
36 #include <linux/io-mapping.h>
37 #include <linux/i2c.h>
38 #include <drm/intel-gtt.h>
39 #include <linux/backlight.h>
40
41 /* General customization:
42 */
43
44 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
45
46 #define DRIVER_NAME "i915"
47 #define DRIVER_DESC "Intel Graphics"
48 #define DRIVER_DATE "20080730"
49
50 enum pipe {
51 PIPE_A = 0,
52 PIPE_B,
53 PIPE_C,
54 I915_MAX_PIPES
55 };
56 #define pipe_name(p) ((p) + 'A')
57
58 enum plane {
59 PLANE_A = 0,
60 PLANE_B,
61 PLANE_C,
62 };
63 #define plane_name(p) ((p) + 'A')
64
65 #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
66
67 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
68
69 /* Interface history:
70 *
71 * 1.1: Original.
72 * 1.2: Add Power Management
73 * 1.3: Add vblank support
74 * 1.4: Fix cmdbuffer path, add heap destroy
75 * 1.5: Add vblank pipe configuration
76 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
77 * - Support vertical blank on secondary display pipe
78 */
79 #define DRIVER_MAJOR 1
80 #define DRIVER_MINOR 6
81 #define DRIVER_PATCHLEVEL 0
82
83 #define WATCH_COHERENCY 0
84 #define WATCH_LISTS 0
85
86 #define I915_GEM_PHYS_CURSOR_0 1
87 #define I915_GEM_PHYS_CURSOR_1 2
88 #define I915_GEM_PHYS_OVERLAY_REGS 3
89 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
90
91 struct drm_i915_gem_phys_object {
92 int id;
93 struct page **page_list;
94 drm_dma_handle_t *handle;
95 struct drm_i915_gem_object *cur_obj;
96 };
97
98 struct mem_block {
99 struct mem_block *next;
100 struct mem_block *prev;
101 int start;
102 int size;
103 struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
104 };
105
106 struct opregion_header;
107 struct opregion_acpi;
108 struct opregion_swsci;
109 struct opregion_asle;
110
111 struct intel_opregion {
112 struct opregion_header *header;
113 struct opregion_acpi *acpi;
114 struct opregion_swsci *swsci;
115 struct opregion_asle *asle;
116 void *vbt;
117 u32 __iomem *lid_state;
118 };
119 #define OPREGION_SIZE (8*1024)
120
121 struct intel_overlay;
122 struct intel_overlay_error_state;
123
124 struct drm_i915_master_private {
125 drm_local_map_t *sarea;
126 struct _drm_i915_sarea *sarea_priv;
127 };
128 #define I915_FENCE_REG_NONE -1
129 #define I915_MAX_NUM_FENCES 16
130 /* 16 fences + sign bit for FENCE_REG_NONE */
131 #define I915_MAX_NUM_FENCE_BITS 5
132
133 struct drm_i915_fence_reg {
134 struct list_head lru_list;
135 struct drm_i915_gem_object *obj;
136 uint32_t setup_seqno;
137 };
138
139 struct sdvo_device_mapping {
140 u8 initialized;
141 u8 dvo_port;
142 u8 slave_addr;
143 u8 dvo_wiring;
144 u8 i2c_pin;
145 u8 ddc_pin;
146 };
147
148 struct intel_display_error_state;
149
150 struct drm_i915_error_state {
151 u32 eir;
152 u32 pgtbl_er;
153 u32 pipestat[I915_MAX_PIPES];
154 u32 ipeir;
155 u32 ipehr;
156 u32 instdone;
157 u32 acthd;
158 u32 error; /* gen6+ */
159 u32 bcs_acthd; /* gen6+ blt engine */
160 u32 bcs_ipehr;
161 u32 bcs_ipeir;
162 u32 bcs_instdone;
163 u32 bcs_seqno;
164 u32 vcs_acthd; /* gen6+ bsd engine */
165 u32 vcs_ipehr;
166 u32 vcs_ipeir;
167 u32 vcs_instdone;
168 u32 vcs_seqno;
169 u32 instpm;
170 u32 instps;
171 u32 instdone1;
172 u32 seqno;
173 u64 bbaddr;
174 u64 fence[I915_MAX_NUM_FENCES];
175 struct timeval time;
176 struct drm_i915_error_object {
177 int page_count;
178 u32 gtt_offset;
179 u32 *pages[0];
180 } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
181 struct drm_i915_error_buffer {
182 u32 size;
183 u32 name;
184 u32 seqno;
185 u32 gtt_offset;
186 u32 read_domains;
187 u32 write_domain;
188 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
189 s32 pinned:2;
190 u32 tiling:2;
191 u32 dirty:1;
192 u32 purgeable:1;
193 u32 ring:4;
194 u32 cache_level:2;
195 } *active_bo, *pinned_bo;
196 u32 active_bo_count, pinned_bo_count;
197 struct intel_overlay_error_state *overlay;
198 struct intel_display_error_state *display;
199 };
200
201 struct drm_i915_display_funcs {
202 void (*dpms)(struct drm_crtc *crtc, int mode);
203 bool (*fbc_enabled)(struct drm_device *dev);
204 void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
205 void (*disable_fbc)(struct drm_device *dev);
206 int (*get_display_clock_speed)(struct drm_device *dev);
207 int (*get_fifo_size)(struct drm_device *dev, int plane);
208 void (*update_wm)(struct drm_device *dev);
209 int (*crtc_mode_set)(struct drm_crtc *crtc,
210 struct drm_display_mode *mode,
211 struct drm_display_mode *adjusted_mode,
212 int x, int y,
213 struct drm_framebuffer *old_fb);
214 void (*write_eld)(struct drm_connector *connector,
215 struct drm_crtc *crtc);
216 void (*fdi_link_train)(struct drm_crtc *crtc);
217 void (*init_clock_gating)(struct drm_device *dev);
218 void (*init_pch_clock_gating)(struct drm_device *dev);
219 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
220 struct drm_framebuffer *fb,
221 struct drm_i915_gem_object *obj);
222 int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
223 int x, int y);
224 /* clock updates for mode set */
225 /* cursor updates */
226 /* render clock increase/decrease */
227 /* display clock increase/decrease */
228 /* pll clock increase/decrease */
229 };
230
231 struct intel_device_info {
232 u8 gen;
233 u8 is_mobile:1;
234 u8 is_i85x:1;
235 u8 is_i915g:1;
236 u8 is_i945gm:1;
237 u8 is_g33:1;
238 u8 need_gfx_hws:1;
239 u8 is_g4x:1;
240 u8 is_pineview:1;
241 u8 is_broadwater:1;
242 u8 is_crestline:1;
243 u8 is_ivybridge:1;
244 u8 has_fbc:1;
245 u8 has_pipe_cxsr:1;
246 u8 has_hotplug:1;
247 u8 cursor_needs_physical:1;
248 u8 has_overlay:1;
249 u8 overlay_needs_physical:1;
250 u8 supports_tv:1;
251 u8 has_bsd_ring:1;
252 u8 has_blt_ring:1;
253 };
254
255 enum no_fbc_reason {
256 FBC_NO_OUTPUT, /* no outputs enabled to compress */
257 FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
258 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
259 FBC_MODE_TOO_LARGE, /* mode too large for compression */
260 FBC_BAD_PLANE, /* fbc not supported on plane */
261 FBC_NOT_TILED, /* buffer not tiled */
262 FBC_MULTIPLE_PIPES, /* more than one pipe active */
263 FBC_MODULE_PARAM,
264 };
265
266 enum intel_pch {
267 PCH_IBX, /* Ibexpeak PCH */
268 PCH_CPT, /* Cougarpoint PCH */
269 };
270
271 #define QUIRK_PIPEA_FORCE (1<<0)
272 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
273
274 struct intel_fbdev;
275 struct intel_fbc_work;
276
277 typedef struct drm_i915_private {
278 struct drm_device *dev;
279
280 const struct intel_device_info *info;
281
282 int has_gem;
283 int relative_constants_mode;
284
285 void __iomem *regs;
286 u32 gt_fifo_count;
287
288 struct intel_gmbus {
289 struct i2c_adapter adapter;
290 struct i2c_adapter *force_bit;
291 u32 reg0;
292 } *gmbus;
293
294 struct pci_dev *bridge_dev;
295 struct intel_ring_buffer ring[I915_NUM_RINGS];
296 uint32_t next_seqno;
297
298 drm_dma_handle_t *status_page_dmah;
299 uint32_t counter;
300 drm_local_map_t hws_map;
301 struct drm_i915_gem_object *pwrctx;
302 struct drm_i915_gem_object *renderctx;
303
304 struct resource mch_res;
305
306 unsigned int cpp;
307 int back_offset;
308 int front_offset;
309 int current_page;
310 int page_flipping;
311
312 atomic_t irq_received;
313
314 /* protects the irq masks */
315 spinlock_t irq_lock;
316 /** Cached value of IMR to avoid reads in updating the bitfield */
317 u32 pipestat[2];
318 u32 irq_mask;
319 u32 gt_irq_mask;
320 u32 pch_irq_mask;
321
322 u32 hotplug_supported_mask;
323 struct work_struct hotplug_work;
324
325 int tex_lru_log_granularity;
326 int allow_batchbuffer;
327 struct mem_block *agp_heap;
328 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
329 int vblank_pipe;
330 int num_pipe;
331
332 /* For hangcheck timer */
333 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
334 struct timer_list hangcheck_timer;
335 int hangcheck_count;
336 uint32_t last_acthd;
337 uint32_t last_instdone;
338 uint32_t last_instdone1;
339
340 unsigned long cfb_size;
341 unsigned int cfb_fb;
342 enum plane cfb_plane;
343 int cfb_y;
344 struct intel_fbc_work *fbc_work;
345
346 struct intel_opregion opregion;
347
348 /* overlay */
349 struct intel_overlay *overlay;
350
351 /* LVDS info */
352 int backlight_level; /* restore backlight to this value */
353 bool backlight_enabled;
354 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
355 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
356
357 /* Feature bits from the VBIOS */
358 unsigned int int_tv_support:1;
359 unsigned int lvds_dither:1;
360 unsigned int lvds_vbt:1;
361 unsigned int int_crt_support:1;
362 unsigned int lvds_use_ssc:1;
363 unsigned int display_clock_mode:1;
364 int lvds_ssc_freq;
365 struct {
366 int rate;
367 int lanes;
368 int preemphasis;
369 int vswing;
370
371 bool initialized;
372 bool support;
373 int bpp;
374 struct edp_power_seq pps;
375 } edp;
376 bool no_aux_handshake;
377
378 struct notifier_block lid_notifier;
379
380 int crt_ddc_pin;
381 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
382 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
383 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
384
385 unsigned int fsb_freq, mem_freq, is_ddr3;
386
387 spinlock_t error_lock;
388 struct drm_i915_error_state *first_error;
389 struct work_struct error_work;
390 struct completion error_completion;
391 struct workqueue_struct *wq;
392
393 /* Display functions */
394 struct drm_i915_display_funcs display;
395
396 /* PCH chipset type */
397 enum intel_pch pch_type;
398
399 unsigned long quirks;
400
401 /* Register state */
402 bool modeset_on_lid;
403 u8 saveLBB;
404 u32 saveDSPACNTR;
405 u32 saveDSPBCNTR;
406 u32 saveDSPARB;
407 u32 saveHWS;
408 u32 savePIPEACONF;
409 u32 savePIPEBCONF;
410 u32 savePIPEASRC;
411 u32 savePIPEBSRC;
412 u32 saveFPA0;
413 u32 saveFPA1;
414 u32 saveDPLL_A;
415 u32 saveDPLL_A_MD;
416 u32 saveHTOTAL_A;
417 u32 saveHBLANK_A;
418 u32 saveHSYNC_A;
419 u32 saveVTOTAL_A;
420 u32 saveVBLANK_A;
421 u32 saveVSYNC_A;
422 u32 saveBCLRPAT_A;
423 u32 saveTRANSACONF;
424 u32 saveTRANS_HTOTAL_A;
425 u32 saveTRANS_HBLANK_A;
426 u32 saveTRANS_HSYNC_A;
427 u32 saveTRANS_VTOTAL_A;
428 u32 saveTRANS_VBLANK_A;
429 u32 saveTRANS_VSYNC_A;
430 u32 savePIPEASTAT;
431 u32 saveDSPASTRIDE;
432 u32 saveDSPASIZE;
433 u32 saveDSPAPOS;
434 u32 saveDSPAADDR;
435 u32 saveDSPASURF;
436 u32 saveDSPATILEOFF;
437 u32 savePFIT_PGM_RATIOS;
438 u32 saveBLC_HIST_CTL;
439 u32 saveBLC_PWM_CTL;
440 u32 saveBLC_PWM_CTL2;
441 u32 saveBLC_CPU_PWM_CTL;
442 u32 saveBLC_CPU_PWM_CTL2;
443 u32 saveFPB0;
444 u32 saveFPB1;
445 u32 saveDPLL_B;
446 u32 saveDPLL_B_MD;
447 u32 saveHTOTAL_B;
448 u32 saveHBLANK_B;
449 u32 saveHSYNC_B;
450 u32 saveVTOTAL_B;
451 u32 saveVBLANK_B;
452 u32 saveVSYNC_B;
453 u32 saveBCLRPAT_B;
454 u32 saveTRANSBCONF;
455 u32 saveTRANS_HTOTAL_B;
456 u32 saveTRANS_HBLANK_B;
457 u32 saveTRANS_HSYNC_B;
458 u32 saveTRANS_VTOTAL_B;
459 u32 saveTRANS_VBLANK_B;
460 u32 saveTRANS_VSYNC_B;
461 u32 savePIPEBSTAT;
462 u32 saveDSPBSTRIDE;
463 u32 saveDSPBSIZE;
464 u32 saveDSPBPOS;
465 u32 saveDSPBADDR;
466 u32 saveDSPBSURF;
467 u32 saveDSPBTILEOFF;
468 u32 saveVGA0;
469 u32 saveVGA1;
470 u32 saveVGA_PD;
471 u32 saveVGACNTRL;
472 u32 saveADPA;
473 u32 saveLVDS;
474 u32 savePP_ON_DELAYS;
475 u32 savePP_OFF_DELAYS;
476 u32 saveDVOA;
477 u32 saveDVOB;
478 u32 saveDVOC;
479 u32 savePP_ON;
480 u32 savePP_OFF;
481 u32 savePP_CONTROL;
482 u32 savePP_DIVISOR;
483 u32 savePFIT_CONTROL;
484 u32 save_palette_a[256];
485 u32 save_palette_b[256];
486 u32 saveDPFC_CB_BASE;
487 u32 saveFBC_CFB_BASE;
488 u32 saveFBC_LL_BASE;
489 u32 saveFBC_CONTROL;
490 u32 saveFBC_CONTROL2;
491 u32 saveIER;
492 u32 saveIIR;
493 u32 saveIMR;
494 u32 saveDEIER;
495 u32 saveDEIMR;
496 u32 saveGTIER;
497 u32 saveGTIMR;
498 u32 saveFDI_RXA_IMR;
499 u32 saveFDI_RXB_IMR;
500 u32 saveCACHE_MODE_0;
501 u32 saveMI_ARB_STATE;
502 u32 saveSWF0[16];
503 u32 saveSWF1[16];
504 u32 saveSWF2[3];
505 u8 saveMSR;
506 u8 saveSR[8];
507 u8 saveGR[25];
508 u8 saveAR_INDEX;
509 u8 saveAR[21];
510 u8 saveDACMASK;
511 u8 saveCR[37];
512 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
513 u32 saveCURACNTR;
514 u32 saveCURAPOS;
515 u32 saveCURABASE;
516 u32 saveCURBCNTR;
517 u32 saveCURBPOS;
518 u32 saveCURBBASE;
519 u32 saveCURSIZE;
520 u32 saveDP_B;
521 u32 saveDP_C;
522 u32 saveDP_D;
523 u32 savePIPEA_GMCH_DATA_M;
524 u32 savePIPEB_GMCH_DATA_M;
525 u32 savePIPEA_GMCH_DATA_N;
526 u32 savePIPEB_GMCH_DATA_N;
527 u32 savePIPEA_DP_LINK_M;
528 u32 savePIPEB_DP_LINK_M;
529 u32 savePIPEA_DP_LINK_N;
530 u32 savePIPEB_DP_LINK_N;
531 u32 saveFDI_RXA_CTL;
532 u32 saveFDI_TXA_CTL;
533 u32 saveFDI_RXB_CTL;
534 u32 saveFDI_TXB_CTL;
535 u32 savePFA_CTL_1;
536 u32 savePFB_CTL_1;
537 u32 savePFA_WIN_SZ;
538 u32 savePFB_WIN_SZ;
539 u32 savePFA_WIN_POS;
540 u32 savePFB_WIN_POS;
541 u32 savePCH_DREF_CONTROL;
542 u32 saveDISP_ARB_CTL;
543 u32 savePIPEA_DATA_M1;
544 u32 savePIPEA_DATA_N1;
545 u32 savePIPEA_LINK_M1;
546 u32 savePIPEA_LINK_N1;
547 u32 savePIPEB_DATA_M1;
548 u32 savePIPEB_DATA_N1;
549 u32 savePIPEB_LINK_M1;
550 u32 savePIPEB_LINK_N1;
551 u32 saveMCHBAR_RENDER_STANDBY;
552 u32 savePCH_PORT_HOTPLUG;
553
554 struct {
555 /** Bridge to intel-gtt-ko */
556 const struct intel_gtt *gtt;
557 /** Memory allocator for GTT stolen memory */
558 struct drm_mm stolen;
559 /** Memory allocator for GTT */
560 struct drm_mm gtt_space;
561 /** List of all objects in gtt_space. Used to restore gtt
562 * mappings on resume */
563 struct list_head gtt_list;
564
565 /** Usable portion of the GTT for GEM */
566 unsigned long gtt_start;
567 unsigned long gtt_mappable_end;
568 unsigned long gtt_end;
569
570 struct io_mapping *gtt_mapping;
571 int gtt_mtrr;
572
573 struct shrinker inactive_shrinker;
574
575 /**
576 * List of objects currently involved in rendering.
577 *
578 * Includes buffers having the contents of their GPU caches
579 * flushed, not necessarily primitives. last_rendering_seqno
580 * represents when the rendering involved will be completed.
581 *
582 * A reference is held on the buffer while on this list.
583 */
584 struct list_head active_list;
585
586 /**
587 * List of objects which are not in the ringbuffer but which
588 * still have a write_domain which needs to be flushed before
589 * unbinding.
590 *
591 * last_rendering_seqno is 0 while an object is in this list.
592 *
593 * A reference is held on the buffer while on this list.
594 */
595 struct list_head flushing_list;
596
597 /**
598 * LRU list of objects which are not in the ringbuffer and
599 * are ready to unbind, but are still in the GTT.
600 *
601 * last_rendering_seqno is 0 while an object is in this list.
602 *
603 * A reference is not held on the buffer while on this list,
604 * as merely being GTT-bound shouldn't prevent its being
605 * freed, and we'll pull it off the list in the free path.
606 */
607 struct list_head inactive_list;
608
609 /**
610 * LRU list of objects which are not in the ringbuffer but
611 * are still pinned in the GTT.
612 */
613 struct list_head pinned_list;
614
615 /** LRU list of objects with fence regs on them. */
616 struct list_head fence_list;
617
618 /**
619 * List of objects currently pending being freed.
620 *
621 * These objects are no longer in use, but due to a signal
622 * we were prevented from freeing them at the appointed time.
623 */
624 struct list_head deferred_free_list;
625
626 /**
627 * We leave the user IRQ off as much as possible,
628 * but this means that requests will finish and never
629 * be retired once the system goes idle. Set a timer to
630 * fire periodically while the ring is running. When it
631 * fires, go retire requests.
632 */
633 struct delayed_work retire_work;
634
635 /**
636 * Are we in a non-interruptible section of code like
637 * modesetting?
638 */
639 bool interruptible;
640
641 /**
642 * Flag if the X Server, and thus DRM, is not currently in
643 * control of the device.
644 *
645 * This is set between LeaveVT and EnterVT. It needs to be
646 * replaced with a semaphore. It also needs to be
647 * transitioned away from for kernel modesetting.
648 */
649 int suspended;
650
651 /**
652 * Flag if the hardware appears to be wedged.
653 *
654 * This is set when attempts to idle the device timeout.
655 * It prevents command submission from occurring and makes
656 * every pending request fail
657 */
658 atomic_t wedged;
659
660 /** Bit 6 swizzling required for X tiling */
661 uint32_t bit_6_swizzle_x;
662 /** Bit 6 swizzling required for Y tiling */
663 uint32_t bit_6_swizzle_y;
664
665 /* storage for physical objects */
666 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
667
668 /* accounting, useful for userland debugging */
669 size_t gtt_total;
670 size_t mappable_gtt_total;
671 size_t object_memory;
672 u32 object_count;
673 } mm;
674 struct sdvo_device_mapping sdvo_mappings[2];
675 /* indicate whether the LVDS_BORDER should be enabled or not */
676 unsigned int lvds_border_bits;
677 /* Panel fitter placement and size for Ironlake+ */
678 u32 pch_pf_pos, pch_pf_size;
679
680 struct drm_crtc *plane_to_crtc_mapping[3];
681 struct drm_crtc *pipe_to_crtc_mapping[3];
682 wait_queue_head_t pending_flip_queue;
683 bool flip_pending_is_done;
684
685 /* Reclocking support */
686 bool render_reclock_avail;
687 bool lvds_downclock_avail;
688 /* indicates the reduced downclock for LVDS*/
689 int lvds_downclock;
690 struct work_struct idle_work;
691 struct timer_list idle_timer;
692 bool busy;
693 u16 orig_clock;
694 int child_dev_num;
695 struct child_device_config *child_dev;
696 struct drm_connector *int_lvds_connector;
697 struct drm_connector *int_edp_connector;
698
699 bool mchbar_need_disable;
700
701 struct work_struct rps_work;
702 spinlock_t rps_lock;
703 u32 pm_iir;
704
705 u8 cur_delay;
706 u8 min_delay;
707 u8 max_delay;
708 u8 fmax;
709 u8 fstart;
710
711 u64 last_count1;
712 unsigned long last_time1;
713 u64 last_count2;
714 struct timespec last_time2;
715 unsigned long gfx_power;
716 int c_m;
717 int r_t;
718 u8 corr;
719 spinlock_t *mchdev_lock;
720
721 enum no_fbc_reason no_fbc_reason;
722
723 struct drm_mm_node *compressed_fb;
724 struct drm_mm_node *compressed_llb;
725
726 unsigned long last_gpu_reset;
727
728 /* list of fbdev register on this device */
729 struct intel_fbdev *fbdev;
730
731 struct backlight_device *backlight;
732
733 struct drm_property *broadcast_rgb_property;
734 struct drm_property *force_audio_property;
735
736 atomic_t forcewake_count;
737 } drm_i915_private_t;
738
739 enum i915_cache_level {
740 I915_CACHE_NONE,
741 I915_CACHE_LLC,
742 I915_CACHE_LLC_MLC, /* gen6+ */
743 };
744
745 struct drm_i915_gem_object {
746 struct drm_gem_object base;
747
748 /** Current space allocated to this object in the GTT, if any. */
749 struct drm_mm_node *gtt_space;
750 struct list_head gtt_list;
751
752 /** This object's place on the active/flushing/inactive lists */
753 struct list_head ring_list;
754 struct list_head mm_list;
755 /** This object's place on GPU write list */
756 struct list_head gpu_write_list;
757 /** This object's place in the batchbuffer or on the eviction list */
758 struct list_head exec_list;
759
760 /**
761 * This is set if the object is on the active or flushing lists
762 * (has pending rendering), and is not set if it's on inactive (ready
763 * to be unbound).
764 */
765 unsigned int active:1;
766
767 /**
768 * This is set if the object has been written to since last bound
769 * to the GTT
770 */
771 unsigned int dirty:1;
772
773 /**
774 * This is set if the object has been written to since the last
775 * GPU flush.
776 */
777 unsigned int pending_gpu_write:1;
778
779 /**
780 * Fence register bits (if any) for this object. Will be set
781 * as needed when mapped into the GTT.
782 * Protected by dev->struct_mutex.
783 */
784 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
785
786 /**
787 * Advice: are the backing pages purgeable?
788 */
789 unsigned int madv:2;
790
791 /**
792 * Current tiling mode for the object.
793 */
794 unsigned int tiling_mode:2;
795 unsigned int tiling_changed:1;
796
797 /** How many users have pinned this object in GTT space. The following
798 * users can each hold at most one reference: pwrite/pread, pin_ioctl
799 * (via user_pin_count), execbuffer (objects are not allowed multiple
800 * times for the same batchbuffer), and the framebuffer code. When
801 * switching/pageflipping, the framebuffer code has at most two buffers
802 * pinned per crtc.
803 *
804 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
805 * bits with absolutely no headroom. So use 4 bits. */
806 unsigned int pin_count:4;
807 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
808
809 /**
810 * Is the object at the current location in the gtt mappable and
811 * fenceable? Used to avoid costly recalculations.
812 */
813 unsigned int map_and_fenceable:1;
814
815 /**
816 * Whether the current gtt mapping needs to be mappable (and isn't just
817 * mappable by accident). Track pin and fault separate for a more
818 * accurate mappable working set.
819 */
820 unsigned int fault_mappable:1;
821 unsigned int pin_mappable:1;
822
823 /*
824 * Is the GPU currently using a fence to access this buffer,
825 */
826 unsigned int pending_fenced_gpu_access:1;
827 unsigned int fenced_gpu_access:1;
828
829 unsigned int cache_level:2;
830
831 struct page **pages;
832
833 /**
834 * DMAR support
835 */
836 struct scatterlist *sg_list;
837 int num_sg;
838
839 /**
840 * Used for performing relocations during execbuffer insertion.
841 */
842 struct hlist_node exec_node;
843 unsigned long exec_handle;
844 struct drm_i915_gem_exec_object2 *exec_entry;
845
846 /**
847 * Current offset of the object in GTT space.
848 *
849 * This is the same as gtt_space->start
850 */
851 uint32_t gtt_offset;
852
853 /** Breadcrumb of last rendering to the buffer. */
854 uint32_t last_rendering_seqno;
855 struct intel_ring_buffer *ring;
856
857 /** Breadcrumb of last fenced GPU access to the buffer. */
858 uint32_t last_fenced_seqno;
859 struct intel_ring_buffer *last_fenced_ring;
860
861 /** Current tiling stride for the object, if it's tiled. */
862 uint32_t stride;
863
864 /** Record of address bit 17 of each page at last unbind. */
865 unsigned long *bit_17;
866
867
868 /**
869 * If present, while GEM_DOMAIN_CPU is in the read domain this array
870 * flags which individual pages are valid.
871 */
872 uint8_t *page_cpu_valid;
873
874 /** User space pin count and filp owning the pin */
875 uint32_t user_pin_count;
876 struct drm_file *pin_filp;
877
878 /** for phy allocated objects */
879 struct drm_i915_gem_phys_object *phys_obj;
880
881 /**
882 * Number of crtcs where this object is currently the fb, but
883 * will be page flipped away on the next vblank. When it
884 * reaches 0, dev_priv->pending_flip_queue will be woken up.
885 */
886 atomic_t pending_flip;
887 };
888
889 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
890
891 /**
892 * Request queue structure.
893 *
894 * The request queue allows us to note sequence numbers that have been emitted
895 * and may be associated with active buffers to be retired.
896 *
897 * By keeping this list, we can avoid having to do questionable
898 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
899 * an emission time with seqnos for tracking how far ahead of the GPU we are.
900 */
901 struct drm_i915_gem_request {
902 /** On Which ring this request was generated */
903 struct intel_ring_buffer *ring;
904
905 /** GEM sequence number associated with this request. */
906 uint32_t seqno;
907
908 /** Time at which this request was emitted, in jiffies. */
909 unsigned long emitted_jiffies;
910
911 /** global list entry for this request */
912 struct list_head list;
913
914 struct drm_i915_file_private *file_priv;
915 /** file_priv list entry for this request */
916 struct list_head client_list;
917 };
918
919 struct drm_i915_file_private {
920 struct {
921 struct spinlock lock;
922 struct list_head request_list;
923 } mm;
924 };
925
926 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
927
928 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
929 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
930 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
931 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
932 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
933 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
934 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
935 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
936 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
937 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
938 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
939 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
940 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
941 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
942 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
943 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
944 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
945 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
946 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
947 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
948
949 /*
950 * The genX designation typically refers to the render engine, so render
951 * capability related checks should use IS_GEN, while display and other checks
952 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
953 * chips, etc.).
954 */
955 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
956 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
957 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
958 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
959 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
960 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
961
962 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
963 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
964 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
965
966 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
967 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
968
969 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
970 * rows, which changed the alignment requirements and fence programming.
971 */
972 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
973 IS_I915GM(dev)))
974 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
975 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
976 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
977 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
978 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
979 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
980 /* dsparb controlled by hw only */
981 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
982
983 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
984 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
985 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
986
987 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
988 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
989
990 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
991 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
992 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
993
994 #include "i915_trace.h"
995
996 extern struct drm_ioctl_desc i915_ioctls[];
997 extern int i915_max_ioctl;
998 extern unsigned int i915_fbpercrtc __always_unused;
999 extern int i915_panel_ignore_lid __read_mostly;
1000 extern unsigned int i915_powersave __read_mostly;
1001 extern unsigned int i915_semaphores __read_mostly;
1002 extern unsigned int i915_lvds_downclock __read_mostly;
1003 extern unsigned int i915_panel_use_ssc __read_mostly;
1004 extern int i915_vbt_sdvo_panel_type __read_mostly;
1005 extern unsigned int i915_enable_rc6 __read_mostly;
1006 extern unsigned int i915_enable_fbc __read_mostly;
1007 extern bool i915_enable_hangcheck __read_mostly;
1008
1009 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1010 extern int i915_resume(struct drm_device *dev);
1011 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1012 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1013
1014 /* i915_dma.c */
1015 extern void i915_kernel_lost_context(struct drm_device * dev);
1016 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1017 extern int i915_driver_unload(struct drm_device *);
1018 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1019 extern void i915_driver_lastclose(struct drm_device * dev);
1020 extern void i915_driver_preclose(struct drm_device *dev,
1021 struct drm_file *file_priv);
1022 extern void i915_driver_postclose(struct drm_device *dev,
1023 struct drm_file *file_priv);
1024 extern int i915_driver_device_is_agp(struct drm_device * dev);
1025 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1026 unsigned long arg);
1027 extern int i915_emit_box(struct drm_device *dev,
1028 struct drm_clip_rect *box,
1029 int DR1, int DR4);
1030 extern int i915_reset(struct drm_device *dev, u8 flags);
1031 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1032 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1033 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1034 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1035
1036
1037 /* i915_irq.c */
1038 void i915_hangcheck_elapsed(unsigned long data);
1039 void i915_handle_error(struct drm_device *dev, bool wedged);
1040 extern int i915_irq_emit(struct drm_device *dev, void *data,
1041 struct drm_file *file_priv);
1042 extern int i915_irq_wait(struct drm_device *dev, void *data,
1043 struct drm_file *file_priv);
1044
1045 extern void intel_irq_init(struct drm_device *dev);
1046
1047 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1048 struct drm_file *file_priv);
1049 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1050 struct drm_file *file_priv);
1051 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1052 struct drm_file *file_priv);
1053
1054 void
1055 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1056
1057 void
1058 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1059
1060 void intel_enable_asle(struct drm_device *dev);
1061
1062 #ifdef CONFIG_DEBUG_FS
1063 extern void i915_destroy_error_state(struct drm_device *dev);
1064 #else
1065 #define i915_destroy_error_state(x)
1066 #endif
1067
1068
1069 /* i915_mem.c */
1070 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1071 struct drm_file *file_priv);
1072 extern int i915_mem_free(struct drm_device *dev, void *data,
1073 struct drm_file *file_priv);
1074 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1075 struct drm_file *file_priv);
1076 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1077 struct drm_file *file_priv);
1078 extern void i915_mem_takedown(struct mem_block **heap);
1079 extern void i915_mem_release(struct drm_device * dev,
1080 struct drm_file *file_priv, struct mem_block *heap);
1081 /* i915_gem.c */
1082 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1083 struct drm_file *file_priv);
1084 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1085 struct drm_file *file_priv);
1086 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1087 struct drm_file *file_priv);
1088 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1089 struct drm_file *file_priv);
1090 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1091 struct drm_file *file_priv);
1092 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1093 struct drm_file *file_priv);
1094 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1095 struct drm_file *file_priv);
1096 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1097 struct drm_file *file_priv);
1098 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1099 struct drm_file *file_priv);
1100 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1101 struct drm_file *file_priv);
1102 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1103 struct drm_file *file_priv);
1104 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1105 struct drm_file *file_priv);
1106 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1107 struct drm_file *file_priv);
1108 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1109 struct drm_file *file_priv);
1110 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1111 struct drm_file *file_priv);
1112 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1113 struct drm_file *file_priv);
1114 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1115 struct drm_file *file_priv);
1116 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1117 struct drm_file *file_priv);
1118 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1119 struct drm_file *file_priv);
1120 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1121 struct drm_file *file_priv);
1122 void i915_gem_load(struct drm_device *dev);
1123 int i915_gem_init_object(struct drm_gem_object *obj);
1124 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1125 uint32_t invalidate_domains,
1126 uint32_t flush_domains);
1127 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1128 size_t size);
1129 void i915_gem_free_object(struct drm_gem_object *obj);
1130 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1131 uint32_t alignment,
1132 bool map_and_fenceable);
1133 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1134 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1135 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1136 void i915_gem_lastclose(struct drm_device *dev);
1137
1138 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1139 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1140 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1141 struct intel_ring_buffer *ring,
1142 u32 seqno);
1143
1144 int i915_gem_dumb_create(struct drm_file *file_priv,
1145 struct drm_device *dev,
1146 struct drm_mode_create_dumb *args);
1147 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1148 uint32_t handle, uint64_t *offset);
1149 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1150 uint32_t handle);
1151 /**
1152 * Returns true if seq1 is later than seq2.
1153 */
1154 static inline bool
1155 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1156 {
1157 return (int32_t)(seq1 - seq2) >= 0;
1158 }
1159
1160 static inline u32
1161 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1162 {
1163 drm_i915_private_t *dev_priv = ring->dev->dev_private;
1164 return ring->outstanding_lazy_request = dev_priv->next_seqno;
1165 }
1166
1167 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1168 struct intel_ring_buffer *pipelined);
1169 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1170
1171 void i915_gem_retire_requests(struct drm_device *dev);
1172 void i915_gem_reset(struct drm_device *dev);
1173 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1174 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1175 uint32_t read_domains,
1176 uint32_t write_domain);
1177 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1178 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1179 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1180 void i915_gem_do_init(struct drm_device *dev,
1181 unsigned long start,
1182 unsigned long mappable_end,
1183 unsigned long end);
1184 int __must_check i915_gpu_idle(struct drm_device *dev);
1185 int __must_check i915_gem_idle(struct drm_device *dev);
1186 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1187 struct drm_file *file,
1188 struct drm_i915_gem_request *request);
1189 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1190 uint32_t seqno);
1191 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1192 int __must_check
1193 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1194 bool write);
1195 int __must_check
1196 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1197 u32 alignment,
1198 struct intel_ring_buffer *pipelined);
1199 int i915_gem_attach_phys_object(struct drm_device *dev,
1200 struct drm_i915_gem_object *obj,
1201 int id,
1202 int align);
1203 void i915_gem_detach_phys_object(struct drm_device *dev,
1204 struct drm_i915_gem_object *obj);
1205 void i915_gem_free_all_phys_object(struct drm_device *dev);
1206 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1207
1208 uint32_t
1209 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1210 uint32_t size,
1211 int tiling_mode);
1212
1213 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1214 enum i915_cache_level cache_level);
1215
1216 /* i915_gem_gtt.c */
1217 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1218 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1219 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1220 enum i915_cache_level cache_level);
1221 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1222
1223 /* i915_gem_evict.c */
1224 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1225 unsigned alignment, bool mappable);
1226 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1227 bool purgeable_only);
1228 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1229 bool purgeable_only);
1230
1231 /* i915_gem_tiling.c */
1232 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1233 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1234 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1235
1236 /* i915_gem_debug.c */
1237 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1238 const char *where, uint32_t mark);
1239 #if WATCH_LISTS
1240 int i915_verify_lists(struct drm_device *dev);
1241 #else
1242 #define i915_verify_lists(dev) 0
1243 #endif
1244 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1245 int handle);
1246 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1247 const char *where, uint32_t mark);
1248
1249 /* i915_debugfs.c */
1250 int i915_debugfs_init(struct drm_minor *minor);
1251 void i915_debugfs_cleanup(struct drm_minor *minor);
1252
1253 /* i915_suspend.c */
1254 extern int i915_save_state(struct drm_device *dev);
1255 extern int i915_restore_state(struct drm_device *dev);
1256
1257 /* i915_suspend.c */
1258 extern int i915_save_state(struct drm_device *dev);
1259 extern int i915_restore_state(struct drm_device *dev);
1260
1261 /* intel_i2c.c */
1262 extern int intel_setup_gmbus(struct drm_device *dev);
1263 extern void intel_teardown_gmbus(struct drm_device *dev);
1264 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1265 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1266 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1267 {
1268 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1269 }
1270 extern void intel_i2c_reset(struct drm_device *dev);
1271
1272 /* intel_opregion.c */
1273 extern int intel_opregion_setup(struct drm_device *dev);
1274 #ifdef CONFIG_ACPI
1275 extern void intel_opregion_init(struct drm_device *dev);
1276 extern void intel_opregion_fini(struct drm_device *dev);
1277 extern void intel_opregion_asle_intr(struct drm_device *dev);
1278 extern void intel_opregion_gse_intr(struct drm_device *dev);
1279 extern void intel_opregion_enable_asle(struct drm_device *dev);
1280 #else
1281 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1282 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1283 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1284 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1285 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1286 #endif
1287
1288 /* intel_acpi.c */
1289 #ifdef CONFIG_ACPI
1290 extern void intel_register_dsm_handler(void);
1291 extern void intel_unregister_dsm_handler(void);
1292 #else
1293 static inline void intel_register_dsm_handler(void) { return; }
1294 static inline void intel_unregister_dsm_handler(void) { return; }
1295 #endif /* CONFIG_ACPI */
1296
1297 /* modesetting */
1298 extern void intel_modeset_init(struct drm_device *dev);
1299 extern void intel_modeset_gem_init(struct drm_device *dev);
1300 extern void intel_modeset_cleanup(struct drm_device *dev);
1301 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1302 extern bool intel_fbc_enabled(struct drm_device *dev);
1303 extern void intel_disable_fbc(struct drm_device *dev);
1304 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1305 extern void ironlake_init_pch_refclk(struct drm_device *dev);
1306 extern void ironlake_enable_rc6(struct drm_device *dev);
1307 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1308 extern void intel_detect_pch(struct drm_device *dev);
1309 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
1310
1311 /* overlay */
1312 #ifdef CONFIG_DEBUG_FS
1313 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1314 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1315
1316 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1317 extern void intel_display_print_error_state(struct seq_file *m,
1318 struct drm_device *dev,
1319 struct intel_display_error_state *error);
1320 #endif
1321
1322 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1323
1324 #define BEGIN_LP_RING(n) \
1325 intel_ring_begin(LP_RING(dev_priv), (n))
1326
1327 #define OUT_RING(x) \
1328 intel_ring_emit(LP_RING(dev_priv), x)
1329
1330 #define ADVANCE_LP_RING() \
1331 intel_ring_advance(LP_RING(dev_priv))
1332
1333 /**
1334 * Lock test for when it's just for synchronization of ring access.
1335 *
1336 * In that case, we don't need to do it when GEM is initialized as nobody else
1337 * has access to the ring.
1338 */
1339 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do { \
1340 if (LP_RING(dev->dev_private)->obj == NULL) \
1341 LOCK_TEST_WITH_RETURN(dev, file); \
1342 } while (0)
1343
1344 /* On SNB platform, before reading ring registers forcewake bit
1345 * must be set to prevent GT core from power down and stale values being
1346 * returned.
1347 */
1348 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1349 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1350 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1351
1352 /* We give fast paths for the really cool registers */
1353 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1354 (((dev_priv)->info->gen >= 6) && \
1355 ((reg) < 0x40000) && \
1356 ((reg) != FORCEWAKE))
1357
1358 #define __i915_read(x, y) \
1359 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1360
1361 __i915_read(8, b)
1362 __i915_read(16, w)
1363 __i915_read(32, l)
1364 __i915_read(64, q)
1365 #undef __i915_read
1366
1367 #define __i915_write(x, y) \
1368 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1369
1370 __i915_write(8, b)
1371 __i915_write(16, w)
1372 __i915_write(32, l)
1373 __i915_write(64, q)
1374 #undef __i915_write
1375
1376 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1377 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1378
1379 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1380 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1381 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1382 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1383
1384 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1385 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1386 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1387 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1388
1389 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1390 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1391
1392 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1393 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1394
1395
1396 #endif
Linux kernel - Deliverables
This page took 0.083795 seconds and 5 git commands to generate.