1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
= POWER_DOMAIN_TRANSCODER_A
+ 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
112 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct drm_i915_private
;
138 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
143 #define I915_NUM_PLLS 2
145 struct intel_dpll_hw_state
{
152 struct intel_shared_dpll
{
153 int refcount
; /* count of number of CRTCs sharing this PLL */
154 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on
; /* is the PLL actually active? Disabled during modeset */
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id
;
159 struct intel_dpll_hw_state hw_state
;
160 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
161 struct intel_shared_dpll
*pll
);
162 void (*enable
)(struct drm_i915_private
*dev_priv
,
163 struct intel_shared_dpll
*pll
);
164 void (*disable
)(struct drm_i915_private
*dev_priv
,
165 struct intel_shared_dpll
*pll
);
166 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
167 struct intel_shared_dpll
*pll
,
168 struct intel_dpll_hw_state
*hw_state
);
171 /* Used by dp and fdi links */
172 struct intel_link_m_n
{
180 void intel_link_compute_m_n(int bpp
, int nlanes
,
181 int pixel_clock
, int link_clock
,
182 struct intel_link_m_n
*m_n
);
184 struct intel_ddi_plls
{
190 /* Interface history:
193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
195 * 1.4: Fix cmdbuffer path, add heap destroy
196 * 1.5: Add vblank pipe configuration
197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
200 #define DRIVER_MAJOR 1
201 #define DRIVER_MINOR 6
202 #define DRIVER_PATCHLEVEL 0
204 #define WATCH_COHERENCY 0
205 #define WATCH_LISTS 0
208 #define I915_GEM_PHYS_CURSOR_0 1
209 #define I915_GEM_PHYS_CURSOR_1 2
210 #define I915_GEM_PHYS_OVERLAY_REGS 3
211 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
213 struct drm_i915_gem_phys_object
{
215 struct page
**page_list
;
216 drm_dma_handle_t
*handle
;
217 struct drm_i915_gem_object
*cur_obj
;
220 struct opregion_header
;
221 struct opregion_acpi
;
222 struct opregion_swsci
;
223 struct opregion_asle
;
225 struct intel_opregion
{
226 struct opregion_header __iomem
*header
;
227 struct opregion_acpi __iomem
*acpi
;
228 struct opregion_swsci __iomem
*swsci
;
229 struct opregion_asle __iomem
*asle
;
231 u32 __iomem
*lid_state
;
233 #define OPREGION_SIZE (8*1024)
235 struct intel_overlay
;
236 struct intel_overlay_error_state
;
238 struct drm_i915_master_private
{
239 drm_local_map_t
*sarea
;
240 struct _drm_i915_sarea
*sarea_priv
;
242 #define I915_FENCE_REG_NONE -1
243 #define I915_MAX_NUM_FENCES 32
244 /* 32 fences + sign bit for FENCE_REG_NONE */
245 #define I915_MAX_NUM_FENCE_BITS 6
247 struct drm_i915_fence_reg
{
248 struct list_head lru_list
;
249 struct drm_i915_gem_object
*obj
;
253 struct sdvo_device_mapping
{
262 struct intel_display_error_state
;
264 struct drm_i915_error_state
{
272 bool waiting
[I915_NUM_RINGS
];
273 u32 pipestat
[I915_MAX_PIPES
];
274 u32 tail
[I915_NUM_RINGS
];
275 u32 head
[I915_NUM_RINGS
];
276 u32 ctl
[I915_NUM_RINGS
];
277 u32 ipeir
[I915_NUM_RINGS
];
278 u32 ipehr
[I915_NUM_RINGS
];
279 u32 instdone
[I915_NUM_RINGS
];
280 u32 acthd
[I915_NUM_RINGS
];
281 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
282 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
283 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
284 /* our own tracking of ring head and tail */
285 u32 cpu_ring_head
[I915_NUM_RINGS
];
286 u32 cpu_ring_tail
[I915_NUM_RINGS
];
287 u32 error
; /* gen6+ */
288 u32 err_int
; /* gen7 */
289 u32 instpm
[I915_NUM_RINGS
];
290 u32 instps
[I915_NUM_RINGS
];
291 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
292 u32 seqno
[I915_NUM_RINGS
];
294 u32 fault_reg
[I915_NUM_RINGS
];
296 u32 faddr
[I915_NUM_RINGS
];
297 u64 fence
[I915_MAX_NUM_FENCES
];
299 struct drm_i915_error_ring
{
300 struct drm_i915_error_object
{
304 } *ringbuffer
, *batchbuffer
, *ctx
;
305 struct drm_i915_error_request
{
311 } ring
[I915_NUM_RINGS
];
312 struct drm_i915_error_buffer
{
319 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
326 } *active_bo
, *pinned_bo
;
327 u32 active_bo_count
, pinned_bo_count
;
328 struct intel_overlay_error_state
*overlay
;
329 struct intel_display_error_state
*display
;
332 struct intel_crtc_config
;
337 struct drm_i915_display_funcs
{
338 bool (*fbc_enabled
)(struct drm_device
*dev
);
339 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
340 void (*disable_fbc
)(struct drm_device
*dev
);
341 int (*get_display_clock_speed
)(struct drm_device
*dev
);
342 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
344 * find_dpll() - Find the best values for the PLL
345 * @limit: limits for the PLL
346 * @crtc: current CRTC
347 * @target: target frequency in kHz
348 * @refclk: reference clock frequency in kHz
349 * @match_clock: if provided, @best_clock P divider must
350 * match the P divider from @match_clock
351 * used for LVDS downclocking
352 * @best_clock: best PLL values found
354 * Returns true on success, false on failure.
356 bool (*find_dpll
)(const struct intel_limit
*limit
,
357 struct drm_crtc
*crtc
,
358 int target
, int refclk
,
359 struct dpll
*match_clock
,
360 struct dpll
*best_clock
);
361 void (*update_wm
)(struct drm_device
*dev
);
362 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
363 uint32_t sprite_width
, int pixel_size
,
365 void (*modeset_global_resources
)(struct drm_device
*dev
);
366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config
)(struct intel_crtc
*,
369 struct intel_crtc_config
*);
370 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
372 struct drm_framebuffer
*old_fb
);
373 void (*crtc_enable
)(struct drm_crtc
*crtc
);
374 void (*crtc_disable
)(struct drm_crtc
*crtc
);
375 void (*off
)(struct drm_crtc
*crtc
);
376 void (*write_eld
)(struct drm_connector
*connector
,
377 struct drm_crtc
*crtc
);
378 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
379 void (*init_clock_gating
)(struct drm_device
*dev
);
380 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
381 struct drm_framebuffer
*fb
,
382 struct drm_i915_gem_object
*obj
);
383 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
385 void (*hpd_irq_setup
)(struct drm_device
*dev
);
386 /* clock updates for mode set */
388 /* render clock increase/decrease */
389 /* display clock increase/decrease */
390 /* pll clock increase/decrease */
393 struct drm_i915_gt_funcs
{
394 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
395 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
398 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
399 func(is_mobile) sep \
402 func(is_i945gm) sep \
404 func(need_gfx_hws) sep \
406 func(is_pineview) sep \
407 func(is_broadwater) sep \
408 func(is_crestline) sep \
409 func(is_ivybridge) sep \
410 func(is_valleyview) sep \
411 func(is_haswell) sep \
412 func(has_force_wake) sep \
414 func(has_pipe_cxsr) sep \
415 func(has_hotplug) sep \
416 func(cursor_needs_physical) sep \
417 func(has_overlay) sep \
418 func(overlay_needs_physical) sep \
419 func(supports_tv) sep \
420 func(has_bsd_ring) sep \
421 func(has_blt_ring) sep \
422 func(has_vebox_ring) sep \
427 #define DEFINE_FLAG(name) u8 name:1
428 #define SEP_SEMICOLON ;
430 struct intel_device_info
{
431 u32 display_mmio_offset
;
434 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
440 enum i915_cache_level
{
443 I915_CACHE_LLC_MLC
, /* gen6+, in docs at least! */
446 typedef uint32_t gen6_gtt_pte_t
;
448 /* The Graphics Translation Table is the way in which GEN hardware translates a
449 * Graphics Virtual Address into a Physical Address. In addition to the normal
450 * collateral associated with any va->pa translations GEN hardware also has a
451 * portion of the GTT which can be mapped by the CPU and remain both coherent
452 * and correct (in cases like swizzling). That region is referred to as GMADR in
456 unsigned long start
; /* Start offset of used GTT */
457 size_t total
; /* Total size GTT can map */
458 size_t stolen_size
; /* Total size of stolen memory */
460 unsigned long mappable_end
; /* End offset that we can CPU map */
461 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
462 phys_addr_t mappable_base
; /* PA of our GMADR */
464 /** "Graphics Stolen Memory" holds the global PTEs */
476 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
477 size_t *stolen
, phys_addr_t
*mappable_base
,
478 unsigned long *mappable_end
);
479 void (*gtt_remove
)(struct drm_device
*dev
);
480 void (*gtt_clear_range
)(struct drm_device
*dev
,
481 unsigned int first_entry
,
482 unsigned int num_entries
);
483 void (*gtt_insert_entries
)(struct drm_device
*dev
,
485 unsigned int pg_start
,
486 enum i915_cache_level cache_level
);
487 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
488 enum i915_cache_level level
);
490 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
492 struct i915_hw_ppgtt
{
493 struct drm_device
*dev
;
494 unsigned num_pd_entries
;
495 struct page
**pt_pages
;
497 dma_addr_t
*pt_dma_addr
;
499 /* pte functions, mirroring the interface of the global gtt. */
500 void (*clear_range
)(struct i915_hw_ppgtt
*ppgtt
,
501 unsigned int first_entry
,
502 unsigned int num_entries
);
503 void (*insert_entries
)(struct i915_hw_ppgtt
*ppgtt
,
505 unsigned int pg_start
,
506 enum i915_cache_level cache_level
);
507 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
508 enum i915_cache_level level
);
509 int (*enable
)(struct drm_device
*dev
);
510 void (*cleanup
)(struct i915_hw_ppgtt
*ppgtt
);
513 struct i915_ctx_hang_stats
{
514 /* This context had batch pending when hang was declared */
515 unsigned batch_pending
;
517 /* This context had batch active when hang was declared */
518 unsigned batch_active
;
521 /* This must match up with the value previously used for execbuf2.rsvd1. */
522 #define DEFAULT_CONTEXT_ID 0
523 struct i915_hw_context
{
527 struct drm_i915_file_private
*file_priv
;
528 struct intel_ring_buffer
*ring
;
529 struct drm_i915_gem_object
*obj
;
530 struct i915_ctx_hang_stats hang_stats
;
539 struct drm_mm_node
*compressed_fb
;
540 struct drm_mm_node
*compressed_llb
;
542 struct intel_fbc_work
{
543 struct delayed_work work
;
544 struct drm_crtc
*crtc
;
545 struct drm_framebuffer
*fb
;
550 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
551 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
552 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
553 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
554 FBC_BAD_PLANE
, /* fbc not supported on plane */
555 FBC_NOT_TILED
, /* buffer not tiled */
556 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
558 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
564 PCH_NONE
= 0, /* No PCH present */
565 PCH_IBX
, /* Ibexpeak PCH */
566 PCH_CPT
, /* Cougarpoint PCH */
567 PCH_LPT
, /* Lynxpoint PCH */
571 enum intel_sbi_destination
{
576 #define QUIRK_PIPEA_FORCE (1<<0)
577 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
578 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
581 struct intel_fbc_work
;
584 struct i2c_adapter adapter
;
588 struct i2c_algo_bit_data bit_algo
;
589 struct drm_i915_private
*dev_priv
;
592 struct i915_suspend_saved_registers
{
613 u32 saveTRANS_HTOTAL_A
;
614 u32 saveTRANS_HBLANK_A
;
615 u32 saveTRANS_HSYNC_A
;
616 u32 saveTRANS_VTOTAL_A
;
617 u32 saveTRANS_VBLANK_A
;
618 u32 saveTRANS_VSYNC_A
;
626 u32 savePFIT_PGM_RATIOS
;
627 u32 saveBLC_HIST_CTL
;
629 u32 saveBLC_PWM_CTL2
;
630 u32 saveBLC_CPU_PWM_CTL
;
631 u32 saveBLC_CPU_PWM_CTL2
;
644 u32 saveTRANS_HTOTAL_B
;
645 u32 saveTRANS_HBLANK_B
;
646 u32 saveTRANS_HSYNC_B
;
647 u32 saveTRANS_VTOTAL_B
;
648 u32 saveTRANS_VBLANK_B
;
649 u32 saveTRANS_VSYNC_B
;
663 u32 savePP_ON_DELAYS
;
664 u32 savePP_OFF_DELAYS
;
672 u32 savePFIT_CONTROL
;
673 u32 save_palette_a
[256];
674 u32 save_palette_b
[256];
675 u32 saveDPFC_CB_BASE
;
676 u32 saveFBC_CFB_BASE
;
679 u32 saveFBC_CONTROL2
;
689 u32 saveCACHE_MODE_0
;
690 u32 saveMI_ARB_STATE
;
701 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
712 u32 savePIPEA_GMCH_DATA_M
;
713 u32 savePIPEB_GMCH_DATA_M
;
714 u32 savePIPEA_GMCH_DATA_N
;
715 u32 savePIPEB_GMCH_DATA_N
;
716 u32 savePIPEA_DP_LINK_M
;
717 u32 savePIPEB_DP_LINK_M
;
718 u32 savePIPEA_DP_LINK_N
;
719 u32 savePIPEB_DP_LINK_N
;
730 u32 savePCH_DREF_CONTROL
;
731 u32 saveDISP_ARB_CTL
;
732 u32 savePIPEA_DATA_M1
;
733 u32 savePIPEA_DATA_N1
;
734 u32 savePIPEA_LINK_M1
;
735 u32 savePIPEA_LINK_N1
;
736 u32 savePIPEB_DATA_M1
;
737 u32 savePIPEB_DATA_N1
;
738 u32 savePIPEB_LINK_M1
;
739 u32 savePIPEB_LINK_N1
;
740 u32 saveMCHBAR_RENDER_STANDBY
;
741 u32 savePCH_PORT_HOTPLUG
;
744 struct intel_gen6_power_mgmt
{
745 struct work_struct work
;
746 struct delayed_work vlv_work
;
748 /* lock - irqsave spinlock that protectects the work_struct and
752 /* The below variables an all the rps hw state are protected by
753 * dev->struct mutext. */
760 struct delayed_work delayed_resume_work
;
763 * Protects RPS/RC6 register access and PCU communication.
764 * Must be taken after struct_mutex if nested.
766 struct mutex hw_lock
;
769 /* defined intel_pm.c */
770 extern spinlock_t mchdev_lock
;
772 struct intel_ilk_power_mgmt
{
780 unsigned long last_time1
;
781 unsigned long chipset_power
;
783 struct timespec last_time2
;
784 unsigned long gfx_power
;
790 struct drm_i915_gem_object
*pwrctx
;
791 struct drm_i915_gem_object
*renderctx
;
794 /* Power well structure for haswell */
795 struct i915_power_well
{
796 struct drm_device
*device
;
798 /* power well enable/disable usage count */
803 struct i915_dri1_state
{
804 unsigned allow_batchbuffer
: 1;
805 u32 __iomem
*gfx_hws_cpu_addr
;
816 struct intel_l3_parity
{
818 struct work_struct error_work
;
822 /** Memory allocator for GTT stolen memory */
823 struct drm_mm stolen
;
824 /** Memory allocator for GTT */
825 struct drm_mm gtt_space
;
826 /** List of all objects in gtt_space. Used to restore gtt
827 * mappings on resume */
828 struct list_head bound_list
;
830 * List of objects which are not bound to the GTT (thus
831 * are idle and not used by the GPU) but still have
832 * (presumably uncached) pages still attached.
834 struct list_head unbound_list
;
836 /** Usable portion of the GTT for GEM */
837 unsigned long stolen_base
; /* limited to low memory (32-bit) */
839 /** PPGTT used for aliasing the PPGTT with the GTT */
840 struct i915_hw_ppgtt
*aliasing_ppgtt
;
842 struct shrinker inactive_shrinker
;
843 bool shrinker_no_lock_stealing
;
846 * List of objects currently involved in rendering.
848 * Includes buffers having the contents of their GPU caches
849 * flushed, not necessarily primitives. last_rendering_seqno
850 * represents when the rendering involved will be completed.
852 * A reference is held on the buffer while on this list.
854 struct list_head active_list
;
857 * LRU list of objects which are not in the ringbuffer and
858 * are ready to unbind, but are still in the GTT.
860 * last_rendering_seqno is 0 while an object is in this list.
862 * A reference is not held on the buffer while on this list,
863 * as merely being GTT-bound shouldn't prevent its being
864 * freed, and we'll pull it off the list in the free path.
866 struct list_head inactive_list
;
868 /** LRU list of objects with fence regs on them. */
869 struct list_head fence_list
;
872 * We leave the user IRQ off as much as possible,
873 * but this means that requests will finish and never
874 * be retired once the system goes idle. Set a timer to
875 * fire periodically while the ring is running. When it
876 * fires, go retire requests.
878 struct delayed_work retire_work
;
881 * Are we in a non-interruptible section of code like
887 * Flag if the X Server, and thus DRM, is not currently in
888 * control of the device.
890 * This is set between LeaveVT and EnterVT. It needs to be
891 * replaced with a semaphore. It also needs to be
892 * transitioned away from for kernel modesetting.
896 /** Bit 6 swizzling required for X tiling */
897 uint32_t bit_6_swizzle_x
;
898 /** Bit 6 swizzling required for Y tiling */
899 uint32_t bit_6_swizzle_y
;
901 /* storage for physical objects */
902 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
904 /* accounting, useful for userland debugging */
905 size_t object_memory
;
909 struct drm_i915_error_state_buf
{
918 struct i915_gpu_error
{
919 /* For hangcheck timer */
920 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
921 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
922 struct timer_list hangcheck_timer
;
924 /* For reset and error_state handling. */
926 /* Protected by the above dev->gpu_error.lock. */
927 struct drm_i915_error_state
*first_error
;
928 struct work_struct work
;
930 unsigned long last_reset
;
933 * State variable and reset counter controlling the reset flow
935 * Upper bits are for the reset counter. This counter is used by the
936 * wait_seqno code to race-free noticed that a reset event happened and
937 * that it needs to restart the entire ioctl (since most likely the
938 * seqno it waited for won't ever signal anytime soon).
940 * This is important for lock-free wait paths, where no contended lock
941 * naturally enforces the correct ordering between the bail-out of the
942 * waiter and the gpu reset work code.
944 * Lowest bit controls the reset state machine: Set means a reset is in
945 * progress. This state will (presuming we don't have any bugs) decay
946 * into either unset (successful reset) or the special WEDGED value (hw
947 * terminally sour). All waiters on the reset_queue will be woken when
950 atomic_t reset_counter
;
953 * Special values/flags for reset_counter
955 * Note that the code relies on
956 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
959 #define I915_RESET_IN_PROGRESS_FLAG 1
960 #define I915_WEDGED 0xffffffff
963 * Waitqueue to signal when the reset has completed. Used by clients
964 * that wait for dev_priv->mm.wedged to settle.
966 wait_queue_head_t reset_queue
;
968 /* For gpu hang simulation. */
969 unsigned int stop_rings
;
972 enum modeset_restore
{
978 struct intel_vbt_data
{
979 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
980 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
983 unsigned int int_tv_support
:1;
984 unsigned int lvds_dither
:1;
985 unsigned int lvds_vbt
:1;
986 unsigned int int_crt_support
:1;
987 unsigned int lvds_use_ssc
:1;
988 unsigned int display_clock_mode
:1;
989 unsigned int fdi_rx_polarity_inverted
:1;
991 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
998 bool edp_initialized
;
1001 struct edp_power_seq edp_pps
;
1006 struct child_device_config
*child_dev
;
1009 typedef struct drm_i915_private
{
1010 struct drm_device
*dev
;
1011 struct kmem_cache
*slab
;
1013 const struct intel_device_info
*info
;
1015 int relative_constants_mode
;
1019 struct drm_i915_gt_funcs gt
;
1020 /** gt_fifo_count and the subsequent register write are synchronized
1021 * with dev->struct_mutex. */
1022 unsigned gt_fifo_count
;
1023 /** forcewake_count is protected by gt_lock */
1024 unsigned forcewake_count
;
1025 /** gt_lock is also taken in irq contexts. */
1028 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1031 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1032 * controller on different i2c buses. */
1033 struct mutex gmbus_mutex
;
1036 * Base address of the gmbus and gpio block.
1038 uint32_t gpio_mmio_base
;
1040 wait_queue_head_t gmbus_wait_queue
;
1042 struct pci_dev
*bridge_dev
;
1043 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1044 uint32_t last_seqno
, next_seqno
;
1046 drm_dma_handle_t
*status_page_dmah
;
1047 struct resource mch_res
;
1049 atomic_t irq_received
;
1051 /* protects the irq masks */
1052 spinlock_t irq_lock
;
1054 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1055 struct pm_qos_request pm_qos
;
1057 /* DPIO indirect register protection */
1058 struct mutex dpio_lock
;
1060 /** Cached value of IMR to avoid reads in updating the bitfield */
1064 struct work_struct hotplug_work
;
1065 bool enable_hotplug_processing
;
1067 unsigned long hpd_last_jiffies
;
1072 HPD_MARK_DISABLED
= 2
1074 } hpd_stats
[HPD_NUM_PINS
];
1076 struct timer_list hotplug_reenable_timer
;
1080 struct i915_fbc fbc
;
1081 struct intel_opregion opregion
;
1082 struct intel_vbt_data vbt
;
1085 struct intel_overlay
*overlay
;
1086 unsigned int sprite_scaling_enabled
;
1092 spinlock_t lock
; /* bl registers and the above bl fields */
1093 struct backlight_device
*device
;
1097 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1098 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1099 bool no_aux_handshake
;
1101 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1102 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1103 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1105 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1107 struct workqueue_struct
*wq
;
1109 /* Display functions */
1110 struct drm_i915_display_funcs display
;
1112 /* PCH chipset type */
1113 enum intel_pch pch_type
;
1114 unsigned short pch_id
;
1116 unsigned long quirks
;
1118 enum modeset_restore modeset_restore
;
1119 struct mutex modeset_restore_lock
;
1121 struct i915_gtt gtt
;
1123 struct i915_gem_mm mm
;
1125 /* Kernel Modesetting */
1127 struct sdvo_device_mapping sdvo_mappings
[2];
1129 struct drm_crtc
*plane_to_crtc_mapping
[3];
1130 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1131 wait_queue_head_t pending_flip_queue
;
1133 int num_shared_dpll
;
1134 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1135 struct intel_ddi_plls ddi_plls
;
1137 /* Reclocking support */
1138 bool render_reclock_avail
;
1139 bool lvds_downclock_avail
;
1140 /* indicates the reduced downclock for LVDS*/
1144 bool mchbar_need_disable
;
1146 struct intel_l3_parity l3_parity
;
1148 /* gen6+ rps state */
1149 struct intel_gen6_power_mgmt rps
;
1151 /* ilk-only ips/rps state. Everything in here is protected by the global
1152 * mchdev_lock in intel_pm.c */
1153 struct intel_ilk_power_mgmt ips
;
1155 /* Haswell power well */
1156 struct i915_power_well power_well
;
1158 struct i915_gpu_error gpu_error
;
1160 struct drm_i915_gem_object
*vlv_pctx
;
1162 /* list of fbdev register on this device */
1163 struct intel_fbdev
*fbdev
;
1166 * The console may be contended at resume, but we don't
1167 * want it to block on it.
1169 struct work_struct console_resume_work
;
1171 struct drm_property
*broadcast_rgb_property
;
1172 struct drm_property
*force_audio_property
;
1174 bool hw_contexts_disabled
;
1175 uint32_t hw_context_size
;
1179 struct i915_suspend_saved_registers regfile
;
1181 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1183 struct i915_dri1_state dri1
;
1184 } drm_i915_private_t
;
1186 /* Iterate over initialised rings */
1187 #define for_each_ring(ring__, dev_priv__, i__) \
1188 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1189 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1191 enum hdmi_force_audio
{
1192 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1193 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1194 HDMI_AUDIO_AUTO
, /* trust EDID */
1195 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1198 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1200 struct drm_i915_gem_object_ops
{
1201 /* Interface between the GEM object and its backing storage.
1202 * get_pages() is called once prior to the use of the associated set
1203 * of pages before to binding them into the GTT, and put_pages() is
1204 * called after we no longer need them. As we expect there to be
1205 * associated cost with migrating pages between the backing storage
1206 * and making them available for the GPU (e.g. clflush), we may hold
1207 * onto the pages after they are no longer referenced by the GPU
1208 * in case they may be used again shortly (for example migrating the
1209 * pages to a different memory domain within the GTT). put_pages()
1210 * will therefore most likely be called when the object itself is
1211 * being released or under memory pressure (where we attempt to
1212 * reap pages for the shrinker).
1214 int (*get_pages
)(struct drm_i915_gem_object
*);
1215 void (*put_pages
)(struct drm_i915_gem_object
*);
1218 struct drm_i915_gem_object
{
1219 struct drm_gem_object base
;
1221 const struct drm_i915_gem_object_ops
*ops
;
1223 /** Current space allocated to this object in the GTT, if any. */
1224 struct drm_mm_node
*gtt_space
;
1225 /** Stolen memory for this object, instead of being backed by shmem. */
1226 struct drm_mm_node
*stolen
;
1227 struct list_head global_list
;
1229 /** This object's place on the active/inactive lists */
1230 struct list_head ring_list
;
1231 struct list_head mm_list
;
1232 /** This object's place in the batchbuffer or on the eviction list */
1233 struct list_head exec_list
;
1236 * This is set if the object is on the active lists (has pending
1237 * rendering and so a non-zero seqno), and is not set if it i s on
1238 * inactive (ready to be unbound) list.
1240 unsigned int active
:1;
1243 * This is set if the object has been written to since last bound
1246 unsigned int dirty
:1;
1249 * Fence register bits (if any) for this object. Will be set
1250 * as needed when mapped into the GTT.
1251 * Protected by dev->struct_mutex.
1253 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1256 * Advice: are the backing pages purgeable?
1258 unsigned int madv
:2;
1261 * Current tiling mode for the object.
1263 unsigned int tiling_mode
:2;
1265 * Whether the tiling parameters for the currently associated fence
1266 * register have changed. Note that for the purposes of tracking
1267 * tiling changes we also treat the unfenced register, the register
1268 * slot that the object occupies whilst it executes a fenced
1269 * command (such as BLT on gen2/3), as a "fence".
1271 unsigned int fence_dirty
:1;
1273 /** How many users have pinned this object in GTT space. The following
1274 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1275 * (via user_pin_count), execbuffer (objects are not allowed multiple
1276 * times for the same batchbuffer), and the framebuffer code. When
1277 * switching/pageflipping, the framebuffer code has at most two buffers
1280 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1281 * bits with absolutely no headroom. So use 4 bits. */
1282 unsigned int pin_count
:4;
1283 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1286 * Is the object at the current location in the gtt mappable and
1287 * fenceable? Used to avoid costly recalculations.
1289 unsigned int map_and_fenceable
:1;
1292 * Whether the current gtt mapping needs to be mappable (and isn't just
1293 * mappable by accident). Track pin and fault separate for a more
1294 * accurate mappable working set.
1296 unsigned int fault_mappable
:1;
1297 unsigned int pin_mappable
:1;
1300 * Is the GPU currently using a fence to access this buffer,
1302 unsigned int pending_fenced_gpu_access
:1;
1303 unsigned int fenced_gpu_access
:1;
1305 unsigned int cache_level
:2;
1307 unsigned int has_aliasing_ppgtt_mapping
:1;
1308 unsigned int has_global_gtt_mapping
:1;
1309 unsigned int has_dma_mapping
:1;
1311 struct sg_table
*pages
;
1312 int pages_pin_count
;
1314 /* prime dma-buf support */
1315 void *dma_buf_vmapping
;
1319 * Used for performing relocations during execbuffer insertion.
1321 struct hlist_node exec_node
;
1322 unsigned long exec_handle
;
1323 struct drm_i915_gem_exec_object2
*exec_entry
;
1326 * Current offset of the object in GTT space.
1328 * This is the same as gtt_space->start
1330 uint32_t gtt_offset
;
1332 struct intel_ring_buffer
*ring
;
1334 /** Breadcrumb of last rendering to the buffer. */
1335 uint32_t last_read_seqno
;
1336 uint32_t last_write_seqno
;
1337 /** Breadcrumb of last fenced GPU access to the buffer. */
1338 uint32_t last_fenced_seqno
;
1340 /** Current tiling stride for the object, if it's tiled. */
1343 /** Record of address bit 17 of each page at last unbind. */
1344 unsigned long *bit_17
;
1346 /** User space pin count and filp owning the pin */
1347 uint32_t user_pin_count
;
1348 struct drm_file
*pin_filp
;
1350 /** for phy allocated objects */
1351 struct drm_i915_gem_phys_object
*phys_obj
;
1353 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1355 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1358 * Request queue structure.
1360 * The request queue allows us to note sequence numbers that have been emitted
1361 * and may be associated with active buffers to be retired.
1363 * By keeping this list, we can avoid having to do questionable
1364 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1365 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1367 struct drm_i915_gem_request
{
1368 /** On Which ring this request was generated */
1369 struct intel_ring_buffer
*ring
;
1371 /** GEM sequence number associated with this request. */
1374 /** Position in the ringbuffer of the start of the request */
1377 /** Position in the ringbuffer of the end of the request */
1380 /** Context related to this request */
1381 struct i915_hw_context
*ctx
;
1383 /** Batch buffer related to this request if any */
1384 struct drm_i915_gem_object
*batch_obj
;
1386 /** Time at which this request was emitted, in jiffies. */
1387 unsigned long emitted_jiffies
;
1389 /** global list entry for this request */
1390 struct list_head list
;
1392 struct drm_i915_file_private
*file_priv
;
1393 /** file_priv list entry for this request */
1394 struct list_head client_list
;
1397 struct drm_i915_file_private
{
1400 struct list_head request_list
;
1402 struct idr context_idr
;
1404 struct i915_ctx_hang_stats hang_stats
;
1407 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1409 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1410 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1411 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1412 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1413 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1414 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1415 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1416 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1417 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1418 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1419 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1420 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1421 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1422 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1423 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1424 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1425 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1426 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1427 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1428 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1429 (dev)->pci_device == 0x0152 || \
1430 (dev)->pci_device == 0x015a)
1431 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1432 (dev)->pci_device == 0x0106 || \
1433 (dev)->pci_device == 0x010A)
1434 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1435 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1436 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1437 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1438 ((dev)->pci_device & 0xFF00) == 0x0A00)
1441 * The genX designation typically refers to the render engine, so render
1442 * capability related checks should use IS_GEN, while display and other checks
1443 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1446 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1447 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1448 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1449 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1450 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1451 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1453 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1454 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1455 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1456 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1457 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1459 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1460 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1462 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1463 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1465 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1466 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1468 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1469 * rows, which changed the alignment requirements and fence programming.
1471 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1473 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1474 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1475 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1476 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1477 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1478 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1479 /* dsparb controlled by hw only */
1480 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1482 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1483 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1484 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1486 #define HAS_IPS(dev) (IS_ULT(dev))
1488 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1490 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1491 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1492 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1494 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1495 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1496 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1497 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1498 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1499 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1501 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1502 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1503 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1504 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1505 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1506 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1508 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1510 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1512 #define GT_FREQUENCY_MULTIPLIER 50
1514 #include "i915_trace.h"
1517 * RC6 is a special power stage which allows the GPU to enter an very
1518 * low-voltage mode when idle, using down to 0V while at this stage. This
1519 * stage is entered automatically when the GPU is idle when RC6 support is
1520 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1522 * There are different RC6 modes available in Intel GPU, which differentiate
1523 * among each other with the latency required to enter and leave RC6 and
1524 * voltage consumed by the GPU in different states.
1526 * The combination of the following flags define which states GPU is allowed
1527 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1528 * RC6pp is deepest RC6. Their support by hardware varies according to the
1529 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1530 * which brings the most power savings; deeper states save more power, but
1531 * require higher latency to switch to and wake up.
1533 #define INTEL_RC6_ENABLE (1<<0)
1534 #define INTEL_RC6p_ENABLE (1<<1)
1535 #define INTEL_RC6pp_ENABLE (1<<2)
1537 extern struct drm_ioctl_desc i915_ioctls
[];
1538 extern int i915_max_ioctl
;
1539 extern unsigned int i915_fbpercrtc __always_unused
;
1540 extern int i915_panel_ignore_lid __read_mostly
;
1541 extern unsigned int i915_powersave __read_mostly
;
1542 extern int i915_semaphores __read_mostly
;
1543 extern unsigned int i915_lvds_downclock __read_mostly
;
1544 extern int i915_lvds_channel_mode __read_mostly
;
1545 extern int i915_panel_use_ssc __read_mostly
;
1546 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1547 extern int i915_enable_rc6 __read_mostly
;
1548 extern int i915_enable_fbc __read_mostly
;
1549 extern bool i915_enable_hangcheck __read_mostly
;
1550 extern int i915_enable_ppgtt __read_mostly
;
1551 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1552 extern int i915_disable_power_well __read_mostly
;
1553 extern int i915_enable_ips __read_mostly
;
1555 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1556 extern int i915_resume(struct drm_device
*dev
);
1557 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1558 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1561 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1562 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1563 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1564 extern int i915_driver_unload(struct drm_device
*);
1565 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1566 extern void i915_driver_lastclose(struct drm_device
* dev
);
1567 extern void i915_driver_preclose(struct drm_device
*dev
,
1568 struct drm_file
*file_priv
);
1569 extern void i915_driver_postclose(struct drm_device
*dev
,
1570 struct drm_file
*file_priv
);
1571 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1572 #ifdef CONFIG_COMPAT
1573 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1576 extern int i915_emit_box(struct drm_device
*dev
,
1577 struct drm_clip_rect
*box
,
1579 extern int intel_gpu_reset(struct drm_device
*dev
);
1580 extern int i915_reset(struct drm_device
*dev
);
1581 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1582 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1583 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1584 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1586 extern void intel_console_resume(struct work_struct
*work
);
1589 void i915_hangcheck_elapsed(unsigned long data
);
1590 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1592 extern void intel_irq_init(struct drm_device
*dev
);
1593 extern void intel_hpd_init(struct drm_device
*dev
);
1594 extern void intel_gt_init(struct drm_device
*dev
);
1595 extern void intel_gt_reset(struct drm_device
*dev
);
1597 void i915_error_state_free(struct kref
*error_ref
);
1600 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1603 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1605 #ifdef CONFIG_DEBUG_FS
1606 extern void i915_destroy_error_state(struct drm_device
*dev
);
1608 #define i915_destroy_error_state(x)
1613 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1614 struct drm_file
*file_priv
);
1615 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1616 struct drm_file
*file_priv
);
1617 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1618 struct drm_file
*file_priv
);
1619 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1620 struct drm_file
*file_priv
);
1621 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1622 struct drm_file
*file_priv
);
1623 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1624 struct drm_file
*file_priv
);
1625 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1626 struct drm_file
*file_priv
);
1627 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1628 struct drm_file
*file_priv
);
1629 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1630 struct drm_file
*file_priv
);
1631 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1632 struct drm_file
*file_priv
);
1633 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1634 struct drm_file
*file_priv
);
1635 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1636 struct drm_file
*file_priv
);
1637 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1638 struct drm_file
*file_priv
);
1639 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1640 struct drm_file
*file
);
1641 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1642 struct drm_file
*file
);
1643 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1644 struct drm_file
*file_priv
);
1645 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1646 struct drm_file
*file_priv
);
1647 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1648 struct drm_file
*file_priv
);
1649 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1650 struct drm_file
*file_priv
);
1651 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1652 struct drm_file
*file_priv
);
1653 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1654 struct drm_file
*file_priv
);
1655 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1656 struct drm_file
*file_priv
);
1657 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1658 struct drm_file
*file_priv
);
1659 void i915_gem_load(struct drm_device
*dev
);
1660 void *i915_gem_object_alloc(struct drm_device
*dev
);
1661 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1662 int i915_gem_init_object(struct drm_gem_object
*obj
);
1663 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1664 const struct drm_i915_gem_object_ops
*ops
);
1665 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1667 void i915_gem_free_object(struct drm_gem_object
*obj
);
1669 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1671 bool map_and_fenceable
,
1673 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1674 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1675 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1676 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1677 void i915_gem_lastclose(struct drm_device
*dev
);
1679 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1680 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1682 struct sg_page_iter sg_iter
;
1684 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1685 return sg_page_iter_page(&sg_iter
);
1689 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1691 BUG_ON(obj
->pages
== NULL
);
1692 obj
->pages_pin_count
++;
1694 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1696 BUG_ON(obj
->pages_pin_count
== 0);
1697 obj
->pages_pin_count
--;
1700 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1701 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1702 struct intel_ring_buffer
*to
);
1703 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1704 struct intel_ring_buffer
*ring
);
1706 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1707 struct drm_device
*dev
,
1708 struct drm_mode_create_dumb
*args
);
1709 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1710 uint32_t handle
, uint64_t *offset
);
1711 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1714 * Returns true if seq1 is later than seq2.
1717 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1719 return (int32_t)(seq1
- seq2
) >= 0;
1722 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1723 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1724 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1725 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1728 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1730 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1731 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1732 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1739 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1741 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1742 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1743 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
1744 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1748 void i915_gem_retire_requests(struct drm_device
*dev
);
1749 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1750 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1751 bool interruptible
);
1752 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1754 return unlikely(atomic_read(&error
->reset_counter
)
1755 & I915_RESET_IN_PROGRESS_FLAG
);
1758 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1760 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1763 void i915_gem_reset(struct drm_device
*dev
);
1764 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1765 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1766 uint32_t read_domains
,
1767 uint32_t write_domain
);
1768 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1769 int __must_check
i915_gem_init(struct drm_device
*dev
);
1770 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1771 void i915_gem_l3_remap(struct drm_device
*dev
);
1772 void i915_gem_init_swizzling(struct drm_device
*dev
);
1773 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1774 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1775 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1776 int __i915_add_request(struct intel_ring_buffer
*ring
,
1777 struct drm_file
*file
,
1778 struct drm_i915_gem_object
*batch_obj
,
1780 #define i915_add_request(ring, seqno) \
1781 __i915_add_request(ring, NULL, NULL, seqno)
1782 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1784 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1786 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1789 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1791 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1793 struct intel_ring_buffer
*pipelined
);
1794 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1795 struct drm_i915_gem_object
*obj
,
1798 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1799 struct drm_i915_gem_object
*obj
);
1800 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1801 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1804 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
1806 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1807 int tiling_mode
, bool fenced
);
1809 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1810 enum i915_cache_level cache_level
);
1812 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1813 struct dma_buf
*dma_buf
);
1815 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1816 struct drm_gem_object
*gem_obj
, int flags
);
1818 /* i915_gem_context.c */
1819 void i915_gem_context_init(struct drm_device
*dev
);
1820 void i915_gem_context_fini(struct drm_device
*dev
);
1821 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1822 int i915_switch_context(struct intel_ring_buffer
*ring
,
1823 struct drm_file
*file
, int to_id
);
1824 void i915_gem_context_free(struct kref
*ctx_ref
);
1825 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
1827 kref_get(&ctx
->ref
);
1830 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
1832 kref_put(&ctx
->ref
, i915_gem_context_free
);
1835 struct i915_ctx_hang_stats
* __must_check
1836 i915_gem_context_get_hang_stats(struct intel_ring_buffer
*ring
,
1837 struct drm_file
*file
,
1839 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1840 struct drm_file
*file
);
1841 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1842 struct drm_file
*file
);
1844 /* i915_gem_gtt.c */
1845 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1846 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1847 struct drm_i915_gem_object
*obj
,
1848 enum i915_cache_level cache_level
);
1849 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1850 struct drm_i915_gem_object
*obj
);
1852 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1853 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1854 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1855 enum i915_cache_level cache_level
);
1856 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1857 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1858 void i915_gem_init_global_gtt(struct drm_device
*dev
);
1859 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
1860 unsigned long mappable_end
, unsigned long end
);
1861 int i915_gem_gtt_init(struct drm_device
*dev
);
1862 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
1864 if (INTEL_INFO(dev
)->gen
< 6)
1865 intel_gtt_chipset_flush();
1869 /* i915_gem_evict.c */
1870 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1872 unsigned cache_level
,
1875 int i915_gem_evict_everything(struct drm_device
*dev
);
1877 /* i915_gem_stolen.c */
1878 int i915_gem_init_stolen(struct drm_device
*dev
);
1879 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
1880 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
1881 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1882 struct drm_i915_gem_object
*
1883 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
1884 struct drm_i915_gem_object
*
1885 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
1889 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
1891 /* i915_gem_tiling.c */
1892 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
1894 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
1896 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
1897 obj
->tiling_mode
!= I915_TILING_NONE
;
1900 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1901 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1902 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1904 /* i915_gem_debug.c */
1905 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1906 const char *where
, uint32_t mark
);
1908 int i915_verify_lists(struct drm_device
*dev
);
1910 #define i915_verify_lists(dev) 0
1912 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1914 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1915 const char *where
, uint32_t mark
);
1917 /* i915_debugfs.c */
1918 int i915_debugfs_init(struct drm_minor
*minor
);
1919 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1921 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
1923 /* i915_suspend.c */
1924 extern int i915_save_state(struct drm_device
*dev
);
1925 extern int i915_restore_state(struct drm_device
*dev
);
1928 void i915_save_display_reg(struct drm_device
*dev
);
1929 void i915_restore_display_reg(struct drm_device
*dev
);
1932 void i915_setup_sysfs(struct drm_device
*dev_priv
);
1933 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
1936 extern int intel_setup_gmbus(struct drm_device
*dev
);
1937 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1938 static inline bool intel_gmbus_is_port_valid(unsigned port
)
1940 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
1943 extern struct i2c_adapter
*intel_gmbus_get_adapter(
1944 struct drm_i915_private
*dev_priv
, unsigned port
);
1945 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1946 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1947 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1949 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1951 extern void intel_i2c_reset(struct drm_device
*dev
);
1953 /* intel_opregion.c */
1954 extern int intel_opregion_setup(struct drm_device
*dev
);
1956 extern void intel_opregion_init(struct drm_device
*dev
);
1957 extern void intel_opregion_fini(struct drm_device
*dev
);
1958 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1960 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1961 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1962 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1967 extern void intel_register_dsm_handler(void);
1968 extern void intel_unregister_dsm_handler(void);
1970 static inline void intel_register_dsm_handler(void) { return; }
1971 static inline void intel_unregister_dsm_handler(void) { return; }
1972 #endif /* CONFIG_ACPI */
1975 extern void intel_modeset_init_hw(struct drm_device
*dev
);
1976 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
1977 extern void intel_modeset_init(struct drm_device
*dev
);
1978 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1979 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1980 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1981 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
1982 bool force_restore
);
1983 extern void i915_redisable_vga(struct drm_device
*dev
);
1984 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1985 extern void intel_disable_fbc(struct drm_device
*dev
);
1986 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1987 extern void intel_init_pch_refclk(struct drm_device
*dev
);
1988 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1989 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
1990 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
1991 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
1992 extern void intel_detect_pch(struct drm_device
*dev
);
1993 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1994 extern int intel_enable_rc6(const struct drm_device
*dev
);
1996 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
1997 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
1998 struct drm_file
*file
);
2001 #ifdef CONFIG_DEBUG_FS
2002 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2003 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2004 struct intel_overlay_error_state
*error
);
2006 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2007 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2008 struct drm_device
*dev
,
2009 struct intel_display_error_state
*error
);
2012 /* On SNB platform, before reading ring registers forcewake bit
2013 * must be set to prevent GT core from power down and stale values being
2016 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
2017 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
2018 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
2020 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2021 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2023 /* intel_sideband.c */
2024 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2025 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2026 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2027 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, int reg
);
2028 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, int reg
, u32 val
);
2029 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2030 enum intel_sbi_destination destination
);
2031 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2032 enum intel_sbi_destination destination
);
2034 int vlv_gpu_freq(int ddr_freq
, int val
);
2035 int vlv_freq_opcode(int ddr_freq
, int val
);
2037 #define __i915_read(x, y) \
2038 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
2046 #define __i915_write(x, y) \
2047 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
2055 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
2056 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
2058 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
2059 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
2060 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
2061 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
2063 #define I915_READ(reg) i915_read32(dev_priv, (reg))
2064 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
2065 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
2066 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
2068 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
2069 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
2071 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2072 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2074 /* "Broadcast RGB" property */
2075 #define INTEL_BROADCAST_RGB_AUTO 0
2076 #define INTEL_BROADCAST_RGB_FULL 1
2077 #define INTEL_BROADCAST_RGB_LIMITED 2
2079 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2081 if (HAS_PCH_SPLIT(dev
))
2082 return CPU_VGACNTRL
;
2083 else if (IS_VALLEYVIEW(dev
))
2084 return VLV_VGACNTRL
;
2089 static inline void __user
*to_user_ptr(u64 address
)
2091 return (void __user
*)(uintptr_t)address
;
2094 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2096 unsigned long j
= msecs_to_jiffies(m
);
2098 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2101 static inline unsigned long
2102 timespec_to_jiffies_timeout(const struct timespec
*value
)
2104 unsigned long j
= timespec_to_jiffies(value
);
2106 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);