1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include <linux/io-mapping.h>
41 #include <linux/i2c.h>
42 #include <linux/i2c-algo-bit.h>
43 #include <drm/intel-gtt.h>
44 #include <linux/backlight.h>
45 #include <linux/hashtable.h>
46 #include <linux/intel-iommu.h>
47 #include <linux/kref.h>
48 #include <linux/pm_qos.h>
50 /* General customization:
53 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
55 #define DRIVER_NAME "i915"
56 #define DRIVER_DESC "Intel Graphics"
57 #define DRIVER_DATE "20140822"
65 I915_MAX_PIPES
= _PIPE_EDP
67 #define pipe_name(p) ((p) + 'A')
76 #define transcoder_name(t) ((t) + 'A')
83 #define plane_name(p) ((p) + 'A')
85 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
95 #define port_name(p) ((p) + 'A')
97 #define I915_NUM_PHYS_VLV 2
109 enum intel_display_power_domain
{
113 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
114 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
115 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
116 POWER_DOMAIN_TRANSCODER_A
,
117 POWER_DOMAIN_TRANSCODER_B
,
118 POWER_DOMAIN_TRANSCODER_C
,
119 POWER_DOMAIN_TRANSCODER_EDP
,
120 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
121 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
122 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
123 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
124 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
125 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
126 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
127 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
128 POWER_DOMAIN_PORT_DSI
,
129 POWER_DOMAIN_PORT_CRT
,
130 POWER_DOMAIN_PORT_OTHER
,
139 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
140 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
141 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
142 #define POWER_DOMAIN_TRANSCODER(tran) \
143 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
144 (tran) + POWER_DOMAIN_TRANSCODER_A)
148 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
149 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
159 #define I915_GEM_GPU_DOMAINS \
160 (I915_GEM_DOMAIN_RENDER | \
161 I915_GEM_DOMAIN_SAMPLER | \
162 I915_GEM_DOMAIN_COMMAND | \
163 I915_GEM_DOMAIN_INSTRUCTION | \
164 I915_GEM_DOMAIN_VERTEX)
166 #define for_each_pipe(__dev_priv, __p) \
167 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
168 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
170 #define for_each_crtc(dev, crtc) \
171 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
173 #define for_each_intel_crtc(dev, intel_crtc) \
174 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
176 #define for_each_intel_encoder(dev, intel_encoder) \
177 list_for_each_entry(intel_encoder, \
178 &(dev)->mode_config.encoder_list, \
181 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
182 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
183 if ((intel_encoder)->base.crtc == (__crtc))
185 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
186 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
187 if ((intel_connector)->base.encoder == (__encoder))
189 #define for_each_power_domain(domain, mask) \
190 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
191 if ((1 << (domain)) & (mask))
193 struct drm_i915_private
;
194 struct i915_mmu_object
;
197 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
198 /* real shared dpll ids must be >= 0 */
199 DPLL_ID_PCH_PLL_A
= 0,
200 DPLL_ID_PCH_PLL_B
= 1,
204 #define I915_NUM_PLLS 2
206 struct intel_dpll_hw_state
{
217 struct intel_shared_dpll
{
218 int refcount
; /* count of number of CRTCs sharing this PLL */
219 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
220 bool on
; /* is the PLL actually active? Disabled during modeset */
222 /* should match the index in the dev_priv->shared_dplls array */
223 enum intel_dpll_id id
;
224 struct intel_dpll_hw_state hw_state
;
225 /* The mode_set hook is optional and should be used together with the
226 * intel_prepare_shared_dpll function. */
227 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
228 struct intel_shared_dpll
*pll
);
229 void (*enable
)(struct drm_i915_private
*dev_priv
,
230 struct intel_shared_dpll
*pll
);
231 void (*disable
)(struct drm_i915_private
*dev_priv
,
232 struct intel_shared_dpll
*pll
);
233 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
234 struct intel_shared_dpll
*pll
,
235 struct intel_dpll_hw_state
*hw_state
);
238 /* Used by dp and fdi links */
239 struct intel_link_m_n
{
247 void intel_link_compute_m_n(int bpp
, int nlanes
,
248 int pixel_clock
, int link_clock
,
249 struct intel_link_m_n
*m_n
);
251 /* Interface history:
254 * 1.2: Add Power Management
255 * 1.3: Add vblank support
256 * 1.4: Fix cmdbuffer path, add heap destroy
257 * 1.5: Add vblank pipe configuration
258 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
259 * - Support vertical blank on secondary display pipe
261 #define DRIVER_MAJOR 1
262 #define DRIVER_MINOR 6
263 #define DRIVER_PATCHLEVEL 0
265 #define WATCH_LISTS 0
268 struct opregion_header
;
269 struct opregion_acpi
;
270 struct opregion_swsci
;
271 struct opregion_asle
;
273 struct intel_opregion
{
274 struct opregion_header __iomem
*header
;
275 struct opregion_acpi __iomem
*acpi
;
276 struct opregion_swsci __iomem
*swsci
;
277 u32 swsci_gbda_sub_functions
;
278 u32 swsci_sbcb_sub_functions
;
279 struct opregion_asle __iomem
*asle
;
281 u32 __iomem
*lid_state
;
282 struct work_struct asle_work
;
284 #define OPREGION_SIZE (8*1024)
286 struct intel_overlay
;
287 struct intel_overlay_error_state
;
289 struct drm_i915_master_private
{
290 drm_local_map_t
*sarea
;
291 struct _drm_i915_sarea
*sarea_priv
;
293 #define I915_FENCE_REG_NONE -1
294 #define I915_MAX_NUM_FENCES 32
295 /* 32 fences + sign bit for FENCE_REG_NONE */
296 #define I915_MAX_NUM_FENCE_BITS 6
298 struct drm_i915_fence_reg
{
299 struct list_head lru_list
;
300 struct drm_i915_gem_object
*obj
;
304 struct sdvo_device_mapping
{
313 struct intel_display_error_state
;
315 struct drm_i915_error_state
{
323 /* Generic register state */
331 u32 error
; /* gen6+ */
332 u32 err_int
; /* gen7 */
338 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
339 u64 fence
[I915_MAX_NUM_FENCES
];
340 struct intel_overlay_error_state
*overlay
;
341 struct intel_display_error_state
*display
;
342 struct drm_i915_error_object
*semaphore_obj
;
344 struct drm_i915_error_ring
{
346 /* Software tracked state */
349 enum intel_ring_hangcheck_action hangcheck_action
;
352 /* our own tracking of ring head and tail */
356 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
374 u32 rc_psmi
; /* sleep state */
375 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
377 struct drm_i915_error_object
{
381 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
383 struct drm_i915_error_request
{
398 char comm
[TASK_COMM_LEN
];
399 } ring
[I915_NUM_RINGS
];
401 struct drm_i915_error_buffer
{
408 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
416 } **active_bo
, **pinned_bo
;
418 u32
*active_bo_count
, *pinned_bo_count
;
422 struct intel_connector
;
423 struct intel_crtc_config
;
424 struct intel_plane_config
;
429 struct drm_i915_display_funcs
{
430 bool (*fbc_enabled
)(struct drm_device
*dev
);
431 void (*enable_fbc
)(struct drm_crtc
*crtc
);
432 void (*disable_fbc
)(struct drm_device
*dev
);
433 int (*get_display_clock_speed
)(struct drm_device
*dev
);
434 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
436 * find_dpll() - Find the best values for the PLL
437 * @limit: limits for the PLL
438 * @crtc: current CRTC
439 * @target: target frequency in kHz
440 * @refclk: reference clock frequency in kHz
441 * @match_clock: if provided, @best_clock P divider must
442 * match the P divider from @match_clock
443 * used for LVDS downclocking
444 * @best_clock: best PLL values found
446 * Returns true on success, false on failure.
448 bool (*find_dpll
)(const struct intel_limit
*limit
,
449 struct drm_crtc
*crtc
,
450 int target
, int refclk
,
451 struct dpll
*match_clock
,
452 struct dpll
*best_clock
);
453 void (*update_wm
)(struct drm_crtc
*crtc
);
454 void (*update_sprite_wm
)(struct drm_plane
*plane
,
455 struct drm_crtc
*crtc
,
456 uint32_t sprite_width
, uint32_t sprite_height
,
457 int pixel_size
, bool enable
, bool scaled
);
458 void (*modeset_global_resources
)(struct drm_device
*dev
);
459 /* Returns the active state of the crtc, and if the crtc is active,
460 * fills out the pipe-config with the hw state. */
461 bool (*get_pipe_config
)(struct intel_crtc
*,
462 struct intel_crtc_config
*);
463 void (*get_plane_config
)(struct intel_crtc
*,
464 struct intel_plane_config
*);
465 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
467 struct drm_framebuffer
*old_fb
);
468 void (*crtc_enable
)(struct drm_crtc
*crtc
);
469 void (*crtc_disable
)(struct drm_crtc
*crtc
);
470 void (*off
)(struct drm_crtc
*crtc
);
471 void (*write_eld
)(struct drm_connector
*connector
,
472 struct drm_crtc
*crtc
,
473 struct drm_display_mode
*mode
);
474 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
475 void (*init_clock_gating
)(struct drm_device
*dev
);
476 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
477 struct drm_framebuffer
*fb
,
478 struct drm_i915_gem_object
*obj
,
479 struct intel_engine_cs
*ring
,
481 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
482 struct drm_framebuffer
*fb
,
484 void (*hpd_irq_setup
)(struct drm_device
*dev
);
485 /* clock updates for mode set */
487 /* render clock increase/decrease */
488 /* display clock increase/decrease */
489 /* pll clock increase/decrease */
491 int (*setup_backlight
)(struct intel_connector
*connector
);
492 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
493 void (*set_backlight
)(struct intel_connector
*connector
,
495 void (*disable_backlight
)(struct intel_connector
*connector
);
496 void (*enable_backlight
)(struct intel_connector
*connector
);
499 struct intel_uncore_funcs
{
500 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
502 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
505 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
506 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
507 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
508 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
510 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
511 uint8_t val
, bool trace
);
512 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
513 uint16_t val
, bool trace
);
514 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
515 uint32_t val
, bool trace
);
516 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
517 uint64_t val
, bool trace
);
520 struct intel_uncore
{
521 spinlock_t lock
; /** lock is also taken in irq contexts. */
523 struct intel_uncore_funcs funcs
;
526 unsigned forcewake_count
;
528 unsigned fw_rendercount
;
529 unsigned fw_mediacount
;
531 struct timer_list force_wake_timer
;
534 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
535 func(is_mobile) sep \
538 func(is_i945gm) sep \
540 func(need_gfx_hws) sep \
542 func(is_pineview) sep \
543 func(is_broadwater) sep \
544 func(is_crestline) sep \
545 func(is_ivybridge) sep \
546 func(is_valleyview) sep \
547 func(is_haswell) sep \
548 func(is_preliminary) sep \
550 func(has_pipe_cxsr) sep \
551 func(has_hotplug) sep \
552 func(cursor_needs_physical) sep \
553 func(has_overlay) sep \
554 func(overlay_needs_physical) sep \
555 func(supports_tv) sep \
560 #define DEFINE_FLAG(name) u8 name:1
561 #define SEP_SEMICOLON ;
563 struct intel_device_info
{
564 u32 display_mmio_offset
;
567 u8 num_sprites
[I915_MAX_PIPES
];
569 u8 ring_mask
; /* Rings supported by the HW */
570 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
571 /* Register offsets for the various display pipes and transcoders */
572 int pipe_offsets
[I915_MAX_TRANSCODERS
];
573 int trans_offsets
[I915_MAX_TRANSCODERS
];
574 int palette_offsets
[I915_MAX_PIPES
];
575 int cursor_offsets
[I915_MAX_PIPES
];
581 enum i915_cache_level
{
583 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
584 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
585 caches, eg sampler/render caches, and the
586 large Last-Level-Cache. LLC is coherent with
587 the CPU, but L3 is only visible to the GPU. */
588 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
591 struct i915_ctx_hang_stats
{
592 /* This context had batch pending when hang was declared */
593 unsigned batch_pending
;
595 /* This context had batch active when hang was declared */
596 unsigned batch_active
;
598 /* Time when this context was last blamed for a GPU reset */
599 unsigned long guilty_ts
;
601 /* This context is banned to submit more work */
605 /* This must match up with the value previously used for execbuf2.rsvd1. */
606 #define DEFAULT_CONTEXT_HANDLE 0
608 * struct intel_context - as the name implies, represents a context.
609 * @ref: reference count.
610 * @user_handle: userspace tracking identity for this context.
611 * @remap_slice: l3 row remapping information.
612 * @file_priv: filp associated with this context (NULL for global default
614 * @hang_stats: information about the role of this context in possible GPU
616 * @vm: virtual memory space used by this context.
617 * @legacy_hw_ctx: render context backing object and whether it is correctly
618 * initialized (legacy ring submission mechanism only).
619 * @link: link in the global list of contexts.
621 * Contexts are memory images used by the hardware to store copies of their
624 struct intel_context
{
628 struct drm_i915_file_private
*file_priv
;
629 struct i915_ctx_hang_stats hang_stats
;
630 struct i915_hw_ppgtt
*ppgtt
;
632 /* Legacy ring buffer submission */
634 struct drm_i915_gem_object
*rcs_state
;
640 struct drm_i915_gem_object
*state
;
641 struct intel_ringbuffer
*ringbuf
;
642 } engine
[I915_NUM_RINGS
];
644 struct list_head link
;
654 struct drm_mm_node compressed_fb
;
655 struct drm_mm_node
*compressed_llb
;
659 struct intel_fbc_work
{
660 struct delayed_work work
;
661 struct drm_crtc
*crtc
;
662 struct drm_framebuffer
*fb
;
666 FBC_OK
, /* FBC is enabled */
667 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
668 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
669 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
670 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
671 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
672 FBC_BAD_PLANE
, /* fbc not supported on plane */
673 FBC_NOT_TILED
, /* buffer not tiled */
674 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
676 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
681 struct intel_connector
*connector
;
689 struct intel_dp
*enabled
;
691 struct delayed_work work
;
692 unsigned busy_frontbuffer_bits
;
696 PCH_NONE
= 0, /* No PCH present */
697 PCH_IBX
, /* Ibexpeak PCH */
698 PCH_CPT
, /* Cougarpoint PCH */
699 PCH_LPT
, /* Lynxpoint PCH */
703 enum intel_sbi_destination
{
708 #define QUIRK_PIPEA_FORCE (1<<0)
709 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
710 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
711 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
714 struct intel_fbc_work
;
717 struct i2c_adapter adapter
;
721 struct i2c_algo_bit_data bit_algo
;
722 struct drm_i915_private
*dev_priv
;
725 struct i915_suspend_saved_registers
{
746 u32 saveTRANS_HTOTAL_A
;
747 u32 saveTRANS_HBLANK_A
;
748 u32 saveTRANS_HSYNC_A
;
749 u32 saveTRANS_VTOTAL_A
;
750 u32 saveTRANS_VBLANK_A
;
751 u32 saveTRANS_VSYNC_A
;
759 u32 savePFIT_PGM_RATIOS
;
760 u32 saveBLC_HIST_CTL
;
762 u32 saveBLC_PWM_CTL2
;
763 u32 saveBLC_HIST_CTL_B
;
764 u32 saveBLC_CPU_PWM_CTL
;
765 u32 saveBLC_CPU_PWM_CTL2
;
778 u32 saveTRANS_HTOTAL_B
;
779 u32 saveTRANS_HBLANK_B
;
780 u32 saveTRANS_HSYNC_B
;
781 u32 saveTRANS_VTOTAL_B
;
782 u32 saveTRANS_VBLANK_B
;
783 u32 saveTRANS_VSYNC_B
;
797 u32 savePP_ON_DELAYS
;
798 u32 savePP_OFF_DELAYS
;
806 u32 savePFIT_CONTROL
;
807 u32 save_palette_a
[256];
808 u32 save_palette_b
[256];
819 u32 saveCACHE_MODE_0
;
820 u32 saveMI_ARB_STATE
;
831 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
842 u32 savePIPEA_GMCH_DATA_M
;
843 u32 savePIPEB_GMCH_DATA_M
;
844 u32 savePIPEA_GMCH_DATA_N
;
845 u32 savePIPEB_GMCH_DATA_N
;
846 u32 savePIPEA_DP_LINK_M
;
847 u32 savePIPEB_DP_LINK_M
;
848 u32 savePIPEA_DP_LINK_N
;
849 u32 savePIPEB_DP_LINK_N
;
860 u32 savePCH_DREF_CONTROL
;
861 u32 saveDISP_ARB_CTL
;
862 u32 savePIPEA_DATA_M1
;
863 u32 savePIPEA_DATA_N1
;
864 u32 savePIPEA_LINK_M1
;
865 u32 savePIPEA_LINK_N1
;
866 u32 savePIPEB_DATA_M1
;
867 u32 savePIPEB_DATA_N1
;
868 u32 savePIPEB_LINK_M1
;
869 u32 savePIPEB_LINK_N1
;
870 u32 saveMCHBAR_RENDER_STANDBY
;
871 u32 savePCH_PORT_HOTPLUG
;
874 struct vlv_s0ix_state
{
881 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
882 u32 media_max_req_count
;
883 u32 gfx_max_req_count
;
915 /* Display 1 CZ domain */
920 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
922 /* GT SA CZ domain */
929 /* Display 2 CZ domain */
935 struct intel_rps_ei
{
941 struct intel_gen6_power_mgmt
{
942 /* work and pm_iir are protected by dev_priv->irq_lock */
943 struct work_struct work
;
946 /* Frequencies are stored in potentially platform dependent multiples.
947 * In other words, *_freq needs to be multiplied by X to be interesting.
948 * Soft limits are those which are used for the dynamic reclocking done
949 * by the driver (raise frequencies under heavy loads, and lower for
950 * lighter loads). Hard limits are those imposed by the hardware.
952 * A distinction is made for overclocking, which is never enabled by
953 * default, and is considered to be above the hard limit if it's
956 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
957 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
958 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
959 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
960 u8 min_freq
; /* AKA RPn. Minimum frequency */
961 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
962 u8 rp1_freq
; /* "less than" RP0 power/freqency */
963 u8 rp0_freq
; /* Non-overclocked max frequency. */
966 u32 ei_interrupt_count
;
969 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
972 struct delayed_work delayed_resume_work
;
974 /* manual wa residency calculations */
975 struct intel_rps_ei up_ei
, down_ei
;
978 * Protects RPS/RC6 register access and PCU communication.
979 * Must be taken after struct_mutex if nested.
981 struct mutex hw_lock
;
984 /* defined intel_pm.c */
985 extern spinlock_t mchdev_lock
;
987 struct intel_ilk_power_mgmt
{
995 unsigned long last_time1
;
996 unsigned long chipset_power
;
999 unsigned long gfx_power
;
1005 struct drm_i915_gem_object
*pwrctx
;
1006 struct drm_i915_gem_object
*renderctx
;
1009 struct drm_i915_private
;
1010 struct i915_power_well
;
1012 struct i915_power_well_ops
{
1014 * Synchronize the well's hw state to match the current sw state, for
1015 * example enable/disable it based on the current refcount. Called
1016 * during driver init and resume time, possibly after first calling
1017 * the enable/disable handlers.
1019 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1020 struct i915_power_well
*power_well
);
1022 * Enable the well and resources that depend on it (for example
1023 * interrupts located on the well). Called after the 0->1 refcount
1026 void (*enable
)(struct drm_i915_private
*dev_priv
,
1027 struct i915_power_well
*power_well
);
1029 * Disable the well and resources that depend on it. Called after
1030 * the 1->0 refcount transition.
1032 void (*disable
)(struct drm_i915_private
*dev_priv
,
1033 struct i915_power_well
*power_well
);
1034 /* Returns the hw enabled state. */
1035 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1036 struct i915_power_well
*power_well
);
1039 /* Power well structure for haswell */
1040 struct i915_power_well
{
1043 /* power well enable/disable usage count */
1045 /* cached hw enabled state */
1047 unsigned long domains
;
1049 const struct i915_power_well_ops
*ops
;
1052 struct i915_power_domains
{
1054 * Power wells needed for initialization at driver init and suspend
1055 * time are on. They are kept on until after the first modeset.
1059 int power_well_count
;
1062 int domain_use_count
[POWER_DOMAIN_NUM
];
1063 struct i915_power_well
*power_wells
;
1066 struct i915_dri1_state
{
1067 unsigned allow_batchbuffer
: 1;
1068 u32 __iomem
*gfx_hws_cpu_addr
;
1079 struct i915_ums_state
{
1081 * Flag if the X Server, and thus DRM, is not currently in
1082 * control of the device.
1084 * This is set between LeaveVT and EnterVT. It needs to be
1085 * replaced with a semaphore. It also needs to be
1086 * transitioned away from for kernel modesetting.
1091 #define MAX_L3_SLICES 2
1092 struct intel_l3_parity
{
1093 u32
*remap_info
[MAX_L3_SLICES
];
1094 struct work_struct error_work
;
1098 struct i915_gem_mm
{
1099 /** Memory allocator for GTT stolen memory */
1100 struct drm_mm stolen
;
1101 /** List of all objects in gtt_space. Used to restore gtt
1102 * mappings on resume */
1103 struct list_head bound_list
;
1105 * List of objects which are not bound to the GTT (thus
1106 * are idle and not used by the GPU) but still have
1107 * (presumably uncached) pages still attached.
1109 struct list_head unbound_list
;
1111 /** Usable portion of the GTT for GEM */
1112 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1114 /** PPGTT used for aliasing the PPGTT with the GTT */
1115 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1117 struct notifier_block oom_notifier
;
1118 struct shrinker shrinker
;
1119 bool shrinker_no_lock_stealing
;
1121 /** LRU list of objects with fence regs on them. */
1122 struct list_head fence_list
;
1125 * We leave the user IRQ off as much as possible,
1126 * but this means that requests will finish and never
1127 * be retired once the system goes idle. Set a timer to
1128 * fire periodically while the ring is running. When it
1129 * fires, go retire requests.
1131 struct delayed_work retire_work
;
1134 * When we detect an idle GPU, we want to turn on
1135 * powersaving features. So once we see that there
1136 * are no more requests outstanding and no more
1137 * arrive within a small period of time, we fire
1138 * off the idle_work.
1140 struct delayed_work idle_work
;
1143 * Are we in a non-interruptible section of code like
1149 * Is the GPU currently considered idle, or busy executing userspace
1150 * requests? Whilst idle, we attempt to power down the hardware and
1151 * display clocks. In order to reduce the effect on performance, there
1152 * is a slight delay before we do so.
1156 /* the indicator for dispatch video commands on two BSD rings */
1157 int bsd_ring_dispatch_index
;
1159 /** Bit 6 swizzling required for X tiling */
1160 uint32_t bit_6_swizzle_x
;
1161 /** Bit 6 swizzling required for Y tiling */
1162 uint32_t bit_6_swizzle_y
;
1164 /* accounting, useful for userland debugging */
1165 spinlock_t object_stat_lock
;
1166 size_t object_memory
;
1170 struct drm_i915_error_state_buf
{
1179 struct i915_error_state_file_priv
{
1180 struct drm_device
*dev
;
1181 struct drm_i915_error_state
*error
;
1184 struct i915_gpu_error
{
1185 /* For hangcheck timer */
1186 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1187 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1188 /* Hang gpu twice in this window and your context gets banned */
1189 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1191 struct timer_list hangcheck_timer
;
1193 /* For reset and error_state handling. */
1195 /* Protected by the above dev->gpu_error.lock. */
1196 struct drm_i915_error_state
*first_error
;
1197 struct work_struct work
;
1200 unsigned long missed_irq_rings
;
1203 * State variable controlling the reset flow and count
1205 * This is a counter which gets incremented when reset is triggered,
1206 * and again when reset has been handled. So odd values (lowest bit set)
1207 * means that reset is in progress and even values that
1208 * (reset_counter >> 1):th reset was successfully completed.
1210 * If reset is not completed succesfully, the I915_WEDGE bit is
1211 * set meaning that hardware is terminally sour and there is no
1212 * recovery. All waiters on the reset_queue will be woken when
1215 * This counter is used by the wait_seqno code to notice that reset
1216 * event happened and it needs to restart the entire ioctl (since most
1217 * likely the seqno it waited for won't ever signal anytime soon).
1219 * This is important for lock-free wait paths, where no contended lock
1220 * naturally enforces the correct ordering between the bail-out of the
1221 * waiter and the gpu reset work code.
1223 atomic_t reset_counter
;
1225 #define I915_RESET_IN_PROGRESS_FLAG 1
1226 #define I915_WEDGED (1 << 31)
1229 * Waitqueue to signal when the reset has completed. Used by clients
1230 * that wait for dev_priv->mm.wedged to settle.
1232 wait_queue_head_t reset_queue
;
1234 /* Userspace knobs for gpu hang simulation;
1235 * combines both a ring mask, and extra flags
1238 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1239 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1241 /* For missed irq/seqno simulation. */
1242 unsigned int test_irq_rings
;
1244 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1245 bool reload_in_reset
;
1248 enum modeset_restore
{
1249 MODESET_ON_LID_OPEN
,
1254 struct ddi_vbt_port_info
{
1256 * This is an index in the HDMI/DVI DDI buffer translation table.
1257 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1258 * populate this field.
1260 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1261 uint8_t hdmi_level_shift
;
1263 uint8_t supports_dvi
:1;
1264 uint8_t supports_hdmi
:1;
1265 uint8_t supports_dp
:1;
1268 enum drrs_support_type
{
1269 DRRS_NOT_SUPPORTED
= 0,
1270 STATIC_DRRS_SUPPORT
= 1,
1271 SEAMLESS_DRRS_SUPPORT
= 2
1274 struct intel_vbt_data
{
1275 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1276 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1279 unsigned int int_tv_support
:1;
1280 unsigned int lvds_dither
:1;
1281 unsigned int lvds_vbt
:1;
1282 unsigned int int_crt_support
:1;
1283 unsigned int lvds_use_ssc
:1;
1284 unsigned int display_clock_mode
:1;
1285 unsigned int fdi_rx_polarity_inverted
:1;
1286 unsigned int has_mipi
:1;
1288 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1290 enum drrs_support_type drrs_type
;
1295 int edp_preemphasis
;
1297 bool edp_initialized
;
1300 struct edp_power_seq edp_pps
;
1305 bool active_low_pwm
;
1306 u8 min_brightness
; /* min_brightness/255 of max */
1313 struct mipi_config
*config
;
1314 struct mipi_pps_data
*pps
;
1318 u8
*sequence
[MIPI_SEQ_MAX
];
1324 union child_device_config
*child_dev
;
1326 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1329 enum intel_ddb_partitioning
{
1331 INTEL_DDB_PART_5_6
, /* IVB+ */
1334 struct intel_wm_level
{
1342 struct ilk_wm_values
{
1343 uint32_t wm_pipe
[3];
1345 uint32_t wm_lp_spr
[3];
1346 uint32_t wm_linetime
[3];
1348 enum intel_ddb_partitioning partitioning
;
1352 * This struct helps tracking the state needed for runtime PM, which puts the
1353 * device in PCI D3 state. Notice that when this happens, nothing on the
1354 * graphics device works, even register access, so we don't get interrupts nor
1357 * Every piece of our code that needs to actually touch the hardware needs to
1358 * either call intel_runtime_pm_get or call intel_display_power_get with the
1359 * appropriate power domain.
1361 * Our driver uses the autosuspend delay feature, which means we'll only really
1362 * suspend if we stay with zero refcount for a certain amount of time. The
1363 * default value is currently very conservative (see intel_init_runtime_pm), but
1364 * it can be changed with the standard runtime PM files from sysfs.
1366 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1367 * goes back to false exactly before we reenable the IRQs. We use this variable
1368 * to check if someone is trying to enable/disable IRQs while they're supposed
1369 * to be disabled. This shouldn't happen and we'll print some error messages in
1372 * For more, read the Documentation/power/runtime_pm.txt.
1374 struct i915_runtime_pm
{
1376 bool _irqs_disabled
;
1379 enum intel_pipe_crc_source
{
1380 INTEL_PIPE_CRC_SOURCE_NONE
,
1381 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1382 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1383 INTEL_PIPE_CRC_SOURCE_PF
,
1384 INTEL_PIPE_CRC_SOURCE_PIPE
,
1385 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1386 INTEL_PIPE_CRC_SOURCE_TV
,
1387 INTEL_PIPE_CRC_SOURCE_DP_B
,
1388 INTEL_PIPE_CRC_SOURCE_DP_C
,
1389 INTEL_PIPE_CRC_SOURCE_DP_D
,
1390 INTEL_PIPE_CRC_SOURCE_AUTO
,
1391 INTEL_PIPE_CRC_SOURCE_MAX
,
1394 struct intel_pipe_crc_entry
{
1399 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1400 struct intel_pipe_crc
{
1402 bool opened
; /* exclusive access to the result file */
1403 struct intel_pipe_crc_entry
*entries
;
1404 enum intel_pipe_crc_source source
;
1406 wait_queue_head_t wq
;
1409 struct i915_frontbuffer_tracking
{
1413 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1420 struct drm_i915_private
{
1421 struct drm_device
*dev
;
1422 struct kmem_cache
*slab
;
1424 const struct intel_device_info info
;
1426 int relative_constants_mode
;
1430 struct intel_uncore uncore
;
1432 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1435 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1436 * controller on different i2c buses. */
1437 struct mutex gmbus_mutex
;
1440 * Base address of the gmbus and gpio block.
1442 uint32_t gpio_mmio_base
;
1444 /* MMIO base address for MIPI regs */
1445 uint32_t mipi_mmio_base
;
1447 wait_queue_head_t gmbus_wait_queue
;
1449 struct pci_dev
*bridge_dev
;
1450 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1451 struct drm_i915_gem_object
*semaphore_obj
;
1452 uint32_t last_seqno
, next_seqno
;
1454 drm_dma_handle_t
*status_page_dmah
;
1455 struct resource mch_res
;
1457 /* protects the irq masks */
1458 spinlock_t irq_lock
;
1460 /* protects the mmio flip data */
1461 spinlock_t mmio_flip_lock
;
1463 bool display_irqs_enabled
;
1465 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1466 struct pm_qos_request pm_qos
;
1468 /* DPIO indirect register protection */
1469 struct mutex dpio_lock
;
1471 /** Cached value of IMR to avoid reads in updating the bitfield */
1474 u32 de_irq_mask
[I915_MAX_PIPES
];
1479 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1481 struct work_struct hotplug_work
;
1483 unsigned long hpd_last_jiffies
;
1488 HPD_MARK_DISABLED
= 2
1490 } hpd_stats
[HPD_NUM_PINS
];
1492 struct delayed_work hotplug_reenable_work
;
1494 struct i915_fbc fbc
;
1495 struct i915_drrs drrs
;
1496 struct intel_opregion opregion
;
1497 struct intel_vbt_data vbt
;
1500 struct intel_overlay
*overlay
;
1502 /* backlight registers and fields in struct intel_panel */
1503 spinlock_t backlight_lock
;
1506 bool no_aux_handshake
;
1508 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1509 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1510 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1512 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1513 unsigned int vlv_cdclk_freq
;
1516 * wq - Driver workqueue for GEM.
1518 * NOTE: Work items scheduled here are not allowed to grab any modeset
1519 * locks, for otherwise the flushing done in the pageflip code will
1520 * result in deadlocks.
1522 struct workqueue_struct
*wq
;
1524 /* Display functions */
1525 struct drm_i915_display_funcs display
;
1527 /* PCH chipset type */
1528 enum intel_pch pch_type
;
1529 unsigned short pch_id
;
1531 unsigned long quirks
;
1533 enum modeset_restore modeset_restore
;
1534 struct mutex modeset_restore_lock
;
1536 struct list_head vm_list
; /* Global list of all address spaces */
1537 struct i915_gtt gtt
; /* VM representing the global address space */
1539 struct i915_gem_mm mm
;
1540 #if defined(CONFIG_MMU_NOTIFIER)
1541 DECLARE_HASHTABLE(mmu_notifiers
, 7);
1544 /* Kernel Modesetting */
1546 struct sdvo_device_mapping sdvo_mappings
[2];
1548 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1549 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1550 wait_queue_head_t pending_flip_queue
;
1552 #ifdef CONFIG_DEBUG_FS
1553 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1556 int num_shared_dpll
;
1557 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1558 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1560 /* Reclocking support */
1561 bool render_reclock_avail
;
1562 bool lvds_downclock_avail
;
1563 /* indicates the reduced downclock for LVDS*/
1566 struct i915_frontbuffer_tracking fb_tracking
;
1570 bool mchbar_need_disable
;
1572 struct intel_l3_parity l3_parity
;
1574 /* Cannot be determined by PCIID. You must always read a register. */
1577 /* gen6+ rps state */
1578 struct intel_gen6_power_mgmt rps
;
1580 /* ilk-only ips/rps state. Everything in here is protected by the global
1581 * mchdev_lock in intel_pm.c */
1582 struct intel_ilk_power_mgmt ips
;
1584 struct i915_power_domains power_domains
;
1586 struct i915_psr psr
;
1588 struct i915_gpu_error gpu_error
;
1590 struct drm_i915_gem_object
*vlv_pctx
;
1592 #ifdef CONFIG_DRM_I915_FBDEV
1593 /* list of fbdev register on this device */
1594 struct intel_fbdev
*fbdev
;
1595 struct work_struct fbdev_suspend_work
;
1598 struct drm_property
*broadcast_rgb_property
;
1599 struct drm_property
*force_audio_property
;
1601 uint32_t hw_context_size
;
1602 struct list_head context_list
;
1607 struct i915_suspend_saved_registers regfile
;
1608 struct vlv_s0ix_state vlv_s0ix_state
;
1612 * Raw watermark latency values:
1613 * in 0.1us units for WM0,
1614 * in 0.5us units for WM1+.
1617 uint16_t pri_latency
[5];
1619 uint16_t spr_latency
[5];
1621 uint16_t cur_latency
[5];
1623 /* current hardware state */
1624 struct ilk_wm_values hw
;
1627 struct i915_runtime_pm pm
;
1629 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1630 u32 long_hpd_port_mask
;
1631 u32 short_hpd_port_mask
;
1632 struct work_struct dig_port_work
;
1635 * if we get a HPD irq from DP and a HPD irq from non-DP
1636 * the non-DP HPD could block the workqueue on a mode config
1637 * mutex getting, that userspace may have taken. However
1638 * userspace is waiting on the DP workqueue to run which is
1639 * blocked behind the non-DP one.
1641 struct workqueue_struct
*dp_wq
;
1643 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1645 struct i915_dri1_state dri1
;
1646 /* Old ums support infrastructure, same warning applies. */
1647 struct i915_ums_state ums
;
1649 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1651 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1652 struct intel_engine_cs
*ring
,
1653 struct intel_context
*ctx
,
1654 struct drm_i915_gem_execbuffer2
*args
,
1655 struct list_head
*vmas
,
1656 struct drm_i915_gem_object
*batch_obj
,
1657 u64 exec_start
, u32 flags
);
1658 int (*init_rings
)(struct drm_device
*dev
);
1659 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1660 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1664 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1665 * will be rejected. Instead look for a better place.
1669 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1671 return dev
->dev_private
;
1674 /* Iterate over initialised rings */
1675 #define for_each_ring(ring__, dev_priv__, i__) \
1676 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1677 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1679 enum hdmi_force_audio
{
1680 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1681 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1682 HDMI_AUDIO_AUTO
, /* trust EDID */
1683 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1686 #define I915_GTT_OFFSET_NONE ((u32)-1)
1688 struct drm_i915_gem_object_ops
{
1689 /* Interface between the GEM object and its backing storage.
1690 * get_pages() is called once prior to the use of the associated set
1691 * of pages before to binding them into the GTT, and put_pages() is
1692 * called after we no longer need them. As we expect there to be
1693 * associated cost with migrating pages between the backing storage
1694 * and making them available for the GPU (e.g. clflush), we may hold
1695 * onto the pages after they are no longer referenced by the GPU
1696 * in case they may be used again shortly (for example migrating the
1697 * pages to a different memory domain within the GTT). put_pages()
1698 * will therefore most likely be called when the object itself is
1699 * being released or under memory pressure (where we attempt to
1700 * reap pages for the shrinker).
1702 int (*get_pages
)(struct drm_i915_gem_object
*);
1703 void (*put_pages
)(struct drm_i915_gem_object
*);
1704 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1705 void (*release
)(struct drm_i915_gem_object
*);
1709 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1710 * considered to be the frontbuffer for the given plane interface-vise. This
1711 * doesn't mean that the hw necessarily already scans it out, but that any
1712 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1714 * We have one bit per pipe and per scanout plane type.
1716 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1717 #define INTEL_FRONTBUFFER_BITS \
1718 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1719 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1720 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1721 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1722 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1723 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1724 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1725 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1726 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1727 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1728 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1730 struct drm_i915_gem_object
{
1731 struct drm_gem_object base
;
1733 const struct drm_i915_gem_object_ops
*ops
;
1735 /** List of VMAs backed by this object */
1736 struct list_head vma_list
;
1738 /** Stolen memory for this object, instead of being backed by shmem. */
1739 struct drm_mm_node
*stolen
;
1740 struct list_head global_list
;
1742 struct list_head ring_list
;
1743 /** Used in execbuf to temporarily hold a ref */
1744 struct list_head obj_exec_link
;
1747 * This is set if the object is on the active lists (has pending
1748 * rendering and so a non-zero seqno), and is not set if it i s on
1749 * inactive (ready to be unbound) list.
1751 unsigned int active
:1;
1754 * This is set if the object has been written to since last bound
1757 unsigned int dirty
:1;
1760 * Fence register bits (if any) for this object. Will be set
1761 * as needed when mapped into the GTT.
1762 * Protected by dev->struct_mutex.
1764 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1767 * Advice: are the backing pages purgeable?
1769 unsigned int madv
:2;
1772 * Current tiling mode for the object.
1774 unsigned int tiling_mode
:2;
1776 * Whether the tiling parameters for the currently associated fence
1777 * register have changed. Note that for the purposes of tracking
1778 * tiling changes we also treat the unfenced register, the register
1779 * slot that the object occupies whilst it executes a fenced
1780 * command (such as BLT on gen2/3), as a "fence".
1782 unsigned int fence_dirty
:1;
1785 * Is the object at the current location in the gtt mappable and
1786 * fenceable? Used to avoid costly recalculations.
1788 unsigned int map_and_fenceable
:1;
1791 * Whether the current gtt mapping needs to be mappable (and isn't just
1792 * mappable by accident). Track pin and fault separate for a more
1793 * accurate mappable working set.
1795 unsigned int fault_mappable
:1;
1796 unsigned int pin_mappable
:1;
1797 unsigned int pin_display
:1;
1800 * Is the object to be mapped as read-only to the GPU
1801 * Only honoured if hardware has relevant pte bit
1803 unsigned long gt_ro
:1;
1804 unsigned int cache_level
:3;
1806 unsigned int has_aliasing_ppgtt_mapping
:1;
1807 unsigned int has_global_gtt_mapping
:1;
1808 unsigned int has_dma_mapping
:1;
1810 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1812 struct sg_table
*pages
;
1813 int pages_pin_count
;
1815 /* prime dma-buf support */
1816 void *dma_buf_vmapping
;
1819 struct intel_engine_cs
*ring
;
1821 /** Breadcrumb of last rendering to the buffer. */
1822 uint32_t last_read_seqno
;
1823 uint32_t last_write_seqno
;
1824 /** Breadcrumb of last fenced GPU access to the buffer. */
1825 uint32_t last_fenced_seqno
;
1827 /** Current tiling stride for the object, if it's tiled. */
1830 /** References from framebuffers, locks out tiling changes. */
1831 unsigned long framebuffer_references
;
1833 /** Record of address bit 17 of each page at last unbind. */
1834 unsigned long *bit_17
;
1836 /** User space pin count and filp owning the pin */
1837 unsigned long user_pin_count
;
1838 struct drm_file
*pin_filp
;
1840 /** for phy allocated objects */
1841 drm_dma_handle_t
*phys_handle
;
1844 struct i915_gem_userptr
{
1846 unsigned read_only
:1;
1847 unsigned workers
:4;
1848 #define I915_GEM_USERPTR_MAX_WORKERS 15
1850 struct mm_struct
*mm
;
1851 struct i915_mmu_object
*mn
;
1852 struct work_struct
*work
;
1856 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1858 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1859 struct drm_i915_gem_object
*new,
1860 unsigned frontbuffer_bits
);
1863 * Request queue structure.
1865 * The request queue allows us to note sequence numbers that have been emitted
1866 * and may be associated with active buffers to be retired.
1868 * By keeping this list, we can avoid having to do questionable
1869 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1870 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1872 struct drm_i915_gem_request
{
1873 /** On Which ring this request was generated */
1874 struct intel_engine_cs
*ring
;
1876 /** GEM sequence number associated with this request. */
1879 /** Position in the ringbuffer of the start of the request */
1882 /** Position in the ringbuffer of the end of the request */
1885 /** Context related to this request */
1886 struct intel_context
*ctx
;
1888 /** Batch buffer related to this request if any */
1889 struct drm_i915_gem_object
*batch_obj
;
1891 /** Time at which this request was emitted, in jiffies. */
1892 unsigned long emitted_jiffies
;
1894 /** global list entry for this request */
1895 struct list_head list
;
1897 struct drm_i915_file_private
*file_priv
;
1898 /** file_priv list entry for this request */
1899 struct list_head client_list
;
1902 struct drm_i915_file_private
{
1903 struct drm_i915_private
*dev_priv
;
1904 struct drm_file
*file
;
1908 struct list_head request_list
;
1909 struct delayed_work idle_work
;
1911 struct idr context_idr
;
1913 atomic_t rps_wait_boost
;
1914 struct intel_engine_cs
*bsd_ring
;
1918 * A command that requires special handling by the command parser.
1920 struct drm_i915_cmd_descriptor
{
1922 * Flags describing how the command parser processes the command.
1924 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1925 * a length mask if not set
1926 * CMD_DESC_SKIP: The command is allowed but does not follow the
1927 * standard length encoding for the opcode range in
1929 * CMD_DESC_REJECT: The command is never allowed
1930 * CMD_DESC_REGISTER: The command should be checked against the
1931 * register whitelist for the appropriate ring
1932 * CMD_DESC_MASTER: The command is allowed if the submitting process
1936 #define CMD_DESC_FIXED (1<<0)
1937 #define CMD_DESC_SKIP (1<<1)
1938 #define CMD_DESC_REJECT (1<<2)
1939 #define CMD_DESC_REGISTER (1<<3)
1940 #define CMD_DESC_BITMASK (1<<4)
1941 #define CMD_DESC_MASTER (1<<5)
1944 * The command's unique identification bits and the bitmask to get them.
1945 * This isn't strictly the opcode field as defined in the spec and may
1946 * also include type, subtype, and/or subop fields.
1954 * The command's length. The command is either fixed length (i.e. does
1955 * not include a length field) or has a length field mask. The flag
1956 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1957 * a length mask. All command entries in a command table must include
1958 * length information.
1966 * Describes where to find a register address in the command to check
1967 * against the ring's register whitelist. Only valid if flags has the
1968 * CMD_DESC_REGISTER bit set.
1975 #define MAX_CMD_DESC_BITMASKS 3
1977 * Describes command checks where a particular dword is masked and
1978 * compared against an expected value. If the command does not match
1979 * the expected value, the parser rejects it. Only valid if flags has
1980 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1983 * If the check specifies a non-zero condition_mask then the parser
1984 * only performs the check when the bits specified by condition_mask
1991 u32 condition_offset
;
1993 } bits
[MAX_CMD_DESC_BITMASKS
];
1997 * A table of commands requiring special handling by the command parser.
1999 * Each ring has an array of tables. Each table consists of an array of command
2000 * descriptors, which must be sorted with command opcodes in ascending order.
2002 struct drm_i915_cmd_table
{
2003 const struct drm_i915_cmd_descriptor
*table
;
2007 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2008 #define __I915__(p) ({ \
2009 struct drm_i915_private *__p; \
2010 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2011 __p = (struct drm_i915_private *)p; \
2012 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2013 __p = to_i915((struct drm_device *)p); \
2018 #define INTEL_INFO(p) (&__I915__(p)->info)
2019 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2021 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2022 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2023 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2024 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2025 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2026 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2027 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2028 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2029 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2030 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2031 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2032 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2033 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2034 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2035 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2036 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2037 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2038 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2039 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2040 INTEL_DEVID(dev) == 0x0152 || \
2041 INTEL_DEVID(dev) == 0x015a)
2042 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2043 INTEL_DEVID(dev) == 0x0106 || \
2044 INTEL_DEVID(dev) == 0x010A)
2045 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2046 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2047 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2048 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2049 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2050 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2051 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2052 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2053 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2054 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2055 (INTEL_DEVID(dev) & 0xf) == 0xe))
2056 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2057 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2058 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
2059 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2060 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2061 /* ULX machines are also considered ULT. */
2062 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2063 INTEL_DEVID(dev) == 0x0A1E)
2064 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2067 * The genX designation typically refers to the render engine, so render
2068 * capability related checks should use IS_GEN, while display and other checks
2069 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2072 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2073 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2074 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2075 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2076 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2077 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2078 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2080 #define RENDER_RING (1<<RCS)
2081 #define BSD_RING (1<<VCS)
2082 #define BLT_RING (1<<BCS)
2083 #define VEBOX_RING (1<<VECS)
2084 #define BSD2_RING (1<<VCS2)
2085 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2086 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2087 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2088 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2089 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2090 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2091 to_i915(dev)->ellc_size)
2092 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2094 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2095 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2096 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2097 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2098 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2099 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2101 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2102 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2104 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2105 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2107 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2108 * even when in MSI mode. This results in spurious interrupt warnings if the
2109 * legacy irq no. is shared with another device. The kernel then disables that
2110 * interrupt source and so prevents the other device from working properly.
2112 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2113 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2115 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2116 * rows, which changed the alignment requirements and fence programming.
2118 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2120 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2121 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2122 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2123 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2124 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2126 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2127 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2128 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2130 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2132 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2133 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2134 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2135 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2136 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2138 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2139 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2140 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2141 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2142 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2143 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2145 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2146 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2147 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2148 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2149 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2150 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2152 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2154 /* DPF == dynamic parity feature */
2155 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2156 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2158 #define GT_FREQUENCY_MULTIPLIER 50
2160 #include "i915_trace.h"
2162 extern const struct drm_ioctl_desc i915_ioctls
[];
2163 extern int i915_max_ioctl
;
2165 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
2166 extern int i915_resume(struct drm_device
*dev
);
2167 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2168 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2171 struct i915_params
{
2173 int panel_ignore_lid
;
2174 unsigned int powersave
;
2176 unsigned int lvds_downclock
;
2177 int lvds_channel_mode
;
2179 int vbt_sdvo_panel_type
;
2183 int enable_execlists
;
2185 unsigned int preliminary_hw_support
;
2186 int disable_power_well
;
2188 int invert_brightness
;
2189 int enable_cmd_parser
;
2190 /* leave bools at the end to not create holes */
2191 bool enable_hangcheck
;
2193 bool prefault_disable
;
2195 bool disable_display
;
2196 bool disable_vtd_wa
;
2200 extern struct i915_params i915 __read_mostly
;
2203 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2204 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2205 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2206 extern int i915_driver_unload(struct drm_device
*);
2207 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2208 extern void i915_driver_lastclose(struct drm_device
* dev
);
2209 extern void i915_driver_preclose(struct drm_device
*dev
,
2210 struct drm_file
*file
);
2211 extern void i915_driver_postclose(struct drm_device
*dev
,
2212 struct drm_file
*file
);
2213 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2214 #ifdef CONFIG_COMPAT
2215 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2218 extern int i915_emit_box(struct drm_device
*dev
,
2219 struct drm_clip_rect
*box
,
2221 extern int intel_gpu_reset(struct drm_device
*dev
);
2222 extern int i915_reset(struct drm_device
*dev
);
2223 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2224 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2225 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2226 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2227 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2228 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2231 void i915_queue_hangcheck(struct drm_device
*dev
);
2233 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2234 const char *fmt
, ...);
2236 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2238 extern void intel_irq_init(struct drm_device
*dev
);
2239 extern void intel_hpd_init(struct drm_device
*dev
);
2241 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2242 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2243 bool restore_forcewake
);
2244 extern void intel_uncore_init(struct drm_device
*dev
);
2245 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2246 extern void intel_uncore_fini(struct drm_device
*dev
);
2247 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2250 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2254 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2257 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2258 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2261 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2262 struct drm_file
*file_priv
);
2263 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2264 struct drm_file
*file_priv
);
2265 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2266 struct drm_file
*file_priv
);
2267 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2268 struct drm_file
*file_priv
);
2269 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2270 struct drm_file
*file_priv
);
2271 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2272 struct drm_file
*file_priv
);
2273 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2274 struct drm_file
*file_priv
);
2275 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2276 struct drm_file
*file_priv
);
2277 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2278 struct intel_engine_cs
*ring
);
2279 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2280 struct drm_file
*file
,
2281 struct intel_engine_cs
*ring
,
2282 struct drm_i915_gem_object
*obj
);
2283 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2284 struct drm_file
*file
,
2285 struct intel_engine_cs
*ring
,
2286 struct intel_context
*ctx
,
2287 struct drm_i915_gem_execbuffer2
*args
,
2288 struct list_head
*vmas
,
2289 struct drm_i915_gem_object
*batch_obj
,
2290 u64 exec_start
, u32 flags
);
2291 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2292 struct drm_file
*file_priv
);
2293 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2294 struct drm_file
*file_priv
);
2295 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2296 struct drm_file
*file_priv
);
2297 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2298 struct drm_file
*file_priv
);
2299 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2300 struct drm_file
*file_priv
);
2301 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2302 struct drm_file
*file
);
2303 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2304 struct drm_file
*file
);
2305 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2306 struct drm_file
*file_priv
);
2307 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2308 struct drm_file
*file_priv
);
2309 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2310 struct drm_file
*file_priv
);
2311 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2312 struct drm_file
*file_priv
);
2313 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2314 struct drm_file
*file_priv
);
2315 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2316 struct drm_file
*file_priv
);
2317 int i915_gem_init_userptr(struct drm_device
*dev
);
2318 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2319 struct drm_file
*file
);
2320 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2321 struct drm_file
*file_priv
);
2322 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2323 struct drm_file
*file_priv
);
2324 void i915_gem_load(struct drm_device
*dev
);
2325 void *i915_gem_object_alloc(struct drm_device
*dev
);
2326 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2327 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2328 const struct drm_i915_gem_object_ops
*ops
);
2329 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2331 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2332 struct i915_address_space
*vm
);
2333 void i915_gem_free_object(struct drm_gem_object
*obj
);
2334 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2336 #define PIN_MAPPABLE 0x1
2337 #define PIN_NONBLOCK 0x2
2338 #define PIN_GLOBAL 0x4
2339 #define PIN_OFFSET_BIAS 0x8
2340 #define PIN_OFFSET_MASK (~4095)
2341 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2342 struct i915_address_space
*vm
,
2345 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2346 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2347 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2348 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2349 void i915_gem_lastclose(struct drm_device
*dev
);
2351 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2352 int *needs_clflush
);
2354 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2355 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2357 struct sg_page_iter sg_iter
;
2359 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2360 return sg_page_iter_page(&sg_iter
);
2364 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2366 BUG_ON(obj
->pages
== NULL
);
2367 obj
->pages_pin_count
++;
2369 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2371 BUG_ON(obj
->pages_pin_count
== 0);
2372 obj
->pages_pin_count
--;
2375 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2376 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2377 struct intel_engine_cs
*to
);
2378 void i915_vma_move_to_active(struct i915_vma
*vma
,
2379 struct intel_engine_cs
*ring
);
2380 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2381 struct drm_device
*dev
,
2382 struct drm_mode_create_dumb
*args
);
2383 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2384 uint32_t handle
, uint64_t *offset
);
2386 * Returns true if seq1 is later than seq2.
2389 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2391 return (int32_t)(seq1
- seq2
) >= 0;
2394 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2395 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2396 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2397 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2399 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2400 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2402 struct drm_i915_gem_request
*
2403 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2405 bool i915_gem_retire_requests(struct drm_device
*dev
);
2406 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2407 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2408 bool interruptible
);
2409 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2411 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2413 return unlikely(atomic_read(&error
->reset_counter
)
2414 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2417 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2419 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2422 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2424 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2427 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2429 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2430 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2433 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2435 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2436 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2439 void i915_gem_reset(struct drm_device
*dev
);
2440 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2441 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2442 int __must_check
i915_gem_init(struct drm_device
*dev
);
2443 int i915_gem_init_rings(struct drm_device
*dev
);
2444 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2445 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2446 void i915_gem_init_swizzling(struct drm_device
*dev
);
2447 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2448 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2449 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2450 int __i915_add_request(struct intel_engine_cs
*ring
,
2451 struct drm_file
*file
,
2452 struct drm_i915_gem_object
*batch_obj
,
2454 #define i915_add_request(ring, seqno) \
2455 __i915_add_request(ring, NULL, NULL, seqno)
2456 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2458 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2460 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2463 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2465 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2467 struct intel_engine_cs
*pipelined
);
2468 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2469 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2471 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2472 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2475 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2477 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2478 int tiling_mode
, bool fenced
);
2480 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2481 enum i915_cache_level cache_level
);
2483 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2484 struct dma_buf
*dma_buf
);
2486 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2487 struct drm_gem_object
*gem_obj
, int flags
);
2489 void i915_gem_restore_fences(struct drm_device
*dev
);
2491 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2492 struct i915_address_space
*vm
);
2493 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2494 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2495 struct i915_address_space
*vm
);
2496 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2497 struct i915_address_space
*vm
);
2498 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2499 struct i915_address_space
*vm
);
2501 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2502 struct i915_address_space
*vm
);
2504 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2505 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2506 struct i915_vma
*vma
;
2507 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2508 if (vma
->pin_count
> 0)
2513 /* Some GGTT VM helpers */
2514 #define i915_obj_to_ggtt(obj) \
2515 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2516 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2518 struct i915_address_space
*ggtt
=
2519 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2523 static inline struct i915_hw_ppgtt
*
2524 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2526 WARN_ON(i915_is_ggtt(vm
));
2528 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2532 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2534 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2537 static inline unsigned long
2538 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2540 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2543 static inline unsigned long
2544 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2546 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2549 static inline int __must_check
2550 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2554 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2555 alignment
, flags
| PIN_GLOBAL
);
2559 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2561 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2564 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2566 /* i915_gem_context.c */
2567 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2568 void i915_gem_context_fini(struct drm_device
*dev
);
2569 void i915_gem_context_reset(struct drm_device
*dev
);
2570 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2571 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2572 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2573 int i915_switch_context(struct intel_engine_cs
*ring
,
2574 struct intel_context
*to
);
2575 struct intel_context
*
2576 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2577 void i915_gem_context_free(struct kref
*ctx_ref
);
2578 struct drm_i915_gem_object
*
2579 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2580 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2582 kref_get(&ctx
->ref
);
2585 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2587 kref_put(&ctx
->ref
, i915_gem_context_free
);
2590 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2592 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2595 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2596 struct drm_file
*file
);
2597 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2598 struct drm_file
*file
);
2600 /* i915_gem_render_state.c */
2601 int i915_gem_render_state_init(struct intel_engine_cs
*ring
);
2602 /* i915_gem_evict.c */
2603 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2604 struct i915_address_space
*vm
,
2607 unsigned cache_level
,
2608 unsigned long start
,
2611 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2612 int i915_gem_evict_everything(struct drm_device
*dev
);
2614 /* belongs in i915_gem_gtt.h */
2615 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2617 if (INTEL_INFO(dev
)->gen
< 6)
2618 intel_gtt_chipset_flush();
2621 /* i915_gem_stolen.c */
2622 int i915_gem_init_stolen(struct drm_device
*dev
);
2623 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2624 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2625 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2626 struct drm_i915_gem_object
*
2627 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2628 struct drm_i915_gem_object
*
2629 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2634 /* i915_gem_tiling.c */
2635 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2637 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2639 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2640 obj
->tiling_mode
!= I915_TILING_NONE
;
2643 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2644 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2645 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2647 /* i915_gem_debug.c */
2649 int i915_verify_lists(struct drm_device
*dev
);
2651 #define i915_verify_lists(dev) 0
2654 /* i915_debugfs.c */
2655 int i915_debugfs_init(struct drm_minor
*minor
);
2656 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2657 #ifdef CONFIG_DEBUG_FS
2658 void intel_display_crc_init(struct drm_device
*dev
);
2660 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2663 /* i915_gpu_error.c */
2665 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2666 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2667 const struct i915_error_state_file_priv
*error
);
2668 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2669 size_t count
, loff_t pos
);
2670 static inline void i915_error_state_buf_release(
2671 struct drm_i915_error_state_buf
*eb
)
2675 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2676 const char *error_msg
);
2677 void i915_error_state_get(struct drm_device
*dev
,
2678 struct i915_error_state_file_priv
*error_priv
);
2679 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2680 void i915_destroy_error_state(struct drm_device
*dev
);
2682 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2683 const char *i915_cache_level_str(int type
);
2685 /* i915_cmd_parser.c */
2686 int i915_cmd_parser_get_version(void);
2687 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2688 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2689 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2690 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2691 struct drm_i915_gem_object
*batch_obj
,
2692 u32 batch_start_offset
,
2695 /* i915_suspend.c */
2696 extern int i915_save_state(struct drm_device
*dev
);
2697 extern int i915_restore_state(struct drm_device
*dev
);
2700 void i915_save_display_reg(struct drm_device
*dev
);
2701 void i915_restore_display_reg(struct drm_device
*dev
);
2704 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2705 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2708 extern int intel_setup_gmbus(struct drm_device
*dev
);
2709 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2710 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2712 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2715 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2716 struct drm_i915_private
*dev_priv
, unsigned port
);
2717 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2718 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2719 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2721 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2723 extern void intel_i2c_reset(struct drm_device
*dev
);
2725 /* intel_opregion.c */
2726 struct intel_encoder
;
2728 extern int intel_opregion_setup(struct drm_device
*dev
);
2729 extern void intel_opregion_init(struct drm_device
*dev
);
2730 extern void intel_opregion_fini(struct drm_device
*dev
);
2731 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2732 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2734 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2737 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2738 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2739 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2740 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2742 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2747 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2755 extern void intel_register_dsm_handler(void);
2756 extern void intel_unregister_dsm_handler(void);
2758 static inline void intel_register_dsm_handler(void) { return; }
2759 static inline void intel_unregister_dsm_handler(void) { return; }
2760 #endif /* CONFIG_ACPI */
2763 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2764 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2765 extern void intel_modeset_init(struct drm_device
*dev
);
2766 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2767 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2768 extern void intel_connector_unregister(struct intel_connector
*);
2769 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2770 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2771 bool force_restore
);
2772 extern void i915_redisable_vga(struct drm_device
*dev
);
2773 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2774 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2775 extern void intel_disable_fbc(struct drm_device
*dev
);
2776 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2777 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2778 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2779 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2780 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2782 extern void intel_detect_pch(struct drm_device
*dev
);
2783 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2784 extern int intel_enable_rc6(const struct drm_device
*dev
);
2786 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2787 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2788 struct drm_file
*file
);
2789 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2790 struct drm_file
*file
);
2792 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2795 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2796 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2797 struct intel_overlay_error_state
*error
);
2799 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2800 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2801 struct drm_device
*dev
,
2802 struct intel_display_error_state
*error
);
2804 /* On SNB platform, before reading ring registers forcewake bit
2805 * must be set to prevent GT core from power down and stale values being
2808 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2809 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2810 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2812 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2813 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2815 /* intel_sideband.c */
2816 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2817 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2818 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2819 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2820 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2821 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2822 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2823 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2824 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2825 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2826 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2827 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2828 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2829 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2830 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2831 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2832 enum intel_sbi_destination destination
);
2833 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2834 enum intel_sbi_destination destination
);
2835 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2836 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2838 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2839 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2841 #define FORCEWAKE_RENDER (1 << 0)
2842 #define FORCEWAKE_MEDIA (1 << 1)
2843 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2846 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2847 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2849 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2850 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2851 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2852 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2854 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2855 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2856 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2857 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2859 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2860 * will be implemented using 2 32-bit writes in an arbitrary order with
2861 * an arbitrary delay between them. This can cause the hardware to
2862 * act upon the intermediate value, possibly leading to corruption and
2863 * machine death. You have been warned.
2865 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2866 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2868 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2869 u32 upper = I915_READ(upper_reg); \
2870 u32 lower = I915_READ(lower_reg); \
2871 u32 tmp = I915_READ(upper_reg); \
2872 if (upper != tmp) { \
2874 lower = I915_READ(lower_reg); \
2875 WARN_ON(I915_READ(upper_reg) != upper); \
2877 (u64)upper << 32 | lower; })
2879 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2880 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2882 /* "Broadcast RGB" property */
2883 #define INTEL_BROADCAST_RGB_AUTO 0
2884 #define INTEL_BROADCAST_RGB_FULL 1
2885 #define INTEL_BROADCAST_RGB_LIMITED 2
2887 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2889 if (IS_VALLEYVIEW(dev
))
2890 return VLV_VGACNTRL
;
2891 else if (INTEL_INFO(dev
)->gen
>= 5)
2892 return CPU_VGACNTRL
;
2897 static inline void __user
*to_user_ptr(u64 address
)
2899 return (void __user
*)(uintptr_t)address
;
2902 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2904 unsigned long j
= msecs_to_jiffies(m
);
2906 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2909 static inline unsigned long
2910 timespec_to_jiffies_timeout(const struct timespec
*value
)
2912 unsigned long j
= timespec_to_jiffies(value
);
2914 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2918 * If you need to wait X milliseconds between events A and B, but event B
2919 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2920 * when event A happened, then just before event B you call this function and
2921 * pass the timestamp as the first argument, and X as the second argument.
2924 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
2926 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
2929 * Don't re-read the value of "jiffies" every time since it may change
2930 * behind our back and break the math.
2932 tmp_jiffies
= jiffies
;
2933 target_jiffies
= timestamp_jiffies
+
2934 msecs_to_jiffies_timeout(to_wait_ms
);
2936 if (time_after(target_jiffies
, tmp_jiffies
)) {
2937 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
2938 while (remaining_jiffies
)
2940 schedule_timeout_uninterruptible(remaining_jiffies
);