1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
79 #define sprite_name(p, s) ((p) * dev_priv->num_plane + (s) + 'A')
89 #define port_name(p) ((p) + 'A')
91 enum intel_display_power_domain
{
95 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
96 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
97 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
98 POWER_DOMAIN_TRANSCODER_A
,
99 POWER_DOMAIN_TRANSCODER_B
,
100 POWER_DOMAIN_TRANSCODER_C
,
101 POWER_DOMAIN_TRANSCODER_EDP
= POWER_DOMAIN_TRANSCODER_A
+ 0xF,
104 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
105 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
106 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
107 #define POWER_DOMAIN_TRANSCODER(tran) ((tran) + POWER_DOMAIN_TRANSCODER_A)
111 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
112 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
122 #define I915_GEM_GPU_DOMAINS \
123 (I915_GEM_DOMAIN_RENDER | \
124 I915_GEM_DOMAIN_SAMPLER | \
125 I915_GEM_DOMAIN_COMMAND | \
126 I915_GEM_DOMAIN_INSTRUCTION | \
127 I915_GEM_DOMAIN_VERTEX)
129 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
131 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
132 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
133 if ((intel_encoder)->base.crtc == (__crtc))
135 struct drm_i915_private
;
138 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
139 /* real shared dpll ids must be >= 0 */
143 #define I915_NUM_PLLS 2
145 struct intel_dpll_hw_state
{
152 struct intel_shared_dpll
{
153 int refcount
; /* count of number of CRTCs sharing this PLL */
154 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
155 bool on
; /* is the PLL actually active? Disabled during modeset */
157 /* should match the index in the dev_priv->shared_dplls array */
158 enum intel_dpll_id id
;
159 struct intel_dpll_hw_state hw_state
;
160 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
161 struct intel_shared_dpll
*pll
);
162 void (*enable
)(struct drm_i915_private
*dev_priv
,
163 struct intel_shared_dpll
*pll
);
164 void (*disable
)(struct drm_i915_private
*dev_priv
,
165 struct intel_shared_dpll
*pll
);
166 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
167 struct intel_shared_dpll
*pll
,
168 struct intel_dpll_hw_state
*hw_state
);
171 /* Used by dp and fdi links */
172 struct intel_link_m_n
{
180 void intel_link_compute_m_n(int bpp
, int nlanes
,
181 int pixel_clock
, int link_clock
,
182 struct intel_link_m_n
*m_n
);
184 struct intel_ddi_plls
{
190 /* Interface history:
193 * 1.2: Add Power Management
194 * 1.3: Add vblank support
195 * 1.4: Fix cmdbuffer path, add heap destroy
196 * 1.5: Add vblank pipe configuration
197 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
198 * - Support vertical blank on secondary display pipe
200 #define DRIVER_MAJOR 1
201 #define DRIVER_MINOR 6
202 #define DRIVER_PATCHLEVEL 0
204 #define WATCH_COHERENCY 0
205 #define WATCH_LISTS 0
208 #define I915_GEM_PHYS_CURSOR_0 1
209 #define I915_GEM_PHYS_CURSOR_1 2
210 #define I915_GEM_PHYS_OVERLAY_REGS 3
211 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
213 struct drm_i915_gem_phys_object
{
215 struct page
**page_list
;
216 drm_dma_handle_t
*handle
;
217 struct drm_i915_gem_object
*cur_obj
;
220 struct opregion_header
;
221 struct opregion_acpi
;
222 struct opregion_swsci
;
223 struct opregion_asle
;
225 struct intel_opregion
{
226 struct opregion_header __iomem
*header
;
227 struct opregion_acpi __iomem
*acpi
;
228 struct opregion_swsci __iomem
*swsci
;
229 struct opregion_asle __iomem
*asle
;
231 u32 __iomem
*lid_state
;
233 #define OPREGION_SIZE (8*1024)
235 struct intel_overlay
;
236 struct intel_overlay_error_state
;
238 struct drm_i915_master_private
{
239 drm_local_map_t
*sarea
;
240 struct _drm_i915_sarea
*sarea_priv
;
242 #define I915_FENCE_REG_NONE -1
243 #define I915_MAX_NUM_FENCES 32
244 /* 32 fences + sign bit for FENCE_REG_NONE */
245 #define I915_MAX_NUM_FENCE_BITS 6
247 struct drm_i915_fence_reg
{
248 struct list_head lru_list
;
249 struct drm_i915_gem_object
*obj
;
253 struct sdvo_device_mapping
{
262 struct intel_display_error_state
;
264 struct drm_i915_error_state
{
272 bool waiting
[I915_NUM_RINGS
];
273 u32 pipestat
[I915_MAX_PIPES
];
274 u32 tail
[I915_NUM_RINGS
];
275 u32 head
[I915_NUM_RINGS
];
276 u32 ctl
[I915_NUM_RINGS
];
277 u32 ipeir
[I915_NUM_RINGS
];
278 u32 ipehr
[I915_NUM_RINGS
];
279 u32 instdone
[I915_NUM_RINGS
];
280 u32 acthd
[I915_NUM_RINGS
];
281 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
282 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
283 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
284 /* our own tracking of ring head and tail */
285 u32 cpu_ring_head
[I915_NUM_RINGS
];
286 u32 cpu_ring_tail
[I915_NUM_RINGS
];
287 u32 error
; /* gen6+ */
288 u32 err_int
; /* gen7 */
289 u32 instpm
[I915_NUM_RINGS
];
290 u32 instps
[I915_NUM_RINGS
];
291 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
292 u32 seqno
[I915_NUM_RINGS
];
294 u32 fault_reg
[I915_NUM_RINGS
];
296 u32 faddr
[I915_NUM_RINGS
];
297 u64 fence
[I915_MAX_NUM_FENCES
];
299 struct drm_i915_error_ring
{
300 struct drm_i915_error_object
{
304 } *ringbuffer
, *batchbuffer
, *ctx
;
305 struct drm_i915_error_request
{
311 } ring
[I915_NUM_RINGS
];
312 struct drm_i915_error_buffer
{
319 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
326 } *active_bo
, *pinned_bo
;
327 u32 active_bo_count
, pinned_bo_count
;
328 struct intel_overlay_error_state
*overlay
;
329 struct intel_display_error_state
*display
;
332 struct intel_crtc_config
;
337 struct drm_i915_display_funcs
{
338 bool (*fbc_enabled
)(struct drm_device
*dev
);
339 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
340 void (*disable_fbc
)(struct drm_device
*dev
);
341 int (*get_display_clock_speed
)(struct drm_device
*dev
);
342 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
344 * find_dpll() - Find the best values for the PLL
345 * @limit: limits for the PLL
346 * @crtc: current CRTC
347 * @target: target frequency in kHz
348 * @refclk: reference clock frequency in kHz
349 * @match_clock: if provided, @best_clock P divider must
350 * match the P divider from @match_clock
351 * used for LVDS downclocking
352 * @best_clock: best PLL values found
354 * Returns true on success, false on failure.
356 bool (*find_dpll
)(const struct intel_limit
*limit
,
357 struct drm_crtc
*crtc
,
358 int target
, int refclk
,
359 struct dpll
*match_clock
,
360 struct dpll
*best_clock
);
361 void (*update_wm
)(struct drm_device
*dev
);
362 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
363 uint32_t sprite_width
, int pixel_size
,
364 bool enable
, bool scaled
);
365 void (*modeset_global_resources
)(struct drm_device
*dev
);
366 /* Returns the active state of the crtc, and if the crtc is active,
367 * fills out the pipe-config with the hw state. */
368 bool (*get_pipe_config
)(struct intel_crtc
*,
369 struct intel_crtc_config
*);
370 void (*get_clock
)(struct intel_crtc
*, struct intel_crtc_config
*);
371 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
373 struct drm_framebuffer
*old_fb
);
374 void (*crtc_enable
)(struct drm_crtc
*crtc
);
375 void (*crtc_disable
)(struct drm_crtc
*crtc
);
376 void (*off
)(struct drm_crtc
*crtc
);
377 void (*write_eld
)(struct drm_connector
*connector
,
378 struct drm_crtc
*crtc
);
379 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
380 void (*init_clock_gating
)(struct drm_device
*dev
);
381 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
382 struct drm_framebuffer
*fb
,
383 struct drm_i915_gem_object
*obj
);
384 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
386 void (*hpd_irq_setup
)(struct drm_device
*dev
);
387 /* clock updates for mode set */
389 /* render clock increase/decrease */
390 /* display clock increase/decrease */
391 /* pll clock increase/decrease */
394 struct intel_uncore_funcs
{
395 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
396 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
399 struct intel_uncore
{
400 spinlock_t lock
; /** lock is also taken in irq contexts. */
402 struct intel_uncore_funcs funcs
;
405 unsigned forcewake_count
;
408 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
409 func(is_mobile) sep \
412 func(is_i945gm) sep \
414 func(need_gfx_hws) sep \
416 func(is_pineview) sep \
417 func(is_broadwater) sep \
418 func(is_crestline) sep \
419 func(is_ivybridge) sep \
420 func(is_valleyview) sep \
421 func(is_haswell) sep \
422 func(has_force_wake) sep \
424 func(has_pipe_cxsr) sep \
425 func(has_hotplug) sep \
426 func(cursor_needs_physical) sep \
427 func(has_overlay) sep \
428 func(overlay_needs_physical) sep \
429 func(supports_tv) sep \
430 func(has_bsd_ring) sep \
431 func(has_blt_ring) sep \
432 func(has_vebox_ring) sep \
437 #define DEFINE_FLAG(name) u8 name:1
438 #define SEP_SEMICOLON ;
440 struct intel_device_info
{
441 u32 display_mmio_offset
;
444 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
450 enum i915_cache_level
{
452 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
453 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
454 caches, eg sampler/render caches, and the
455 large Last-Level-Cache. LLC is coherent with
456 the CPU, but L3 is only visible to the GPU. */
459 typedef uint32_t gen6_gtt_pte_t
;
461 struct i915_address_space
{
463 struct drm_device
*dev
;
464 struct list_head global_link
;
465 unsigned long start
; /* Start offset always 0 for dri2 */
466 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
474 * List of objects currently involved in rendering.
476 * Includes buffers having the contents of their GPU caches
477 * flushed, not necessarily primitives. last_rendering_seqno
478 * represents when the rendering involved will be completed.
480 * A reference is held on the buffer while on this list.
482 struct list_head active_list
;
485 * LRU list of objects which are not in the ringbuffer and
486 * are ready to unbind, but are still in the GTT.
488 * last_rendering_seqno is 0 while an object is in this list.
490 * A reference is not held on the buffer while on this list,
491 * as merely being GTT-bound shouldn't prevent its being
492 * freed, and we'll pull it off the list in the free path.
494 struct list_head inactive_list
;
496 /* FIXME: Need a more generic return type */
497 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
498 enum i915_cache_level level
);
499 void (*clear_range
)(struct i915_address_space
*vm
,
500 unsigned int first_entry
,
501 unsigned int num_entries
);
502 void (*insert_entries
)(struct i915_address_space
*vm
,
504 unsigned int first_entry
,
505 enum i915_cache_level cache_level
);
506 void (*cleanup
)(struct i915_address_space
*vm
);
509 /* The Graphics Translation Table is the way in which GEN hardware translates a
510 * Graphics Virtual Address into a Physical Address. In addition to the normal
511 * collateral associated with any va->pa translations GEN hardware also has a
512 * portion of the GTT which can be mapped by the CPU and remain both coherent
513 * and correct (in cases like swizzling). That region is referred to as GMADR in
517 struct i915_address_space base
;
518 size_t stolen_size
; /* Total size of stolen memory */
520 unsigned long mappable_end
; /* End offset that we can CPU map */
521 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
522 phys_addr_t mappable_base
; /* PA of our GMADR */
524 /** "Graphics Stolen Memory" holds the global PTEs */
532 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
533 size_t *stolen
, phys_addr_t
*mappable_base
,
534 unsigned long *mappable_end
);
536 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
538 struct i915_hw_ppgtt
{
539 struct i915_address_space base
;
540 unsigned num_pd_entries
;
541 struct page
**pt_pages
;
543 dma_addr_t
*pt_dma_addr
;
545 int (*enable
)(struct drm_device
*dev
);
549 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
550 * VMA's presence cannot be guaranteed before binding, or after unbinding the
551 * object into/from the address space.
553 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
554 * will always be <= an objects lifetime. So object refcounting should cover us.
557 struct drm_mm_node node
;
558 struct drm_i915_gem_object
*obj
;
559 struct i915_address_space
*vm
;
561 struct list_head vma_link
; /* Link in the object's VMA list */
564 struct i915_ctx_hang_stats
{
565 /* This context had batch pending when hang was declared */
566 unsigned batch_pending
;
568 /* This context had batch active when hang was declared */
569 unsigned batch_active
;
572 /* This must match up with the value previously used for execbuf2.rsvd1. */
573 #define DEFAULT_CONTEXT_ID 0
574 struct i915_hw_context
{
578 struct drm_i915_file_private
*file_priv
;
579 struct intel_ring_buffer
*ring
;
580 struct drm_i915_gem_object
*obj
;
581 struct i915_ctx_hang_stats hang_stats
;
590 struct drm_mm_node
*compressed_fb
;
591 struct drm_mm_node
*compressed_llb
;
593 struct intel_fbc_work
{
594 struct delayed_work work
;
595 struct drm_crtc
*crtc
;
596 struct drm_framebuffer
*fb
;
601 FBC_OK
, /* FBC is enabled */
602 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
603 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
604 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
605 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
606 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
607 FBC_BAD_PLANE
, /* fbc not supported on plane */
608 FBC_NOT_TILED
, /* buffer not tiled */
609 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
611 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
616 PSR_NO_SOURCE
, /* Not supported on platform */
617 PSR_NO_SINK
, /* Not supported by panel */
620 PSR_PWR_WELL_ENABLED
,
624 PSR_INTERLACED_ENABLED
,
629 PCH_NONE
= 0, /* No PCH present */
630 PCH_IBX
, /* Ibexpeak PCH */
631 PCH_CPT
, /* Cougarpoint PCH */
632 PCH_LPT
, /* Lynxpoint PCH */
636 enum intel_sbi_destination
{
641 #define QUIRK_PIPEA_FORCE (1<<0)
642 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
643 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
644 #define QUIRK_NO_PCH_PWM_ENABLE (1<<3)
647 struct intel_fbc_work
;
650 struct i2c_adapter adapter
;
654 struct i2c_algo_bit_data bit_algo
;
655 struct drm_i915_private
*dev_priv
;
658 struct i915_suspend_saved_registers
{
679 u32 saveTRANS_HTOTAL_A
;
680 u32 saveTRANS_HBLANK_A
;
681 u32 saveTRANS_HSYNC_A
;
682 u32 saveTRANS_VTOTAL_A
;
683 u32 saveTRANS_VBLANK_A
;
684 u32 saveTRANS_VSYNC_A
;
692 u32 savePFIT_PGM_RATIOS
;
693 u32 saveBLC_HIST_CTL
;
695 u32 saveBLC_PWM_CTL2
;
696 u32 saveBLC_CPU_PWM_CTL
;
697 u32 saveBLC_CPU_PWM_CTL2
;
710 u32 saveTRANS_HTOTAL_B
;
711 u32 saveTRANS_HBLANK_B
;
712 u32 saveTRANS_HSYNC_B
;
713 u32 saveTRANS_VTOTAL_B
;
714 u32 saveTRANS_VBLANK_B
;
715 u32 saveTRANS_VSYNC_B
;
729 u32 savePP_ON_DELAYS
;
730 u32 savePP_OFF_DELAYS
;
738 u32 savePFIT_CONTROL
;
739 u32 save_palette_a
[256];
740 u32 save_palette_b
[256];
741 u32 saveDPFC_CB_BASE
;
742 u32 saveFBC_CFB_BASE
;
745 u32 saveFBC_CONTROL2
;
755 u32 saveCACHE_MODE_0
;
756 u32 saveMI_ARB_STATE
;
767 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
778 u32 savePIPEA_GMCH_DATA_M
;
779 u32 savePIPEB_GMCH_DATA_M
;
780 u32 savePIPEA_GMCH_DATA_N
;
781 u32 savePIPEB_GMCH_DATA_N
;
782 u32 savePIPEA_DP_LINK_M
;
783 u32 savePIPEB_DP_LINK_M
;
784 u32 savePIPEA_DP_LINK_N
;
785 u32 savePIPEB_DP_LINK_N
;
796 u32 savePCH_DREF_CONTROL
;
797 u32 saveDISP_ARB_CTL
;
798 u32 savePIPEA_DATA_M1
;
799 u32 savePIPEA_DATA_N1
;
800 u32 savePIPEA_LINK_M1
;
801 u32 savePIPEA_LINK_N1
;
802 u32 savePIPEB_DATA_M1
;
803 u32 savePIPEB_DATA_N1
;
804 u32 savePIPEB_LINK_M1
;
805 u32 savePIPEB_LINK_N1
;
806 u32 saveMCHBAR_RENDER_STANDBY
;
807 u32 savePCH_PORT_HOTPLUG
;
810 struct intel_gen6_power_mgmt
{
811 /* work and pm_iir are protected by dev_priv->irq_lock */
812 struct work_struct work
;
815 /* On vlv we need to manually drop to Vmin with a delayed work. */
816 struct delayed_work vlv_work
;
818 /* The below variables an all the rps hw state are protected by
819 * dev->struct mutext. */
826 struct delayed_work delayed_resume_work
;
829 * Protects RPS/RC6 register access and PCU communication.
830 * Must be taken after struct_mutex if nested.
832 struct mutex hw_lock
;
835 /* defined intel_pm.c */
836 extern spinlock_t mchdev_lock
;
838 struct intel_ilk_power_mgmt
{
846 unsigned long last_time1
;
847 unsigned long chipset_power
;
849 struct timespec last_time2
;
850 unsigned long gfx_power
;
856 struct drm_i915_gem_object
*pwrctx
;
857 struct drm_i915_gem_object
*renderctx
;
860 /* Power well structure for haswell */
861 struct i915_power_well
{
862 struct drm_device
*device
;
864 /* power well enable/disable usage count */
869 struct i915_dri1_state
{
870 unsigned allow_batchbuffer
: 1;
871 u32 __iomem
*gfx_hws_cpu_addr
;
882 struct i915_ums_state
{
884 * Flag if the X Server, and thus DRM, is not currently in
885 * control of the device.
887 * This is set between LeaveVT and EnterVT. It needs to be
888 * replaced with a semaphore. It also needs to be
889 * transitioned away from for kernel modesetting.
894 struct intel_l3_parity
{
896 struct work_struct error_work
;
900 /** Memory allocator for GTT stolen memory */
901 struct drm_mm stolen
;
902 /** List of all objects in gtt_space. Used to restore gtt
903 * mappings on resume */
904 struct list_head bound_list
;
906 * List of objects which are not bound to the GTT (thus
907 * are idle and not used by the GPU) but still have
908 * (presumably uncached) pages still attached.
910 struct list_head unbound_list
;
912 /** Usable portion of the GTT for GEM */
913 unsigned long stolen_base
; /* limited to low memory (32-bit) */
915 /** PPGTT used for aliasing the PPGTT with the GTT */
916 struct i915_hw_ppgtt
*aliasing_ppgtt
;
918 struct shrinker inactive_shrinker
;
919 bool shrinker_no_lock_stealing
;
921 /** LRU list of objects with fence regs on them. */
922 struct list_head fence_list
;
925 * We leave the user IRQ off as much as possible,
926 * but this means that requests will finish and never
927 * be retired once the system goes idle. Set a timer to
928 * fire periodically while the ring is running. When it
929 * fires, go retire requests.
931 struct delayed_work retire_work
;
934 * Are we in a non-interruptible section of code like
939 /** Bit 6 swizzling required for X tiling */
940 uint32_t bit_6_swizzle_x
;
941 /** Bit 6 swizzling required for Y tiling */
942 uint32_t bit_6_swizzle_y
;
944 /* storage for physical objects */
945 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
947 /* accounting, useful for userland debugging */
948 spinlock_t object_stat_lock
;
949 size_t object_memory
;
953 struct drm_i915_error_state_buf
{
962 struct i915_error_state_file_priv
{
963 struct drm_device
*dev
;
964 struct drm_i915_error_state
*error
;
967 struct i915_gpu_error
{
968 /* For hangcheck timer */
969 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
970 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
971 struct timer_list hangcheck_timer
;
973 /* For reset and error_state handling. */
975 /* Protected by the above dev->gpu_error.lock. */
976 struct drm_i915_error_state
*first_error
;
977 struct work_struct work
;
979 unsigned long last_reset
;
982 * State variable and reset counter controlling the reset flow
984 * Upper bits are for the reset counter. This counter is used by the
985 * wait_seqno code to race-free noticed that a reset event happened and
986 * that it needs to restart the entire ioctl (since most likely the
987 * seqno it waited for won't ever signal anytime soon).
989 * This is important for lock-free wait paths, where no contended lock
990 * naturally enforces the correct ordering between the bail-out of the
991 * waiter and the gpu reset work code.
993 * Lowest bit controls the reset state machine: Set means a reset is in
994 * progress. This state will (presuming we don't have any bugs) decay
995 * into either unset (successful reset) or the special WEDGED value (hw
996 * terminally sour). All waiters on the reset_queue will be woken when
999 atomic_t reset_counter
;
1002 * Special values/flags for reset_counter
1004 * Note that the code relies on
1005 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
1008 #define I915_RESET_IN_PROGRESS_FLAG 1
1009 #define I915_WEDGED 0xffffffff
1012 * Waitqueue to signal when the reset has completed. Used by clients
1013 * that wait for dev_priv->mm.wedged to settle.
1015 wait_queue_head_t reset_queue
;
1017 /* For gpu hang simulation. */
1018 unsigned int stop_rings
;
1021 enum modeset_restore
{
1022 MODESET_ON_LID_OPEN
,
1027 struct intel_vbt_data
{
1028 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1029 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1032 unsigned int int_tv_support
:1;
1033 unsigned int lvds_dither
:1;
1034 unsigned int lvds_vbt
:1;
1035 unsigned int int_crt_support
:1;
1036 unsigned int lvds_use_ssc
:1;
1037 unsigned int display_clock_mode
:1;
1038 unsigned int fdi_rx_polarity_inverted
:1;
1040 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1045 int edp_preemphasis
;
1047 bool edp_initialized
;
1050 struct edp_power_seq edp_pps
;
1055 struct child_device_config
*child_dev
;
1058 typedef struct drm_i915_private
{
1059 struct drm_device
*dev
;
1060 struct kmem_cache
*slab
;
1062 const struct intel_device_info
*info
;
1064 int relative_constants_mode
;
1068 struct intel_uncore uncore
;
1070 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1073 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1074 * controller on different i2c buses. */
1075 struct mutex gmbus_mutex
;
1078 * Base address of the gmbus and gpio block.
1080 uint32_t gpio_mmio_base
;
1082 wait_queue_head_t gmbus_wait_queue
;
1084 struct pci_dev
*bridge_dev
;
1085 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1086 uint32_t last_seqno
, next_seqno
;
1088 drm_dma_handle_t
*status_page_dmah
;
1089 struct resource mch_res
;
1091 atomic_t irq_received
;
1093 /* protects the irq masks */
1094 spinlock_t irq_lock
;
1096 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1097 struct pm_qos_request pm_qos
;
1099 /* DPIO indirect register protection */
1100 struct mutex dpio_lock
;
1102 /** Cached value of IMR to avoid reads in updating the bitfield */
1106 struct work_struct hotplug_work
;
1107 bool enable_hotplug_processing
;
1109 unsigned long hpd_last_jiffies
;
1114 HPD_MARK_DISABLED
= 2
1116 } hpd_stats
[HPD_NUM_PINS
];
1118 struct timer_list hotplug_reenable_timer
;
1122 struct i915_fbc fbc
;
1123 struct intel_opregion opregion
;
1124 struct intel_vbt_data vbt
;
1127 struct intel_overlay
*overlay
;
1128 unsigned int sprite_scaling_enabled
;
1134 spinlock_t lock
; /* bl registers and the above bl fields */
1135 struct backlight_device
*device
;
1139 bool no_aux_handshake
;
1141 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1142 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1143 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1145 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1147 struct workqueue_struct
*wq
;
1149 /* Display functions */
1150 struct drm_i915_display_funcs display
;
1152 /* PCH chipset type */
1153 enum intel_pch pch_type
;
1154 unsigned short pch_id
;
1156 unsigned long quirks
;
1158 enum modeset_restore modeset_restore
;
1159 struct mutex modeset_restore_lock
;
1161 struct list_head vm_list
; /* Global list of all address spaces */
1162 struct i915_gtt gtt
; /* VMA representing the global address space */
1164 struct i915_gem_mm mm
;
1166 /* Kernel Modesetting */
1168 struct sdvo_device_mapping sdvo_mappings
[2];
1170 struct drm_crtc
*plane_to_crtc_mapping
[3];
1171 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1172 wait_queue_head_t pending_flip_queue
;
1174 int num_shared_dpll
;
1175 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1176 struct intel_ddi_plls ddi_plls
;
1178 /* Reclocking support */
1179 bool render_reclock_avail
;
1180 bool lvds_downclock_avail
;
1181 /* indicates the reduced downclock for LVDS*/
1185 bool mchbar_need_disable
;
1187 struct intel_l3_parity l3_parity
;
1189 /* Cannot be determined by PCIID. You must always read a register. */
1192 /* gen6+ rps state */
1193 struct intel_gen6_power_mgmt rps
;
1195 /* ilk-only ips/rps state. Everything in here is protected by the global
1196 * mchdev_lock in intel_pm.c */
1197 struct intel_ilk_power_mgmt ips
;
1199 /* Haswell power well */
1200 struct i915_power_well power_well
;
1202 enum no_psr_reason no_psr_reason
;
1204 struct i915_gpu_error gpu_error
;
1206 struct drm_i915_gem_object
*vlv_pctx
;
1208 /* list of fbdev register on this device */
1209 struct intel_fbdev
*fbdev
;
1212 * The console may be contended at resume, but we don't
1213 * want it to block on it.
1215 struct work_struct console_resume_work
;
1217 struct drm_property
*broadcast_rgb_property
;
1218 struct drm_property
*force_audio_property
;
1220 bool hw_contexts_disabled
;
1221 uint32_t hw_context_size
;
1225 struct i915_suspend_saved_registers regfile
;
1229 * Raw watermark latency values:
1230 * in 0.1us units for WM0,
1231 * in 0.5us units for WM1+.
1234 uint16_t pri_latency
[5];
1236 uint16_t spr_latency
[5];
1238 uint16_t cur_latency
[5];
1241 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1243 struct i915_dri1_state dri1
;
1244 /* Old ums support infrastructure, same warning applies. */
1245 struct i915_ums_state ums
;
1246 } drm_i915_private_t
;
1248 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1250 return dev
->dev_private
;
1253 /* Iterate over initialised rings */
1254 #define for_each_ring(ring__, dev_priv__, i__) \
1255 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1256 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1258 enum hdmi_force_audio
{
1259 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1260 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1261 HDMI_AUDIO_AUTO
, /* trust EDID */
1262 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1265 #define I915_GTT_OFFSET_NONE ((u32)-1)
1267 struct drm_i915_gem_object_ops
{
1268 /* Interface between the GEM object and its backing storage.
1269 * get_pages() is called once prior to the use of the associated set
1270 * of pages before to binding them into the GTT, and put_pages() is
1271 * called after we no longer need them. As we expect there to be
1272 * associated cost with migrating pages between the backing storage
1273 * and making them available for the GPU (e.g. clflush), we may hold
1274 * onto the pages after they are no longer referenced by the GPU
1275 * in case they may be used again shortly (for example migrating the
1276 * pages to a different memory domain within the GTT). put_pages()
1277 * will therefore most likely be called when the object itself is
1278 * being released or under memory pressure (where we attempt to
1279 * reap pages for the shrinker).
1281 int (*get_pages
)(struct drm_i915_gem_object
*);
1282 void (*put_pages
)(struct drm_i915_gem_object
*);
1285 struct drm_i915_gem_object
{
1286 struct drm_gem_object base
;
1288 const struct drm_i915_gem_object_ops
*ops
;
1290 /** List of VMAs backed by this object */
1291 struct list_head vma_list
;
1293 /** Stolen memory for this object, instead of being backed by shmem. */
1294 struct drm_mm_node
*stolen
;
1295 struct list_head global_list
;
1297 /** This object's place on the active/inactive lists */
1298 struct list_head ring_list
;
1299 struct list_head mm_list
;
1300 /** This object's place in the batchbuffer or on the eviction list */
1301 struct list_head exec_list
;
1304 * This is set if the object is on the active lists (has pending
1305 * rendering and so a non-zero seqno), and is not set if it i s on
1306 * inactive (ready to be unbound) list.
1308 unsigned int active
:1;
1311 * This is set if the object has been written to since last bound
1314 unsigned int dirty
:1;
1317 * Fence register bits (if any) for this object. Will be set
1318 * as needed when mapped into the GTT.
1319 * Protected by dev->struct_mutex.
1321 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1324 * Advice: are the backing pages purgeable?
1326 unsigned int madv
:2;
1329 * Current tiling mode for the object.
1331 unsigned int tiling_mode
:2;
1333 * Whether the tiling parameters for the currently associated fence
1334 * register have changed. Note that for the purposes of tracking
1335 * tiling changes we also treat the unfenced register, the register
1336 * slot that the object occupies whilst it executes a fenced
1337 * command (such as BLT on gen2/3), as a "fence".
1339 unsigned int fence_dirty
:1;
1341 /** How many users have pinned this object in GTT space. The following
1342 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1343 * (via user_pin_count), execbuffer (objects are not allowed multiple
1344 * times for the same batchbuffer), and the framebuffer code. When
1345 * switching/pageflipping, the framebuffer code has at most two buffers
1348 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1349 * bits with absolutely no headroom. So use 4 bits. */
1350 unsigned int pin_count
:4;
1351 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1354 * Is the object at the current location in the gtt mappable and
1355 * fenceable? Used to avoid costly recalculations.
1357 unsigned int map_and_fenceable
:1;
1360 * Whether the current gtt mapping needs to be mappable (and isn't just
1361 * mappable by accident). Track pin and fault separate for a more
1362 * accurate mappable working set.
1364 unsigned int fault_mappable
:1;
1365 unsigned int pin_mappable
:1;
1368 * Is the GPU currently using a fence to access this buffer,
1370 unsigned int pending_fenced_gpu_access
:1;
1371 unsigned int fenced_gpu_access
:1;
1373 unsigned int cache_level
:2;
1375 unsigned int has_aliasing_ppgtt_mapping
:1;
1376 unsigned int has_global_gtt_mapping
:1;
1377 unsigned int has_dma_mapping
:1;
1379 struct sg_table
*pages
;
1380 int pages_pin_count
;
1382 /* prime dma-buf support */
1383 void *dma_buf_vmapping
;
1387 * Used for performing relocations during execbuffer insertion.
1389 struct hlist_node exec_node
;
1390 unsigned long exec_handle
;
1391 struct drm_i915_gem_exec_object2
*exec_entry
;
1393 struct intel_ring_buffer
*ring
;
1395 /** Breadcrumb of last rendering to the buffer. */
1396 uint32_t last_read_seqno
;
1397 uint32_t last_write_seqno
;
1398 /** Breadcrumb of last fenced GPU access to the buffer. */
1399 uint32_t last_fenced_seqno
;
1401 /** Current tiling stride for the object, if it's tiled. */
1404 /** Record of address bit 17 of each page at last unbind. */
1405 unsigned long *bit_17
;
1407 /** User space pin count and filp owning the pin */
1408 uint32_t user_pin_count
;
1409 struct drm_file
*pin_filp
;
1411 /** for phy allocated objects */
1412 struct drm_i915_gem_phys_object
*phys_obj
;
1414 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1416 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1419 * Request queue structure.
1421 * The request queue allows us to note sequence numbers that have been emitted
1422 * and may be associated with active buffers to be retired.
1424 * By keeping this list, we can avoid having to do questionable
1425 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1426 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1428 struct drm_i915_gem_request
{
1429 /** On Which ring this request was generated */
1430 struct intel_ring_buffer
*ring
;
1432 /** GEM sequence number associated with this request. */
1435 /** Position in the ringbuffer of the start of the request */
1438 /** Position in the ringbuffer of the end of the request */
1441 /** Context related to this request */
1442 struct i915_hw_context
*ctx
;
1444 /** Batch buffer related to this request if any */
1445 struct drm_i915_gem_object
*batch_obj
;
1447 /** Time at which this request was emitted, in jiffies. */
1448 unsigned long emitted_jiffies
;
1450 /** global list entry for this request */
1451 struct list_head list
;
1453 struct drm_i915_file_private
*file_priv
;
1454 /** file_priv list entry for this request */
1455 struct list_head client_list
;
1458 struct drm_i915_file_private
{
1461 struct list_head request_list
;
1463 struct idr context_idr
;
1465 struct i915_ctx_hang_stats hang_stats
;
1468 #define INTEL_INFO(dev) (to_i915(dev)->info)
1470 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1471 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1472 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1473 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1474 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1475 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1476 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1477 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1478 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1479 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1480 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1481 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1482 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1483 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1484 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1485 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1486 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1487 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1488 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1489 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1490 (dev)->pci_device == 0x0152 || \
1491 (dev)->pci_device == 0x015a)
1492 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1493 (dev)->pci_device == 0x0106 || \
1494 (dev)->pci_device == 0x010A)
1495 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1496 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1497 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1498 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1499 ((dev)->pci_device & 0xFF00) == 0x0A00)
1502 * The genX designation typically refers to the render engine, so render
1503 * capability related checks should use IS_GEN, while display and other checks
1504 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1507 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1508 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1509 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1510 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1511 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1512 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1514 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1515 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1516 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->has_vebox_ring)
1517 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1518 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1520 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1521 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1523 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1524 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1526 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1527 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1529 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1530 * rows, which changed the alignment requirements and fence programming.
1532 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1534 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1535 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1536 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1537 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1538 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1539 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1540 /* dsparb controlled by hw only */
1541 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1543 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1544 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1545 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1547 #define HAS_IPS(dev) (IS_ULT(dev))
1549 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1551 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1552 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1553 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1555 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1556 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1557 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1558 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1559 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1560 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1562 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1563 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1564 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1565 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1566 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1567 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1569 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1571 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1573 #define GT_FREQUENCY_MULTIPLIER 50
1575 #include "i915_trace.h"
1578 * RC6 is a special power stage which allows the GPU to enter an very
1579 * low-voltage mode when idle, using down to 0V while at this stage. This
1580 * stage is entered automatically when the GPU is idle when RC6 support is
1581 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1583 * There are different RC6 modes available in Intel GPU, which differentiate
1584 * among each other with the latency required to enter and leave RC6 and
1585 * voltage consumed by the GPU in different states.
1587 * The combination of the following flags define which states GPU is allowed
1588 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1589 * RC6pp is deepest RC6. Their support by hardware varies according to the
1590 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1591 * which brings the most power savings; deeper states save more power, but
1592 * require higher latency to switch to and wake up.
1594 #define INTEL_RC6_ENABLE (1<<0)
1595 #define INTEL_RC6p_ENABLE (1<<1)
1596 #define INTEL_RC6pp_ENABLE (1<<2)
1598 extern struct drm_ioctl_desc i915_ioctls
[];
1599 extern int i915_max_ioctl
;
1600 extern unsigned int i915_fbpercrtc __always_unused
;
1601 extern int i915_panel_ignore_lid __read_mostly
;
1602 extern unsigned int i915_powersave __read_mostly
;
1603 extern int i915_semaphores __read_mostly
;
1604 extern unsigned int i915_lvds_downclock __read_mostly
;
1605 extern int i915_lvds_channel_mode __read_mostly
;
1606 extern int i915_panel_use_ssc __read_mostly
;
1607 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1608 extern int i915_enable_rc6 __read_mostly
;
1609 extern int i915_enable_fbc __read_mostly
;
1610 extern bool i915_enable_hangcheck __read_mostly
;
1611 extern int i915_enable_ppgtt __read_mostly
;
1612 extern int i915_enable_psr __read_mostly
;
1613 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1614 extern int i915_disable_power_well __read_mostly
;
1615 extern int i915_enable_ips __read_mostly
;
1616 extern bool i915_fastboot __read_mostly
;
1617 extern bool i915_prefault_disable __read_mostly
;
1619 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1620 extern int i915_resume(struct drm_device
*dev
);
1621 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1622 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1625 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1626 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1627 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1628 extern int i915_driver_unload(struct drm_device
*);
1629 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1630 extern void i915_driver_lastclose(struct drm_device
* dev
);
1631 extern void i915_driver_preclose(struct drm_device
*dev
,
1632 struct drm_file
*file_priv
);
1633 extern void i915_driver_postclose(struct drm_device
*dev
,
1634 struct drm_file
*file_priv
);
1635 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1636 #ifdef CONFIG_COMPAT
1637 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1640 extern int i915_emit_box(struct drm_device
*dev
,
1641 struct drm_clip_rect
*box
,
1643 extern int intel_gpu_reset(struct drm_device
*dev
);
1644 extern int i915_reset(struct drm_device
*dev
);
1645 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1646 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1647 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1648 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1650 extern void intel_console_resume(struct work_struct
*work
);
1653 void i915_queue_hangcheck(struct drm_device
*dev
);
1654 void i915_hangcheck_elapsed(unsigned long data
);
1655 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1657 extern void intel_irq_init(struct drm_device
*dev
);
1658 extern void intel_hpd_init(struct drm_device
*dev
);
1659 extern void intel_pm_init(struct drm_device
*dev
);
1661 extern void intel_uncore_sanitize(struct drm_device
*dev
);
1662 extern void intel_uncore_early_sanitize(struct drm_device
*dev
);
1663 extern void intel_uncore_init(struct drm_device
*dev
);
1664 extern void intel_uncore_reset(struct drm_device
*dev
);
1665 extern void intel_uncore_clear_errors(struct drm_device
*dev
);
1666 extern void intel_uncore_check_errors(struct drm_device
*dev
);
1669 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1672 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1675 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1676 struct drm_file
*file_priv
);
1677 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1678 struct drm_file
*file_priv
);
1679 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1680 struct drm_file
*file_priv
);
1681 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1682 struct drm_file
*file_priv
);
1683 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1684 struct drm_file
*file_priv
);
1685 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1686 struct drm_file
*file_priv
);
1687 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1688 struct drm_file
*file_priv
);
1689 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1690 struct drm_file
*file_priv
);
1691 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1692 struct drm_file
*file_priv
);
1693 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1694 struct drm_file
*file_priv
);
1695 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1696 struct drm_file
*file_priv
);
1697 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1698 struct drm_file
*file_priv
);
1699 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1700 struct drm_file
*file_priv
);
1701 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1702 struct drm_file
*file
);
1703 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1704 struct drm_file
*file
);
1705 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1706 struct drm_file
*file_priv
);
1707 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1708 struct drm_file
*file_priv
);
1709 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1710 struct drm_file
*file_priv
);
1711 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1712 struct drm_file
*file_priv
);
1713 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1714 struct drm_file
*file_priv
);
1715 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1716 struct drm_file
*file_priv
);
1717 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1718 struct drm_file
*file_priv
);
1719 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1720 struct drm_file
*file_priv
);
1721 void i915_gem_load(struct drm_device
*dev
);
1722 void *i915_gem_object_alloc(struct drm_device
*dev
);
1723 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1724 int i915_gem_init_object(struct drm_gem_object
*obj
);
1725 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1726 const struct drm_i915_gem_object_ops
*ops
);
1727 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1729 void i915_gem_free_object(struct drm_gem_object
*obj
);
1730 struct i915_vma
*i915_gem_vma_create(struct drm_i915_gem_object
*obj
,
1731 struct i915_address_space
*vm
);
1732 void i915_gem_vma_destroy(struct i915_vma
*vma
);
1734 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1735 struct i915_address_space
*vm
,
1737 bool map_and_fenceable
,
1739 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1740 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1741 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1742 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1743 void i915_gem_lastclose(struct drm_device
*dev
);
1745 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1746 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1748 struct sg_page_iter sg_iter
;
1750 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1751 return sg_page_iter_page(&sg_iter
);
1755 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1757 BUG_ON(obj
->pages
== NULL
);
1758 obj
->pages_pin_count
++;
1760 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1762 BUG_ON(obj
->pages_pin_count
== 0);
1763 obj
->pages_pin_count
--;
1766 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1767 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1768 struct intel_ring_buffer
*to
);
1769 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1770 struct intel_ring_buffer
*ring
);
1772 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1773 struct drm_device
*dev
,
1774 struct drm_mode_create_dumb
*args
);
1775 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1776 uint32_t handle
, uint64_t *offset
);
1777 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1780 * Returns true if seq1 is later than seq2.
1783 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1785 return (int32_t)(seq1
- seq2
) >= 0;
1788 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1789 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1790 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1791 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1794 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1796 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1797 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1798 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1805 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1807 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1808 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1809 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
1810 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1814 void i915_gem_retire_requests(struct drm_device
*dev
);
1815 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1816 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1817 bool interruptible
);
1818 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1820 return unlikely(atomic_read(&error
->reset_counter
)
1821 & I915_RESET_IN_PROGRESS_FLAG
);
1824 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1826 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1829 void i915_gem_reset(struct drm_device
*dev
);
1830 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1831 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1832 uint32_t read_domains
,
1833 uint32_t write_domain
);
1834 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1835 int __must_check
i915_gem_init(struct drm_device
*dev
);
1836 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1837 void i915_gem_l3_remap(struct drm_device
*dev
);
1838 void i915_gem_init_swizzling(struct drm_device
*dev
);
1839 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1840 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1841 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1842 int __i915_add_request(struct intel_ring_buffer
*ring
,
1843 struct drm_file
*file
,
1844 struct drm_i915_gem_object
*batch_obj
,
1846 #define i915_add_request(ring, seqno) \
1847 __i915_add_request(ring, NULL, NULL, seqno)
1848 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1850 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1852 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1855 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1857 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1859 struct intel_ring_buffer
*pipelined
);
1860 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1861 struct drm_i915_gem_object
*obj
,
1864 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1865 struct drm_i915_gem_object
*obj
);
1866 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1867 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1870 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
1872 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1873 int tiling_mode
, bool fenced
);
1875 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1876 enum i915_cache_level cache_level
);
1878 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1879 struct dma_buf
*dma_buf
);
1881 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1882 struct drm_gem_object
*gem_obj
, int flags
);
1884 void i915_gem_restore_fences(struct drm_device
*dev
);
1886 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
1887 struct i915_address_space
*vm
);
1888 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
1889 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
1890 struct i915_address_space
*vm
);
1891 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
1892 struct i915_address_space
*vm
);
1893 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
1894 struct i915_address_space
*vm
);
1895 /* Some GGTT VM helpers */
1896 #define obj_to_ggtt(obj) \
1897 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
1898 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
1900 struct i915_address_space
*ggtt
=
1901 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
1905 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
1907 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
1910 static inline unsigned long
1911 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
1913 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
1916 static inline unsigned long
1917 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
1919 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
1922 static inline int __must_check
1923 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
1925 bool map_and_fenceable
,
1928 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
,
1929 map_and_fenceable
, nonblocking
);
1933 /* i915_gem_context.c */
1934 void i915_gem_context_init(struct drm_device
*dev
);
1935 void i915_gem_context_fini(struct drm_device
*dev
);
1936 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1937 int i915_switch_context(struct intel_ring_buffer
*ring
,
1938 struct drm_file
*file
, int to_id
);
1939 void i915_gem_context_free(struct kref
*ctx_ref
);
1940 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
1942 kref_get(&ctx
->ref
);
1945 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
1947 kref_put(&ctx
->ref
, i915_gem_context_free
);
1950 struct i915_ctx_hang_stats
* __must_check
1951 i915_gem_context_get_hang_stats(struct drm_device
*dev
,
1952 struct drm_file
*file
,
1954 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1955 struct drm_file
*file
);
1956 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1957 struct drm_file
*file
);
1959 /* i915_gem_gtt.c */
1960 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1961 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1962 struct drm_i915_gem_object
*obj
,
1963 enum i915_cache_level cache_level
);
1964 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1965 struct drm_i915_gem_object
*obj
);
1967 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1968 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1969 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1970 enum i915_cache_level cache_level
);
1971 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1972 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1973 void i915_gem_init_global_gtt(struct drm_device
*dev
);
1974 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
1975 unsigned long mappable_end
, unsigned long end
);
1976 int i915_gem_gtt_init(struct drm_device
*dev
);
1977 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
1979 if (INTEL_INFO(dev
)->gen
< 6)
1980 intel_gtt_chipset_flush();
1984 /* i915_gem_evict.c */
1985 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1987 unsigned cache_level
,
1990 int i915_gem_evict_everything(struct drm_device
*dev
);
1992 /* i915_gem_stolen.c */
1993 int i915_gem_init_stolen(struct drm_device
*dev
);
1994 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
1995 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
1996 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1997 struct drm_i915_gem_object
*
1998 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
1999 struct drm_i915_gem_object
*
2000 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2004 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
2006 /* i915_gem_tiling.c */
2007 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2009 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
2011 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2012 obj
->tiling_mode
!= I915_TILING_NONE
;
2015 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2016 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2017 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2019 /* i915_gem_debug.c */
2020 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
2021 const char *where
, uint32_t mark
);
2023 int i915_verify_lists(struct drm_device
*dev
);
2025 #define i915_verify_lists(dev) 0
2027 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
2029 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
2030 const char *where
, uint32_t mark
);
2032 /* i915_debugfs.c */
2033 int i915_debugfs_init(struct drm_minor
*minor
);
2034 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2036 /* i915_gpu_error.c */
2038 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2039 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2040 const struct i915_error_state_file_priv
*error
);
2041 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2042 size_t count
, loff_t pos
);
2043 static inline void i915_error_state_buf_release(
2044 struct drm_i915_error_state_buf
*eb
)
2048 void i915_capture_error_state(struct drm_device
*dev
);
2049 void i915_error_state_get(struct drm_device
*dev
,
2050 struct i915_error_state_file_priv
*error_priv
);
2051 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2052 void i915_destroy_error_state(struct drm_device
*dev
);
2054 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2055 const char *i915_cache_level_str(int type
);
2057 /* i915_suspend.c */
2058 extern int i915_save_state(struct drm_device
*dev
);
2059 extern int i915_restore_state(struct drm_device
*dev
);
2062 void i915_save_display_reg(struct drm_device
*dev
);
2063 void i915_restore_display_reg(struct drm_device
*dev
);
2066 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2067 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2070 extern int intel_setup_gmbus(struct drm_device
*dev
);
2071 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2072 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2074 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2077 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2078 struct drm_i915_private
*dev_priv
, unsigned port
);
2079 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2080 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2081 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2083 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2085 extern void intel_i2c_reset(struct drm_device
*dev
);
2087 /* intel_opregion.c */
2088 extern int intel_opregion_setup(struct drm_device
*dev
);
2090 extern void intel_opregion_init(struct drm_device
*dev
);
2091 extern void intel_opregion_fini(struct drm_device
*dev
);
2092 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2094 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2095 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2096 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2101 extern void intel_register_dsm_handler(void);
2102 extern void intel_unregister_dsm_handler(void);
2104 static inline void intel_register_dsm_handler(void) { return; }
2105 static inline void intel_unregister_dsm_handler(void) { return; }
2106 #endif /* CONFIG_ACPI */
2109 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2110 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2111 extern void intel_modeset_init(struct drm_device
*dev
);
2112 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2113 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2114 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2115 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2116 bool force_restore
);
2117 extern void i915_redisable_vga(struct drm_device
*dev
);
2118 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2119 extern void intel_disable_fbc(struct drm_device
*dev
);
2120 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2121 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2122 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2123 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2124 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2125 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2126 extern void intel_detect_pch(struct drm_device
*dev
);
2127 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2128 extern int intel_enable_rc6(const struct drm_device
*dev
);
2130 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2131 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2132 struct drm_file
*file
);
2135 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2136 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2137 struct intel_overlay_error_state
*error
);
2139 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2140 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2141 struct drm_device
*dev
,
2142 struct intel_display_error_state
*error
);
2144 /* On SNB platform, before reading ring registers forcewake bit
2145 * must be set to prevent GT core from power down and stale values being
2148 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
2149 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
2151 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2152 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2154 /* intel_sideband.c */
2155 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2156 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2157 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2158 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, int reg
);
2159 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, int reg
, u32 val
);
2160 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2161 enum intel_sbi_destination destination
);
2162 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2163 enum intel_sbi_destination destination
);
2165 int vlv_gpu_freq(int ddr_freq
, int val
);
2166 int vlv_freq_opcode(int ddr_freq
, int val
);
2168 #define __i915_read(x) \
2169 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg, bool trace);
2176 #define __i915_write(x) \
2177 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val, bool trace);
2184 #define I915_READ8(reg) i915_read8(dev_priv, (reg), true)
2185 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val), true)
2187 #define I915_READ16(reg) i915_read16(dev_priv, (reg), true)
2188 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val), true)
2189 #define I915_READ16_NOTRACE(reg) i915_read16(dev_priv, (reg), false)
2190 #define I915_WRITE16_NOTRACE(reg, val) i915_write16(dev_priv, (reg), (val), false)
2192 #define I915_READ(reg) i915_read32(dev_priv, (reg), true)
2193 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val), true)
2194 #define I915_READ_NOTRACE(reg) i915_read32(dev_priv, (reg), false)
2195 #define I915_WRITE_NOTRACE(reg, val) i915_write32(dev_priv, (reg), (val), false)
2197 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val), true)
2198 #define I915_READ64(reg) i915_read64(dev_priv, (reg), true)
2200 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2201 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2203 /* "Broadcast RGB" property */
2204 #define INTEL_BROADCAST_RGB_AUTO 0
2205 #define INTEL_BROADCAST_RGB_FULL 1
2206 #define INTEL_BROADCAST_RGB_LIMITED 2
2208 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2210 if (HAS_PCH_SPLIT(dev
))
2211 return CPU_VGACNTRL
;
2212 else if (IS_VALLEYVIEW(dev
))
2213 return VLV_VGACNTRL
;
2218 static inline void __user
*to_user_ptr(u64 address
)
2220 return (void __user
*)(uintptr_t)address
;
2223 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2225 unsigned long j
= msecs_to_jiffies(m
);
2227 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2230 static inline unsigned long
2231 timespec_to_jiffies_timeout(const struct timespec
*value
)
2233 unsigned long j
= timespec_to_jiffies(value
);
2235 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);