1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 I915_MAX_PIPES
= _PIPE_EDP
64 #define pipe_name(p) ((p) + 'A')
73 #define transcoder_name(t) ((t) + 'A')
80 #define plane_name(p) ((p) + 'A')
82 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
92 #define port_name(p) ((p) + 'A')
94 #define I915_NUM_PHYS_VLV 1
106 enum intel_display_power_domain
{
110 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
111 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
112 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
113 POWER_DOMAIN_TRANSCODER_A
,
114 POWER_DOMAIN_TRANSCODER_B
,
115 POWER_DOMAIN_TRANSCODER_C
,
116 POWER_DOMAIN_TRANSCODER_EDP
,
117 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
118 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
119 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
120 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
121 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
122 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
123 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
124 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
125 POWER_DOMAIN_PORT_DSI
,
126 POWER_DOMAIN_PORT_CRT
,
127 POWER_DOMAIN_PORT_OTHER
,
135 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
136 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
137 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
138 #define POWER_DOMAIN_TRANSCODER(tran) \
139 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
140 (tran) + POWER_DOMAIN_TRANSCODER_A)
144 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
145 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
155 #define I915_GEM_GPU_DOMAINS \
156 (I915_GEM_DOMAIN_RENDER | \
157 I915_GEM_DOMAIN_SAMPLER | \
158 I915_GEM_DOMAIN_COMMAND | \
159 I915_GEM_DOMAIN_INSTRUCTION | \
160 I915_GEM_DOMAIN_VERTEX)
162 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
163 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
165 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
166 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
167 if ((intel_encoder)->base.crtc == (__crtc))
169 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
170 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
171 if ((intel_connector)->base.encoder == (__encoder))
173 struct drm_i915_private
;
176 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
177 /* real shared dpll ids must be >= 0 */
181 #define I915_NUM_PLLS 2
183 struct intel_dpll_hw_state
{
190 struct intel_shared_dpll
{
191 int refcount
; /* count of number of CRTCs sharing this PLL */
192 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
193 bool on
; /* is the PLL actually active? Disabled during modeset */
195 /* should match the index in the dev_priv->shared_dplls array */
196 enum intel_dpll_id id
;
197 struct intel_dpll_hw_state hw_state
;
198 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
199 struct intel_shared_dpll
*pll
);
200 void (*enable
)(struct drm_i915_private
*dev_priv
,
201 struct intel_shared_dpll
*pll
);
202 void (*disable
)(struct drm_i915_private
*dev_priv
,
203 struct intel_shared_dpll
*pll
);
204 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
205 struct intel_shared_dpll
*pll
,
206 struct intel_dpll_hw_state
*hw_state
);
209 /* Used by dp and fdi links */
210 struct intel_link_m_n
{
218 void intel_link_compute_m_n(int bpp
, int nlanes
,
219 int pixel_clock
, int link_clock
,
220 struct intel_link_m_n
*m_n
);
222 struct intel_ddi_plls
{
228 /* Interface history:
231 * 1.2: Add Power Management
232 * 1.3: Add vblank support
233 * 1.4: Fix cmdbuffer path, add heap destroy
234 * 1.5: Add vblank pipe configuration
235 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
236 * - Support vertical blank on secondary display pipe
238 #define DRIVER_MAJOR 1
239 #define DRIVER_MINOR 6
240 #define DRIVER_PATCHLEVEL 0
242 #define WATCH_LISTS 0
245 #define I915_GEM_PHYS_CURSOR_0 1
246 #define I915_GEM_PHYS_CURSOR_1 2
247 #define I915_GEM_PHYS_OVERLAY_REGS 3
248 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
250 struct drm_i915_gem_phys_object
{
252 struct page
**page_list
;
253 drm_dma_handle_t
*handle
;
254 struct drm_i915_gem_object
*cur_obj
;
257 struct opregion_header
;
258 struct opregion_acpi
;
259 struct opregion_swsci
;
260 struct opregion_asle
;
262 struct intel_opregion
{
263 struct opregion_header __iomem
*header
;
264 struct opregion_acpi __iomem
*acpi
;
265 struct opregion_swsci __iomem
*swsci
;
266 u32 swsci_gbda_sub_functions
;
267 u32 swsci_sbcb_sub_functions
;
268 struct opregion_asle __iomem
*asle
;
270 u32 __iomem
*lid_state
;
271 struct work_struct asle_work
;
273 #define OPREGION_SIZE (8*1024)
275 struct intel_overlay
;
276 struct intel_overlay_error_state
;
278 struct drm_i915_master_private
{
279 drm_local_map_t
*sarea
;
280 struct _drm_i915_sarea
*sarea_priv
;
282 #define I915_FENCE_REG_NONE -1
283 #define I915_MAX_NUM_FENCES 32
284 /* 32 fences + sign bit for FENCE_REG_NONE */
285 #define I915_MAX_NUM_FENCE_BITS 6
287 struct drm_i915_fence_reg
{
288 struct list_head lru_list
;
289 struct drm_i915_gem_object
*obj
;
293 struct sdvo_device_mapping
{
302 struct intel_display_error_state
;
304 struct drm_i915_error_state
{
312 /* Generic register state */
319 u32 error
; /* gen6+ */
320 u32 err_int
; /* gen7 */
326 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
327 u32 pipestat
[I915_MAX_PIPES
];
328 u64 fence
[I915_MAX_NUM_FENCES
];
329 struct intel_overlay_error_state
*overlay
;
330 struct intel_display_error_state
*display
;
332 struct drm_i915_error_ring
{
334 /* Software tracked state */
337 enum intel_ring_hangcheck_action hangcheck_action
;
340 /* our own tracking of ring head and tail */
344 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
362 u32 rc_psmi
; /* sleep state */
363 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
365 struct drm_i915_error_object
{
369 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
371 struct drm_i915_error_request
{
386 char comm
[TASK_COMM_LEN
];
387 } ring
[I915_NUM_RINGS
];
388 struct drm_i915_error_buffer
{
395 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
402 } **active_bo
, **pinned_bo
;
404 u32
*active_bo_count
, *pinned_bo_count
;
407 struct intel_connector
;
408 struct intel_crtc_config
;
409 struct intel_plane_config
;
414 struct drm_i915_display_funcs
{
415 bool (*fbc_enabled
)(struct drm_device
*dev
);
416 void (*enable_fbc
)(struct drm_crtc
*crtc
);
417 void (*disable_fbc
)(struct drm_device
*dev
);
418 int (*get_display_clock_speed
)(struct drm_device
*dev
);
419 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
421 * find_dpll() - Find the best values for the PLL
422 * @limit: limits for the PLL
423 * @crtc: current CRTC
424 * @target: target frequency in kHz
425 * @refclk: reference clock frequency in kHz
426 * @match_clock: if provided, @best_clock P divider must
427 * match the P divider from @match_clock
428 * used for LVDS downclocking
429 * @best_clock: best PLL values found
431 * Returns true on success, false on failure.
433 bool (*find_dpll
)(const struct intel_limit
*limit
,
434 struct drm_crtc
*crtc
,
435 int target
, int refclk
,
436 struct dpll
*match_clock
,
437 struct dpll
*best_clock
);
438 void (*update_wm
)(struct drm_crtc
*crtc
);
439 void (*update_sprite_wm
)(struct drm_plane
*plane
,
440 struct drm_crtc
*crtc
,
441 uint32_t sprite_width
, int pixel_size
,
442 bool enable
, bool scaled
);
443 void (*modeset_global_resources
)(struct drm_device
*dev
);
444 /* Returns the active state of the crtc, and if the crtc is active,
445 * fills out the pipe-config with the hw state. */
446 bool (*get_pipe_config
)(struct intel_crtc
*,
447 struct intel_crtc_config
*);
448 void (*get_plane_config
)(struct intel_crtc
*,
449 struct intel_plane_config
*);
450 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
452 struct drm_framebuffer
*old_fb
);
453 void (*crtc_enable
)(struct drm_crtc
*crtc
);
454 void (*crtc_disable
)(struct drm_crtc
*crtc
);
455 void (*off
)(struct drm_crtc
*crtc
);
456 void (*write_eld
)(struct drm_connector
*connector
,
457 struct drm_crtc
*crtc
,
458 struct drm_display_mode
*mode
);
459 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
460 void (*init_clock_gating
)(struct drm_device
*dev
);
461 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
462 struct drm_framebuffer
*fb
,
463 struct drm_i915_gem_object
*obj
,
465 int (*update_primary_plane
)(struct drm_crtc
*crtc
,
466 struct drm_framebuffer
*fb
,
468 void (*hpd_irq_setup
)(struct drm_device
*dev
);
469 /* clock updates for mode set */
471 /* render clock increase/decrease */
472 /* display clock increase/decrease */
473 /* pll clock increase/decrease */
475 int (*setup_backlight
)(struct intel_connector
*connector
);
476 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
477 void (*set_backlight
)(struct intel_connector
*connector
,
479 void (*disable_backlight
)(struct intel_connector
*connector
);
480 void (*enable_backlight
)(struct intel_connector
*connector
);
483 struct intel_uncore_funcs
{
484 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
486 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
489 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
490 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
491 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
492 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
494 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
495 uint8_t val
, bool trace
);
496 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
497 uint16_t val
, bool trace
);
498 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
499 uint32_t val
, bool trace
);
500 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
501 uint64_t val
, bool trace
);
504 struct intel_uncore
{
505 spinlock_t lock
; /** lock is also taken in irq contexts. */
507 struct intel_uncore_funcs funcs
;
510 unsigned forcewake_count
;
512 unsigned fw_rendercount
;
513 unsigned fw_mediacount
;
515 struct timer_list force_wake_timer
;
518 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
519 func(is_mobile) sep \
522 func(is_i945gm) sep \
524 func(need_gfx_hws) sep \
526 func(is_pineview) sep \
527 func(is_broadwater) sep \
528 func(is_crestline) sep \
529 func(is_ivybridge) sep \
530 func(is_valleyview) sep \
531 func(is_haswell) sep \
532 func(is_preliminary) sep \
534 func(has_pipe_cxsr) sep \
535 func(has_hotplug) sep \
536 func(cursor_needs_physical) sep \
537 func(has_overlay) sep \
538 func(overlay_needs_physical) sep \
539 func(supports_tv) sep \
544 #define DEFINE_FLAG(name) u8 name:1
545 #define SEP_SEMICOLON ;
547 struct intel_device_info
{
548 u32 display_mmio_offset
;
550 u8 num_sprites
[I915_MAX_PIPES
];
552 u8 ring_mask
; /* Rings supported by the HW */
553 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
554 /* Register offsets for the various display pipes and transcoders */
555 int pipe_offsets
[I915_MAX_TRANSCODERS
];
556 int trans_offsets
[I915_MAX_TRANSCODERS
];
557 int dpll_offsets
[I915_MAX_PIPES
];
558 int dpll_md_offsets
[I915_MAX_PIPES
];
559 int palette_offsets
[I915_MAX_PIPES
];
565 enum i915_cache_level
{
567 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
568 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
569 caches, eg sampler/render caches, and the
570 large Last-Level-Cache. LLC is coherent with
571 the CPU, but L3 is only visible to the GPU. */
572 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
575 typedef uint32_t gen6_gtt_pte_t
;
578 * A VMA represents a GEM BO that is bound into an address space. Therefore, a
579 * VMA's presence cannot be guaranteed before binding, or after unbinding the
580 * object into/from the address space.
582 * To make things as simple as possible (ie. no refcounting), a VMA's lifetime
583 * will always be <= an objects lifetime. So object refcounting should cover us.
586 struct drm_mm_node node
;
587 struct drm_i915_gem_object
*obj
;
588 struct i915_address_space
*vm
;
590 /** This object's place on the active/inactive lists */
591 struct list_head mm_list
;
593 struct list_head vma_link
; /* Link in the object's VMA list */
595 /** This vma's place in the batchbuffer or on the eviction list */
596 struct list_head exec_list
;
599 * Used for performing relocations during execbuffer insertion.
601 struct hlist_node exec_node
;
602 unsigned long exec_handle
;
603 struct drm_i915_gem_exec_object2
*exec_entry
;
606 * How many users have pinned this object in GTT space. The following
607 * users can each hold at most one reference: pwrite/pread, pin_ioctl
608 * (via user_pin_count), execbuffer (objects are not allowed multiple
609 * times for the same batchbuffer), and the framebuffer code. When
610 * switching/pageflipping, the framebuffer code has at most two buffers
613 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
614 * bits with absolutely no headroom. So use 4 bits. */
615 unsigned int pin_count
:4;
616 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
618 /** Unmap an object from an address space. This usually consists of
619 * setting the valid PTE entries to a reserved scratch page. */
620 void (*unbind_vma
)(struct i915_vma
*vma
);
621 /* Map an object into an address space with the given cache flags. */
622 #define GLOBAL_BIND (1<<0)
623 void (*bind_vma
)(struct i915_vma
*vma
,
624 enum i915_cache_level cache_level
,
628 struct i915_address_space
{
630 struct drm_device
*dev
;
631 struct list_head global_link
;
632 unsigned long start
; /* Start offset always 0 for dri2 */
633 size_t total
; /* size addr space maps (ex. 2GB for ggtt) */
641 * List of objects currently involved in rendering.
643 * Includes buffers having the contents of their GPU caches
644 * flushed, not necessarily primitives. last_rendering_seqno
645 * represents when the rendering involved will be completed.
647 * A reference is held on the buffer while on this list.
649 struct list_head active_list
;
652 * LRU list of objects which are not in the ringbuffer and
653 * are ready to unbind, but are still in the GTT.
655 * last_rendering_seqno is 0 while an object is in this list.
657 * A reference is not held on the buffer while on this list,
658 * as merely being GTT-bound shouldn't prevent its being
659 * freed, and we'll pull it off the list in the free path.
661 struct list_head inactive_list
;
663 /* FIXME: Need a more generic return type */
664 gen6_gtt_pte_t (*pte_encode
)(dma_addr_t addr
,
665 enum i915_cache_level level
,
666 bool valid
); /* Create a valid PTE */
667 void (*clear_range
)(struct i915_address_space
*vm
,
671 void (*insert_entries
)(struct i915_address_space
*vm
,
674 enum i915_cache_level cache_level
);
675 void (*cleanup
)(struct i915_address_space
*vm
);
678 /* The Graphics Translation Table is the way in which GEN hardware translates a
679 * Graphics Virtual Address into a Physical Address. In addition to the normal
680 * collateral associated with any va->pa translations GEN hardware also has a
681 * portion of the GTT which can be mapped by the CPU and remain both coherent
682 * and correct (in cases like swizzling). That region is referred to as GMADR in
686 struct i915_address_space base
;
687 size_t stolen_size
; /* Total size of stolen memory */
689 unsigned long mappable_end
; /* End offset that we can CPU map */
690 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
691 phys_addr_t mappable_base
; /* PA of our GMADR */
693 /** "Graphics Stolen Memory" holds the global PTEs */
701 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
702 size_t *stolen
, phys_addr_t
*mappable_base
,
703 unsigned long *mappable_end
);
705 #define gtt_total_entries(gtt) ((gtt).base.total >> PAGE_SHIFT)
707 #define GEN8_LEGACY_PDPS 4
708 struct i915_hw_ppgtt
{
709 struct i915_address_space base
;
711 struct drm_mm_node node
;
712 unsigned num_pd_entries
;
713 unsigned num_pd_pages
; /* gen8+ */
715 struct page
**pt_pages
;
716 struct page
**gen8_pt_pages
[GEN8_LEGACY_PDPS
];
718 struct page
*pd_pages
;
721 dma_addr_t pd_dma_addr
[GEN8_LEGACY_PDPS
];
724 dma_addr_t
*pt_dma_addr
;
725 dma_addr_t
*gen8_pt_dma_addr
[4];
728 struct i915_hw_context
*ctx
;
730 int (*enable
)(struct i915_hw_ppgtt
*ppgtt
);
731 int (*switch_mm
)(struct i915_hw_ppgtt
*ppgtt
,
732 struct intel_ring_buffer
*ring
,
734 void (*debug_dump
)(struct i915_hw_ppgtt
*ppgtt
, struct seq_file
*m
);
737 struct i915_ctx_hang_stats
{
738 /* This context had batch pending when hang was declared */
739 unsigned batch_pending
;
741 /* This context had batch active when hang was declared */
742 unsigned batch_active
;
744 /* Time when this context was last blamed for a GPU reset */
745 unsigned long guilty_ts
;
747 /* This context is banned to submit more work */
751 /* This must match up with the value previously used for execbuf2.rsvd1. */
752 #define DEFAULT_CONTEXT_ID 0
753 struct i915_hw_context
{
758 struct drm_i915_file_private
*file_priv
;
759 struct intel_ring_buffer
*last_ring
;
760 struct drm_i915_gem_object
*obj
;
761 struct i915_ctx_hang_stats hang_stats
;
762 struct i915_address_space
*vm
;
764 struct list_head link
;
773 struct drm_mm_node
*compressed_fb
;
774 struct drm_mm_node
*compressed_llb
;
776 struct intel_fbc_work
{
777 struct delayed_work work
;
778 struct drm_crtc
*crtc
;
779 struct drm_framebuffer
*fb
;
783 FBC_OK
, /* FBC is enabled */
784 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
785 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
786 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
787 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
788 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
789 FBC_BAD_PLANE
, /* fbc not supported on plane */
790 FBC_NOT_TILED
, /* buffer not tiled */
791 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
793 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
803 PCH_NONE
= 0, /* No PCH present */
804 PCH_IBX
, /* Ibexpeak PCH */
805 PCH_CPT
, /* Cougarpoint PCH */
806 PCH_LPT
, /* Lynxpoint PCH */
810 enum intel_sbi_destination
{
815 #define QUIRK_PIPEA_FORCE (1<<0)
816 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
817 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
820 struct intel_fbc_work
;
823 struct i2c_adapter adapter
;
827 struct i2c_algo_bit_data bit_algo
;
828 struct drm_i915_private
*dev_priv
;
831 struct i915_suspend_saved_registers
{
852 u32 saveTRANS_HTOTAL_A
;
853 u32 saveTRANS_HBLANK_A
;
854 u32 saveTRANS_HSYNC_A
;
855 u32 saveTRANS_VTOTAL_A
;
856 u32 saveTRANS_VBLANK_A
;
857 u32 saveTRANS_VSYNC_A
;
865 u32 savePFIT_PGM_RATIOS
;
866 u32 saveBLC_HIST_CTL
;
868 u32 saveBLC_PWM_CTL2
;
869 u32 saveBLC_HIST_CTL_B
;
870 u32 saveBLC_CPU_PWM_CTL
;
871 u32 saveBLC_CPU_PWM_CTL2
;
884 u32 saveTRANS_HTOTAL_B
;
885 u32 saveTRANS_HBLANK_B
;
886 u32 saveTRANS_HSYNC_B
;
887 u32 saveTRANS_VTOTAL_B
;
888 u32 saveTRANS_VBLANK_B
;
889 u32 saveTRANS_VSYNC_B
;
903 u32 savePP_ON_DELAYS
;
904 u32 savePP_OFF_DELAYS
;
912 u32 savePFIT_CONTROL
;
913 u32 save_palette_a
[256];
914 u32 save_palette_b
[256];
925 u32 saveCACHE_MODE_0
;
926 u32 saveMI_ARB_STATE
;
937 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
948 u32 savePIPEA_GMCH_DATA_M
;
949 u32 savePIPEB_GMCH_DATA_M
;
950 u32 savePIPEA_GMCH_DATA_N
;
951 u32 savePIPEB_GMCH_DATA_N
;
952 u32 savePIPEA_DP_LINK_M
;
953 u32 savePIPEB_DP_LINK_M
;
954 u32 savePIPEA_DP_LINK_N
;
955 u32 savePIPEB_DP_LINK_N
;
966 u32 savePCH_DREF_CONTROL
;
967 u32 saveDISP_ARB_CTL
;
968 u32 savePIPEA_DATA_M1
;
969 u32 savePIPEA_DATA_N1
;
970 u32 savePIPEA_LINK_M1
;
971 u32 savePIPEA_LINK_N1
;
972 u32 savePIPEB_DATA_M1
;
973 u32 savePIPEB_DATA_N1
;
974 u32 savePIPEB_LINK_M1
;
975 u32 savePIPEB_LINK_N1
;
976 u32 saveMCHBAR_RENDER_STANDBY
;
977 u32 savePCH_PORT_HOTPLUG
;
980 struct intel_gen6_power_mgmt
{
981 /* work and pm_iir are protected by dev_priv->irq_lock */
982 struct work_struct work
;
985 /* Frequencies are stored in potentially platform dependent multiples.
986 * In other words, *_freq needs to be multiplied by X to be interesting.
987 * Soft limits are those which are used for the dynamic reclocking done
988 * by the driver (raise frequencies under heavy loads, and lower for
989 * lighter loads). Hard limits are those imposed by the hardware.
991 * A distinction is made for overclocking, which is never enabled by
992 * default, and is considered to be above the hard limit if it's
995 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
996 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
997 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
998 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
999 u8 min_freq
; /* AKA RPn. Minimum frequency */
1000 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1001 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1002 u8 rp0_freq
; /* Non-overclocked max frequency. */
1005 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1008 struct delayed_work delayed_resume_work
;
1011 * Protects RPS/RC6 register access and PCU communication.
1012 * Must be taken after struct_mutex if nested.
1014 struct mutex hw_lock
;
1017 /* defined intel_pm.c */
1018 extern spinlock_t mchdev_lock
;
1020 struct intel_ilk_power_mgmt
{
1028 unsigned long last_time1
;
1029 unsigned long chipset_power
;
1031 struct timespec last_time2
;
1032 unsigned long gfx_power
;
1038 struct drm_i915_gem_object
*pwrctx
;
1039 struct drm_i915_gem_object
*renderctx
;
1042 struct drm_i915_private
;
1043 struct i915_power_well
;
1045 struct i915_power_well_ops
{
1047 * Synchronize the well's hw state to match the current sw state, for
1048 * example enable/disable it based on the current refcount. Called
1049 * during driver init and resume time, possibly after first calling
1050 * the enable/disable handlers.
1052 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1053 struct i915_power_well
*power_well
);
1055 * Enable the well and resources that depend on it (for example
1056 * interrupts located on the well). Called after the 0->1 refcount
1059 void (*enable
)(struct drm_i915_private
*dev_priv
,
1060 struct i915_power_well
*power_well
);
1062 * Disable the well and resources that depend on it. Called after
1063 * the 1->0 refcount transition.
1065 void (*disable
)(struct drm_i915_private
*dev_priv
,
1066 struct i915_power_well
*power_well
);
1067 /* Returns the hw enabled state. */
1068 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1069 struct i915_power_well
*power_well
);
1072 /* Power well structure for haswell */
1073 struct i915_power_well
{
1076 /* power well enable/disable usage count */
1078 unsigned long domains
;
1080 const struct i915_power_well_ops
*ops
;
1083 struct i915_power_domains
{
1085 * Power wells needed for initialization at driver init and suspend
1086 * time are on. They are kept on until after the first modeset.
1089 int power_well_count
;
1092 int domain_use_count
[POWER_DOMAIN_NUM
];
1093 struct i915_power_well
*power_wells
;
1096 struct i915_dri1_state
{
1097 unsigned allow_batchbuffer
: 1;
1098 u32 __iomem
*gfx_hws_cpu_addr
;
1109 struct i915_ums_state
{
1111 * Flag if the X Server, and thus DRM, is not currently in
1112 * control of the device.
1114 * This is set between LeaveVT and EnterVT. It needs to be
1115 * replaced with a semaphore. It also needs to be
1116 * transitioned away from for kernel modesetting.
1121 #define MAX_L3_SLICES 2
1122 struct intel_l3_parity
{
1123 u32
*remap_info
[MAX_L3_SLICES
];
1124 struct work_struct error_work
;
1128 struct i915_gem_mm
{
1129 /** Memory allocator for GTT stolen memory */
1130 struct drm_mm stolen
;
1131 /** List of all objects in gtt_space. Used to restore gtt
1132 * mappings on resume */
1133 struct list_head bound_list
;
1135 * List of objects which are not bound to the GTT (thus
1136 * are idle and not used by the GPU) but still have
1137 * (presumably uncached) pages still attached.
1139 struct list_head unbound_list
;
1141 /** Usable portion of the GTT for GEM */
1142 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1144 /** PPGTT used for aliasing the PPGTT with the GTT */
1145 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1147 struct shrinker inactive_shrinker
;
1148 bool shrinker_no_lock_stealing
;
1150 /** LRU list of objects with fence regs on them. */
1151 struct list_head fence_list
;
1154 * We leave the user IRQ off as much as possible,
1155 * but this means that requests will finish and never
1156 * be retired once the system goes idle. Set a timer to
1157 * fire periodically while the ring is running. When it
1158 * fires, go retire requests.
1160 struct delayed_work retire_work
;
1163 * When we detect an idle GPU, we want to turn on
1164 * powersaving features. So once we see that there
1165 * are no more requests outstanding and no more
1166 * arrive within a small period of time, we fire
1167 * off the idle_work.
1169 struct delayed_work idle_work
;
1172 * Are we in a non-interruptible section of code like
1178 * Is the GPU currently considered idle, or busy executing userspace
1179 * requests? Whilst idle, we attempt to power down the hardware and
1180 * display clocks. In order to reduce the effect on performance, there
1181 * is a slight delay before we do so.
1185 /** Bit 6 swizzling required for X tiling */
1186 uint32_t bit_6_swizzle_x
;
1187 /** Bit 6 swizzling required for Y tiling */
1188 uint32_t bit_6_swizzle_y
;
1190 /* storage for physical objects */
1191 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
1193 /* accounting, useful for userland debugging */
1194 spinlock_t object_stat_lock
;
1195 size_t object_memory
;
1199 struct drm_i915_error_state_buf
{
1208 struct i915_error_state_file_priv
{
1209 struct drm_device
*dev
;
1210 struct drm_i915_error_state
*error
;
1213 struct i915_gpu_error
{
1214 /* For hangcheck timer */
1215 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1216 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1217 /* Hang gpu twice in this window and your context gets banned */
1218 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1220 struct timer_list hangcheck_timer
;
1222 /* For reset and error_state handling. */
1224 /* Protected by the above dev->gpu_error.lock. */
1225 struct drm_i915_error_state
*first_error
;
1226 struct work_struct work
;
1229 unsigned long missed_irq_rings
;
1232 * State variable controlling the reset flow and count
1234 * This is a counter which gets incremented when reset is triggered,
1235 * and again when reset has been handled. So odd values (lowest bit set)
1236 * means that reset is in progress and even values that
1237 * (reset_counter >> 1):th reset was successfully completed.
1239 * If reset is not completed succesfully, the I915_WEDGE bit is
1240 * set meaning that hardware is terminally sour and there is no
1241 * recovery. All waiters on the reset_queue will be woken when
1244 * This counter is used by the wait_seqno code to notice that reset
1245 * event happened and it needs to restart the entire ioctl (since most
1246 * likely the seqno it waited for won't ever signal anytime soon).
1248 * This is important for lock-free wait paths, where no contended lock
1249 * naturally enforces the correct ordering between the bail-out of the
1250 * waiter and the gpu reset work code.
1252 atomic_t reset_counter
;
1254 #define I915_RESET_IN_PROGRESS_FLAG 1
1255 #define I915_WEDGED (1 << 31)
1258 * Waitqueue to signal when the reset has completed. Used by clients
1259 * that wait for dev_priv->mm.wedged to settle.
1261 wait_queue_head_t reset_queue
;
1263 /* For gpu hang simulation. */
1264 unsigned int stop_rings
;
1266 /* For missed irq/seqno simulation. */
1267 unsigned int test_irq_rings
;
1270 enum modeset_restore
{
1271 MODESET_ON_LID_OPEN
,
1276 struct ddi_vbt_port_info
{
1277 uint8_t hdmi_level_shift
;
1279 uint8_t supports_dvi
:1;
1280 uint8_t supports_hdmi
:1;
1281 uint8_t supports_dp
:1;
1284 struct intel_vbt_data
{
1285 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1286 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1289 unsigned int int_tv_support
:1;
1290 unsigned int lvds_dither
:1;
1291 unsigned int lvds_vbt
:1;
1292 unsigned int int_crt_support
:1;
1293 unsigned int lvds_use_ssc
:1;
1294 unsigned int display_clock_mode
:1;
1295 unsigned int fdi_rx_polarity_inverted
:1;
1297 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1302 int edp_preemphasis
;
1304 bool edp_initialized
;
1307 struct edp_power_seq edp_pps
;
1311 bool active_low_pwm
;
1322 union child_device_config
*child_dev
;
1324 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1327 enum intel_ddb_partitioning
{
1329 INTEL_DDB_PART_5_6
, /* IVB+ */
1332 struct intel_wm_level
{
1340 struct ilk_wm_values
{
1341 uint32_t wm_pipe
[3];
1343 uint32_t wm_lp_spr
[3];
1344 uint32_t wm_linetime
[3];
1346 enum intel_ddb_partitioning partitioning
;
1350 * This struct helps tracking the state needed for runtime PM, which puts the
1351 * device in PCI D3 state. Notice that when this happens, nothing on the
1352 * graphics device works, even register access, so we don't get interrupts nor
1355 * Every piece of our code that needs to actually touch the hardware needs to
1356 * either call intel_runtime_pm_get or call intel_display_power_get with the
1357 * appropriate power domain.
1359 * Our driver uses the autosuspend delay feature, which means we'll only really
1360 * suspend if we stay with zero refcount for a certain amount of time. The
1361 * default value is currently very conservative (see intel_init_runtime_pm), but
1362 * it can be changed with the standard runtime PM files from sysfs.
1364 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1365 * goes back to false exactly before we reenable the IRQs. We use this variable
1366 * to check if someone is trying to enable/disable IRQs while they're supposed
1367 * to be disabled. This shouldn't happen and we'll print some error messages in
1368 * case it happens, but if it actually happens we'll also update the variables
1369 * inside struct regsave so when we restore the IRQs they will contain the
1370 * latest expected values.
1372 * For more, read the Documentation/power/runtime_pm.txt.
1374 struct i915_runtime_pm
{
1383 uint32_t gen6_pmimr
;
1387 enum intel_pipe_crc_source
{
1388 INTEL_PIPE_CRC_SOURCE_NONE
,
1389 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1390 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1391 INTEL_PIPE_CRC_SOURCE_PF
,
1392 INTEL_PIPE_CRC_SOURCE_PIPE
,
1393 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1394 INTEL_PIPE_CRC_SOURCE_TV
,
1395 INTEL_PIPE_CRC_SOURCE_DP_B
,
1396 INTEL_PIPE_CRC_SOURCE_DP_C
,
1397 INTEL_PIPE_CRC_SOURCE_DP_D
,
1398 INTEL_PIPE_CRC_SOURCE_AUTO
,
1399 INTEL_PIPE_CRC_SOURCE_MAX
,
1402 struct intel_pipe_crc_entry
{
1407 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1408 struct intel_pipe_crc
{
1410 bool opened
; /* exclusive access to the result file */
1411 struct intel_pipe_crc_entry
*entries
;
1412 enum intel_pipe_crc_source source
;
1414 wait_queue_head_t wq
;
1417 typedef struct drm_i915_private
{
1418 struct drm_device
*dev
;
1419 struct kmem_cache
*slab
;
1421 const struct intel_device_info info
;
1423 int relative_constants_mode
;
1427 struct intel_uncore uncore
;
1429 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1432 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1433 * controller on different i2c buses. */
1434 struct mutex gmbus_mutex
;
1437 * Base address of the gmbus and gpio block.
1439 uint32_t gpio_mmio_base
;
1441 wait_queue_head_t gmbus_wait_queue
;
1443 struct pci_dev
*bridge_dev
;
1444 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
1445 uint32_t last_seqno
, next_seqno
;
1447 drm_dma_handle_t
*status_page_dmah
;
1448 struct resource mch_res
;
1450 /* protects the irq masks */
1451 spinlock_t irq_lock
;
1453 bool display_irqs_enabled
;
1455 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1456 struct pm_qos_request pm_qos
;
1458 /* DPIO indirect register protection */
1459 struct mutex dpio_lock
;
1461 /** Cached value of IMR to avoid reads in updating the bitfield */
1464 u32 de_irq_mask
[I915_MAX_PIPES
];
1469 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1471 struct work_struct hotplug_work
;
1472 bool enable_hotplug_processing
;
1474 unsigned long hpd_last_jiffies
;
1479 HPD_MARK_DISABLED
= 2
1481 } hpd_stats
[HPD_NUM_PINS
];
1483 struct timer_list hotplug_reenable_timer
;
1485 struct i915_fbc fbc
;
1486 struct intel_opregion opregion
;
1487 struct intel_vbt_data vbt
;
1490 struct intel_overlay
*overlay
;
1492 /* backlight registers and fields in struct intel_panel */
1493 spinlock_t backlight_lock
;
1496 bool no_aux_handshake
;
1498 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1499 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1500 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1502 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1505 * wq - Driver workqueue for GEM.
1507 * NOTE: Work items scheduled here are not allowed to grab any modeset
1508 * locks, for otherwise the flushing done in the pageflip code will
1509 * result in deadlocks.
1511 struct workqueue_struct
*wq
;
1513 /* Display functions */
1514 struct drm_i915_display_funcs display
;
1516 /* PCH chipset type */
1517 enum intel_pch pch_type
;
1518 unsigned short pch_id
;
1520 unsigned long quirks
;
1522 enum modeset_restore modeset_restore
;
1523 struct mutex modeset_restore_lock
;
1525 struct list_head vm_list
; /* Global list of all address spaces */
1526 struct i915_gtt gtt
; /* VMA representing the global address space */
1528 struct i915_gem_mm mm
;
1530 /* Kernel Modesetting */
1532 struct sdvo_device_mapping sdvo_mappings
[2];
1534 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1535 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1536 wait_queue_head_t pending_flip_queue
;
1538 #ifdef CONFIG_DEBUG_FS
1539 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1542 int num_shared_dpll
;
1543 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1544 struct intel_ddi_plls ddi_plls
;
1545 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1547 /* Reclocking support */
1548 bool render_reclock_avail
;
1549 bool lvds_downclock_avail
;
1550 /* indicates the reduced downclock for LVDS*/
1554 bool mchbar_need_disable
;
1556 struct intel_l3_parity l3_parity
;
1558 /* Cannot be determined by PCIID. You must always read a register. */
1561 /* gen6+ rps state */
1562 struct intel_gen6_power_mgmt rps
;
1564 /* ilk-only ips/rps state. Everything in here is protected by the global
1565 * mchdev_lock in intel_pm.c */
1566 struct intel_ilk_power_mgmt ips
;
1568 struct i915_power_domains power_domains
;
1570 struct i915_psr psr
;
1572 struct i915_gpu_error gpu_error
;
1574 struct drm_i915_gem_object
*vlv_pctx
;
1576 #ifdef CONFIG_DRM_I915_FBDEV
1577 /* list of fbdev register on this device */
1578 struct intel_fbdev
*fbdev
;
1582 * The console may be contended at resume, but we don't
1583 * want it to block on it.
1585 struct work_struct console_resume_work
;
1587 struct drm_property
*broadcast_rgb_property
;
1588 struct drm_property
*force_audio_property
;
1590 uint32_t hw_context_size
;
1591 struct list_head context_list
;
1596 struct i915_suspend_saved_registers regfile
;
1600 * Raw watermark latency values:
1601 * in 0.1us units for WM0,
1602 * in 0.5us units for WM1+.
1605 uint16_t pri_latency
[5];
1607 uint16_t spr_latency
[5];
1609 uint16_t cur_latency
[5];
1611 /* current hardware state */
1612 struct ilk_wm_values hw
;
1615 struct i915_runtime_pm pm
;
1617 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1619 struct i915_dri1_state dri1
;
1620 /* Old ums support infrastructure, same warning applies. */
1621 struct i915_ums_state ums
;
1622 } drm_i915_private_t
;
1624 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1626 return dev
->dev_private
;
1629 /* Iterate over initialised rings */
1630 #define for_each_ring(ring__, dev_priv__, i__) \
1631 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1632 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1634 enum hdmi_force_audio
{
1635 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1636 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1637 HDMI_AUDIO_AUTO
, /* trust EDID */
1638 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1641 #define I915_GTT_OFFSET_NONE ((u32)-1)
1643 struct drm_i915_gem_object_ops
{
1644 /* Interface between the GEM object and its backing storage.
1645 * get_pages() is called once prior to the use of the associated set
1646 * of pages before to binding them into the GTT, and put_pages() is
1647 * called after we no longer need them. As we expect there to be
1648 * associated cost with migrating pages between the backing storage
1649 * and making them available for the GPU (e.g. clflush), we may hold
1650 * onto the pages after they are no longer referenced by the GPU
1651 * in case they may be used again shortly (for example migrating the
1652 * pages to a different memory domain within the GTT). put_pages()
1653 * will therefore most likely be called when the object itself is
1654 * being released or under memory pressure (where we attempt to
1655 * reap pages for the shrinker).
1657 int (*get_pages
)(struct drm_i915_gem_object
*);
1658 void (*put_pages
)(struct drm_i915_gem_object
*);
1661 struct drm_i915_gem_object
{
1662 struct drm_gem_object base
;
1664 const struct drm_i915_gem_object_ops
*ops
;
1666 /** List of VMAs backed by this object */
1667 struct list_head vma_list
;
1669 /** Stolen memory for this object, instead of being backed by shmem. */
1670 struct drm_mm_node
*stolen
;
1671 struct list_head global_list
;
1673 struct list_head ring_list
;
1674 /** Used in execbuf to temporarily hold a ref */
1675 struct list_head obj_exec_link
;
1678 * This is set if the object is on the active lists (has pending
1679 * rendering and so a non-zero seqno), and is not set if it i s on
1680 * inactive (ready to be unbound) list.
1682 unsigned int active
:1;
1685 * This is set if the object has been written to since last bound
1688 unsigned int dirty
:1;
1691 * Fence register bits (if any) for this object. Will be set
1692 * as needed when mapped into the GTT.
1693 * Protected by dev->struct_mutex.
1695 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1698 * Advice: are the backing pages purgeable?
1700 unsigned int madv
:2;
1703 * Current tiling mode for the object.
1705 unsigned int tiling_mode
:2;
1707 * Whether the tiling parameters for the currently associated fence
1708 * register have changed. Note that for the purposes of tracking
1709 * tiling changes we also treat the unfenced register, the register
1710 * slot that the object occupies whilst it executes a fenced
1711 * command (such as BLT on gen2/3), as a "fence".
1713 unsigned int fence_dirty
:1;
1716 * Is the object at the current location in the gtt mappable and
1717 * fenceable? Used to avoid costly recalculations.
1719 unsigned int map_and_fenceable
:1;
1722 * Whether the current gtt mapping needs to be mappable (and isn't just
1723 * mappable by accident). Track pin and fault separate for a more
1724 * accurate mappable working set.
1726 unsigned int fault_mappable
:1;
1727 unsigned int pin_mappable
:1;
1728 unsigned int pin_display
:1;
1731 * Is the GPU currently using a fence to access this buffer,
1733 unsigned int pending_fenced_gpu_access
:1;
1734 unsigned int fenced_gpu_access
:1;
1736 unsigned int cache_level
:3;
1738 unsigned int has_aliasing_ppgtt_mapping
:1;
1739 unsigned int has_global_gtt_mapping
:1;
1740 unsigned int has_dma_mapping
:1;
1742 struct sg_table
*pages
;
1743 int pages_pin_count
;
1745 /* prime dma-buf support */
1746 void *dma_buf_vmapping
;
1749 struct intel_ring_buffer
*ring
;
1751 /** Breadcrumb of last rendering to the buffer. */
1752 uint32_t last_read_seqno
;
1753 uint32_t last_write_seqno
;
1754 /** Breadcrumb of last fenced GPU access to the buffer. */
1755 uint32_t last_fenced_seqno
;
1757 /** Current tiling stride for the object, if it's tiled. */
1760 /** References from framebuffers, locks out tiling changes. */
1761 unsigned long framebuffer_references
;
1763 /** Record of address bit 17 of each page at last unbind. */
1764 unsigned long *bit_17
;
1766 /** User space pin count and filp owning the pin */
1767 unsigned long user_pin_count
;
1768 struct drm_file
*pin_filp
;
1770 /** for phy allocated objects */
1771 struct drm_i915_gem_phys_object
*phys_obj
;
1774 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1777 * Request queue structure.
1779 * The request queue allows us to note sequence numbers that have been emitted
1780 * and may be associated with active buffers to be retired.
1782 * By keeping this list, we can avoid having to do questionable
1783 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1784 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1786 struct drm_i915_gem_request
{
1787 /** On Which ring this request was generated */
1788 struct intel_ring_buffer
*ring
;
1790 /** GEM sequence number associated with this request. */
1793 /** Position in the ringbuffer of the start of the request */
1796 /** Position in the ringbuffer of the end of the request */
1799 /** Context related to this request */
1800 struct i915_hw_context
*ctx
;
1802 /** Batch buffer related to this request if any */
1803 struct drm_i915_gem_object
*batch_obj
;
1805 /** Time at which this request was emitted, in jiffies. */
1806 unsigned long emitted_jiffies
;
1808 /** global list entry for this request */
1809 struct list_head list
;
1811 struct drm_i915_file_private
*file_priv
;
1812 /** file_priv list entry for this request */
1813 struct list_head client_list
;
1816 struct drm_i915_file_private
{
1817 struct drm_i915_private
*dev_priv
;
1818 struct drm_file
*file
;
1822 struct list_head request_list
;
1823 struct delayed_work idle_work
;
1825 struct idr context_idr
;
1827 struct i915_hw_context
*private_default_ctx
;
1828 atomic_t rps_wait_boost
;
1832 * A command that requires special handling by the command parser.
1834 struct drm_i915_cmd_descriptor
{
1836 * Flags describing how the command parser processes the command.
1838 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1839 * a length mask if not set
1840 * CMD_DESC_SKIP: The command is allowed but does not follow the
1841 * standard length encoding for the opcode range in
1843 * CMD_DESC_REJECT: The command is never allowed
1844 * CMD_DESC_REGISTER: The command should be checked against the
1845 * register whitelist for the appropriate ring
1846 * CMD_DESC_MASTER: The command is allowed if the submitting process
1850 #define CMD_DESC_FIXED (1<<0)
1851 #define CMD_DESC_SKIP (1<<1)
1852 #define CMD_DESC_REJECT (1<<2)
1853 #define CMD_DESC_REGISTER (1<<3)
1854 #define CMD_DESC_BITMASK (1<<4)
1855 #define CMD_DESC_MASTER (1<<5)
1858 * The command's unique identification bits and the bitmask to get them.
1859 * This isn't strictly the opcode field as defined in the spec and may
1860 * also include type, subtype, and/or subop fields.
1868 * The command's length. The command is either fixed length (i.e. does
1869 * not include a length field) or has a length field mask. The flag
1870 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1871 * a length mask. All command entries in a command table must include
1872 * length information.
1880 * Describes where to find a register address in the command to check
1881 * against the ring's register whitelist. Only valid if flags has the
1882 * CMD_DESC_REGISTER bit set.
1889 #define MAX_CMD_DESC_BITMASKS 3
1891 * Describes command checks where a particular dword is masked and
1892 * compared against an expected value. If the command does not match
1893 * the expected value, the parser rejects it. Only valid if flags has
1894 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1901 } bits
[MAX_CMD_DESC_BITMASKS
];
1905 * A table of commands requiring special handling by the command parser.
1907 * Each ring has an array of tables. Each table consists of an array of command
1908 * descriptors, which must be sorted with command opcodes in ascending order.
1910 struct drm_i915_cmd_table
{
1911 const struct drm_i915_cmd_descriptor
*table
;
1915 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1917 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1918 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1919 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1920 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1921 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1922 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1923 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1924 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1925 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1926 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1927 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1928 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1929 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1930 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1931 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1932 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1933 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1934 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1935 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1936 (dev)->pdev->device == 0x0152 || \
1937 (dev)->pdev->device == 0x015a)
1938 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1939 (dev)->pdev->device == 0x0106 || \
1940 (dev)->pdev->device == 0x010A)
1941 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1942 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1943 #define IS_BROADWELL(dev) (INTEL_INFO(dev)->gen == 8)
1944 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1945 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1946 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1947 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1948 (((dev)->pdev->device & 0xf) == 0x2 || \
1949 ((dev)->pdev->device & 0xf) == 0x6 || \
1950 ((dev)->pdev->device & 0xf) == 0xe))
1951 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1952 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1953 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1954 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1955 ((dev)->pdev->device & 0x00F0) == 0x0020)
1956 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1959 * The genX designation typically refers to the render engine, so render
1960 * capability related checks should use IS_GEN, while display and other checks
1961 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1964 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1965 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1966 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1967 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1968 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1969 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1970 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1972 #define RENDER_RING (1<<RCS)
1973 #define BSD_RING (1<<VCS)
1974 #define BLT_RING (1<<BCS)
1975 #define VEBOX_RING (1<<VECS)
1976 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1977 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1978 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1979 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1980 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1981 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1983 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1984 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1985 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1986 && !IS_BROADWELL(dev))
1987 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1988 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1990 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1991 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1993 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1994 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1996 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1997 * even when in MSI mode. This results in spurious interrupt warnings if the
1998 * legacy irq no. is shared with another device. The kernel then disables that
1999 * interrupt source and so prevents the other device from working properly.
2001 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2002 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2004 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2005 * rows, which changed the alignment requirements and fence programming.
2007 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2009 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2010 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2011 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2012 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2013 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2015 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2016 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2017 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2019 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2021 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2022 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2023 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2024 #define HAS_PC8(dev) (IS_HASWELL(dev)) /* XXX HSW:ULX */
2025 #define HAS_RUNTIME_PM(dev) (IS_HASWELL(dev))
2027 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2028 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2029 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2030 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2031 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2032 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2034 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2035 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2036 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2037 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2038 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2039 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2041 /* DPF == dynamic parity feature */
2042 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2043 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2045 #define GT_FREQUENCY_MULTIPLIER 50
2047 #include "i915_trace.h"
2049 extern const struct drm_ioctl_desc i915_ioctls
[];
2050 extern int i915_max_ioctl
;
2052 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
2053 extern int i915_resume(struct drm_device
*dev
);
2054 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2055 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2058 struct i915_params
{
2060 int panel_ignore_lid
;
2061 unsigned int powersave
;
2063 unsigned int lvds_downclock
;
2064 int lvds_channel_mode
;
2066 int vbt_sdvo_panel_type
;
2071 unsigned int preliminary_hw_support
;
2072 int disable_power_well
;
2074 int invert_brightness
;
2075 int enable_cmd_parser
;
2076 /* leave bools at the end to not create holes */
2077 bool enable_hangcheck
;
2079 bool prefault_disable
;
2081 bool disable_display
;
2083 extern struct i915_params i915 __read_mostly
;
2086 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2087 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2088 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2089 extern int i915_driver_unload(struct drm_device
*);
2090 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
2091 extern void i915_driver_lastclose(struct drm_device
* dev
);
2092 extern void i915_driver_preclose(struct drm_device
*dev
,
2093 struct drm_file
*file_priv
);
2094 extern void i915_driver_postclose(struct drm_device
*dev
,
2095 struct drm_file
*file_priv
);
2096 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2097 #ifdef CONFIG_COMPAT
2098 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2101 extern int i915_emit_box(struct drm_device
*dev
,
2102 struct drm_clip_rect
*box
,
2104 extern int intel_gpu_reset(struct drm_device
*dev
);
2105 extern int i915_reset(struct drm_device
*dev
);
2106 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2107 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2108 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2109 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2111 extern void intel_console_resume(struct work_struct
*work
);
2114 void i915_queue_hangcheck(struct drm_device
*dev
);
2116 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2117 const char *fmt
, ...);
2119 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2121 extern void intel_irq_init(struct drm_device
*dev
);
2122 extern void intel_hpd_init(struct drm_device
*dev
);
2124 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2125 extern void intel_uncore_early_sanitize(struct drm_device
*dev
);
2126 extern void intel_uncore_init(struct drm_device
*dev
);
2127 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2128 extern void intel_uncore_fini(struct drm_device
*dev
);
2131 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2135 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2138 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2139 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2142 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2143 struct drm_file
*file_priv
);
2144 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2145 struct drm_file
*file_priv
);
2146 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2147 struct drm_file
*file_priv
);
2148 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2149 struct drm_file
*file_priv
);
2150 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2151 struct drm_file
*file_priv
);
2152 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2153 struct drm_file
*file_priv
);
2154 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2155 struct drm_file
*file_priv
);
2156 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2157 struct drm_file
*file_priv
);
2158 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2159 struct drm_file
*file_priv
);
2160 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2161 struct drm_file
*file_priv
);
2162 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2163 struct drm_file
*file_priv
);
2164 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2165 struct drm_file
*file_priv
);
2166 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2167 struct drm_file
*file_priv
);
2168 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2169 struct drm_file
*file
);
2170 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2171 struct drm_file
*file
);
2172 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2173 struct drm_file
*file_priv
);
2174 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2175 struct drm_file
*file_priv
);
2176 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2177 struct drm_file
*file_priv
);
2178 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2179 struct drm_file
*file_priv
);
2180 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2181 struct drm_file
*file_priv
);
2182 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2183 struct drm_file
*file_priv
);
2184 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2185 struct drm_file
*file_priv
);
2186 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2187 struct drm_file
*file_priv
);
2188 void i915_gem_load(struct drm_device
*dev
);
2189 void *i915_gem_object_alloc(struct drm_device
*dev
);
2190 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2191 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2192 const struct drm_i915_gem_object_ops
*ops
);
2193 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2195 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2196 struct i915_address_space
*vm
);
2197 void i915_gem_free_object(struct drm_gem_object
*obj
);
2198 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2200 #define PIN_MAPPABLE 0x1
2201 #define PIN_NONBLOCK 0x2
2202 #define PIN_GLOBAL 0x4
2203 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2204 struct i915_address_space
*vm
,
2207 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2208 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2209 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2210 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2211 void i915_gem_lastclose(struct drm_device
*dev
);
2213 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2214 int *needs_clflush
);
2216 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2217 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2219 struct sg_page_iter sg_iter
;
2221 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2222 return sg_page_iter_page(&sg_iter
);
2226 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2228 BUG_ON(obj
->pages
== NULL
);
2229 obj
->pages_pin_count
++;
2231 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2233 BUG_ON(obj
->pages_pin_count
== 0);
2234 obj
->pages_pin_count
--;
2237 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2238 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2239 struct intel_ring_buffer
*to
);
2240 void i915_vma_move_to_active(struct i915_vma
*vma
,
2241 struct intel_ring_buffer
*ring
);
2242 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2243 struct drm_device
*dev
,
2244 struct drm_mode_create_dumb
*args
);
2245 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2246 uint32_t handle
, uint64_t *offset
);
2248 * Returns true if seq1 is later than seq2.
2251 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2253 return (int32_t)(seq1
- seq2
) >= 0;
2256 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2257 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2258 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2259 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2262 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
2264 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2265 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2266 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
2273 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
2275 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
2276 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2277 WARN_ON(dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
<= 0);
2278 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
2282 struct drm_i915_gem_request
*
2283 i915_gem_find_active_request(struct intel_ring_buffer
*ring
);
2285 bool i915_gem_retire_requests(struct drm_device
*dev
);
2286 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2287 bool interruptible
);
2288 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2290 return unlikely(atomic_read(&error
->reset_counter
)
2291 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2294 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2296 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2299 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2301 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2304 void i915_gem_reset(struct drm_device
*dev
);
2305 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2306 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2307 int __must_check
i915_gem_init(struct drm_device
*dev
);
2308 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2309 int i915_gem_l3_remap(struct intel_ring_buffer
*ring
, int slice
);
2310 void i915_gem_init_swizzling(struct drm_device
*dev
);
2311 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2312 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2313 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2314 int __i915_add_request(struct intel_ring_buffer
*ring
,
2315 struct drm_file
*file
,
2316 struct drm_i915_gem_object
*batch_obj
,
2318 #define i915_add_request(ring, seqno) \
2319 __i915_add_request(ring, NULL, NULL, seqno)
2320 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
2322 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2324 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2327 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2329 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2331 struct intel_ring_buffer
*pipelined
);
2332 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2333 int i915_gem_attach_phys_object(struct drm_device
*dev
,
2334 struct drm_i915_gem_object
*obj
,
2337 void i915_gem_detach_phys_object(struct drm_device
*dev
,
2338 struct drm_i915_gem_object
*obj
);
2339 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
2340 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2341 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2344 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2346 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2347 int tiling_mode
, bool fenced
);
2349 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2350 enum i915_cache_level cache_level
);
2352 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2353 struct dma_buf
*dma_buf
);
2355 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2356 struct drm_gem_object
*gem_obj
, int flags
);
2358 void i915_gem_restore_fences(struct drm_device
*dev
);
2360 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2361 struct i915_address_space
*vm
);
2362 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2363 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2364 struct i915_address_space
*vm
);
2365 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2366 struct i915_address_space
*vm
);
2367 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2368 struct i915_address_space
*vm
);
2370 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2371 struct i915_address_space
*vm
);
2373 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2374 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2375 struct i915_vma
*vma
;
2376 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2377 if (vma
->pin_count
> 0)
2382 /* Some GGTT VM helpers */
2383 #define obj_to_ggtt(obj) \
2384 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2385 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2387 struct i915_address_space
*ggtt
=
2388 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2392 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2394 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
2397 static inline unsigned long
2398 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2400 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
2403 static inline unsigned long
2404 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2406 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
2409 static inline int __must_check
2410 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2414 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
, flags
| PIN_GLOBAL
);
2418 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2420 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2423 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2425 /* i915_gem_context.c */
2426 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2427 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2428 void i915_gem_context_fini(struct drm_device
*dev
);
2429 void i915_gem_context_reset(struct drm_device
*dev
);
2430 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2431 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2432 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2433 int i915_switch_context(struct intel_ring_buffer
*ring
,
2434 struct drm_file
*file
, struct i915_hw_context
*to
);
2435 struct i915_hw_context
*
2436 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2437 void i915_gem_context_free(struct kref
*ctx_ref
);
2438 static inline void i915_gem_context_reference(struct i915_hw_context
*ctx
)
2440 if (ctx
->obj
&& HAS_HW_CONTEXTS(ctx
->obj
->base
.dev
))
2441 kref_get(&ctx
->ref
);
2444 static inline void i915_gem_context_unreference(struct i915_hw_context
*ctx
)
2446 if (ctx
->obj
&& HAS_HW_CONTEXTS(ctx
->obj
->base
.dev
))
2447 kref_put(&ctx
->ref
, i915_gem_context_free
);
2450 static inline bool i915_gem_context_is_default(const struct i915_hw_context
*c
)
2452 return c
->id
== DEFAULT_CONTEXT_ID
;
2455 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2456 struct drm_file
*file
);
2457 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2458 struct drm_file
*file
);
2460 /* i915_gem_evict.c */
2461 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2462 struct i915_address_space
*vm
,
2465 unsigned cache_level
,
2467 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2468 int i915_gem_evict_everything(struct drm_device
*dev
);
2470 /* i915_gem_gtt.c */
2471 void i915_check_and_clear_faults(struct drm_device
*dev
);
2472 void i915_gem_suspend_gtt_mappings(struct drm_device
*dev
);
2473 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
2474 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
2475 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
2476 void i915_gem_init_global_gtt(struct drm_device
*dev
);
2477 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
2478 unsigned long mappable_end
, unsigned long end
);
2479 int i915_gem_gtt_init(struct drm_device
*dev
);
2480 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2482 if (INTEL_INFO(dev
)->gen
< 6)
2483 intel_gtt_chipset_flush();
2485 int i915_gem_init_ppgtt(struct drm_device
*dev
, struct i915_hw_ppgtt
*ppgtt
);
2486 bool intel_enable_ppgtt(struct drm_device
*dev
, bool full
);
2488 /* i915_gem_stolen.c */
2489 int i915_gem_init_stolen(struct drm_device
*dev
);
2490 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
2491 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2492 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2493 struct drm_i915_gem_object
*
2494 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2495 struct drm_i915_gem_object
*
2496 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2500 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
2502 /* i915_gem_tiling.c */
2503 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2505 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2507 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2508 obj
->tiling_mode
!= I915_TILING_NONE
;
2511 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2512 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2513 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2515 /* i915_gem_debug.c */
2517 int i915_verify_lists(struct drm_device
*dev
);
2519 #define i915_verify_lists(dev) 0
2522 /* i915_debugfs.c */
2523 int i915_debugfs_init(struct drm_minor
*minor
);
2524 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2525 #ifdef CONFIG_DEBUG_FS
2526 void intel_display_crc_init(struct drm_device
*dev
);
2528 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2531 /* i915_gpu_error.c */
2533 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2534 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2535 const struct i915_error_state_file_priv
*error
);
2536 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2537 size_t count
, loff_t pos
);
2538 static inline void i915_error_state_buf_release(
2539 struct drm_i915_error_state_buf
*eb
)
2543 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2544 const char *error_msg
);
2545 void i915_error_state_get(struct drm_device
*dev
,
2546 struct i915_error_state_file_priv
*error_priv
);
2547 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2548 void i915_destroy_error_state(struct drm_device
*dev
);
2550 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2551 const char *i915_cache_level_str(int type
);
2553 /* i915_cmd_parser.c */
2554 void i915_cmd_parser_init_ring(struct intel_ring_buffer
*ring
);
2555 bool i915_needs_cmd_parser(struct intel_ring_buffer
*ring
);
2556 int i915_parse_cmds(struct intel_ring_buffer
*ring
,
2557 struct drm_i915_gem_object
*batch_obj
,
2558 u32 batch_start_offset
,
2561 /* i915_suspend.c */
2562 extern int i915_save_state(struct drm_device
*dev
);
2563 extern int i915_restore_state(struct drm_device
*dev
);
2566 void i915_save_display_reg(struct drm_device
*dev
);
2567 void i915_restore_display_reg(struct drm_device
*dev
);
2570 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2571 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2574 extern int intel_setup_gmbus(struct drm_device
*dev
);
2575 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2576 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2578 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2581 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2582 struct drm_i915_private
*dev_priv
, unsigned port
);
2583 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2584 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2585 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2587 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2589 extern void intel_i2c_reset(struct drm_device
*dev
);
2591 /* intel_opregion.c */
2592 struct intel_encoder
;
2594 extern int intel_opregion_setup(struct drm_device
*dev
);
2595 extern void intel_opregion_init(struct drm_device
*dev
);
2596 extern void intel_opregion_fini(struct drm_device
*dev
);
2597 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2598 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2600 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2603 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2604 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2605 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2606 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2608 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2613 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2621 extern void intel_register_dsm_handler(void);
2622 extern void intel_unregister_dsm_handler(void);
2624 static inline void intel_register_dsm_handler(void) { return; }
2625 static inline void intel_unregister_dsm_handler(void) { return; }
2626 #endif /* CONFIG_ACPI */
2629 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2630 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2631 extern void intel_modeset_init(struct drm_device
*dev
);
2632 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2633 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2634 extern void intel_connector_unregister(struct intel_connector
*);
2635 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2636 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2637 bool force_restore
);
2638 extern void i915_redisable_vga(struct drm_device
*dev
);
2639 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2640 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2641 extern void intel_disable_fbc(struct drm_device
*dev
);
2642 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2643 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2644 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2645 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2646 extern int valleyview_rps_max_freq(struct drm_i915_private
*dev_priv
);
2647 extern int valleyview_rps_min_freq(struct drm_i915_private
*dev_priv
);
2648 extern void intel_detect_pch(struct drm_device
*dev
);
2649 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2650 extern int intel_enable_rc6(const struct drm_device
*dev
);
2652 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2653 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2654 struct drm_file
*file
);
2655 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2656 struct drm_file
*file
);
2659 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2660 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2661 struct intel_overlay_error_state
*error
);
2663 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2664 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2665 struct drm_device
*dev
,
2666 struct intel_display_error_state
*error
);
2668 /* On SNB platform, before reading ring registers forcewake bit
2669 * must be set to prevent GT core from power down and stale values being
2672 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2673 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2674 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2676 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2677 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2679 /* intel_sideband.c */
2680 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2681 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2682 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2683 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2684 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2685 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2686 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2687 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2688 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2689 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2690 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2691 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2692 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2693 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2694 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2695 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2696 enum intel_sbi_destination destination
);
2697 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2698 enum intel_sbi_destination destination
);
2699 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2700 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2702 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2703 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2705 void vlv_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2706 void vlv_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2708 #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \
2709 (((reg) >= 0x2000 && (reg) < 0x4000) ||\
2710 ((reg) >= 0x5000 && (reg) < 0x8000) ||\
2711 ((reg) >= 0xB000 && (reg) < 0x12000) ||\
2712 ((reg) >= 0x2E000 && (reg) < 0x30000))
2714 #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)\
2715 (((reg) >= 0x12000 && (reg) < 0x14000) ||\
2716 ((reg) >= 0x22000 && (reg) < 0x24000) ||\
2717 ((reg) >= 0x30000 && (reg) < 0x40000))
2719 #define FORCEWAKE_RENDER (1 << 0)
2720 #define FORCEWAKE_MEDIA (1 << 1)
2721 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2724 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2725 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2727 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2728 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2729 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2730 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2732 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2733 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2734 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2735 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2737 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2738 * will be implemented using 2 32-bit writes in an arbitrary order with
2739 * an arbitrary delay between them. This can cause the hardware to
2740 * act upon the intermediate value, possibly leading to corruption and
2741 * machine death. You have been warned.
2743 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2744 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2746 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2747 u32 upper = I915_READ(upper_reg); \
2748 u32 lower = I915_READ(lower_reg); \
2749 u32 tmp = I915_READ(upper_reg); \
2750 if (upper != tmp) { \
2752 lower = I915_READ(lower_reg); \
2753 WARN_ON(I915_READ(upper_reg) != upper); \
2755 (u64)upper << 32 | lower; })
2757 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2758 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2760 /* "Broadcast RGB" property */
2761 #define INTEL_BROADCAST_RGB_AUTO 0
2762 #define INTEL_BROADCAST_RGB_FULL 1
2763 #define INTEL_BROADCAST_RGB_LIMITED 2
2765 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2767 if (HAS_PCH_SPLIT(dev
))
2768 return CPU_VGACNTRL
;
2769 else if (IS_VALLEYVIEW(dev
))
2770 return VLV_VGACNTRL
;
2775 static inline void __user
*to_user_ptr(u64 address
)
2777 return (void __user
*)(uintptr_t)address
;
2780 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2782 unsigned long j
= msecs_to_jiffies(m
);
2784 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2787 static inline unsigned long
2788 timespec_to_jiffies_timeout(const struct timespec
*value
)
2790 unsigned long j
= timespec_to_jiffies(value
);
2792 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2796 * If you need to wait X milliseconds between events A and B, but event B
2797 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2798 * when event A happened, then just before event B you call this function and
2799 * pass the timestamp as the first argument, and X as the second argument.
2802 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
2804 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
2807 * Don't re-read the value of "jiffies" every time since it may change
2808 * behind our back and break the math.
2810 tmp_jiffies
= jiffies
;
2811 target_jiffies
= timestamp_jiffies
+
2812 msecs_to_jiffies_timeout(to_wait_ms
);
2814 if (time_after(target_jiffies
, tmp_jiffies
)) {
2815 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
2816 while (remaining_jiffies
)
2818 schedule_timeout_uninterruptible(remaining_jiffies
);