1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include <linux/io-mapping.h>
39 #include <linux/i2c.h>
40 #include <linux/i2c-algo-bit.h>
41 #include <drm/intel-gtt.h>
42 #include <linux/backlight.h>
43 #include <linux/intel-iommu.h>
44 #include <linux/kref.h>
45 #include <linux/pm_qos.h>
47 /* General customization:
50 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52 #define DRIVER_NAME "i915"
53 #define DRIVER_DESC "Intel Graphics"
54 #define DRIVER_DATE "20080730"
62 #define pipe_name(p) ((p) + 'A')
70 #define transcoder_name(t) ((t) + 'A')
77 #define plane_name(p) ((p) + 'A')
87 #define port_name(p) ((p) + 'A')
91 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
92 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
102 #define I915_GEM_GPU_DOMAINS \
103 (I915_GEM_DOMAIN_RENDER | \
104 I915_GEM_DOMAIN_SAMPLER | \
105 I915_GEM_DOMAIN_COMMAND | \
106 I915_GEM_DOMAIN_INSTRUCTION | \
107 I915_GEM_DOMAIN_VERTEX)
109 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
111 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
112 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
113 if ((intel_encoder)->base.crtc == (__crtc))
115 struct intel_pch_pll
{
116 int refcount
; /* count of number of CRTCs sharing this PLL */
117 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
118 bool on
; /* is the PLL actually active? Disabled during modeset */
123 #define I915_NUM_PLLS 2
125 /* Used by dp and fdi links */
126 struct intel_link_m_n
{
134 void intel_link_compute_m_n(int bpp
, int nlanes
,
135 int pixel_clock
, int link_clock
,
136 struct intel_link_m_n
*m_n
);
138 struct intel_ddi_plls
{
144 /* Interface history:
147 * 1.2: Add Power Management
148 * 1.3: Add vblank support
149 * 1.4: Fix cmdbuffer path, add heap destroy
150 * 1.5: Add vblank pipe configuration
151 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
152 * - Support vertical blank on secondary display pipe
154 #define DRIVER_MAJOR 1
155 #define DRIVER_MINOR 6
156 #define DRIVER_PATCHLEVEL 0
158 #define WATCH_COHERENCY 0
159 #define WATCH_LISTS 0
162 #define I915_GEM_PHYS_CURSOR_0 1
163 #define I915_GEM_PHYS_CURSOR_1 2
164 #define I915_GEM_PHYS_OVERLAY_REGS 3
165 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
167 struct drm_i915_gem_phys_object
{
169 struct page
**page_list
;
170 drm_dma_handle_t
*handle
;
171 struct drm_i915_gem_object
*cur_obj
;
174 struct opregion_header
;
175 struct opregion_acpi
;
176 struct opregion_swsci
;
177 struct opregion_asle
;
178 struct drm_i915_private
;
180 struct intel_opregion
{
181 struct opregion_header __iomem
*header
;
182 struct opregion_acpi __iomem
*acpi
;
183 struct opregion_swsci __iomem
*swsci
;
184 struct opregion_asle __iomem
*asle
;
186 u32 __iomem
*lid_state
;
188 #define OPREGION_SIZE (8*1024)
190 struct intel_overlay
;
191 struct intel_overlay_error_state
;
193 struct drm_i915_master_private
{
194 drm_local_map_t
*sarea
;
195 struct _drm_i915_sarea
*sarea_priv
;
197 #define I915_FENCE_REG_NONE -1
198 #define I915_MAX_NUM_FENCES 32
199 /* 32 fences + sign bit for FENCE_REG_NONE */
200 #define I915_MAX_NUM_FENCE_BITS 6
202 struct drm_i915_fence_reg
{
203 struct list_head lru_list
;
204 struct drm_i915_gem_object
*obj
;
208 struct sdvo_device_mapping
{
217 struct intel_display_error_state
;
219 struct drm_i915_error_state
{
227 bool waiting
[I915_NUM_RINGS
];
228 u32 pipestat
[I915_MAX_PIPES
];
229 u32 tail
[I915_NUM_RINGS
];
230 u32 head
[I915_NUM_RINGS
];
231 u32 ctl
[I915_NUM_RINGS
];
232 u32 ipeir
[I915_NUM_RINGS
];
233 u32 ipehr
[I915_NUM_RINGS
];
234 u32 instdone
[I915_NUM_RINGS
];
235 u32 acthd
[I915_NUM_RINGS
];
236 u32 semaphore_mboxes
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
237 u32 semaphore_seqno
[I915_NUM_RINGS
][I915_NUM_RINGS
- 1];
238 u32 rc_psmi
[I915_NUM_RINGS
]; /* sleep state */
239 /* our own tracking of ring head and tail */
240 u32 cpu_ring_head
[I915_NUM_RINGS
];
241 u32 cpu_ring_tail
[I915_NUM_RINGS
];
242 u32 error
; /* gen6+ */
243 u32 err_int
; /* gen7 */
244 u32 instpm
[I915_NUM_RINGS
];
245 u32 instps
[I915_NUM_RINGS
];
246 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
247 u32 seqno
[I915_NUM_RINGS
];
249 u32 fault_reg
[I915_NUM_RINGS
];
251 u32 faddr
[I915_NUM_RINGS
];
252 u64 fence
[I915_MAX_NUM_FENCES
];
254 struct drm_i915_error_ring
{
255 struct drm_i915_error_object
{
259 } *ringbuffer
, *batchbuffer
, *ctx
;
260 struct drm_i915_error_request
{
266 } ring
[I915_NUM_RINGS
];
267 struct drm_i915_error_buffer
{
274 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
281 } *active_bo
, *pinned_bo
;
282 u32 active_bo_count
, pinned_bo_count
;
283 struct intel_overlay_error_state
*overlay
;
284 struct intel_display_error_state
*display
;
287 struct intel_crtc_config
;
290 struct drm_i915_display_funcs
{
291 bool (*fbc_enabled
)(struct drm_device
*dev
);
292 void (*enable_fbc
)(struct drm_crtc
*crtc
, unsigned long interval
);
293 void (*disable_fbc
)(struct drm_device
*dev
);
294 int (*get_display_clock_speed
)(struct drm_device
*dev
);
295 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
296 void (*update_wm
)(struct drm_device
*dev
);
297 void (*update_sprite_wm
)(struct drm_device
*dev
, int pipe
,
298 uint32_t sprite_width
, int pixel_size
);
299 void (*update_linetime_wm
)(struct drm_device
*dev
, int pipe
,
300 struct drm_display_mode
*mode
);
301 void (*modeset_global_resources
)(struct drm_device
*dev
);
302 /* Returns the active state of the crtc, and if the crtc is active,
303 * fills out the pipe-config with the hw state. */
304 bool (*get_pipe_config
)(struct intel_crtc
*,
305 struct intel_crtc_config
*);
306 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
308 struct drm_framebuffer
*old_fb
);
309 void (*crtc_enable
)(struct drm_crtc
*crtc
);
310 void (*crtc_disable
)(struct drm_crtc
*crtc
);
311 void (*off
)(struct drm_crtc
*crtc
);
312 void (*write_eld
)(struct drm_connector
*connector
,
313 struct drm_crtc
*crtc
);
314 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
315 void (*init_clock_gating
)(struct drm_device
*dev
);
316 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
317 struct drm_framebuffer
*fb
,
318 struct drm_i915_gem_object
*obj
);
319 int (*update_plane
)(struct drm_crtc
*crtc
, struct drm_framebuffer
*fb
,
321 void (*hpd_irq_setup
)(struct drm_device
*dev
);
322 /* clock updates for mode set */
324 /* render clock increase/decrease */
325 /* display clock increase/decrease */
326 /* pll clock increase/decrease */
329 struct drm_i915_gt_funcs
{
330 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
);
331 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
);
334 #define DEV_INFO_FLAGS \
335 DEV_INFO_FLAG(is_mobile) DEV_INFO_SEP \
336 DEV_INFO_FLAG(is_i85x) DEV_INFO_SEP \
337 DEV_INFO_FLAG(is_i915g) DEV_INFO_SEP \
338 DEV_INFO_FLAG(is_i945gm) DEV_INFO_SEP \
339 DEV_INFO_FLAG(is_g33) DEV_INFO_SEP \
340 DEV_INFO_FLAG(need_gfx_hws) DEV_INFO_SEP \
341 DEV_INFO_FLAG(is_g4x) DEV_INFO_SEP \
342 DEV_INFO_FLAG(is_pineview) DEV_INFO_SEP \
343 DEV_INFO_FLAG(is_broadwater) DEV_INFO_SEP \
344 DEV_INFO_FLAG(is_crestline) DEV_INFO_SEP \
345 DEV_INFO_FLAG(is_ivybridge) DEV_INFO_SEP \
346 DEV_INFO_FLAG(is_valleyview) DEV_INFO_SEP \
347 DEV_INFO_FLAG(is_haswell) DEV_INFO_SEP \
348 DEV_INFO_FLAG(has_force_wake) DEV_INFO_SEP \
349 DEV_INFO_FLAG(has_fbc) DEV_INFO_SEP \
350 DEV_INFO_FLAG(has_pipe_cxsr) DEV_INFO_SEP \
351 DEV_INFO_FLAG(has_hotplug) DEV_INFO_SEP \
352 DEV_INFO_FLAG(cursor_needs_physical) DEV_INFO_SEP \
353 DEV_INFO_FLAG(has_overlay) DEV_INFO_SEP \
354 DEV_INFO_FLAG(overlay_needs_physical) DEV_INFO_SEP \
355 DEV_INFO_FLAG(supports_tv) DEV_INFO_SEP \
356 DEV_INFO_FLAG(has_bsd_ring) DEV_INFO_SEP \
357 DEV_INFO_FLAG(has_blt_ring) DEV_INFO_SEP \
358 DEV_INFO_FLAG(has_llc)
360 struct intel_device_info
{
361 u32 display_mmio_offset
;
381 u8 cursor_needs_physical
:1;
383 u8 overlay_needs_physical
:1;
390 enum i915_cache_level
{
393 I915_CACHE_LLC_MLC
, /* gen6+, in docs at least! */
396 /* The Graphics Translation Table is the way in which GEN hardware translates a
397 * Graphics Virtual Address into a Physical Address. In addition to the normal
398 * collateral associated with any va->pa translations GEN hardware also has a
399 * portion of the GTT which can be mapped by the CPU and remain both coherent
400 * and correct (in cases like swizzling). That region is referred to as GMADR in
404 unsigned long start
; /* Start offset of used GTT */
405 size_t total
; /* Total size GTT can map */
406 size_t stolen_size
; /* Total size of stolen memory */
408 unsigned long mappable_end
; /* End offset that we can CPU map */
409 struct io_mapping
*mappable
; /* Mapping to our CPU mappable region */
410 phys_addr_t mappable_base
; /* PA of our GMADR */
412 /** "Graphics Stolen Memory" holds the global PTEs */
416 dma_addr_t scratch_page_dma
;
417 struct page
*scratch_page
;
420 int (*gtt_probe
)(struct drm_device
*dev
, size_t *gtt_total
,
421 size_t *stolen
, phys_addr_t
*mappable_base
,
422 unsigned long *mappable_end
);
423 void (*gtt_remove
)(struct drm_device
*dev
);
424 void (*gtt_clear_range
)(struct drm_device
*dev
,
425 unsigned int first_entry
,
426 unsigned int num_entries
);
427 void (*gtt_insert_entries
)(struct drm_device
*dev
,
429 unsigned int pg_start
,
430 enum i915_cache_level cache_level
);
432 #define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
434 #define I915_PPGTT_PD_ENTRIES 512
435 #define I915_PPGTT_PT_ENTRIES 1024
436 struct i915_hw_ppgtt
{
437 struct drm_device
*dev
;
438 unsigned num_pd_entries
;
439 struct page
**pt_pages
;
441 dma_addr_t
*pt_dma_addr
;
442 dma_addr_t scratch_page_dma_addr
;
444 /* pte functions, mirroring the interface of the global gtt. */
445 void (*clear_range
)(struct i915_hw_ppgtt
*ppgtt
,
446 unsigned int first_entry
,
447 unsigned int num_entries
);
448 void (*insert_entries
)(struct i915_hw_ppgtt
*ppgtt
,
450 unsigned int pg_start
,
451 enum i915_cache_level cache_level
);
452 int (*enable
)(struct drm_device
*dev
);
453 void (*cleanup
)(struct i915_hw_ppgtt
*ppgtt
);
457 /* This must match up with the value previously used for execbuf2.rsvd1. */
458 #define DEFAULT_CONTEXT_ID 0
459 struct i915_hw_context
{
462 struct drm_i915_file_private
*file_priv
;
463 struct intel_ring_buffer
*ring
;
464 struct drm_i915_gem_object
*obj
;
468 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
469 FBC_STOLEN_TOO_SMALL
, /* not enough space to hold compressed buffers */
470 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
471 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
472 FBC_BAD_PLANE
, /* fbc not supported on plane */
473 FBC_NOT_TILED
, /* buffer not tiled */
474 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
479 PCH_NONE
= 0, /* No PCH present */
480 PCH_IBX
, /* Ibexpeak PCH */
481 PCH_CPT
, /* Cougarpoint PCH */
482 PCH_LPT
, /* Lynxpoint PCH */
486 enum intel_sbi_destination
{
491 #define QUIRK_PIPEA_FORCE (1<<0)
492 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
493 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
496 struct intel_fbc_work
;
499 struct i2c_adapter adapter
;
503 struct i2c_algo_bit_data bit_algo
;
504 struct drm_i915_private
*dev_priv
;
507 struct i915_suspend_saved_registers
{
528 u32 saveTRANS_HTOTAL_A
;
529 u32 saveTRANS_HBLANK_A
;
530 u32 saveTRANS_HSYNC_A
;
531 u32 saveTRANS_VTOTAL_A
;
532 u32 saveTRANS_VBLANK_A
;
533 u32 saveTRANS_VSYNC_A
;
541 u32 savePFIT_PGM_RATIOS
;
542 u32 saveBLC_HIST_CTL
;
544 u32 saveBLC_PWM_CTL2
;
545 u32 saveBLC_CPU_PWM_CTL
;
546 u32 saveBLC_CPU_PWM_CTL2
;
559 u32 saveTRANS_HTOTAL_B
;
560 u32 saveTRANS_HBLANK_B
;
561 u32 saveTRANS_HSYNC_B
;
562 u32 saveTRANS_VTOTAL_B
;
563 u32 saveTRANS_VBLANK_B
;
564 u32 saveTRANS_VSYNC_B
;
578 u32 savePP_ON_DELAYS
;
579 u32 savePP_OFF_DELAYS
;
587 u32 savePFIT_CONTROL
;
588 u32 save_palette_a
[256];
589 u32 save_palette_b
[256];
590 u32 saveDPFC_CB_BASE
;
591 u32 saveFBC_CFB_BASE
;
594 u32 saveFBC_CONTROL2
;
604 u32 saveCACHE_MODE_0
;
605 u32 saveMI_ARB_STATE
;
616 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
627 u32 savePIPEA_GMCH_DATA_M
;
628 u32 savePIPEB_GMCH_DATA_M
;
629 u32 savePIPEA_GMCH_DATA_N
;
630 u32 savePIPEB_GMCH_DATA_N
;
631 u32 savePIPEA_DP_LINK_M
;
632 u32 savePIPEB_DP_LINK_M
;
633 u32 savePIPEA_DP_LINK_N
;
634 u32 savePIPEB_DP_LINK_N
;
645 u32 savePCH_DREF_CONTROL
;
646 u32 saveDISP_ARB_CTL
;
647 u32 savePIPEA_DATA_M1
;
648 u32 savePIPEA_DATA_N1
;
649 u32 savePIPEA_LINK_M1
;
650 u32 savePIPEA_LINK_N1
;
651 u32 savePIPEB_DATA_M1
;
652 u32 savePIPEB_DATA_N1
;
653 u32 savePIPEB_LINK_M1
;
654 u32 savePIPEB_LINK_N1
;
655 u32 saveMCHBAR_RENDER_STANDBY
;
656 u32 savePCH_PORT_HOTPLUG
;
659 struct intel_gen6_power_mgmt
{
660 struct work_struct work
;
662 /* lock - irqsave spinlock that protectects the work_struct and
666 /* The below variables an all the rps hw state are protected by
667 * dev->struct mutext. */
673 struct delayed_work delayed_resume_work
;
676 * Protects RPS/RC6 register access and PCU communication.
677 * Must be taken after struct_mutex if nested.
679 struct mutex hw_lock
;
682 /* defined intel_pm.c */
683 extern spinlock_t mchdev_lock
;
685 struct intel_ilk_power_mgmt
{
693 unsigned long last_time1
;
694 unsigned long chipset_power
;
696 struct timespec last_time2
;
697 unsigned long gfx_power
;
703 struct drm_i915_gem_object
*pwrctx
;
704 struct drm_i915_gem_object
*renderctx
;
707 struct i915_dri1_state
{
708 unsigned allow_batchbuffer
: 1;
709 u32 __iomem
*gfx_hws_cpu_addr
;
720 struct intel_l3_parity
{
722 struct work_struct error_work
;
726 /** Memory allocator for GTT stolen memory */
727 struct drm_mm stolen
;
728 /** Memory allocator for GTT */
729 struct drm_mm gtt_space
;
730 /** List of all objects in gtt_space. Used to restore gtt
731 * mappings on resume */
732 struct list_head bound_list
;
734 * List of objects which are not bound to the GTT (thus
735 * are idle and not used by the GPU) but still have
736 * (presumably uncached) pages still attached.
738 struct list_head unbound_list
;
740 /** Usable portion of the GTT for GEM */
741 unsigned long stolen_base
; /* limited to low memory (32-bit) */
745 /** PPGTT used for aliasing the PPGTT with the GTT */
746 struct i915_hw_ppgtt
*aliasing_ppgtt
;
748 struct shrinker inactive_shrinker
;
749 bool shrinker_no_lock_stealing
;
752 * List of objects currently involved in rendering.
754 * Includes buffers having the contents of their GPU caches
755 * flushed, not necessarily primitives. last_rendering_seqno
756 * represents when the rendering involved will be completed.
758 * A reference is held on the buffer while on this list.
760 struct list_head active_list
;
763 * LRU list of objects which are not in the ringbuffer and
764 * are ready to unbind, but are still in the GTT.
766 * last_rendering_seqno is 0 while an object is in this list.
768 * A reference is not held on the buffer while on this list,
769 * as merely being GTT-bound shouldn't prevent its being
770 * freed, and we'll pull it off the list in the free path.
772 struct list_head inactive_list
;
774 /** LRU list of objects with fence regs on them. */
775 struct list_head fence_list
;
778 * We leave the user IRQ off as much as possible,
779 * but this means that requests will finish and never
780 * be retired once the system goes idle. Set a timer to
781 * fire periodically while the ring is running. When it
782 * fires, go retire requests.
784 struct delayed_work retire_work
;
787 * Are we in a non-interruptible section of code like
793 * Flag if the X Server, and thus DRM, is not currently in
794 * control of the device.
796 * This is set between LeaveVT and EnterVT. It needs to be
797 * replaced with a semaphore. It also needs to be
798 * transitioned away from for kernel modesetting.
802 /** Bit 6 swizzling required for X tiling */
803 uint32_t bit_6_swizzle_x
;
804 /** Bit 6 swizzling required for Y tiling */
805 uint32_t bit_6_swizzle_y
;
807 /* storage for physical objects */
808 struct drm_i915_gem_phys_object
*phys_objs
[I915_MAX_PHYS_OBJECT
];
810 /* accounting, useful for userland debugging */
811 size_t object_memory
;
815 struct i915_gpu_error
{
816 /* For hangcheck timer */
817 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
818 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
819 struct timer_list hangcheck_timer
;
821 uint32_t last_acthd
[I915_NUM_RINGS
];
822 uint32_t prev_instdone
[I915_NUM_INSTDONE_REG
];
824 /* For reset and error_state handling. */
826 /* Protected by the above dev->gpu_error.lock. */
827 struct drm_i915_error_state
*first_error
;
828 struct work_struct work
;
830 unsigned long last_reset
;
833 * State variable and reset counter controlling the reset flow
835 * Upper bits are for the reset counter. This counter is used by the
836 * wait_seqno code to race-free noticed that a reset event happened and
837 * that it needs to restart the entire ioctl (since most likely the
838 * seqno it waited for won't ever signal anytime soon).
840 * This is important for lock-free wait paths, where no contended lock
841 * naturally enforces the correct ordering between the bail-out of the
842 * waiter and the gpu reset work code.
844 * Lowest bit controls the reset state machine: Set means a reset is in
845 * progress. This state will (presuming we don't have any bugs) decay
846 * into either unset (successful reset) or the special WEDGED value (hw
847 * terminally sour). All waiters on the reset_queue will be woken when
850 atomic_t reset_counter
;
853 * Special values/flags for reset_counter
855 * Note that the code relies on
856 * I915_WEDGED & I915_RESET_IN_PROGRESS_FLAG
859 #define I915_RESET_IN_PROGRESS_FLAG 1
860 #define I915_WEDGED 0xffffffff
863 * Waitqueue to signal when the reset has completed. Used by clients
864 * that wait for dev_priv->mm.wedged to settle.
866 wait_queue_head_t reset_queue
;
868 /* For gpu hang simulation. */
869 unsigned int stop_rings
;
872 enum modeset_restore
{
878 typedef struct drm_i915_private
{
879 struct drm_device
*dev
;
880 struct kmem_cache
*slab
;
882 const struct intel_device_info
*info
;
884 int relative_constants_mode
;
888 struct drm_i915_gt_funcs gt
;
889 /** gt_fifo_count and the subsequent register write are synchronized
890 * with dev->struct_mutex. */
891 unsigned gt_fifo_count
;
892 /** forcewake_count is protected by gt_lock */
893 unsigned forcewake_count
;
894 /** gt_lock is also taken in irq contexts. */
897 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
900 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
901 * controller on different i2c buses. */
902 struct mutex gmbus_mutex
;
905 * Base address of the gmbus and gpio block.
907 uint32_t gpio_mmio_base
;
909 wait_queue_head_t gmbus_wait_queue
;
911 struct pci_dev
*bridge_dev
;
912 struct intel_ring_buffer ring
[I915_NUM_RINGS
];
913 uint32_t last_seqno
, next_seqno
;
915 drm_dma_handle_t
*status_page_dmah
;
916 struct resource mch_res
;
918 atomic_t irq_received
;
920 /* protects the irq masks */
923 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
924 struct pm_qos_request pm_qos
;
926 /* DPIO indirect register protection */
927 struct mutex dpio_lock
;
929 /** Cached value of IMR to avoid reads in updating the bitfield */
933 struct work_struct hotplug_work
;
934 bool enable_hotplug_processing
;
936 unsigned long hpd_last_jiffies
;
941 HPD_MARK_DISABLED
= 2
943 } hpd_stats
[HPD_NUM_PINS
];
944 struct timer_list hotplug_reenable_timer
;
949 unsigned long cfb_size
;
951 enum plane cfb_plane
;
953 struct intel_fbc_work
*fbc_work
;
955 struct intel_opregion opregion
;
958 struct intel_overlay
*overlay
;
959 unsigned int sprite_scaling_enabled
;
965 struct backlight_device
*device
;
969 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
970 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
972 /* Feature bits from the VBIOS */
973 unsigned int int_tv_support
:1;
974 unsigned int lvds_dither
:1;
975 unsigned int lvds_vbt
:1;
976 unsigned int int_crt_support
:1;
977 unsigned int lvds_use_ssc
:1;
978 unsigned int display_clock_mode
:1;
979 unsigned int fdi_rx_polarity_inverted
:1;
981 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
991 struct edp_power_seq pps
;
993 bool no_aux_handshake
;
996 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
997 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
998 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1000 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1002 struct workqueue_struct
*wq
;
1004 /* Display functions */
1005 struct drm_i915_display_funcs display
;
1007 /* PCH chipset type */
1008 enum intel_pch pch_type
;
1009 unsigned short pch_id
;
1011 unsigned long quirks
;
1013 enum modeset_restore modeset_restore
;
1014 struct mutex modeset_restore_lock
;
1016 struct i915_gtt gtt
;
1018 struct i915_gem_mm mm
;
1020 /* Kernel Modesetting */
1022 struct sdvo_device_mapping sdvo_mappings
[2];
1023 /* indicate whether the LVDS_BORDER should be enabled or not */
1024 unsigned int lvds_border_bits
;
1025 /* Panel fitter placement and size for Ironlake+ */
1026 u32 pch_pf_pos
, pch_pf_size
;
1028 struct drm_crtc
*plane_to_crtc_mapping
[3];
1029 struct drm_crtc
*pipe_to_crtc_mapping
[3];
1030 wait_queue_head_t pending_flip_queue
;
1032 struct intel_pch_pll pch_plls
[I915_NUM_PLLS
];
1033 struct intel_ddi_plls ddi_plls
;
1035 /* Reclocking support */
1036 bool render_reclock_avail
;
1037 bool lvds_downclock_avail
;
1038 /* indicates the reduced downclock for LVDS*/
1042 struct child_device_config
*child_dev
;
1044 bool mchbar_need_disable
;
1046 struct intel_l3_parity l3_parity
;
1048 /* gen6+ rps state */
1049 struct intel_gen6_power_mgmt rps
;
1051 /* ilk-only ips/rps state. Everything in here is protected by the global
1052 * mchdev_lock in intel_pm.c */
1053 struct intel_ilk_power_mgmt ips
;
1055 enum no_fbc_reason no_fbc_reason
;
1057 struct drm_mm_node
*compressed_fb
;
1058 struct drm_mm_node
*compressed_llb
;
1060 struct i915_gpu_error gpu_error
;
1062 /* list of fbdev register on this device */
1063 struct intel_fbdev
*fbdev
;
1066 * The console may be contended at resume, but we don't
1067 * want it to block on it.
1069 struct work_struct console_resume_work
;
1071 struct drm_property
*broadcast_rgb_property
;
1072 struct drm_property
*force_audio_property
;
1074 bool hw_contexts_disabled
;
1075 uint32_t hw_context_size
;
1079 struct i915_suspend_saved_registers regfile
;
1081 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1083 struct i915_dri1_state dri1
;
1084 } drm_i915_private_t
;
1086 /* Iterate over initialised rings */
1087 #define for_each_ring(ring__, dev_priv__, i__) \
1088 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1089 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1091 enum hdmi_force_audio
{
1092 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1093 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1094 HDMI_AUDIO_AUTO
, /* trust EDID */
1095 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1098 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
1100 struct drm_i915_gem_object_ops
{
1101 /* Interface between the GEM object and its backing storage.
1102 * get_pages() is called once prior to the use of the associated set
1103 * of pages before to binding them into the GTT, and put_pages() is
1104 * called after we no longer need them. As we expect there to be
1105 * associated cost with migrating pages between the backing storage
1106 * and making them available for the GPU (e.g. clflush), we may hold
1107 * onto the pages after they are no longer referenced by the GPU
1108 * in case they may be used again shortly (for example migrating the
1109 * pages to a different memory domain within the GTT). put_pages()
1110 * will therefore most likely be called when the object itself is
1111 * being released or under memory pressure (where we attempt to
1112 * reap pages for the shrinker).
1114 int (*get_pages
)(struct drm_i915_gem_object
*);
1115 void (*put_pages
)(struct drm_i915_gem_object
*);
1118 struct drm_i915_gem_object
{
1119 struct drm_gem_object base
;
1121 const struct drm_i915_gem_object_ops
*ops
;
1123 /** Current space allocated to this object in the GTT, if any. */
1124 struct drm_mm_node
*gtt_space
;
1125 /** Stolen memory for this object, instead of being backed by shmem. */
1126 struct drm_mm_node
*stolen
;
1127 struct list_head gtt_list
;
1129 /** This object's place on the active/inactive lists */
1130 struct list_head ring_list
;
1131 struct list_head mm_list
;
1132 /** This object's place in the batchbuffer or on the eviction list */
1133 struct list_head exec_list
;
1136 * This is set if the object is on the active lists (has pending
1137 * rendering and so a non-zero seqno), and is not set if it i s on
1138 * inactive (ready to be unbound) list.
1140 unsigned int active
:1;
1143 * This is set if the object has been written to since last bound
1146 unsigned int dirty
:1;
1149 * Fence register bits (if any) for this object. Will be set
1150 * as needed when mapped into the GTT.
1151 * Protected by dev->struct_mutex.
1153 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1156 * Advice: are the backing pages purgeable?
1158 unsigned int madv
:2;
1161 * Current tiling mode for the object.
1163 unsigned int tiling_mode
:2;
1165 * Whether the tiling parameters for the currently associated fence
1166 * register have changed. Note that for the purposes of tracking
1167 * tiling changes we also treat the unfenced register, the register
1168 * slot that the object occupies whilst it executes a fenced
1169 * command (such as BLT on gen2/3), as a "fence".
1171 unsigned int fence_dirty
:1;
1173 /** How many users have pinned this object in GTT space. The following
1174 * users can each hold at most one reference: pwrite/pread, pin_ioctl
1175 * (via user_pin_count), execbuffer (objects are not allowed multiple
1176 * times for the same batchbuffer), and the framebuffer code. When
1177 * switching/pageflipping, the framebuffer code has at most two buffers
1180 * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
1181 * bits with absolutely no headroom. So use 4 bits. */
1182 unsigned int pin_count
:4;
1183 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
1186 * Is the object at the current location in the gtt mappable and
1187 * fenceable? Used to avoid costly recalculations.
1189 unsigned int map_and_fenceable
:1;
1192 * Whether the current gtt mapping needs to be mappable (and isn't just
1193 * mappable by accident). Track pin and fault separate for a more
1194 * accurate mappable working set.
1196 unsigned int fault_mappable
:1;
1197 unsigned int pin_mappable
:1;
1200 * Is the GPU currently using a fence to access this buffer,
1202 unsigned int pending_fenced_gpu_access
:1;
1203 unsigned int fenced_gpu_access
:1;
1205 unsigned int cache_level
:2;
1207 unsigned int has_aliasing_ppgtt_mapping
:1;
1208 unsigned int has_global_gtt_mapping
:1;
1209 unsigned int has_dma_mapping
:1;
1211 struct sg_table
*pages
;
1212 int pages_pin_count
;
1214 /* prime dma-buf support */
1215 void *dma_buf_vmapping
;
1219 * Used for performing relocations during execbuffer insertion.
1221 struct hlist_node exec_node
;
1222 unsigned long exec_handle
;
1223 struct drm_i915_gem_exec_object2
*exec_entry
;
1226 * Current offset of the object in GTT space.
1228 * This is the same as gtt_space->start
1230 uint32_t gtt_offset
;
1232 struct intel_ring_buffer
*ring
;
1234 /** Breadcrumb of last rendering to the buffer. */
1235 uint32_t last_read_seqno
;
1236 uint32_t last_write_seqno
;
1237 /** Breadcrumb of last fenced GPU access to the buffer. */
1238 uint32_t last_fenced_seqno
;
1240 /** Current tiling stride for the object, if it's tiled. */
1243 /** Record of address bit 17 of each page at last unbind. */
1244 unsigned long *bit_17
;
1246 /** User space pin count and filp owning the pin */
1247 uint32_t user_pin_count
;
1248 struct drm_file
*pin_filp
;
1250 /** for phy allocated objects */
1251 struct drm_i915_gem_phys_object
*phys_obj
;
1253 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
1255 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1258 * Request queue structure.
1260 * The request queue allows us to note sequence numbers that have been emitted
1261 * and may be associated with active buffers to be retired.
1263 * By keeping this list, we can avoid having to do questionable
1264 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1265 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1267 struct drm_i915_gem_request
{
1268 /** On Which ring this request was generated */
1269 struct intel_ring_buffer
*ring
;
1271 /** GEM sequence number associated with this request. */
1274 /** Postion in the ringbuffer of the end of the request */
1277 /** Time at which this request was emitted, in jiffies. */
1278 unsigned long emitted_jiffies
;
1280 /** global list entry for this request */
1281 struct list_head list
;
1283 struct drm_i915_file_private
*file_priv
;
1284 /** file_priv list entry for this request */
1285 struct list_head client_list
;
1288 struct drm_i915_file_private
{
1291 struct list_head request_list
;
1293 struct idr context_idr
;
1296 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
1298 #define IS_I830(dev) ((dev)->pci_device == 0x3577)
1299 #define IS_845G(dev) ((dev)->pci_device == 0x2562)
1300 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1301 #define IS_I865G(dev) ((dev)->pci_device == 0x2572)
1302 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1303 #define IS_I915GM(dev) ((dev)->pci_device == 0x2592)
1304 #define IS_I945G(dev) ((dev)->pci_device == 0x2772)
1305 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1306 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1307 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1308 #define IS_GM45(dev) ((dev)->pci_device == 0x2A42)
1309 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1310 #define IS_PINEVIEW_G(dev) ((dev)->pci_device == 0xa001)
1311 #define IS_PINEVIEW_M(dev) ((dev)->pci_device == 0xa011)
1312 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1313 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1314 #define IS_IRONLAKE_D(dev) ((dev)->pci_device == 0x0042)
1315 #define IS_IRONLAKE_M(dev) ((dev)->pci_device == 0x0046)
1316 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1317 #define IS_IVB_GT1(dev) ((dev)->pci_device == 0x0156 || \
1318 (dev)->pci_device == 0x0152 || \
1319 (dev)->pci_device == 0x015a)
1320 #define IS_SNB_GT1(dev) ((dev)->pci_device == 0x0102 || \
1321 (dev)->pci_device == 0x0106 || \
1322 (dev)->pci_device == 0x010A)
1323 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1324 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1325 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1326 #define IS_ULT(dev) (IS_HASWELL(dev) && \
1327 ((dev)->pci_device & 0xFF00) == 0x0A00)
1330 * The genX designation typically refers to the render engine, so render
1331 * capability related checks should use IS_GEN, while display and other checks
1332 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1335 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1336 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1337 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1338 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1339 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1340 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1342 #define HAS_BSD(dev) (INTEL_INFO(dev)->has_bsd_ring)
1343 #define HAS_BLT(dev) (INTEL_INFO(dev)->has_blt_ring)
1344 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1345 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1347 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1348 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >=6 && !IS_VALLEYVIEW(dev))
1350 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1351 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1353 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1354 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1356 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1357 * rows, which changed the alignment requirements and fence programming.
1359 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1361 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1362 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1363 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1364 #define SUPPORTS_EDP(dev) (IS_IRONLAKE_M(dev))
1365 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1366 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1367 /* dsparb controlled by hw only */
1368 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
1370 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1371 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1372 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1374 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
1376 #define HAS_DDI(dev) (IS_HASWELL(dev))
1377 #define HAS_POWER_WELL(dev) (IS_HASWELL(dev))
1379 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1380 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1381 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1382 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1383 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1384 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1386 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
1387 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1388 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1389 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1390 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1391 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1393 #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake)
1395 #define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1397 #define GT_FREQUENCY_MULTIPLIER 50
1399 #include "i915_trace.h"
1402 * RC6 is a special power stage which allows the GPU to enter an very
1403 * low-voltage mode when idle, using down to 0V while at this stage. This
1404 * stage is entered automatically when the GPU is idle when RC6 support is
1405 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
1407 * There are different RC6 modes available in Intel GPU, which differentiate
1408 * among each other with the latency required to enter and leave RC6 and
1409 * voltage consumed by the GPU in different states.
1411 * The combination of the following flags define which states GPU is allowed
1412 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
1413 * RC6pp is deepest RC6. Their support by hardware varies according to the
1414 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
1415 * which brings the most power savings; deeper states save more power, but
1416 * require higher latency to switch to and wake up.
1418 #define INTEL_RC6_ENABLE (1<<0)
1419 #define INTEL_RC6p_ENABLE (1<<1)
1420 #define INTEL_RC6pp_ENABLE (1<<2)
1422 extern struct drm_ioctl_desc i915_ioctls
[];
1423 extern int i915_max_ioctl
;
1424 extern unsigned int i915_fbpercrtc __always_unused
;
1425 extern int i915_panel_ignore_lid __read_mostly
;
1426 extern unsigned int i915_powersave __read_mostly
;
1427 extern int i915_semaphores __read_mostly
;
1428 extern unsigned int i915_lvds_downclock __read_mostly
;
1429 extern int i915_lvds_channel_mode __read_mostly
;
1430 extern int i915_panel_use_ssc __read_mostly
;
1431 extern int i915_vbt_sdvo_panel_type __read_mostly
;
1432 extern int i915_enable_rc6 __read_mostly
;
1433 extern int i915_enable_fbc __read_mostly
;
1434 extern bool i915_enable_hangcheck __read_mostly
;
1435 extern int i915_enable_ppgtt __read_mostly
;
1436 extern unsigned int i915_preliminary_hw_support __read_mostly
;
1437 extern int i915_disable_power_well __read_mostly
;
1439 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
1440 extern int i915_resume(struct drm_device
*dev
);
1441 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
1442 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
1445 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
1446 extern void i915_kernel_lost_context(struct drm_device
* dev
);
1447 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
1448 extern int i915_driver_unload(struct drm_device
*);
1449 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file_priv
);
1450 extern void i915_driver_lastclose(struct drm_device
* dev
);
1451 extern void i915_driver_preclose(struct drm_device
*dev
,
1452 struct drm_file
*file_priv
);
1453 extern void i915_driver_postclose(struct drm_device
*dev
,
1454 struct drm_file
*file_priv
);
1455 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
1456 #ifdef CONFIG_COMPAT
1457 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
1460 extern int i915_emit_box(struct drm_device
*dev
,
1461 struct drm_clip_rect
*box
,
1463 extern int intel_gpu_reset(struct drm_device
*dev
);
1464 extern int i915_reset(struct drm_device
*dev
);
1465 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
1466 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
1467 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
1468 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
1470 extern void intel_console_resume(struct work_struct
*work
);
1473 void i915_hangcheck_elapsed(unsigned long data
);
1474 void i915_handle_error(struct drm_device
*dev
, bool wedged
);
1476 extern void intel_irq_init(struct drm_device
*dev
);
1477 extern void intel_hpd_init(struct drm_device
*dev
);
1478 extern void intel_gt_init(struct drm_device
*dev
);
1479 extern void intel_gt_reset(struct drm_device
*dev
);
1481 void i915_error_state_free(struct kref
*error_ref
);
1484 i915_enable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1487 i915_disable_pipestat(drm_i915_private_t
*dev_priv
, int pipe
, u32 mask
);
1489 void intel_enable_asle(struct drm_device
*dev
);
1491 #ifdef CONFIG_DEBUG_FS
1492 extern void i915_destroy_error_state(struct drm_device
*dev
);
1494 #define i915_destroy_error_state(x)
1499 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
1500 struct drm_file
*file_priv
);
1501 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
1502 struct drm_file
*file_priv
);
1503 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
1504 struct drm_file
*file_priv
);
1505 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
1506 struct drm_file
*file_priv
);
1507 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
1508 struct drm_file
*file_priv
);
1509 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
1510 struct drm_file
*file_priv
);
1511 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
1512 struct drm_file
*file_priv
);
1513 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
1514 struct drm_file
*file_priv
);
1515 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
1516 struct drm_file
*file_priv
);
1517 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
1518 struct drm_file
*file_priv
);
1519 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
1520 struct drm_file
*file_priv
);
1521 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
1522 struct drm_file
*file_priv
);
1523 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
1524 struct drm_file
*file_priv
);
1525 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
1526 struct drm_file
*file
);
1527 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
1528 struct drm_file
*file
);
1529 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
1530 struct drm_file
*file_priv
);
1531 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
1532 struct drm_file
*file_priv
);
1533 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
1534 struct drm_file
*file_priv
);
1535 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
1536 struct drm_file
*file_priv
);
1537 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
1538 struct drm_file
*file_priv
);
1539 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
1540 struct drm_file
*file_priv
);
1541 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
1542 struct drm_file
*file_priv
);
1543 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
1544 struct drm_file
*file_priv
);
1545 void i915_gem_load(struct drm_device
*dev
);
1546 void *i915_gem_object_alloc(struct drm_device
*dev
);
1547 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
1548 int i915_gem_init_object(struct drm_gem_object
*obj
);
1549 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
1550 const struct drm_i915_gem_object_ops
*ops
);
1551 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
1553 void i915_gem_free_object(struct drm_gem_object
*obj
);
1555 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
1557 bool map_and_fenceable
,
1559 void i915_gem_object_unpin(struct drm_i915_gem_object
*obj
);
1560 int __must_check
i915_gem_object_unbind(struct drm_i915_gem_object
*obj
);
1561 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
1562 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
1563 void i915_gem_lastclose(struct drm_device
*dev
);
1565 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
1566 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
1568 struct sg_page_iter sg_iter
;
1570 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
1571 return sg_page_iter_page(&sg_iter
);
1575 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
1577 BUG_ON(obj
->pages
== NULL
);
1578 obj
->pages_pin_count
++;
1580 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
1582 BUG_ON(obj
->pages_pin_count
== 0);
1583 obj
->pages_pin_count
--;
1586 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
1587 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
1588 struct intel_ring_buffer
*to
);
1589 void i915_gem_object_move_to_active(struct drm_i915_gem_object
*obj
,
1590 struct intel_ring_buffer
*ring
);
1592 int i915_gem_dumb_create(struct drm_file
*file_priv
,
1593 struct drm_device
*dev
,
1594 struct drm_mode_create_dumb
*args
);
1595 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
1596 uint32_t handle
, uint64_t *offset
);
1597 int i915_gem_dumb_destroy(struct drm_file
*file_priv
, struct drm_device
*dev
,
1600 * Returns true if seq1 is later than seq2.
1603 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
1605 return (int32_t)(seq1
- seq2
) >= 0;
1608 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
1609 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
1610 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
1611 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
1614 i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
)
1616 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1617 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1618 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
++;
1625 i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
)
1627 if (obj
->fence_reg
!= I915_FENCE_REG_NONE
) {
1628 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
1629 dev_priv
->fence_regs
[obj
->fence_reg
].pin_count
--;
1633 void i915_gem_retire_requests(struct drm_device
*dev
);
1634 void i915_gem_retire_requests_ring(struct intel_ring_buffer
*ring
);
1635 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
1636 bool interruptible
);
1637 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
1639 return unlikely(atomic_read(&error
->reset_counter
)
1640 & I915_RESET_IN_PROGRESS_FLAG
);
1643 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
1645 return atomic_read(&error
->reset_counter
) == I915_WEDGED
;
1648 void i915_gem_reset(struct drm_device
*dev
);
1649 void i915_gem_clflush_object(struct drm_i915_gem_object
*obj
);
1650 int __must_check
i915_gem_object_set_domain(struct drm_i915_gem_object
*obj
,
1651 uint32_t read_domains
,
1652 uint32_t write_domain
);
1653 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
1654 int __must_check
i915_gem_init(struct drm_device
*dev
);
1655 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
1656 void i915_gem_l3_remap(struct drm_device
*dev
);
1657 void i915_gem_init_swizzling(struct drm_device
*dev
);
1658 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
1659 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
1660 int __must_check
i915_gem_idle(struct drm_device
*dev
);
1661 int i915_add_request(struct intel_ring_buffer
*ring
,
1662 struct drm_file
*file
,
1664 int __must_check
i915_wait_seqno(struct intel_ring_buffer
*ring
,
1666 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
1668 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
1671 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
1673 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
1675 struct intel_ring_buffer
*pipelined
);
1676 int i915_gem_attach_phys_object(struct drm_device
*dev
,
1677 struct drm_i915_gem_object
*obj
,
1680 void i915_gem_detach_phys_object(struct drm_device
*dev
,
1681 struct drm_i915_gem_object
*obj
);
1682 void i915_gem_free_all_phys_object(struct drm_device
*dev
);
1683 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
1686 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
1688 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
1689 int tiling_mode
, bool fenced
);
1691 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
1692 enum i915_cache_level cache_level
);
1694 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
1695 struct dma_buf
*dma_buf
);
1697 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
1698 struct drm_gem_object
*gem_obj
, int flags
);
1700 /* i915_gem_context.c */
1701 void i915_gem_context_init(struct drm_device
*dev
);
1702 void i915_gem_context_fini(struct drm_device
*dev
);
1703 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
1704 int i915_switch_context(struct intel_ring_buffer
*ring
,
1705 struct drm_file
*file
, int to_id
);
1706 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
1707 struct drm_file
*file
);
1708 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
1709 struct drm_file
*file
);
1711 /* i915_gem_gtt.c */
1712 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device
*dev
);
1713 void i915_ppgtt_bind_object(struct i915_hw_ppgtt
*ppgtt
,
1714 struct drm_i915_gem_object
*obj
,
1715 enum i915_cache_level cache_level
);
1716 void i915_ppgtt_unbind_object(struct i915_hw_ppgtt
*ppgtt
,
1717 struct drm_i915_gem_object
*obj
);
1719 void i915_gem_restore_gtt_mappings(struct drm_device
*dev
);
1720 int __must_check
i915_gem_gtt_prepare_object(struct drm_i915_gem_object
*obj
);
1721 void i915_gem_gtt_bind_object(struct drm_i915_gem_object
*obj
,
1722 enum i915_cache_level cache_level
);
1723 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object
*obj
);
1724 void i915_gem_gtt_finish_object(struct drm_i915_gem_object
*obj
);
1725 void i915_gem_init_global_gtt(struct drm_device
*dev
);
1726 void i915_gem_setup_global_gtt(struct drm_device
*dev
, unsigned long start
,
1727 unsigned long mappable_end
, unsigned long end
);
1728 int i915_gem_gtt_init(struct drm_device
*dev
);
1729 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
1731 if (INTEL_INFO(dev
)->gen
< 6)
1732 intel_gtt_chipset_flush();
1736 /* i915_gem_evict.c */
1737 int __must_check
i915_gem_evict_something(struct drm_device
*dev
, int min_size
,
1739 unsigned cache_level
,
1742 int i915_gem_evict_everything(struct drm_device
*dev
);
1744 /* i915_gem_stolen.c */
1745 int i915_gem_init_stolen(struct drm_device
*dev
);
1746 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
);
1747 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
1748 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
1749 struct drm_i915_gem_object
*
1750 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
1751 struct drm_i915_gem_object
*
1752 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
1756 void i915_gem_object_release_stolen(struct drm_i915_gem_object
*obj
);
1758 /* i915_gem_tiling.c */
1759 inline static bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
1761 drm_i915_private_t
*dev_priv
= obj
->base
.dev
->dev_private
;
1763 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
1764 obj
->tiling_mode
!= I915_TILING_NONE
;
1767 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
1768 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1769 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
1771 /* i915_gem_debug.c */
1772 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1773 const char *where
, uint32_t mark
);
1775 int i915_verify_lists(struct drm_device
*dev
);
1777 #define i915_verify_lists(dev) 0
1779 void i915_gem_object_check_coherency(struct drm_i915_gem_object
*obj
,
1781 void i915_gem_dump_object(struct drm_i915_gem_object
*obj
, int len
,
1782 const char *where
, uint32_t mark
);
1784 /* i915_debugfs.c */
1785 int i915_debugfs_init(struct drm_minor
*minor
);
1786 void i915_debugfs_cleanup(struct drm_minor
*minor
);
1788 /* i915_suspend.c */
1789 extern int i915_save_state(struct drm_device
*dev
);
1790 extern int i915_restore_state(struct drm_device
*dev
);
1793 void i915_save_display_reg(struct drm_device
*dev
);
1794 void i915_restore_display_reg(struct drm_device
*dev
);
1797 void i915_setup_sysfs(struct drm_device
*dev_priv
);
1798 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
1801 extern int intel_setup_gmbus(struct drm_device
*dev
);
1802 extern void intel_teardown_gmbus(struct drm_device
*dev
);
1803 extern inline bool intel_gmbus_is_port_valid(unsigned port
)
1805 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
1808 extern struct i2c_adapter
*intel_gmbus_get_adapter(
1809 struct drm_i915_private
*dev_priv
, unsigned port
);
1810 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
1811 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
1812 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
1814 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
1816 extern void intel_i2c_reset(struct drm_device
*dev
);
1818 /* intel_opregion.c */
1819 extern int intel_opregion_setup(struct drm_device
*dev
);
1821 extern void intel_opregion_init(struct drm_device
*dev
);
1822 extern void intel_opregion_fini(struct drm_device
*dev
);
1823 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
1824 extern void intel_opregion_gse_intr(struct drm_device
*dev
);
1825 extern void intel_opregion_enable_asle(struct drm_device
*dev
);
1827 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
1828 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
1829 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
1830 static inline void intel_opregion_gse_intr(struct drm_device
*dev
) { return; }
1831 static inline void intel_opregion_enable_asle(struct drm_device
*dev
) { return; }
1836 extern void intel_register_dsm_handler(void);
1837 extern void intel_unregister_dsm_handler(void);
1839 static inline void intel_register_dsm_handler(void) { return; }
1840 static inline void intel_unregister_dsm_handler(void) { return; }
1841 #endif /* CONFIG_ACPI */
1844 extern void intel_modeset_init_hw(struct drm_device
*dev
);
1845 extern void intel_modeset_init(struct drm_device
*dev
);
1846 extern void intel_modeset_gem_init(struct drm_device
*dev
);
1847 extern void intel_modeset_cleanup(struct drm_device
*dev
);
1848 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
1849 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
1850 bool force_restore
);
1851 extern void i915_redisable_vga(struct drm_device
*dev
);
1852 extern bool intel_fbc_enabled(struct drm_device
*dev
);
1853 extern void intel_disable_fbc(struct drm_device
*dev
);
1854 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
1855 extern void intel_init_pch_refclk(struct drm_device
*dev
);
1856 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
1857 extern void intel_detect_pch(struct drm_device
*dev
);
1858 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
1859 extern int intel_enable_rc6(const struct drm_device
*dev
);
1861 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
1862 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
1863 struct drm_file
*file
);
1866 #ifdef CONFIG_DEBUG_FS
1867 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
1868 extern void intel_overlay_print_error_state(struct seq_file
*m
, struct intel_overlay_error_state
*error
);
1870 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
1871 extern void intel_display_print_error_state(struct seq_file
*m
,
1872 struct drm_device
*dev
,
1873 struct intel_display_error_state
*error
);
1876 /* On SNB platform, before reading ring registers forcewake bit
1877 * must be set to prevent GT core from power down and stale values being
1880 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
);
1881 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
);
1882 int __gen6_gt_wait_for_fifo(struct drm_i915_private
*dev_priv
);
1884 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
1885 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
1886 int valleyview_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
, u32
*val
);
1887 int valleyview_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
1889 #define __i915_read(x, y) \
1890 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg);
1898 #define __i915_write(x, y) \
1899 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val);
1907 #define I915_READ8(reg) i915_read8(dev_priv, (reg))
1908 #define I915_WRITE8(reg, val) i915_write8(dev_priv, (reg), (val))
1910 #define I915_READ16(reg) i915_read16(dev_priv, (reg))
1911 #define I915_WRITE16(reg, val) i915_write16(dev_priv, (reg), (val))
1912 #define I915_READ16_NOTRACE(reg) readw(dev_priv->regs + (reg))
1913 #define I915_WRITE16_NOTRACE(reg, val) writew(val, dev_priv->regs + (reg))
1915 #define I915_READ(reg) i915_read32(dev_priv, (reg))
1916 #define I915_WRITE(reg, val) i915_write32(dev_priv, (reg), (val))
1917 #define I915_READ_NOTRACE(reg) readl(dev_priv->regs + (reg))
1918 #define I915_WRITE_NOTRACE(reg, val) writel(val, dev_priv->regs + (reg))
1920 #define I915_WRITE64(reg, val) i915_write64(dev_priv, (reg), (val))
1921 #define I915_READ64(reg) i915_read64(dev_priv, (reg))
1923 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
1924 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
1926 /* "Broadcast RGB" property */
1927 #define INTEL_BROADCAST_RGB_AUTO 0
1928 #define INTEL_BROADCAST_RGB_FULL 1
1929 #define INTEL_BROADCAST_RGB_LIMITED 2
1931 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
1933 if (HAS_PCH_SPLIT(dev
))
1934 return CPU_VGACNTRL
;
1935 else if (IS_VALLEYVIEW(dev
))
1936 return VLV_VGACNTRL
;
1941 static inline void __user
*to_user_ptr(u64 address
)
1943 return (void __user
*)(uintptr_t)address
;