1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141024"
66 I915_MAX_PIPES
= _PIPE_EDP
68 #define pipe_name(p) ((p) + 'A')
77 #define transcoder_name(t) ((t) + 'A')
80 * This is the maximum (across all platforms) number of planes (primary +
81 * sprites) that can be active at the same time on one pipe.
83 * This value doesn't count the cursor plane.
85 #define I915_MAX_PLANES 3
92 #define plane_name(p) ((p) + 'A')
94 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
104 #define port_name(p) ((p) + 'A')
106 #define I915_NUM_PHYS_VLV 2
118 enum intel_display_power_domain
{
122 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
123 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
124 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
125 POWER_DOMAIN_TRANSCODER_A
,
126 POWER_DOMAIN_TRANSCODER_B
,
127 POWER_DOMAIN_TRANSCODER_C
,
128 POWER_DOMAIN_TRANSCODER_EDP
,
129 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
130 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
131 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
132 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
133 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
134 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
135 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
136 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
137 POWER_DOMAIN_PORT_DSI
,
138 POWER_DOMAIN_PORT_CRT
,
139 POWER_DOMAIN_PORT_OTHER
,
148 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
149 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
150 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
151 #define POWER_DOMAIN_TRANSCODER(tran) \
152 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
153 (tran) + POWER_DOMAIN_TRANSCODER_A)
157 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
158 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
168 #define I915_GEM_GPU_DOMAINS \
169 (I915_GEM_DOMAIN_RENDER | \
170 I915_GEM_DOMAIN_SAMPLER | \
171 I915_GEM_DOMAIN_COMMAND | \
172 I915_GEM_DOMAIN_INSTRUCTION | \
173 I915_GEM_DOMAIN_VERTEX)
175 #define for_each_pipe(__dev_priv, __p) \
176 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
177 #define for_each_plane(pipe, p) \
178 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
179 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
181 #define for_each_crtc(dev, crtc) \
182 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
184 #define for_each_intel_crtc(dev, intel_crtc) \
185 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
187 #define for_each_intel_encoder(dev, intel_encoder) \
188 list_for_each_entry(intel_encoder, \
189 &(dev)->mode_config.encoder_list, \
192 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
193 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
194 if ((intel_encoder)->base.crtc == (__crtc))
196 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
197 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
198 if ((intel_connector)->base.encoder == (__encoder))
200 #define for_each_power_domain(domain, mask) \
201 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
202 if ((1 << (domain)) & (mask))
204 struct drm_i915_private
;
205 struct i915_mm_struct
;
206 struct i915_mmu_object
;
209 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
210 /* real shared dpll ids must be >= 0 */
211 DPLL_ID_PCH_PLL_A
= 0,
212 DPLL_ID_PCH_PLL_B
= 1,
216 #define I915_NUM_PLLS 2
218 struct intel_dpll_hw_state
{
229 struct intel_shared_dpll
{
230 int refcount
; /* count of number of CRTCs sharing this PLL */
231 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
232 bool on
; /* is the PLL actually active? Disabled during modeset */
234 /* should match the index in the dev_priv->shared_dplls array */
235 enum intel_dpll_id id
;
236 struct intel_dpll_hw_state hw_state
;
237 /* The mode_set hook is optional and should be used together with the
238 * intel_prepare_shared_dpll function. */
239 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
240 struct intel_shared_dpll
*pll
);
241 void (*enable
)(struct drm_i915_private
*dev_priv
,
242 struct intel_shared_dpll
*pll
);
243 void (*disable
)(struct drm_i915_private
*dev_priv
,
244 struct intel_shared_dpll
*pll
);
245 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
246 struct intel_shared_dpll
*pll
,
247 struct intel_dpll_hw_state
*hw_state
);
250 /* Used by dp and fdi links */
251 struct intel_link_m_n
{
259 void intel_link_compute_m_n(int bpp
, int nlanes
,
260 int pixel_clock
, int link_clock
,
261 struct intel_link_m_n
*m_n
);
263 /* Interface history:
266 * 1.2: Add Power Management
267 * 1.3: Add vblank support
268 * 1.4: Fix cmdbuffer path, add heap destroy
269 * 1.5: Add vblank pipe configuration
270 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
271 * - Support vertical blank on secondary display pipe
273 #define DRIVER_MAJOR 1
274 #define DRIVER_MINOR 6
275 #define DRIVER_PATCHLEVEL 0
277 #define WATCH_LISTS 0
280 struct opregion_header
;
281 struct opregion_acpi
;
282 struct opregion_swsci
;
283 struct opregion_asle
;
285 struct intel_opregion
{
286 struct opregion_header __iomem
*header
;
287 struct opregion_acpi __iomem
*acpi
;
288 struct opregion_swsci __iomem
*swsci
;
289 u32 swsci_gbda_sub_functions
;
290 u32 swsci_sbcb_sub_functions
;
291 struct opregion_asle __iomem
*asle
;
293 u32 __iomem
*lid_state
;
294 struct work_struct asle_work
;
296 #define OPREGION_SIZE (8*1024)
298 struct intel_overlay
;
299 struct intel_overlay_error_state
;
301 struct drm_local_map
;
303 struct drm_i915_master_private
{
304 struct drm_local_map
*sarea
;
305 struct _drm_i915_sarea
*sarea_priv
;
307 #define I915_FENCE_REG_NONE -1
308 #define I915_MAX_NUM_FENCES 32
309 /* 32 fences + sign bit for FENCE_REG_NONE */
310 #define I915_MAX_NUM_FENCE_BITS 6
312 struct drm_i915_fence_reg
{
313 struct list_head lru_list
;
314 struct drm_i915_gem_object
*obj
;
318 struct sdvo_device_mapping
{
327 struct intel_display_error_state
;
329 struct drm_i915_error_state
{
337 /* Generic register state */
345 u32 error
; /* gen6+ */
346 u32 err_int
; /* gen7 */
352 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
353 u64 fence
[I915_MAX_NUM_FENCES
];
354 struct intel_overlay_error_state
*overlay
;
355 struct intel_display_error_state
*display
;
356 struct drm_i915_error_object
*semaphore_obj
;
358 struct drm_i915_error_ring
{
360 /* Software tracked state */
363 enum intel_ring_hangcheck_action hangcheck_action
;
366 /* our own tracking of ring head and tail */
370 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
388 u32 rc_psmi
; /* sleep state */
389 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
391 struct drm_i915_error_object
{
395 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
397 struct drm_i915_error_request
{
412 char comm
[TASK_COMM_LEN
];
413 } ring
[I915_NUM_RINGS
];
415 struct drm_i915_error_buffer
{
422 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
430 } **active_bo
, **pinned_bo
;
432 u32
*active_bo_count
, *pinned_bo_count
;
436 struct intel_connector
;
437 struct intel_crtc_config
;
438 struct intel_plane_config
;
443 struct drm_i915_display_funcs
{
444 bool (*fbc_enabled
)(struct drm_device
*dev
);
445 void (*enable_fbc
)(struct drm_crtc
*crtc
);
446 void (*disable_fbc
)(struct drm_device
*dev
);
447 int (*get_display_clock_speed
)(struct drm_device
*dev
);
448 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
450 * find_dpll() - Find the best values for the PLL
451 * @limit: limits for the PLL
452 * @crtc: current CRTC
453 * @target: target frequency in kHz
454 * @refclk: reference clock frequency in kHz
455 * @match_clock: if provided, @best_clock P divider must
456 * match the P divider from @match_clock
457 * used for LVDS downclocking
458 * @best_clock: best PLL values found
460 * Returns true on success, false on failure.
462 bool (*find_dpll
)(const struct intel_limit
*limit
,
463 struct intel_crtc
*crtc
,
464 int target
, int refclk
,
465 struct dpll
*match_clock
,
466 struct dpll
*best_clock
);
467 void (*update_wm
)(struct drm_crtc
*crtc
);
468 void (*update_sprite_wm
)(struct drm_plane
*plane
,
469 struct drm_crtc
*crtc
,
470 uint32_t sprite_width
, uint32_t sprite_height
,
471 int pixel_size
, bool enable
, bool scaled
);
472 void (*modeset_global_resources
)(struct drm_device
*dev
);
473 /* Returns the active state of the crtc, and if the crtc is active,
474 * fills out the pipe-config with the hw state. */
475 bool (*get_pipe_config
)(struct intel_crtc
*,
476 struct intel_crtc_config
*);
477 void (*get_plane_config
)(struct intel_crtc
*,
478 struct intel_plane_config
*);
479 int (*crtc_mode_set
)(struct intel_crtc
*crtc
,
481 struct drm_framebuffer
*old_fb
);
482 void (*crtc_enable
)(struct drm_crtc
*crtc
);
483 void (*crtc_disable
)(struct drm_crtc
*crtc
);
484 void (*off
)(struct drm_crtc
*crtc
);
485 void (*write_eld
)(struct drm_connector
*connector
,
486 struct drm_crtc
*crtc
,
487 struct drm_display_mode
*mode
);
488 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
489 void (*init_clock_gating
)(struct drm_device
*dev
);
490 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
491 struct drm_framebuffer
*fb
,
492 struct drm_i915_gem_object
*obj
,
493 struct intel_engine_cs
*ring
,
495 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
496 struct drm_framebuffer
*fb
,
498 void (*hpd_irq_setup
)(struct drm_device
*dev
);
499 /* clock updates for mode set */
501 /* render clock increase/decrease */
502 /* display clock increase/decrease */
503 /* pll clock increase/decrease */
505 int (*setup_backlight
)(struct intel_connector
*connector
);
506 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
507 void (*set_backlight
)(struct intel_connector
*connector
,
509 void (*disable_backlight
)(struct intel_connector
*connector
);
510 void (*enable_backlight
)(struct intel_connector
*connector
);
513 struct intel_uncore_funcs
{
514 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
516 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
519 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
520 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
521 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
522 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
524 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
525 uint8_t val
, bool trace
);
526 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
527 uint16_t val
, bool trace
);
528 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
529 uint32_t val
, bool trace
);
530 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
531 uint64_t val
, bool trace
);
534 struct intel_uncore
{
535 spinlock_t lock
; /** lock is also taken in irq contexts. */
537 struct intel_uncore_funcs funcs
;
540 unsigned forcewake_count
;
542 unsigned fw_rendercount
;
543 unsigned fw_mediacount
;
545 struct timer_list force_wake_timer
;
548 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
549 func(is_mobile) sep \
552 func(is_i945gm) sep \
554 func(need_gfx_hws) sep \
556 func(is_pineview) sep \
557 func(is_broadwater) sep \
558 func(is_crestline) sep \
559 func(is_ivybridge) sep \
560 func(is_valleyview) sep \
561 func(is_haswell) sep \
562 func(is_skylake) sep \
563 func(is_preliminary) sep \
565 func(has_pipe_cxsr) sep \
566 func(has_hotplug) sep \
567 func(cursor_needs_physical) sep \
568 func(has_overlay) sep \
569 func(overlay_needs_physical) sep \
570 func(supports_tv) sep \
575 #define DEFINE_FLAG(name) u8 name:1
576 #define SEP_SEMICOLON ;
578 struct intel_device_info
{
579 u32 display_mmio_offset
;
582 u8 num_sprites
[I915_MAX_PIPES
];
584 u8 ring_mask
; /* Rings supported by the HW */
585 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
586 /* Register offsets for the various display pipes and transcoders */
587 int pipe_offsets
[I915_MAX_TRANSCODERS
];
588 int trans_offsets
[I915_MAX_TRANSCODERS
];
589 int palette_offsets
[I915_MAX_PIPES
];
590 int cursor_offsets
[I915_MAX_PIPES
];
596 enum i915_cache_level
{
598 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
599 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
600 caches, eg sampler/render caches, and the
601 large Last-Level-Cache. LLC is coherent with
602 the CPU, but L3 is only visible to the GPU. */
603 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
606 struct i915_ctx_hang_stats
{
607 /* This context had batch pending when hang was declared */
608 unsigned batch_pending
;
610 /* This context had batch active when hang was declared */
611 unsigned batch_active
;
613 /* Time when this context was last blamed for a GPU reset */
614 unsigned long guilty_ts
;
616 /* This context is banned to submit more work */
620 /* This must match up with the value previously used for execbuf2.rsvd1. */
621 #define DEFAULT_CONTEXT_HANDLE 0
623 * struct intel_context - as the name implies, represents a context.
624 * @ref: reference count.
625 * @user_handle: userspace tracking identity for this context.
626 * @remap_slice: l3 row remapping information.
627 * @file_priv: filp associated with this context (NULL for global default
629 * @hang_stats: information about the role of this context in possible GPU
631 * @vm: virtual memory space used by this context.
632 * @legacy_hw_ctx: render context backing object and whether it is correctly
633 * initialized (legacy ring submission mechanism only).
634 * @link: link in the global list of contexts.
636 * Contexts are memory images used by the hardware to store copies of their
639 struct intel_context
{
643 struct drm_i915_file_private
*file_priv
;
644 struct i915_ctx_hang_stats hang_stats
;
645 struct i915_hw_ppgtt
*ppgtt
;
647 /* Legacy ring buffer submission */
649 struct drm_i915_gem_object
*rcs_state
;
654 bool rcs_initialized
;
656 struct drm_i915_gem_object
*state
;
657 struct intel_ringbuffer
*ringbuf
;
658 } engine
[I915_NUM_RINGS
];
660 struct list_head link
;
670 struct drm_mm_node compressed_fb
;
671 struct drm_mm_node
*compressed_llb
;
675 /* Tracks whether the HW is actually enabled, not whether the feature is
679 /* On gen8 some rings cannont perform fbc clean operation so for now
680 * we are doing this on SW with mmio.
681 * This variable works in the opposite information direction
682 * of ring->fbc_dirty telling software on frontbuffer tracking
683 * to perform the cache clean on sw side.
685 bool need_sw_cache_clean
;
687 struct intel_fbc_work
{
688 struct delayed_work work
;
689 struct drm_crtc
*crtc
;
690 struct drm_framebuffer
*fb
;
694 FBC_OK
, /* FBC is enabled */
695 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
696 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
697 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
698 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
699 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
700 FBC_BAD_PLANE
, /* fbc not supported on plane */
701 FBC_NOT_TILED
, /* buffer not tiled */
702 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
704 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
709 struct intel_connector
*connector
;
717 struct intel_dp
*enabled
;
719 struct delayed_work work
;
720 unsigned busy_frontbuffer_bits
;
724 PCH_NONE
= 0, /* No PCH present */
725 PCH_IBX
, /* Ibexpeak PCH */
726 PCH_CPT
, /* Cougarpoint PCH */
727 PCH_LPT
, /* Lynxpoint PCH */
728 PCH_SPT
, /* Sunrisepoint PCH */
732 enum intel_sbi_destination
{
737 #define QUIRK_PIPEA_FORCE (1<<0)
738 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
739 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
740 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
741 #define QUIRK_PIPEB_FORCE (1<<4)
744 struct intel_fbc_work
;
747 struct i2c_adapter adapter
;
751 struct i2c_algo_bit_data bit_algo
;
752 struct drm_i915_private
*dev_priv
;
755 struct i915_suspend_saved_registers
{
776 u32 saveTRANS_HTOTAL_A
;
777 u32 saveTRANS_HBLANK_A
;
778 u32 saveTRANS_HSYNC_A
;
779 u32 saveTRANS_VTOTAL_A
;
780 u32 saveTRANS_VBLANK_A
;
781 u32 saveTRANS_VSYNC_A
;
789 u32 savePFIT_PGM_RATIOS
;
790 u32 saveBLC_HIST_CTL
;
792 u32 saveBLC_PWM_CTL2
;
793 u32 saveBLC_HIST_CTL_B
;
794 u32 saveBLC_CPU_PWM_CTL
;
795 u32 saveBLC_CPU_PWM_CTL2
;
808 u32 saveTRANS_HTOTAL_B
;
809 u32 saveTRANS_HBLANK_B
;
810 u32 saveTRANS_HSYNC_B
;
811 u32 saveTRANS_VTOTAL_B
;
812 u32 saveTRANS_VBLANK_B
;
813 u32 saveTRANS_VSYNC_B
;
827 u32 savePP_ON_DELAYS
;
828 u32 savePP_OFF_DELAYS
;
836 u32 savePFIT_CONTROL
;
837 u32 save_palette_a
[256];
838 u32 save_palette_b
[256];
849 u32 saveCACHE_MODE_0
;
850 u32 saveMI_ARB_STATE
;
861 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
872 u32 savePIPEA_GMCH_DATA_M
;
873 u32 savePIPEB_GMCH_DATA_M
;
874 u32 savePIPEA_GMCH_DATA_N
;
875 u32 savePIPEB_GMCH_DATA_N
;
876 u32 savePIPEA_DP_LINK_M
;
877 u32 savePIPEB_DP_LINK_M
;
878 u32 savePIPEA_DP_LINK_N
;
879 u32 savePIPEB_DP_LINK_N
;
890 u32 savePCH_DREF_CONTROL
;
891 u32 saveDISP_ARB_CTL
;
892 u32 savePIPEA_DATA_M1
;
893 u32 savePIPEA_DATA_N1
;
894 u32 savePIPEA_LINK_M1
;
895 u32 savePIPEA_LINK_N1
;
896 u32 savePIPEB_DATA_M1
;
897 u32 savePIPEB_DATA_N1
;
898 u32 savePIPEB_LINK_M1
;
899 u32 savePIPEB_LINK_N1
;
900 u32 saveMCHBAR_RENDER_STANDBY
;
901 u32 savePCH_PORT_HOTPLUG
;
904 struct vlv_s0ix_state
{
911 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
912 u32 media_max_req_count
;
913 u32 gfx_max_req_count
;
945 /* Display 1 CZ domain */
950 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
952 /* GT SA CZ domain */
959 /* Display 2 CZ domain */
965 struct intel_rps_ei
{
971 struct intel_gen6_power_mgmt
{
972 /* work and pm_iir are protected by dev_priv->irq_lock */
973 struct work_struct work
;
976 /* Frequencies are stored in potentially platform dependent multiples.
977 * In other words, *_freq needs to be multiplied by X to be interesting.
978 * Soft limits are those which are used for the dynamic reclocking done
979 * by the driver (raise frequencies under heavy loads, and lower for
980 * lighter loads). Hard limits are those imposed by the hardware.
982 * A distinction is made for overclocking, which is never enabled by
983 * default, and is considered to be above the hard limit if it's
986 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
987 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
988 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
989 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
990 u8 min_freq
; /* AKA RPn. Minimum frequency */
991 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
992 u8 rp1_freq
; /* "less than" RP0 power/freqency */
993 u8 rp0_freq
; /* Non-overclocked max frequency. */
996 u32 ei_interrupt_count
;
999 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1002 struct delayed_work delayed_resume_work
;
1004 /* manual wa residency calculations */
1005 struct intel_rps_ei up_ei
, down_ei
;
1008 * Protects RPS/RC6 register access and PCU communication.
1009 * Must be taken after struct_mutex if nested.
1011 struct mutex hw_lock
;
1014 /* defined intel_pm.c */
1015 extern spinlock_t mchdev_lock
;
1017 struct intel_ilk_power_mgmt
{
1025 unsigned long last_time1
;
1026 unsigned long chipset_power
;
1029 unsigned long gfx_power
;
1035 struct drm_i915_gem_object
*pwrctx
;
1036 struct drm_i915_gem_object
*renderctx
;
1039 struct drm_i915_private
;
1040 struct i915_power_well
;
1042 struct i915_power_well_ops
{
1044 * Synchronize the well's hw state to match the current sw state, for
1045 * example enable/disable it based on the current refcount. Called
1046 * during driver init and resume time, possibly after first calling
1047 * the enable/disable handlers.
1049 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1050 struct i915_power_well
*power_well
);
1052 * Enable the well and resources that depend on it (for example
1053 * interrupts located on the well). Called after the 0->1 refcount
1056 void (*enable
)(struct drm_i915_private
*dev_priv
,
1057 struct i915_power_well
*power_well
);
1059 * Disable the well and resources that depend on it. Called after
1060 * the 1->0 refcount transition.
1062 void (*disable
)(struct drm_i915_private
*dev_priv
,
1063 struct i915_power_well
*power_well
);
1064 /* Returns the hw enabled state. */
1065 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1066 struct i915_power_well
*power_well
);
1069 /* Power well structure for haswell */
1070 struct i915_power_well
{
1073 /* power well enable/disable usage count */
1075 /* cached hw enabled state */
1077 unsigned long domains
;
1079 const struct i915_power_well_ops
*ops
;
1082 struct i915_power_domains
{
1084 * Power wells needed for initialization at driver init and suspend
1085 * time are on. They are kept on until after the first modeset.
1089 int power_well_count
;
1092 int domain_use_count
[POWER_DOMAIN_NUM
];
1093 struct i915_power_well
*power_wells
;
1096 struct i915_dri1_state
{
1097 unsigned allow_batchbuffer
: 1;
1098 u32 __iomem
*gfx_hws_cpu_addr
;
1109 struct i915_ums_state
{
1111 * Flag if the X Server, and thus DRM, is not currently in
1112 * control of the device.
1114 * This is set between LeaveVT and EnterVT. It needs to be
1115 * replaced with a semaphore. It also needs to be
1116 * transitioned away from for kernel modesetting.
1121 #define MAX_L3_SLICES 2
1122 struct intel_l3_parity
{
1123 u32
*remap_info
[MAX_L3_SLICES
];
1124 struct work_struct error_work
;
1128 struct i915_gem_mm
{
1129 /** Memory allocator for GTT stolen memory */
1130 struct drm_mm stolen
;
1131 /** List of all objects in gtt_space. Used to restore gtt
1132 * mappings on resume */
1133 struct list_head bound_list
;
1135 * List of objects which are not bound to the GTT (thus
1136 * are idle and not used by the GPU) but still have
1137 * (presumably uncached) pages still attached.
1139 struct list_head unbound_list
;
1141 /** Usable portion of the GTT for GEM */
1142 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1144 /** PPGTT used for aliasing the PPGTT with the GTT */
1145 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1147 struct notifier_block oom_notifier
;
1148 struct shrinker shrinker
;
1149 bool shrinker_no_lock_stealing
;
1151 /** LRU list of objects with fence regs on them. */
1152 struct list_head fence_list
;
1155 * We leave the user IRQ off as much as possible,
1156 * but this means that requests will finish and never
1157 * be retired once the system goes idle. Set a timer to
1158 * fire periodically while the ring is running. When it
1159 * fires, go retire requests.
1161 struct delayed_work retire_work
;
1164 * When we detect an idle GPU, we want to turn on
1165 * powersaving features. So once we see that there
1166 * are no more requests outstanding and no more
1167 * arrive within a small period of time, we fire
1168 * off the idle_work.
1170 struct delayed_work idle_work
;
1173 * Are we in a non-interruptible section of code like
1179 * Is the GPU currently considered idle, or busy executing userspace
1180 * requests? Whilst idle, we attempt to power down the hardware and
1181 * display clocks. In order to reduce the effect on performance, there
1182 * is a slight delay before we do so.
1186 /* the indicator for dispatch video commands on two BSD rings */
1187 int bsd_ring_dispatch_index
;
1189 /** Bit 6 swizzling required for X tiling */
1190 uint32_t bit_6_swizzle_x
;
1191 /** Bit 6 swizzling required for Y tiling */
1192 uint32_t bit_6_swizzle_y
;
1194 /* accounting, useful for userland debugging */
1195 spinlock_t object_stat_lock
;
1196 size_t object_memory
;
1200 struct drm_i915_error_state_buf
{
1201 struct drm_i915_private
*i915
;
1210 struct i915_error_state_file_priv
{
1211 struct drm_device
*dev
;
1212 struct drm_i915_error_state
*error
;
1215 struct i915_gpu_error
{
1216 /* For hangcheck timer */
1217 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1218 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1219 /* Hang gpu twice in this window and your context gets banned */
1220 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1222 struct timer_list hangcheck_timer
;
1224 /* For reset and error_state handling. */
1226 /* Protected by the above dev->gpu_error.lock. */
1227 struct drm_i915_error_state
*first_error
;
1228 struct work_struct work
;
1231 unsigned long missed_irq_rings
;
1234 * State variable controlling the reset flow and count
1236 * This is a counter which gets incremented when reset is triggered,
1237 * and again when reset has been handled. So odd values (lowest bit set)
1238 * means that reset is in progress and even values that
1239 * (reset_counter >> 1):th reset was successfully completed.
1241 * If reset is not completed succesfully, the I915_WEDGE bit is
1242 * set meaning that hardware is terminally sour and there is no
1243 * recovery. All waiters on the reset_queue will be woken when
1246 * This counter is used by the wait_seqno code to notice that reset
1247 * event happened and it needs to restart the entire ioctl (since most
1248 * likely the seqno it waited for won't ever signal anytime soon).
1250 * This is important for lock-free wait paths, where no contended lock
1251 * naturally enforces the correct ordering between the bail-out of the
1252 * waiter and the gpu reset work code.
1254 atomic_t reset_counter
;
1256 #define I915_RESET_IN_PROGRESS_FLAG 1
1257 #define I915_WEDGED (1 << 31)
1260 * Waitqueue to signal when the reset has completed. Used by clients
1261 * that wait for dev_priv->mm.wedged to settle.
1263 wait_queue_head_t reset_queue
;
1265 /* Userspace knobs for gpu hang simulation;
1266 * combines both a ring mask, and extra flags
1269 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1270 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1272 /* For missed irq/seqno simulation. */
1273 unsigned int test_irq_rings
;
1275 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1276 bool reload_in_reset
;
1279 enum modeset_restore
{
1280 MODESET_ON_LID_OPEN
,
1285 struct ddi_vbt_port_info
{
1287 * This is an index in the HDMI/DVI DDI buffer translation table.
1288 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1289 * populate this field.
1291 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1292 uint8_t hdmi_level_shift
;
1294 uint8_t supports_dvi
:1;
1295 uint8_t supports_hdmi
:1;
1296 uint8_t supports_dp
:1;
1299 enum drrs_support_type
{
1300 DRRS_NOT_SUPPORTED
= 0,
1301 STATIC_DRRS_SUPPORT
= 1,
1302 SEAMLESS_DRRS_SUPPORT
= 2
1305 struct intel_vbt_data
{
1306 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1307 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1310 unsigned int int_tv_support
:1;
1311 unsigned int lvds_dither
:1;
1312 unsigned int lvds_vbt
:1;
1313 unsigned int int_crt_support
:1;
1314 unsigned int lvds_use_ssc
:1;
1315 unsigned int display_clock_mode
:1;
1316 unsigned int fdi_rx_polarity_inverted
:1;
1317 unsigned int has_mipi
:1;
1319 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1321 enum drrs_support_type drrs_type
;
1326 int edp_preemphasis
;
1328 bool edp_initialized
;
1331 struct edp_power_seq edp_pps
;
1336 bool active_low_pwm
;
1337 u8 min_brightness
; /* min_brightness/255 of max */
1344 struct mipi_config
*config
;
1345 struct mipi_pps_data
*pps
;
1349 u8
*sequence
[MIPI_SEQ_MAX
];
1355 union child_device_config
*child_dev
;
1357 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1360 enum intel_ddb_partitioning
{
1362 INTEL_DDB_PART_5_6
, /* IVB+ */
1365 struct intel_wm_level
{
1373 struct ilk_wm_values
{
1374 uint32_t wm_pipe
[3];
1376 uint32_t wm_lp_spr
[3];
1377 uint32_t wm_linetime
[3];
1379 enum intel_ddb_partitioning partitioning
;
1383 * This struct helps tracking the state needed for runtime PM, which puts the
1384 * device in PCI D3 state. Notice that when this happens, nothing on the
1385 * graphics device works, even register access, so we don't get interrupts nor
1388 * Every piece of our code that needs to actually touch the hardware needs to
1389 * either call intel_runtime_pm_get or call intel_display_power_get with the
1390 * appropriate power domain.
1392 * Our driver uses the autosuspend delay feature, which means we'll only really
1393 * suspend if we stay with zero refcount for a certain amount of time. The
1394 * default value is currently very conservative (see intel_runtime_pm_enable), but
1395 * it can be changed with the standard runtime PM files from sysfs.
1397 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1398 * goes back to false exactly before we reenable the IRQs. We use this variable
1399 * to check if someone is trying to enable/disable IRQs while they're supposed
1400 * to be disabled. This shouldn't happen and we'll print some error messages in
1403 * For more, read the Documentation/power/runtime_pm.txt.
1405 struct i915_runtime_pm
{
1410 enum intel_pipe_crc_source
{
1411 INTEL_PIPE_CRC_SOURCE_NONE
,
1412 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1413 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1414 INTEL_PIPE_CRC_SOURCE_PF
,
1415 INTEL_PIPE_CRC_SOURCE_PIPE
,
1416 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1417 INTEL_PIPE_CRC_SOURCE_TV
,
1418 INTEL_PIPE_CRC_SOURCE_DP_B
,
1419 INTEL_PIPE_CRC_SOURCE_DP_C
,
1420 INTEL_PIPE_CRC_SOURCE_DP_D
,
1421 INTEL_PIPE_CRC_SOURCE_AUTO
,
1422 INTEL_PIPE_CRC_SOURCE_MAX
,
1425 struct intel_pipe_crc_entry
{
1430 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1431 struct intel_pipe_crc
{
1433 bool opened
; /* exclusive access to the result file */
1434 struct intel_pipe_crc_entry
*entries
;
1435 enum intel_pipe_crc_source source
;
1437 wait_queue_head_t wq
;
1440 struct i915_frontbuffer_tracking
{
1444 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1451 struct i915_wa_reg
{
1454 /* bitmask representing WA bits */
1458 #define I915_MAX_WA_REGS 16
1460 struct i915_workarounds
{
1461 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1465 struct drm_i915_private
{
1466 struct drm_device
*dev
;
1467 struct kmem_cache
*slab
;
1469 const struct intel_device_info info
;
1471 int relative_constants_mode
;
1475 struct intel_uncore uncore
;
1477 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1480 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1481 * controller on different i2c buses. */
1482 struct mutex gmbus_mutex
;
1485 * Base address of the gmbus and gpio block.
1487 uint32_t gpio_mmio_base
;
1489 /* MMIO base address for MIPI regs */
1490 uint32_t mipi_mmio_base
;
1492 wait_queue_head_t gmbus_wait_queue
;
1494 struct pci_dev
*bridge_dev
;
1495 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1496 struct drm_i915_gem_object
*semaphore_obj
;
1497 uint32_t last_seqno
, next_seqno
;
1499 struct drm_dma_handle
*status_page_dmah
;
1500 struct resource mch_res
;
1502 /* protects the irq masks */
1503 spinlock_t irq_lock
;
1505 /* protects the mmio flip data */
1506 spinlock_t mmio_flip_lock
;
1508 bool display_irqs_enabled
;
1510 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1511 struct pm_qos_request pm_qos
;
1513 /* DPIO indirect register protection */
1514 struct mutex dpio_lock
;
1516 /** Cached value of IMR to avoid reads in updating the bitfield */
1519 u32 de_irq_mask
[I915_MAX_PIPES
];
1524 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1526 struct work_struct hotplug_work
;
1528 unsigned long hpd_last_jiffies
;
1533 HPD_MARK_DISABLED
= 2
1535 } hpd_stats
[HPD_NUM_PINS
];
1537 struct delayed_work hotplug_reenable_work
;
1539 struct i915_fbc fbc
;
1540 struct i915_drrs drrs
;
1541 struct intel_opregion opregion
;
1542 struct intel_vbt_data vbt
;
1544 bool preserve_bios_swizzle
;
1547 struct intel_overlay
*overlay
;
1549 /* backlight registers and fields in struct intel_panel */
1550 struct mutex backlight_lock
;
1553 bool no_aux_handshake
;
1555 /* protects panel power sequencer state */
1556 struct mutex pps_mutex
;
1558 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1559 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1560 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1562 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1563 unsigned int vlv_cdclk_freq
;
1566 * wq - Driver workqueue for GEM.
1568 * NOTE: Work items scheduled here are not allowed to grab any modeset
1569 * locks, for otherwise the flushing done in the pageflip code will
1570 * result in deadlocks.
1572 struct workqueue_struct
*wq
;
1574 /* Display functions */
1575 struct drm_i915_display_funcs display
;
1577 /* PCH chipset type */
1578 enum intel_pch pch_type
;
1579 unsigned short pch_id
;
1581 unsigned long quirks
;
1583 enum modeset_restore modeset_restore
;
1584 struct mutex modeset_restore_lock
;
1586 struct list_head vm_list
; /* Global list of all address spaces */
1587 struct i915_gtt gtt
; /* VM representing the global address space */
1589 struct i915_gem_mm mm
;
1590 DECLARE_HASHTABLE(mm_structs
, 7);
1591 struct mutex mm_lock
;
1593 /* Kernel Modesetting */
1595 struct sdvo_device_mapping sdvo_mappings
[2];
1597 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1598 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1599 wait_queue_head_t pending_flip_queue
;
1601 #ifdef CONFIG_DEBUG_FS
1602 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1605 int num_shared_dpll
;
1606 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1607 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1609 struct i915_workarounds workarounds
;
1611 /* Reclocking support */
1612 bool render_reclock_avail
;
1613 bool lvds_downclock_avail
;
1614 /* indicates the reduced downclock for LVDS*/
1617 struct i915_frontbuffer_tracking fb_tracking
;
1621 bool mchbar_need_disable
;
1623 struct intel_l3_parity l3_parity
;
1625 /* Cannot be determined by PCIID. You must always read a register. */
1628 /* gen6+ rps state */
1629 struct intel_gen6_power_mgmt rps
;
1631 /* ilk-only ips/rps state. Everything in here is protected by the global
1632 * mchdev_lock in intel_pm.c */
1633 struct intel_ilk_power_mgmt ips
;
1635 struct i915_power_domains power_domains
;
1637 struct i915_psr psr
;
1639 struct i915_gpu_error gpu_error
;
1641 struct drm_i915_gem_object
*vlv_pctx
;
1643 #ifdef CONFIG_DRM_I915_FBDEV
1644 /* list of fbdev register on this device */
1645 struct intel_fbdev
*fbdev
;
1646 struct work_struct fbdev_suspend_work
;
1649 struct drm_property
*broadcast_rgb_property
;
1650 struct drm_property
*force_audio_property
;
1652 uint32_t hw_context_size
;
1653 struct list_head context_list
;
1658 struct i915_suspend_saved_registers regfile
;
1659 struct vlv_s0ix_state vlv_s0ix_state
;
1663 * Raw watermark latency values:
1664 * in 0.1us units for WM0,
1665 * in 0.5us units for WM1+.
1668 uint16_t pri_latency
[5];
1670 uint16_t spr_latency
[5];
1672 uint16_t cur_latency
[5];
1674 /* current hardware state */
1675 struct ilk_wm_values hw
;
1678 struct i915_runtime_pm pm
;
1680 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1681 u32 long_hpd_port_mask
;
1682 u32 short_hpd_port_mask
;
1683 struct work_struct dig_port_work
;
1686 * if we get a HPD irq from DP and a HPD irq from non-DP
1687 * the non-DP HPD could block the workqueue on a mode config
1688 * mutex getting, that userspace may have taken. However
1689 * userspace is waiting on the DP workqueue to run which is
1690 * blocked behind the non-DP one.
1692 struct workqueue_struct
*dp_wq
;
1694 uint32_t bios_vgacntr
;
1696 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1698 struct i915_dri1_state dri1
;
1699 /* Old ums support infrastructure, same warning applies. */
1700 struct i915_ums_state ums
;
1702 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1704 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1705 struct intel_engine_cs
*ring
,
1706 struct intel_context
*ctx
,
1707 struct drm_i915_gem_execbuffer2
*args
,
1708 struct list_head
*vmas
,
1709 struct drm_i915_gem_object
*batch_obj
,
1710 u64 exec_start
, u32 flags
);
1711 int (*init_rings
)(struct drm_device
*dev
);
1712 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1713 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1717 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1718 * will be rejected. Instead look for a better place.
1722 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1724 return dev
->dev_private
;
1727 /* Iterate over initialised rings */
1728 #define for_each_ring(ring__, dev_priv__, i__) \
1729 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1730 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1732 enum hdmi_force_audio
{
1733 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1734 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1735 HDMI_AUDIO_AUTO
, /* trust EDID */
1736 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1739 #define I915_GTT_OFFSET_NONE ((u32)-1)
1741 struct drm_i915_gem_object_ops
{
1742 /* Interface between the GEM object and its backing storage.
1743 * get_pages() is called once prior to the use of the associated set
1744 * of pages before to binding them into the GTT, and put_pages() is
1745 * called after we no longer need them. As we expect there to be
1746 * associated cost with migrating pages between the backing storage
1747 * and making them available for the GPU (e.g. clflush), we may hold
1748 * onto the pages after they are no longer referenced by the GPU
1749 * in case they may be used again shortly (for example migrating the
1750 * pages to a different memory domain within the GTT). put_pages()
1751 * will therefore most likely be called when the object itself is
1752 * being released or under memory pressure (where we attempt to
1753 * reap pages for the shrinker).
1755 int (*get_pages
)(struct drm_i915_gem_object
*);
1756 void (*put_pages
)(struct drm_i915_gem_object
*);
1757 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1758 void (*release
)(struct drm_i915_gem_object
*);
1762 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1763 * considered to be the frontbuffer for the given plane interface-vise. This
1764 * doesn't mean that the hw necessarily already scans it out, but that any
1765 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1767 * We have one bit per pipe and per scanout plane type.
1769 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1770 #define INTEL_FRONTBUFFER_BITS \
1771 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1772 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1773 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1774 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1775 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1776 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1777 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1778 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1779 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1780 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1781 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1783 struct drm_i915_gem_object
{
1784 struct drm_gem_object base
;
1786 const struct drm_i915_gem_object_ops
*ops
;
1788 /** List of VMAs backed by this object */
1789 struct list_head vma_list
;
1791 /** Stolen memory for this object, instead of being backed by shmem. */
1792 struct drm_mm_node
*stolen
;
1793 struct list_head global_list
;
1795 struct list_head ring_list
;
1796 /** Used in execbuf to temporarily hold a ref */
1797 struct list_head obj_exec_link
;
1800 * This is set if the object is on the active lists (has pending
1801 * rendering and so a non-zero seqno), and is not set if it i s on
1802 * inactive (ready to be unbound) list.
1804 unsigned int active
:1;
1807 * This is set if the object has been written to since last bound
1810 unsigned int dirty
:1;
1813 * Fence register bits (if any) for this object. Will be set
1814 * as needed when mapped into the GTT.
1815 * Protected by dev->struct_mutex.
1817 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1820 * Advice: are the backing pages purgeable?
1822 unsigned int madv
:2;
1825 * Current tiling mode for the object.
1827 unsigned int tiling_mode
:2;
1829 * Whether the tiling parameters for the currently associated fence
1830 * register have changed. Note that for the purposes of tracking
1831 * tiling changes we also treat the unfenced register, the register
1832 * slot that the object occupies whilst it executes a fenced
1833 * command (such as BLT on gen2/3), as a "fence".
1835 unsigned int fence_dirty
:1;
1838 * Is the object at the current location in the gtt mappable and
1839 * fenceable? Used to avoid costly recalculations.
1841 unsigned int map_and_fenceable
:1;
1844 * Whether the current gtt mapping needs to be mappable (and isn't just
1845 * mappable by accident). Track pin and fault separate for a more
1846 * accurate mappable working set.
1848 unsigned int fault_mappable
:1;
1849 unsigned int pin_mappable
:1;
1850 unsigned int pin_display
:1;
1853 * Is the object to be mapped as read-only to the GPU
1854 * Only honoured if hardware has relevant pte bit
1856 unsigned long gt_ro
:1;
1857 unsigned int cache_level
:3;
1859 unsigned int has_aliasing_ppgtt_mapping
:1;
1860 unsigned int has_global_gtt_mapping
:1;
1861 unsigned int has_dma_mapping
:1;
1863 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1865 struct sg_table
*pages
;
1866 int pages_pin_count
;
1868 /* prime dma-buf support */
1869 void *dma_buf_vmapping
;
1872 struct intel_engine_cs
*ring
;
1874 /** Breadcrumb of last rendering to the buffer. */
1875 uint32_t last_read_seqno
;
1876 uint32_t last_write_seqno
;
1877 /** Breadcrumb of last fenced GPU access to the buffer. */
1878 uint32_t last_fenced_seqno
;
1880 /** Current tiling stride for the object, if it's tiled. */
1883 /** References from framebuffers, locks out tiling changes. */
1884 unsigned long framebuffer_references
;
1886 /** Record of address bit 17 of each page at last unbind. */
1887 unsigned long *bit_17
;
1889 /** User space pin count and filp owning the pin */
1890 unsigned long user_pin_count
;
1891 struct drm_file
*pin_filp
;
1893 /** for phy allocated objects */
1894 struct drm_dma_handle
*phys_handle
;
1897 struct i915_gem_userptr
{
1899 unsigned read_only
:1;
1900 unsigned workers
:4;
1901 #define I915_GEM_USERPTR_MAX_WORKERS 15
1903 struct i915_mm_struct
*mm
;
1904 struct i915_mmu_object
*mmu_object
;
1905 struct work_struct
*work
;
1909 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1911 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1912 struct drm_i915_gem_object
*new,
1913 unsigned frontbuffer_bits
);
1916 * Request queue structure.
1918 * The request queue allows us to note sequence numbers that have been emitted
1919 * and may be associated with active buffers to be retired.
1921 * By keeping this list, we can avoid having to do questionable
1922 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1923 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1925 struct drm_i915_gem_request
{
1926 /** On Which ring this request was generated */
1927 struct intel_engine_cs
*ring
;
1929 /** GEM sequence number associated with this request. */
1932 /** Position in the ringbuffer of the start of the request */
1935 /** Position in the ringbuffer of the end of the request */
1938 /** Context related to this request */
1939 struct intel_context
*ctx
;
1941 /** Batch buffer related to this request if any */
1942 struct drm_i915_gem_object
*batch_obj
;
1944 /** Time at which this request was emitted, in jiffies. */
1945 unsigned long emitted_jiffies
;
1947 /** global list entry for this request */
1948 struct list_head list
;
1950 struct drm_i915_file_private
*file_priv
;
1951 /** file_priv list entry for this request */
1952 struct list_head client_list
;
1955 struct drm_i915_file_private
{
1956 struct drm_i915_private
*dev_priv
;
1957 struct drm_file
*file
;
1961 struct list_head request_list
;
1962 struct delayed_work idle_work
;
1964 struct idr context_idr
;
1966 atomic_t rps_wait_boost
;
1967 struct intel_engine_cs
*bsd_ring
;
1971 * A command that requires special handling by the command parser.
1973 struct drm_i915_cmd_descriptor
{
1975 * Flags describing how the command parser processes the command.
1977 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1978 * a length mask if not set
1979 * CMD_DESC_SKIP: The command is allowed but does not follow the
1980 * standard length encoding for the opcode range in
1982 * CMD_DESC_REJECT: The command is never allowed
1983 * CMD_DESC_REGISTER: The command should be checked against the
1984 * register whitelist for the appropriate ring
1985 * CMD_DESC_MASTER: The command is allowed if the submitting process
1989 #define CMD_DESC_FIXED (1<<0)
1990 #define CMD_DESC_SKIP (1<<1)
1991 #define CMD_DESC_REJECT (1<<2)
1992 #define CMD_DESC_REGISTER (1<<3)
1993 #define CMD_DESC_BITMASK (1<<4)
1994 #define CMD_DESC_MASTER (1<<5)
1997 * The command's unique identification bits and the bitmask to get them.
1998 * This isn't strictly the opcode field as defined in the spec and may
1999 * also include type, subtype, and/or subop fields.
2007 * The command's length. The command is either fixed length (i.e. does
2008 * not include a length field) or has a length field mask. The flag
2009 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2010 * a length mask. All command entries in a command table must include
2011 * length information.
2019 * Describes where to find a register address in the command to check
2020 * against the ring's register whitelist. Only valid if flags has the
2021 * CMD_DESC_REGISTER bit set.
2028 #define MAX_CMD_DESC_BITMASKS 3
2030 * Describes command checks where a particular dword is masked and
2031 * compared against an expected value. If the command does not match
2032 * the expected value, the parser rejects it. Only valid if flags has
2033 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2036 * If the check specifies a non-zero condition_mask then the parser
2037 * only performs the check when the bits specified by condition_mask
2044 u32 condition_offset
;
2046 } bits
[MAX_CMD_DESC_BITMASKS
];
2050 * A table of commands requiring special handling by the command parser.
2052 * Each ring has an array of tables. Each table consists of an array of command
2053 * descriptors, which must be sorted with command opcodes in ascending order.
2055 struct drm_i915_cmd_table
{
2056 const struct drm_i915_cmd_descriptor
*table
;
2060 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2061 #define __I915__(p) ({ \
2062 struct drm_i915_private *__p; \
2063 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2064 __p = (struct drm_i915_private *)p; \
2065 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2066 __p = to_i915((struct drm_device *)p); \
2071 #define INTEL_INFO(p) (&__I915__(p)->info)
2072 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2074 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2075 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2076 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2077 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2078 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2079 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2080 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2081 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2082 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2083 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2084 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2085 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2086 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2087 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2088 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2089 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2090 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2091 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2092 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2093 INTEL_DEVID(dev) == 0x0152 || \
2094 INTEL_DEVID(dev) == 0x015a)
2095 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2096 INTEL_DEVID(dev) == 0x0106 || \
2097 INTEL_DEVID(dev) == 0x010A)
2098 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2099 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2100 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2101 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2102 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2103 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2104 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2105 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2106 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2107 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2108 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2109 (INTEL_DEVID(dev) & 0xf) == 0xe))
2110 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2111 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2112 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2113 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2114 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2115 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2116 /* ULX machines are also considered ULT. */
2117 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2118 INTEL_DEVID(dev) == 0x0A1E)
2119 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2122 * The genX designation typically refers to the render engine, so render
2123 * capability related checks should use IS_GEN, while display and other checks
2124 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2127 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2128 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2129 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2130 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2131 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2132 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2133 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2134 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2136 #define RENDER_RING (1<<RCS)
2137 #define BSD_RING (1<<VCS)
2138 #define BLT_RING (1<<BCS)
2139 #define VEBOX_RING (1<<VECS)
2140 #define BSD2_RING (1<<VCS2)
2141 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2142 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2143 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2144 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2145 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2146 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2147 __I915__(dev)->ellc_size)
2148 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2150 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2151 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2152 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2153 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2155 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2156 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2158 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2159 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2161 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2162 * even when in MSI mode. This results in spurious interrupt warnings if the
2163 * legacy irq no. is shared with another device. The kernel then disables that
2164 * interrupt source and so prevents the other device from working properly.
2166 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2167 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2169 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2170 * rows, which changed the alignment requirements and fence programming.
2172 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2174 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2175 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2176 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2177 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2178 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2180 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2181 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2182 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2184 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2186 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2187 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2188 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2189 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2190 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2191 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2192 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2194 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2195 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2196 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2197 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2198 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2199 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2200 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2201 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2203 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2204 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2205 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2206 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2207 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2208 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2209 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2211 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2213 /* DPF == dynamic parity feature */
2214 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2215 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2217 #define GT_FREQUENCY_MULTIPLIER 50
2219 #include "i915_trace.h"
2221 extern const struct drm_ioctl_desc i915_ioctls
[];
2222 extern int i915_max_ioctl
;
2224 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2225 extern int i915_resume_legacy(struct drm_device
*dev
);
2226 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2227 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2230 struct i915_params
{
2232 int panel_ignore_lid
;
2233 unsigned int powersave
;
2235 unsigned int lvds_downclock
;
2236 int lvds_channel_mode
;
2238 int vbt_sdvo_panel_type
;
2242 int enable_execlists
;
2244 unsigned int preliminary_hw_support
;
2245 int disable_power_well
;
2247 int invert_brightness
;
2248 int enable_cmd_parser
;
2249 /* leave bools at the end to not create holes */
2250 bool enable_hangcheck
;
2252 bool prefault_disable
;
2254 bool disable_display
;
2255 bool disable_vtd_wa
;
2259 extern struct i915_params i915 __read_mostly
;
2262 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2263 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2264 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2265 extern int i915_driver_unload(struct drm_device
*);
2266 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2267 extern void i915_driver_lastclose(struct drm_device
* dev
);
2268 extern void i915_driver_preclose(struct drm_device
*dev
,
2269 struct drm_file
*file
);
2270 extern void i915_driver_postclose(struct drm_device
*dev
,
2271 struct drm_file
*file
);
2272 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2273 #ifdef CONFIG_COMPAT
2274 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2277 extern int i915_emit_box(struct drm_device
*dev
,
2278 struct drm_clip_rect
*box
,
2280 extern int intel_gpu_reset(struct drm_device
*dev
);
2281 extern int i915_reset(struct drm_device
*dev
);
2282 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2283 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2284 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2285 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2286 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2287 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2290 void i915_queue_hangcheck(struct drm_device
*dev
);
2292 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2293 const char *fmt
, ...);
2295 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2297 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2298 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2299 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2300 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2302 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2303 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2304 bool restore_forcewake
);
2305 extern void intel_uncore_init(struct drm_device
*dev
);
2306 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2307 extern void intel_uncore_fini(struct drm_device
*dev
);
2308 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2311 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2315 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2318 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2319 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2321 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2323 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2324 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2325 uint32_t interrupt_mask
,
2326 uint32_t enabled_irq_mask
);
2327 #define ibx_enable_display_interrupt(dev_priv, bits) \
2328 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2329 #define ibx_disable_display_interrupt(dev_priv, bits) \
2330 ibx_display_interrupt_update((dev_priv), (bits), 0)
2333 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2334 struct drm_file
*file_priv
);
2335 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2336 struct drm_file
*file_priv
);
2337 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2338 struct drm_file
*file_priv
);
2339 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2340 struct drm_file
*file_priv
);
2341 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2342 struct drm_file
*file_priv
);
2343 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2344 struct drm_file
*file_priv
);
2345 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2346 struct drm_file
*file_priv
);
2347 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2348 struct drm_file
*file_priv
);
2349 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2350 struct intel_engine_cs
*ring
);
2351 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2352 struct drm_file
*file
,
2353 struct intel_engine_cs
*ring
,
2354 struct drm_i915_gem_object
*obj
);
2355 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2356 struct drm_file
*file
,
2357 struct intel_engine_cs
*ring
,
2358 struct intel_context
*ctx
,
2359 struct drm_i915_gem_execbuffer2
*args
,
2360 struct list_head
*vmas
,
2361 struct drm_i915_gem_object
*batch_obj
,
2362 u64 exec_start
, u32 flags
);
2363 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2364 struct drm_file
*file_priv
);
2365 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2366 struct drm_file
*file_priv
);
2367 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2368 struct drm_file
*file_priv
);
2369 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2370 struct drm_file
*file_priv
);
2371 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2372 struct drm_file
*file_priv
);
2373 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2374 struct drm_file
*file
);
2375 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2376 struct drm_file
*file
);
2377 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2378 struct drm_file
*file_priv
);
2379 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2380 struct drm_file
*file_priv
);
2381 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2382 struct drm_file
*file_priv
);
2383 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2384 struct drm_file
*file_priv
);
2385 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2386 struct drm_file
*file_priv
);
2387 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2388 struct drm_file
*file_priv
);
2389 int i915_gem_init_userptr(struct drm_device
*dev
);
2390 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2391 struct drm_file
*file
);
2392 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2393 struct drm_file
*file_priv
);
2394 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2395 struct drm_file
*file_priv
);
2396 void i915_gem_load(struct drm_device
*dev
);
2397 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2400 #define I915_SHRINK_PURGEABLE 0x1
2401 #define I915_SHRINK_UNBOUND 0x2
2402 #define I915_SHRINK_BOUND 0x4
2403 void *i915_gem_object_alloc(struct drm_device
*dev
);
2404 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2405 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2406 const struct drm_i915_gem_object_ops
*ops
);
2407 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2409 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2410 struct i915_address_space
*vm
);
2411 void i915_gem_free_object(struct drm_gem_object
*obj
);
2412 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2414 #define PIN_MAPPABLE 0x1
2415 #define PIN_NONBLOCK 0x2
2416 #define PIN_GLOBAL 0x4
2417 #define PIN_OFFSET_BIAS 0x8
2418 #define PIN_OFFSET_MASK (~4095)
2419 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2420 struct i915_address_space
*vm
,
2423 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2424 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2425 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2426 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2427 void i915_gem_lastclose(struct drm_device
*dev
);
2429 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2430 int *needs_clflush
);
2432 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2433 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2435 struct sg_page_iter sg_iter
;
2437 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2438 return sg_page_iter_page(&sg_iter
);
2442 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2444 BUG_ON(obj
->pages
== NULL
);
2445 obj
->pages_pin_count
++;
2447 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2449 BUG_ON(obj
->pages_pin_count
== 0);
2450 obj
->pages_pin_count
--;
2453 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2454 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2455 struct intel_engine_cs
*to
);
2456 void i915_vma_move_to_active(struct i915_vma
*vma
,
2457 struct intel_engine_cs
*ring
);
2458 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2459 struct drm_device
*dev
,
2460 struct drm_mode_create_dumb
*args
);
2461 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2462 uint32_t handle
, uint64_t *offset
);
2464 * Returns true if seq1 is later than seq2.
2467 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2469 return (int32_t)(seq1
- seq2
) >= 0;
2472 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2473 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2474 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2475 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2477 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2478 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2480 struct drm_i915_gem_request
*
2481 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2483 bool i915_gem_retire_requests(struct drm_device
*dev
);
2484 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2485 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2486 bool interruptible
);
2487 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2489 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2491 return unlikely(atomic_read(&error
->reset_counter
)
2492 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2495 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2497 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2500 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2502 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2505 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2507 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2508 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2511 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2513 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2514 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2517 void i915_gem_reset(struct drm_device
*dev
);
2518 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2519 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2520 int __must_check
i915_gem_init(struct drm_device
*dev
);
2521 int i915_gem_init_rings(struct drm_device
*dev
);
2522 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2523 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2524 void i915_gem_init_swizzling(struct drm_device
*dev
);
2525 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2526 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2527 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2528 int __i915_add_request(struct intel_engine_cs
*ring
,
2529 struct drm_file
*file
,
2530 struct drm_i915_gem_object
*batch_obj
,
2532 #define i915_add_request(ring, seqno) \
2533 __i915_add_request(ring, NULL, NULL, seqno)
2534 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2536 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2538 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2541 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2543 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2545 struct intel_engine_cs
*pipelined
);
2546 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2547 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2549 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2550 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2553 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2555 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2556 int tiling_mode
, bool fenced
);
2558 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2559 enum i915_cache_level cache_level
);
2561 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2562 struct dma_buf
*dma_buf
);
2564 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2565 struct drm_gem_object
*gem_obj
, int flags
);
2567 void i915_gem_restore_fences(struct drm_device
*dev
);
2569 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2570 struct i915_address_space
*vm
);
2571 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2572 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2573 struct i915_address_space
*vm
);
2574 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2575 struct i915_address_space
*vm
);
2576 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2577 struct i915_address_space
*vm
);
2579 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2580 struct i915_address_space
*vm
);
2582 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2583 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2584 struct i915_vma
*vma
;
2585 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2586 if (vma
->pin_count
> 0)
2591 /* Some GGTT VM helpers */
2592 #define i915_obj_to_ggtt(obj) \
2593 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2594 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2596 struct i915_address_space
*ggtt
=
2597 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2601 static inline struct i915_hw_ppgtt
*
2602 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2604 WARN_ON(i915_is_ggtt(vm
));
2606 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2610 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2612 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2615 static inline unsigned long
2616 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2618 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2621 static inline unsigned long
2622 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2624 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2627 static inline int __must_check
2628 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2632 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2633 alignment
, flags
| PIN_GLOBAL
);
2637 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2639 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2642 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2644 /* i915_gem_context.c */
2645 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2646 void i915_gem_context_fini(struct drm_device
*dev
);
2647 void i915_gem_context_reset(struct drm_device
*dev
);
2648 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2649 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2650 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2651 int i915_switch_context(struct intel_engine_cs
*ring
,
2652 struct intel_context
*to
);
2653 struct intel_context
*
2654 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2655 void i915_gem_context_free(struct kref
*ctx_ref
);
2656 struct drm_i915_gem_object
*
2657 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2658 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2660 kref_get(&ctx
->ref
);
2663 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2665 kref_put(&ctx
->ref
, i915_gem_context_free
);
2668 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2670 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2673 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2674 struct drm_file
*file
);
2675 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2676 struct drm_file
*file
);
2678 /* i915_gem_evict.c */
2679 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2680 struct i915_address_space
*vm
,
2683 unsigned cache_level
,
2684 unsigned long start
,
2687 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2688 int i915_gem_evict_everything(struct drm_device
*dev
);
2690 /* belongs in i915_gem_gtt.h */
2691 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2693 if (INTEL_INFO(dev
)->gen
< 6)
2694 intel_gtt_chipset_flush();
2697 /* i915_gem_stolen.c */
2698 int i915_gem_init_stolen(struct drm_device
*dev
);
2699 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2700 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2701 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2702 struct drm_i915_gem_object
*
2703 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2704 struct drm_i915_gem_object
*
2705 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2710 /* i915_gem_tiling.c */
2711 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2713 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2715 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2716 obj
->tiling_mode
!= I915_TILING_NONE
;
2719 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2720 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2721 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2723 /* i915_gem_debug.c */
2725 int i915_verify_lists(struct drm_device
*dev
);
2727 #define i915_verify_lists(dev) 0
2730 /* i915_debugfs.c */
2731 int i915_debugfs_init(struct drm_minor
*minor
);
2732 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2733 #ifdef CONFIG_DEBUG_FS
2734 void intel_display_crc_init(struct drm_device
*dev
);
2736 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2739 /* i915_gpu_error.c */
2741 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2742 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2743 const struct i915_error_state_file_priv
*error
);
2744 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2745 struct drm_i915_private
*i915
,
2746 size_t count
, loff_t pos
);
2747 static inline void i915_error_state_buf_release(
2748 struct drm_i915_error_state_buf
*eb
)
2752 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2753 const char *error_msg
);
2754 void i915_error_state_get(struct drm_device
*dev
,
2755 struct i915_error_state_file_priv
*error_priv
);
2756 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2757 void i915_destroy_error_state(struct drm_device
*dev
);
2759 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2760 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
2762 /* i915_cmd_parser.c */
2763 int i915_cmd_parser_get_version(void);
2764 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2765 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2766 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2767 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2768 struct drm_i915_gem_object
*batch_obj
,
2769 u32 batch_start_offset
,
2772 /* i915_suspend.c */
2773 extern int i915_save_state(struct drm_device
*dev
);
2774 extern int i915_restore_state(struct drm_device
*dev
);
2777 void i915_save_display_reg(struct drm_device
*dev
);
2778 void i915_restore_display_reg(struct drm_device
*dev
);
2781 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2782 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2785 extern int intel_setup_gmbus(struct drm_device
*dev
);
2786 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2787 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2789 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2792 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2793 struct drm_i915_private
*dev_priv
, unsigned port
);
2794 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2795 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2796 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2798 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2800 extern void intel_i2c_reset(struct drm_device
*dev
);
2802 /* intel_opregion.c */
2803 struct intel_encoder
;
2805 extern int intel_opregion_setup(struct drm_device
*dev
);
2806 extern void intel_opregion_init(struct drm_device
*dev
);
2807 extern void intel_opregion_fini(struct drm_device
*dev
);
2808 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2809 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2811 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2814 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2815 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2816 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2817 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2819 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2824 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2832 extern void intel_register_dsm_handler(void);
2833 extern void intel_unregister_dsm_handler(void);
2835 static inline void intel_register_dsm_handler(void) { return; }
2836 static inline void intel_unregister_dsm_handler(void) { return; }
2837 #endif /* CONFIG_ACPI */
2840 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2841 extern void intel_modeset_init(struct drm_device
*dev
);
2842 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2843 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2844 extern void intel_connector_unregister(struct intel_connector
*);
2845 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2846 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2847 bool force_restore
);
2848 extern void i915_redisable_vga(struct drm_device
*dev
);
2849 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2850 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2851 extern void bdw_fbc_sw_flush(struct drm_device
*dev
, u32 value
);
2852 extern void intel_disable_fbc(struct drm_device
*dev
);
2853 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2854 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2855 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2856 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2857 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2859 extern void intel_detect_pch(struct drm_device
*dev
);
2860 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2861 extern int intel_enable_rc6(const struct drm_device
*dev
);
2863 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2864 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2865 struct drm_file
*file
);
2866 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2867 struct drm_file
*file
);
2869 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2872 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2873 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2874 struct intel_overlay_error_state
*error
);
2876 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2877 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2878 struct drm_device
*dev
,
2879 struct intel_display_error_state
*error
);
2881 /* On SNB platform, before reading ring registers forcewake bit
2882 * must be set to prevent GT core from power down and stale values being
2885 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2886 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2887 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2889 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2890 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2892 /* intel_sideband.c */
2893 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2894 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2895 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2896 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2897 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2898 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2899 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2900 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2901 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2902 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2903 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2904 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2905 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2906 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2907 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2908 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2909 enum intel_sbi_destination destination
);
2910 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2911 enum intel_sbi_destination destination
);
2912 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2913 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2915 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2916 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2918 #define FORCEWAKE_RENDER (1 << 0)
2919 #define FORCEWAKE_MEDIA (1 << 1)
2920 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2923 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2924 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2926 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2927 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2928 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2929 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2931 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2932 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2933 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2934 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2936 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2937 * will be implemented using 2 32-bit writes in an arbitrary order with
2938 * an arbitrary delay between them. This can cause the hardware to
2939 * act upon the intermediate value, possibly leading to corruption and
2940 * machine death. You have been warned.
2942 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2943 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2945 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2946 u32 upper = I915_READ(upper_reg); \
2947 u32 lower = I915_READ(lower_reg); \
2948 u32 tmp = I915_READ(upper_reg); \
2949 if (upper != tmp) { \
2951 lower = I915_READ(lower_reg); \
2952 WARN_ON(I915_READ(upper_reg) != upper); \
2954 (u64)upper << 32 | lower; })
2956 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2957 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2959 /* "Broadcast RGB" property */
2960 #define INTEL_BROADCAST_RGB_AUTO 0
2961 #define INTEL_BROADCAST_RGB_FULL 1
2962 #define INTEL_BROADCAST_RGB_LIMITED 2
2964 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2966 if (IS_VALLEYVIEW(dev
))
2967 return VLV_VGACNTRL
;
2968 else if (INTEL_INFO(dev
)->gen
>= 5)
2969 return CPU_VGACNTRL
;
2974 static inline void __user
*to_user_ptr(u64 address
)
2976 return (void __user
*)(uintptr_t)address
;
2979 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2981 unsigned long j
= msecs_to_jiffies(m
);
2983 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2986 static inline unsigned long
2987 timespec_to_jiffies_timeout(const struct timespec
*value
)
2989 unsigned long j
= timespec_to_jiffies(value
);
2991 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2995 * If you need to wait X milliseconds between events A and B, but event B
2996 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2997 * when event A happened, then just before event B you call this function and
2998 * pass the timestamp as the first argument, and X as the second argument.
3001 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3003 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3006 * Don't re-read the value of "jiffies" every time since it may change
3007 * behind our back and break the math.
3009 tmp_jiffies
= jiffies
;
3010 target_jiffies
= timestamp_jiffies
+
3011 msecs_to_jiffies_timeout(to_wait_ms
);
3013 if (time_after(target_jiffies
, tmp_jiffies
)) {
3014 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3015 while (remaining_jiffies
)
3017 schedule_timeout_uninterruptible(remaining_jiffies
);