1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141024"
61 #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
69 I915_MAX_PIPES
= _PIPE_EDP
71 #define pipe_name(p) ((p) + 'A')
80 #define transcoder_name(t) ((t) + 'A')
83 * This is the maximum (across all platforms) number of planes (primary +
84 * sprites) that can be active at the same time on one pipe.
86 * This value doesn't count the cursor plane.
88 #define I915_MAX_PLANES 3
95 #define plane_name(p) ((p) + 'A')
97 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
107 #define port_name(p) ((p) + 'A')
109 #define I915_NUM_PHYS_VLV 2
121 enum intel_display_power_domain
{
125 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
126 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
127 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
128 POWER_DOMAIN_TRANSCODER_A
,
129 POWER_DOMAIN_TRANSCODER_B
,
130 POWER_DOMAIN_TRANSCODER_C
,
131 POWER_DOMAIN_TRANSCODER_EDP
,
132 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
133 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
134 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
135 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
136 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
137 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
138 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
139 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
140 POWER_DOMAIN_PORT_DSI
,
141 POWER_DOMAIN_PORT_CRT
,
142 POWER_DOMAIN_PORT_OTHER
,
151 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
152 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
153 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
154 #define POWER_DOMAIN_TRANSCODER(tran) \
155 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
156 (tran) + POWER_DOMAIN_TRANSCODER_A)
160 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
161 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
171 #define I915_GEM_GPU_DOMAINS \
172 (I915_GEM_DOMAIN_RENDER | \
173 I915_GEM_DOMAIN_SAMPLER | \
174 I915_GEM_DOMAIN_COMMAND | \
175 I915_GEM_DOMAIN_INSTRUCTION | \
176 I915_GEM_DOMAIN_VERTEX)
178 #define for_each_pipe(__dev_priv, __p) \
179 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
180 #define for_each_plane(pipe, p) \
181 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
182 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
184 #define for_each_crtc(dev, crtc) \
185 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
187 #define for_each_intel_crtc(dev, intel_crtc) \
188 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
190 #define for_each_intel_encoder(dev, intel_encoder) \
191 list_for_each_entry(intel_encoder, \
192 &(dev)->mode_config.encoder_list, \
195 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
196 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
197 if ((intel_encoder)->base.crtc == (__crtc))
199 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
200 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
201 if ((intel_connector)->base.encoder == (__encoder))
203 #define for_each_power_domain(domain, mask) \
204 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
205 if ((1 << (domain)) & (mask))
207 struct drm_i915_private
;
208 struct i915_mm_struct
;
209 struct i915_mmu_object
;
212 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
213 /* real shared dpll ids must be >= 0 */
214 DPLL_ID_PCH_PLL_A
= 0,
215 DPLL_ID_PCH_PLL_B
= 1,
219 #define I915_NUM_PLLS 2
221 struct intel_dpll_hw_state
{
232 struct intel_shared_dpll_config
{
233 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
234 struct intel_dpll_hw_state hw_state
;
237 struct intel_shared_dpll
{
238 struct intel_shared_dpll_config config
;
239 struct intel_shared_dpll_config
*new_config
;
241 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
242 bool on
; /* is the PLL actually active? Disabled during modeset */
244 /* should match the index in the dev_priv->shared_dplls array */
245 enum intel_dpll_id id
;
246 /* The mode_set hook is optional and should be used together with the
247 * intel_prepare_shared_dpll function. */
248 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
249 struct intel_shared_dpll
*pll
);
250 void (*enable
)(struct drm_i915_private
*dev_priv
,
251 struct intel_shared_dpll
*pll
);
252 void (*disable
)(struct drm_i915_private
*dev_priv
,
253 struct intel_shared_dpll
*pll
);
254 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
255 struct intel_shared_dpll
*pll
,
256 struct intel_dpll_hw_state
*hw_state
);
259 /* Used by dp and fdi links */
260 struct intel_link_m_n
{
268 void intel_link_compute_m_n(int bpp
, int nlanes
,
269 int pixel_clock
, int link_clock
,
270 struct intel_link_m_n
*m_n
);
272 /* Interface history:
275 * 1.2: Add Power Management
276 * 1.3: Add vblank support
277 * 1.4: Fix cmdbuffer path, add heap destroy
278 * 1.5: Add vblank pipe configuration
279 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
280 * - Support vertical blank on secondary display pipe
282 #define DRIVER_MAJOR 1
283 #define DRIVER_MINOR 6
284 #define DRIVER_PATCHLEVEL 0
286 #define WATCH_LISTS 0
288 struct opregion_header
;
289 struct opregion_acpi
;
290 struct opregion_swsci
;
291 struct opregion_asle
;
293 struct intel_opregion
{
294 struct opregion_header __iomem
*header
;
295 struct opregion_acpi __iomem
*acpi
;
296 struct opregion_swsci __iomem
*swsci
;
297 u32 swsci_gbda_sub_functions
;
298 u32 swsci_sbcb_sub_functions
;
299 struct opregion_asle __iomem
*asle
;
301 u32 __iomem
*lid_state
;
302 struct work_struct asle_work
;
304 #define OPREGION_SIZE (8*1024)
306 struct intel_overlay
;
307 struct intel_overlay_error_state
;
309 struct drm_local_map
;
311 struct drm_i915_master_private
{
312 struct drm_local_map
*sarea
;
313 struct _drm_i915_sarea
*sarea_priv
;
315 #define I915_FENCE_REG_NONE -1
316 #define I915_MAX_NUM_FENCES 32
317 /* 32 fences + sign bit for FENCE_REG_NONE */
318 #define I915_MAX_NUM_FENCE_BITS 6
320 struct drm_i915_fence_reg
{
321 struct list_head lru_list
;
322 struct drm_i915_gem_object
*obj
;
326 struct sdvo_device_mapping
{
335 struct intel_display_error_state
;
337 struct drm_i915_error_state
{
345 /* Generic register state */
353 u32 error
; /* gen6+ */
354 u32 err_int
; /* gen7 */
360 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
361 u64 fence
[I915_MAX_NUM_FENCES
];
362 struct intel_overlay_error_state
*overlay
;
363 struct intel_display_error_state
*display
;
364 struct drm_i915_error_object
*semaphore_obj
;
366 struct drm_i915_error_ring
{
368 /* Software tracked state */
371 enum intel_ring_hangcheck_action hangcheck_action
;
374 /* our own tracking of ring head and tail */
378 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
396 u32 rc_psmi
; /* sleep state */
397 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
399 struct drm_i915_error_object
{
403 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
405 struct drm_i915_error_request
{
420 char comm
[TASK_COMM_LEN
];
421 } ring
[I915_NUM_RINGS
];
423 struct drm_i915_error_buffer
{
430 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
438 } **active_bo
, **pinned_bo
;
440 u32
*active_bo_count
, *pinned_bo_count
;
444 struct intel_connector
;
445 struct intel_encoder
;
446 struct intel_crtc_config
;
447 struct intel_plane_config
;
452 struct drm_i915_display_funcs
{
453 bool (*fbc_enabled
)(struct drm_device
*dev
);
454 void (*enable_fbc
)(struct drm_crtc
*crtc
);
455 void (*disable_fbc
)(struct drm_device
*dev
);
456 int (*get_display_clock_speed
)(struct drm_device
*dev
);
457 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
459 * find_dpll() - Find the best values for the PLL
460 * @limit: limits for the PLL
461 * @crtc: current CRTC
462 * @target: target frequency in kHz
463 * @refclk: reference clock frequency in kHz
464 * @match_clock: if provided, @best_clock P divider must
465 * match the P divider from @match_clock
466 * used for LVDS downclocking
467 * @best_clock: best PLL values found
469 * Returns true on success, false on failure.
471 bool (*find_dpll
)(const struct intel_limit
*limit
,
472 struct intel_crtc
*crtc
,
473 int target
, int refclk
,
474 struct dpll
*match_clock
,
475 struct dpll
*best_clock
);
476 void (*update_wm
)(struct drm_crtc
*crtc
);
477 void (*update_sprite_wm
)(struct drm_plane
*plane
,
478 struct drm_crtc
*crtc
,
479 uint32_t sprite_width
, uint32_t sprite_height
,
480 int pixel_size
, bool enable
, bool scaled
);
481 void (*modeset_global_resources
)(struct drm_device
*dev
);
482 /* Returns the active state of the crtc, and if the crtc is active,
483 * fills out the pipe-config with the hw state. */
484 bool (*get_pipe_config
)(struct intel_crtc
*,
485 struct intel_crtc_config
*);
486 void (*get_plane_config
)(struct intel_crtc
*,
487 struct intel_plane_config
*);
488 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
);
489 void (*crtc_enable
)(struct drm_crtc
*crtc
);
490 void (*crtc_disable
)(struct drm_crtc
*crtc
);
491 void (*off
)(struct drm_crtc
*crtc
);
492 void (*audio_codec_enable
)(struct drm_connector
*connector
,
493 struct intel_encoder
*encoder
,
494 struct drm_display_mode
*mode
);
495 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
496 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
497 void (*init_clock_gating
)(struct drm_device
*dev
);
498 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
499 struct drm_framebuffer
*fb
,
500 struct drm_i915_gem_object
*obj
,
501 struct intel_engine_cs
*ring
,
503 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
504 struct drm_framebuffer
*fb
,
506 void (*hpd_irq_setup
)(struct drm_device
*dev
);
507 /* clock updates for mode set */
509 /* render clock increase/decrease */
510 /* display clock increase/decrease */
511 /* pll clock increase/decrease */
513 int (*setup_backlight
)(struct intel_connector
*connector
);
514 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
515 void (*set_backlight
)(struct intel_connector
*connector
,
517 void (*disable_backlight
)(struct intel_connector
*connector
);
518 void (*enable_backlight
)(struct intel_connector
*connector
);
521 struct intel_uncore_funcs
{
522 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
524 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
527 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
528 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
529 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
530 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
532 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
533 uint8_t val
, bool trace
);
534 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
535 uint16_t val
, bool trace
);
536 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
537 uint32_t val
, bool trace
);
538 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
539 uint64_t val
, bool trace
);
542 struct intel_uncore
{
543 spinlock_t lock
; /** lock is also taken in irq contexts. */
545 struct intel_uncore_funcs funcs
;
548 unsigned forcewake_count
;
550 unsigned fw_rendercount
;
551 unsigned fw_mediacount
;
553 struct timer_list force_wake_timer
;
556 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
557 func(is_mobile) sep \
560 func(is_i945gm) sep \
562 func(need_gfx_hws) sep \
564 func(is_pineview) sep \
565 func(is_broadwater) sep \
566 func(is_crestline) sep \
567 func(is_ivybridge) sep \
568 func(is_valleyview) sep \
569 func(is_haswell) sep \
570 func(is_skylake) sep \
571 func(is_preliminary) sep \
573 func(has_pipe_cxsr) sep \
574 func(has_hotplug) sep \
575 func(cursor_needs_physical) sep \
576 func(has_overlay) sep \
577 func(overlay_needs_physical) sep \
578 func(supports_tv) sep \
583 #define DEFINE_FLAG(name) u8 name:1
584 #define SEP_SEMICOLON ;
586 struct intel_device_info
{
587 u32 display_mmio_offset
;
590 u8 num_sprites
[I915_MAX_PIPES
];
592 u8 ring_mask
; /* Rings supported by the HW */
593 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
594 /* Register offsets for the various display pipes and transcoders */
595 int pipe_offsets
[I915_MAX_TRANSCODERS
];
596 int trans_offsets
[I915_MAX_TRANSCODERS
];
597 int palette_offsets
[I915_MAX_PIPES
];
598 int cursor_offsets
[I915_MAX_PIPES
];
604 enum i915_cache_level
{
606 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
607 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
608 caches, eg sampler/render caches, and the
609 large Last-Level-Cache. LLC is coherent with
610 the CPU, but L3 is only visible to the GPU. */
611 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
614 struct i915_ctx_hang_stats
{
615 /* This context had batch pending when hang was declared */
616 unsigned batch_pending
;
618 /* This context had batch active when hang was declared */
619 unsigned batch_active
;
621 /* Time when this context was last blamed for a GPU reset */
622 unsigned long guilty_ts
;
624 /* This context is banned to submit more work */
628 /* This must match up with the value previously used for execbuf2.rsvd1. */
629 #define DEFAULT_CONTEXT_HANDLE 0
631 * struct intel_context - as the name implies, represents a context.
632 * @ref: reference count.
633 * @user_handle: userspace tracking identity for this context.
634 * @remap_slice: l3 row remapping information.
635 * @file_priv: filp associated with this context (NULL for global default
637 * @hang_stats: information about the role of this context in possible GPU
639 * @vm: virtual memory space used by this context.
640 * @legacy_hw_ctx: render context backing object and whether it is correctly
641 * initialized (legacy ring submission mechanism only).
642 * @link: link in the global list of contexts.
644 * Contexts are memory images used by the hardware to store copies of their
647 struct intel_context
{
651 struct drm_i915_file_private
*file_priv
;
652 struct i915_ctx_hang_stats hang_stats
;
653 struct i915_hw_ppgtt
*ppgtt
;
655 /* Legacy ring buffer submission */
657 struct drm_i915_gem_object
*rcs_state
;
662 bool rcs_initialized
;
664 struct drm_i915_gem_object
*state
;
665 struct intel_ringbuffer
*ringbuf
;
666 } engine
[I915_NUM_RINGS
];
668 struct list_head link
;
678 struct drm_mm_node compressed_fb
;
679 struct drm_mm_node
*compressed_llb
;
683 /* Tracks whether the HW is actually enabled, not whether the feature is
687 /* On gen8 some rings cannont perform fbc clean operation so for now
688 * we are doing this on SW with mmio.
689 * This variable works in the opposite information direction
690 * of ring->fbc_dirty telling software on frontbuffer tracking
691 * to perform the cache clean on sw side.
693 bool need_sw_cache_clean
;
695 struct intel_fbc_work
{
696 struct delayed_work work
;
697 struct drm_crtc
*crtc
;
698 struct drm_framebuffer
*fb
;
702 FBC_OK
, /* FBC is enabled */
703 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
704 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
705 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
706 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
707 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
708 FBC_BAD_PLANE
, /* fbc not supported on plane */
709 FBC_NOT_TILED
, /* buffer not tiled */
710 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
712 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
717 struct intel_connector
*connector
;
725 struct intel_dp
*enabled
;
727 struct delayed_work work
;
728 unsigned busy_frontbuffer_bits
;
732 PCH_NONE
= 0, /* No PCH present */
733 PCH_IBX
, /* Ibexpeak PCH */
734 PCH_CPT
, /* Cougarpoint PCH */
735 PCH_LPT
, /* Lynxpoint PCH */
736 PCH_SPT
, /* Sunrisepoint PCH */
740 enum intel_sbi_destination
{
745 #define QUIRK_PIPEA_FORCE (1<<0)
746 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
747 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
748 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
749 #define QUIRK_PIPEB_FORCE (1<<4)
752 struct intel_fbc_work
;
755 struct i2c_adapter adapter
;
759 struct i2c_algo_bit_data bit_algo
;
760 struct drm_i915_private
*dev_priv
;
763 struct i915_suspend_saved_registers
{
784 u32 saveTRANS_HTOTAL_A
;
785 u32 saveTRANS_HBLANK_A
;
786 u32 saveTRANS_HSYNC_A
;
787 u32 saveTRANS_VTOTAL_A
;
788 u32 saveTRANS_VBLANK_A
;
789 u32 saveTRANS_VSYNC_A
;
797 u32 savePFIT_PGM_RATIOS
;
798 u32 saveBLC_HIST_CTL
;
800 u32 saveBLC_PWM_CTL2
;
801 u32 saveBLC_HIST_CTL_B
;
802 u32 saveBLC_CPU_PWM_CTL
;
803 u32 saveBLC_CPU_PWM_CTL2
;
816 u32 saveTRANS_HTOTAL_B
;
817 u32 saveTRANS_HBLANK_B
;
818 u32 saveTRANS_HSYNC_B
;
819 u32 saveTRANS_VTOTAL_B
;
820 u32 saveTRANS_VBLANK_B
;
821 u32 saveTRANS_VSYNC_B
;
835 u32 savePP_ON_DELAYS
;
836 u32 savePP_OFF_DELAYS
;
844 u32 savePFIT_CONTROL
;
845 u32 save_palette_a
[256];
846 u32 save_palette_b
[256];
857 u32 saveCACHE_MODE_0
;
858 u32 saveMI_ARB_STATE
;
869 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
880 u32 savePIPEA_GMCH_DATA_M
;
881 u32 savePIPEB_GMCH_DATA_M
;
882 u32 savePIPEA_GMCH_DATA_N
;
883 u32 savePIPEB_GMCH_DATA_N
;
884 u32 savePIPEA_DP_LINK_M
;
885 u32 savePIPEB_DP_LINK_M
;
886 u32 savePIPEA_DP_LINK_N
;
887 u32 savePIPEB_DP_LINK_N
;
898 u32 savePCH_DREF_CONTROL
;
899 u32 saveDISP_ARB_CTL
;
900 u32 savePIPEA_DATA_M1
;
901 u32 savePIPEA_DATA_N1
;
902 u32 savePIPEA_LINK_M1
;
903 u32 savePIPEA_LINK_N1
;
904 u32 savePIPEB_DATA_M1
;
905 u32 savePIPEB_DATA_N1
;
906 u32 savePIPEB_LINK_M1
;
907 u32 savePIPEB_LINK_N1
;
908 u32 saveMCHBAR_RENDER_STANDBY
;
909 u32 savePCH_PORT_HOTPLUG
;
912 struct vlv_s0ix_state
{
919 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
920 u32 media_max_req_count
;
921 u32 gfx_max_req_count
;
953 /* Display 1 CZ domain */
958 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
960 /* GT SA CZ domain */
967 /* Display 2 CZ domain */
973 struct intel_rps_ei
{
979 struct intel_gen6_power_mgmt
{
980 /* work and pm_iir are protected by dev_priv->irq_lock */
981 struct work_struct work
;
984 /* Frequencies are stored in potentially platform dependent multiples.
985 * In other words, *_freq needs to be multiplied by X to be interesting.
986 * Soft limits are those which are used for the dynamic reclocking done
987 * by the driver (raise frequencies under heavy loads, and lower for
988 * lighter loads). Hard limits are those imposed by the hardware.
990 * A distinction is made for overclocking, which is never enabled by
991 * default, and is considered to be above the hard limit if it's
994 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
995 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
996 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
997 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
998 u8 min_freq
; /* AKA RPn. Minimum frequency */
999 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1000 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1001 u8 rp0_freq
; /* Non-overclocked max frequency. */
1004 u32 ei_interrupt_count
;
1007 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1010 struct delayed_work delayed_resume_work
;
1012 /* manual wa residency calculations */
1013 struct intel_rps_ei up_ei
, down_ei
;
1016 * Protects RPS/RC6 register access and PCU communication.
1017 * Must be taken after struct_mutex if nested.
1019 struct mutex hw_lock
;
1022 /* defined intel_pm.c */
1023 extern spinlock_t mchdev_lock
;
1025 struct intel_ilk_power_mgmt
{
1033 unsigned long last_time1
;
1034 unsigned long chipset_power
;
1037 unsigned long gfx_power
;
1043 struct drm_i915_gem_object
*pwrctx
;
1044 struct drm_i915_gem_object
*renderctx
;
1047 struct drm_i915_private
;
1048 struct i915_power_well
;
1050 struct i915_power_well_ops
{
1052 * Synchronize the well's hw state to match the current sw state, for
1053 * example enable/disable it based on the current refcount. Called
1054 * during driver init and resume time, possibly after first calling
1055 * the enable/disable handlers.
1057 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1058 struct i915_power_well
*power_well
);
1060 * Enable the well and resources that depend on it (for example
1061 * interrupts located on the well). Called after the 0->1 refcount
1064 void (*enable
)(struct drm_i915_private
*dev_priv
,
1065 struct i915_power_well
*power_well
);
1067 * Disable the well and resources that depend on it. Called after
1068 * the 1->0 refcount transition.
1070 void (*disable
)(struct drm_i915_private
*dev_priv
,
1071 struct i915_power_well
*power_well
);
1072 /* Returns the hw enabled state. */
1073 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1074 struct i915_power_well
*power_well
);
1077 /* Power well structure for haswell */
1078 struct i915_power_well
{
1081 /* power well enable/disable usage count */
1083 /* cached hw enabled state */
1085 unsigned long domains
;
1087 const struct i915_power_well_ops
*ops
;
1090 struct i915_power_domains
{
1092 * Power wells needed for initialization at driver init and suspend
1093 * time are on. They are kept on until after the first modeset.
1097 int power_well_count
;
1100 int domain_use_count
[POWER_DOMAIN_NUM
];
1101 struct i915_power_well
*power_wells
;
1104 struct i915_dri1_state
{
1105 unsigned allow_batchbuffer
: 1;
1106 u32 __iomem
*gfx_hws_cpu_addr
;
1117 struct i915_ums_state
{
1119 * Flag if the X Server, and thus DRM, is not currently in
1120 * control of the device.
1122 * This is set between LeaveVT and EnterVT. It needs to be
1123 * replaced with a semaphore. It also needs to be
1124 * transitioned away from for kernel modesetting.
1129 #define MAX_L3_SLICES 2
1130 struct intel_l3_parity
{
1131 u32
*remap_info
[MAX_L3_SLICES
];
1132 struct work_struct error_work
;
1136 struct i915_gem_mm
{
1137 /** Memory allocator for GTT stolen memory */
1138 struct drm_mm stolen
;
1139 /** List of all objects in gtt_space. Used to restore gtt
1140 * mappings on resume */
1141 struct list_head bound_list
;
1143 * List of objects which are not bound to the GTT (thus
1144 * are idle and not used by the GPU) but still have
1145 * (presumably uncached) pages still attached.
1147 struct list_head unbound_list
;
1149 /** Usable portion of the GTT for GEM */
1150 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1152 /** PPGTT used for aliasing the PPGTT with the GTT */
1153 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1155 struct notifier_block oom_notifier
;
1156 struct shrinker shrinker
;
1157 bool shrinker_no_lock_stealing
;
1159 /** LRU list of objects with fence regs on them. */
1160 struct list_head fence_list
;
1163 * We leave the user IRQ off as much as possible,
1164 * but this means that requests will finish and never
1165 * be retired once the system goes idle. Set a timer to
1166 * fire periodically while the ring is running. When it
1167 * fires, go retire requests.
1169 struct delayed_work retire_work
;
1172 * When we detect an idle GPU, we want to turn on
1173 * powersaving features. So once we see that there
1174 * are no more requests outstanding and no more
1175 * arrive within a small period of time, we fire
1176 * off the idle_work.
1178 struct delayed_work idle_work
;
1181 * Are we in a non-interruptible section of code like
1187 * Is the GPU currently considered idle, or busy executing userspace
1188 * requests? Whilst idle, we attempt to power down the hardware and
1189 * display clocks. In order to reduce the effect on performance, there
1190 * is a slight delay before we do so.
1194 /* the indicator for dispatch video commands on two BSD rings */
1195 int bsd_ring_dispatch_index
;
1197 /** Bit 6 swizzling required for X tiling */
1198 uint32_t bit_6_swizzle_x
;
1199 /** Bit 6 swizzling required for Y tiling */
1200 uint32_t bit_6_swizzle_y
;
1202 /* accounting, useful for userland debugging */
1203 spinlock_t object_stat_lock
;
1204 size_t object_memory
;
1208 struct drm_i915_error_state_buf
{
1209 struct drm_i915_private
*i915
;
1218 struct i915_error_state_file_priv
{
1219 struct drm_device
*dev
;
1220 struct drm_i915_error_state
*error
;
1223 struct i915_gpu_error
{
1224 /* For hangcheck timer */
1225 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1226 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1227 /* Hang gpu twice in this window and your context gets banned */
1228 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1230 struct timer_list hangcheck_timer
;
1232 /* For reset and error_state handling. */
1234 /* Protected by the above dev->gpu_error.lock. */
1235 struct drm_i915_error_state
*first_error
;
1236 struct work_struct work
;
1239 unsigned long missed_irq_rings
;
1242 * State variable controlling the reset flow and count
1244 * This is a counter which gets incremented when reset is triggered,
1245 * and again when reset has been handled. So odd values (lowest bit set)
1246 * means that reset is in progress and even values that
1247 * (reset_counter >> 1):th reset was successfully completed.
1249 * If reset is not completed succesfully, the I915_WEDGE bit is
1250 * set meaning that hardware is terminally sour and there is no
1251 * recovery. All waiters on the reset_queue will be woken when
1254 * This counter is used by the wait_seqno code to notice that reset
1255 * event happened and it needs to restart the entire ioctl (since most
1256 * likely the seqno it waited for won't ever signal anytime soon).
1258 * This is important for lock-free wait paths, where no contended lock
1259 * naturally enforces the correct ordering between the bail-out of the
1260 * waiter and the gpu reset work code.
1262 atomic_t reset_counter
;
1264 #define I915_RESET_IN_PROGRESS_FLAG 1
1265 #define I915_WEDGED (1 << 31)
1268 * Waitqueue to signal when the reset has completed. Used by clients
1269 * that wait for dev_priv->mm.wedged to settle.
1271 wait_queue_head_t reset_queue
;
1273 /* Userspace knobs for gpu hang simulation;
1274 * combines both a ring mask, and extra flags
1277 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1278 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1280 /* For missed irq/seqno simulation. */
1281 unsigned int test_irq_rings
;
1283 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1284 bool reload_in_reset
;
1287 enum modeset_restore
{
1288 MODESET_ON_LID_OPEN
,
1293 struct ddi_vbt_port_info
{
1295 * This is an index in the HDMI/DVI DDI buffer translation table.
1296 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1297 * populate this field.
1299 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1300 uint8_t hdmi_level_shift
;
1302 uint8_t supports_dvi
:1;
1303 uint8_t supports_hdmi
:1;
1304 uint8_t supports_dp
:1;
1307 enum drrs_support_type
{
1308 DRRS_NOT_SUPPORTED
= 0,
1309 STATIC_DRRS_SUPPORT
= 1,
1310 SEAMLESS_DRRS_SUPPORT
= 2
1313 struct intel_vbt_data
{
1314 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1315 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1318 unsigned int int_tv_support
:1;
1319 unsigned int lvds_dither
:1;
1320 unsigned int lvds_vbt
:1;
1321 unsigned int int_crt_support
:1;
1322 unsigned int lvds_use_ssc
:1;
1323 unsigned int display_clock_mode
:1;
1324 unsigned int fdi_rx_polarity_inverted
:1;
1325 unsigned int has_mipi
:1;
1327 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1329 enum drrs_support_type drrs_type
;
1334 int edp_preemphasis
;
1336 bool edp_initialized
;
1339 struct edp_power_seq edp_pps
;
1344 bool active_low_pwm
;
1345 u8 min_brightness
; /* min_brightness/255 of max */
1352 struct mipi_config
*config
;
1353 struct mipi_pps_data
*pps
;
1357 u8
*sequence
[MIPI_SEQ_MAX
];
1363 union child_device_config
*child_dev
;
1365 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1368 enum intel_ddb_partitioning
{
1370 INTEL_DDB_PART_5_6
, /* IVB+ */
1373 struct intel_wm_level
{
1381 struct ilk_wm_values
{
1382 uint32_t wm_pipe
[3];
1384 uint32_t wm_lp_spr
[3];
1385 uint32_t wm_linetime
[3];
1387 enum intel_ddb_partitioning partitioning
;
1390 struct skl_ddb_entry
{
1391 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1394 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1396 return entry
->end
- entry
->start
;
1399 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1400 const struct skl_ddb_entry
*e2
)
1402 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1408 struct skl_ddb_allocation
{
1409 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1410 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1411 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1414 struct skl_wm_values
{
1415 bool dirty
[I915_MAX_PIPES
];
1416 struct skl_ddb_allocation ddb
;
1417 uint32_t wm_linetime
[I915_MAX_PIPES
];
1418 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1419 uint32_t cursor
[I915_MAX_PIPES
][8];
1420 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1421 uint32_t cursor_trans
[I915_MAX_PIPES
];
1424 struct skl_wm_level
{
1425 bool plane_en
[I915_MAX_PLANES
];
1427 uint16_t plane_res_b
[I915_MAX_PLANES
];
1428 uint8_t plane_res_l
[I915_MAX_PLANES
];
1429 uint16_t cursor_res_b
;
1430 uint8_t cursor_res_l
;
1434 * This struct helps tracking the state needed for runtime PM, which puts the
1435 * device in PCI D3 state. Notice that when this happens, nothing on the
1436 * graphics device works, even register access, so we don't get interrupts nor
1439 * Every piece of our code that needs to actually touch the hardware needs to
1440 * either call intel_runtime_pm_get or call intel_display_power_get with the
1441 * appropriate power domain.
1443 * Our driver uses the autosuspend delay feature, which means we'll only really
1444 * suspend if we stay with zero refcount for a certain amount of time. The
1445 * default value is currently very conservative (see intel_runtime_pm_enable), but
1446 * it can be changed with the standard runtime PM files from sysfs.
1448 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1449 * goes back to false exactly before we reenable the IRQs. We use this variable
1450 * to check if someone is trying to enable/disable IRQs while they're supposed
1451 * to be disabled. This shouldn't happen and we'll print some error messages in
1454 * For more, read the Documentation/power/runtime_pm.txt.
1456 struct i915_runtime_pm
{
1461 enum intel_pipe_crc_source
{
1462 INTEL_PIPE_CRC_SOURCE_NONE
,
1463 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1464 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1465 INTEL_PIPE_CRC_SOURCE_PF
,
1466 INTEL_PIPE_CRC_SOURCE_PIPE
,
1467 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1468 INTEL_PIPE_CRC_SOURCE_TV
,
1469 INTEL_PIPE_CRC_SOURCE_DP_B
,
1470 INTEL_PIPE_CRC_SOURCE_DP_C
,
1471 INTEL_PIPE_CRC_SOURCE_DP_D
,
1472 INTEL_PIPE_CRC_SOURCE_AUTO
,
1473 INTEL_PIPE_CRC_SOURCE_MAX
,
1476 struct intel_pipe_crc_entry
{
1481 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1482 struct intel_pipe_crc
{
1484 bool opened
; /* exclusive access to the result file */
1485 struct intel_pipe_crc_entry
*entries
;
1486 enum intel_pipe_crc_source source
;
1488 wait_queue_head_t wq
;
1491 struct i915_frontbuffer_tracking
{
1495 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1502 struct i915_wa_reg
{
1505 /* bitmask representing WA bits */
1509 #define I915_MAX_WA_REGS 16
1511 struct i915_workarounds
{
1512 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1516 struct drm_i915_private
{
1517 struct drm_device
*dev
;
1518 struct kmem_cache
*slab
;
1520 const struct intel_device_info info
;
1522 int relative_constants_mode
;
1526 struct intel_uncore uncore
;
1528 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1531 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1532 * controller on different i2c buses. */
1533 struct mutex gmbus_mutex
;
1536 * Base address of the gmbus and gpio block.
1538 uint32_t gpio_mmio_base
;
1540 /* MMIO base address for MIPI regs */
1541 uint32_t mipi_mmio_base
;
1543 wait_queue_head_t gmbus_wait_queue
;
1545 struct pci_dev
*bridge_dev
;
1546 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1547 struct drm_i915_gem_object
*semaphore_obj
;
1548 uint32_t last_seqno
, next_seqno
;
1550 struct drm_dma_handle
*status_page_dmah
;
1551 struct resource mch_res
;
1553 /* protects the irq masks */
1554 spinlock_t irq_lock
;
1556 /* protects the mmio flip data */
1557 spinlock_t mmio_flip_lock
;
1559 bool display_irqs_enabled
;
1561 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1562 struct pm_qos_request pm_qos
;
1564 /* DPIO indirect register protection */
1565 struct mutex dpio_lock
;
1567 /** Cached value of IMR to avoid reads in updating the bitfield */
1570 u32 de_irq_mask
[I915_MAX_PIPES
];
1575 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1577 struct work_struct hotplug_work
;
1579 unsigned long hpd_last_jiffies
;
1584 HPD_MARK_DISABLED
= 2
1586 } hpd_stats
[HPD_NUM_PINS
];
1588 struct delayed_work hotplug_reenable_work
;
1590 struct i915_fbc fbc
;
1591 struct i915_drrs drrs
;
1592 struct intel_opregion opregion
;
1593 struct intel_vbt_data vbt
;
1595 bool preserve_bios_swizzle
;
1598 struct intel_overlay
*overlay
;
1600 /* backlight registers and fields in struct intel_panel */
1601 struct mutex backlight_lock
;
1604 bool no_aux_handshake
;
1606 /* protects panel power sequencer state */
1607 struct mutex pps_mutex
;
1609 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1610 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1611 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1613 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1614 unsigned int vlv_cdclk_freq
;
1617 * wq - Driver workqueue for GEM.
1619 * NOTE: Work items scheduled here are not allowed to grab any modeset
1620 * locks, for otherwise the flushing done in the pageflip code will
1621 * result in deadlocks.
1623 struct workqueue_struct
*wq
;
1625 /* Display functions */
1626 struct drm_i915_display_funcs display
;
1628 /* PCH chipset type */
1629 enum intel_pch pch_type
;
1630 unsigned short pch_id
;
1632 unsigned long quirks
;
1634 enum modeset_restore modeset_restore
;
1635 struct mutex modeset_restore_lock
;
1637 struct list_head vm_list
; /* Global list of all address spaces */
1638 struct i915_gtt gtt
; /* VM representing the global address space */
1640 struct i915_gem_mm mm
;
1641 DECLARE_HASHTABLE(mm_structs
, 7);
1642 struct mutex mm_lock
;
1644 /* Kernel Modesetting */
1646 struct sdvo_device_mapping sdvo_mappings
[2];
1648 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1649 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1650 wait_queue_head_t pending_flip_queue
;
1652 #ifdef CONFIG_DEBUG_FS
1653 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1656 int num_shared_dpll
;
1657 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1658 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1660 struct i915_workarounds workarounds
;
1662 /* Reclocking support */
1663 bool render_reclock_avail
;
1664 bool lvds_downclock_avail
;
1665 /* indicates the reduced downclock for LVDS*/
1668 struct i915_frontbuffer_tracking fb_tracking
;
1672 bool mchbar_need_disable
;
1674 struct intel_l3_parity l3_parity
;
1676 /* Cannot be determined by PCIID. You must always read a register. */
1679 /* gen6+ rps state */
1680 struct intel_gen6_power_mgmt rps
;
1682 /* ilk-only ips/rps state. Everything in here is protected by the global
1683 * mchdev_lock in intel_pm.c */
1684 struct intel_ilk_power_mgmt ips
;
1686 struct i915_power_domains power_domains
;
1688 struct i915_psr psr
;
1690 struct i915_gpu_error gpu_error
;
1692 struct drm_i915_gem_object
*vlv_pctx
;
1694 #ifdef CONFIG_DRM_I915_FBDEV
1695 /* list of fbdev register on this device */
1696 struct intel_fbdev
*fbdev
;
1697 struct work_struct fbdev_suspend_work
;
1700 struct drm_property
*broadcast_rgb_property
;
1701 struct drm_property
*force_audio_property
;
1703 uint32_t hw_context_size
;
1704 struct list_head context_list
;
1709 struct i915_suspend_saved_registers regfile
;
1710 struct vlv_s0ix_state vlv_s0ix_state
;
1714 * Raw watermark latency values:
1715 * in 0.1us units for WM0,
1716 * in 0.5us units for WM1+.
1719 uint16_t pri_latency
[5];
1721 uint16_t spr_latency
[5];
1723 uint16_t cur_latency
[5];
1725 * Raw watermark memory latency values
1726 * for SKL for all 8 levels
1729 uint16_t skl_latency
[8];
1732 * The skl_wm_values structure is a bit too big for stack
1733 * allocation, so we keep the staging struct where we store
1734 * intermediate results here instead.
1736 struct skl_wm_values skl_results
;
1738 /* current hardware state */
1740 struct ilk_wm_values hw
;
1741 struct skl_wm_values skl_hw
;
1745 struct i915_runtime_pm pm
;
1747 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1748 u32 long_hpd_port_mask
;
1749 u32 short_hpd_port_mask
;
1750 struct work_struct dig_port_work
;
1753 * if we get a HPD irq from DP and a HPD irq from non-DP
1754 * the non-DP HPD could block the workqueue on a mode config
1755 * mutex getting, that userspace may have taken. However
1756 * userspace is waiting on the DP workqueue to run which is
1757 * blocked behind the non-DP one.
1759 struct workqueue_struct
*dp_wq
;
1761 uint32_t bios_vgacntr
;
1763 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1765 struct i915_dri1_state dri1
;
1766 /* Old ums support infrastructure, same warning applies. */
1767 struct i915_ums_state ums
;
1769 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1771 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1772 struct intel_engine_cs
*ring
,
1773 struct intel_context
*ctx
,
1774 struct drm_i915_gem_execbuffer2
*args
,
1775 struct list_head
*vmas
,
1776 struct drm_i915_gem_object
*batch_obj
,
1777 u64 exec_start
, u32 flags
);
1778 int (*init_rings
)(struct drm_device
*dev
);
1779 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1780 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1784 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1785 * will be rejected. Instead look for a better place.
1789 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1791 return dev
->dev_private
;
1794 /* Iterate over initialised rings */
1795 #define for_each_ring(ring__, dev_priv__, i__) \
1796 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1797 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1799 enum hdmi_force_audio
{
1800 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1801 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1802 HDMI_AUDIO_AUTO
, /* trust EDID */
1803 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1806 #define I915_GTT_OFFSET_NONE ((u32)-1)
1808 struct drm_i915_gem_object_ops
{
1809 /* Interface between the GEM object and its backing storage.
1810 * get_pages() is called once prior to the use of the associated set
1811 * of pages before to binding them into the GTT, and put_pages() is
1812 * called after we no longer need them. As we expect there to be
1813 * associated cost with migrating pages between the backing storage
1814 * and making them available for the GPU (e.g. clflush), we may hold
1815 * onto the pages after they are no longer referenced by the GPU
1816 * in case they may be used again shortly (for example migrating the
1817 * pages to a different memory domain within the GTT). put_pages()
1818 * will therefore most likely be called when the object itself is
1819 * being released or under memory pressure (where we attempt to
1820 * reap pages for the shrinker).
1822 int (*get_pages
)(struct drm_i915_gem_object
*);
1823 void (*put_pages
)(struct drm_i915_gem_object
*);
1824 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1825 void (*release
)(struct drm_i915_gem_object
*);
1829 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1830 * considered to be the frontbuffer for the given plane interface-vise. This
1831 * doesn't mean that the hw necessarily already scans it out, but that any
1832 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1834 * We have one bit per pipe and per scanout plane type.
1836 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1837 #define INTEL_FRONTBUFFER_BITS \
1838 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1839 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1840 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1841 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1842 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1843 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1844 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1845 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1846 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1847 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1848 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1850 struct drm_i915_gem_object
{
1851 struct drm_gem_object base
;
1853 const struct drm_i915_gem_object_ops
*ops
;
1855 /** List of VMAs backed by this object */
1856 struct list_head vma_list
;
1858 /** Stolen memory for this object, instead of being backed by shmem. */
1859 struct drm_mm_node
*stolen
;
1860 struct list_head global_list
;
1862 struct list_head ring_list
;
1863 /** Used in execbuf to temporarily hold a ref */
1864 struct list_head obj_exec_link
;
1867 * This is set if the object is on the active lists (has pending
1868 * rendering and so a non-zero seqno), and is not set if it i s on
1869 * inactive (ready to be unbound) list.
1871 unsigned int active
:1;
1874 * This is set if the object has been written to since last bound
1877 unsigned int dirty
:1;
1880 * Fence register bits (if any) for this object. Will be set
1881 * as needed when mapped into the GTT.
1882 * Protected by dev->struct_mutex.
1884 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1887 * Advice: are the backing pages purgeable?
1889 unsigned int madv
:2;
1892 * Current tiling mode for the object.
1894 unsigned int tiling_mode
:2;
1896 * Whether the tiling parameters for the currently associated fence
1897 * register have changed. Note that for the purposes of tracking
1898 * tiling changes we also treat the unfenced register, the register
1899 * slot that the object occupies whilst it executes a fenced
1900 * command (such as BLT on gen2/3), as a "fence".
1902 unsigned int fence_dirty
:1;
1905 * Is the object at the current location in the gtt mappable and
1906 * fenceable? Used to avoid costly recalculations.
1908 unsigned int map_and_fenceable
:1;
1911 * Whether the current gtt mapping needs to be mappable (and isn't just
1912 * mappable by accident). Track pin and fault separate for a more
1913 * accurate mappable working set.
1915 unsigned int fault_mappable
:1;
1916 unsigned int pin_mappable
:1;
1917 unsigned int pin_display
:1;
1920 * Is the object to be mapped as read-only to the GPU
1921 * Only honoured if hardware has relevant pte bit
1923 unsigned long gt_ro
:1;
1924 unsigned int cache_level
:3;
1926 unsigned int has_dma_mapping
:1;
1928 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1930 struct sg_table
*pages
;
1931 int pages_pin_count
;
1933 /* prime dma-buf support */
1934 void *dma_buf_vmapping
;
1937 struct intel_engine_cs
*ring
;
1939 /** Breadcrumb of last rendering to the buffer. */
1940 uint32_t last_read_seqno
;
1941 uint32_t last_write_seqno
;
1942 /** Breadcrumb of last fenced GPU access to the buffer. */
1943 uint32_t last_fenced_seqno
;
1945 /** Current tiling stride for the object, if it's tiled. */
1948 /** References from framebuffers, locks out tiling changes. */
1949 unsigned long framebuffer_references
;
1951 /** Record of address bit 17 of each page at last unbind. */
1952 unsigned long *bit_17
;
1954 /** User space pin count and filp owning the pin */
1955 unsigned long user_pin_count
;
1956 struct drm_file
*pin_filp
;
1958 /** for phy allocated objects */
1959 struct drm_dma_handle
*phys_handle
;
1962 struct i915_gem_userptr
{
1964 unsigned read_only
:1;
1965 unsigned workers
:4;
1966 #define I915_GEM_USERPTR_MAX_WORKERS 15
1968 struct i915_mm_struct
*mm
;
1969 struct i915_mmu_object
*mmu_object
;
1970 struct work_struct
*work
;
1974 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1976 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1977 struct drm_i915_gem_object
*new,
1978 unsigned frontbuffer_bits
);
1981 * Request queue structure.
1983 * The request queue allows us to note sequence numbers that have been emitted
1984 * and may be associated with active buffers to be retired.
1986 * By keeping this list, we can avoid having to do questionable
1987 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1988 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1990 struct drm_i915_gem_request
{
1991 /** On Which ring this request was generated */
1992 struct intel_engine_cs
*ring
;
1994 /** GEM sequence number associated with this request. */
1997 /** Position in the ringbuffer of the start of the request */
2000 /** Position in the ringbuffer of the end of the request */
2003 /** Context related to this request */
2004 struct intel_context
*ctx
;
2006 /** Batch buffer related to this request if any */
2007 struct drm_i915_gem_object
*batch_obj
;
2009 /** Time at which this request was emitted, in jiffies. */
2010 unsigned long emitted_jiffies
;
2012 /** global list entry for this request */
2013 struct list_head list
;
2015 struct drm_i915_file_private
*file_priv
;
2016 /** file_priv list entry for this request */
2017 struct list_head client_list
;
2020 struct drm_i915_file_private
{
2021 struct drm_i915_private
*dev_priv
;
2022 struct drm_file
*file
;
2026 struct list_head request_list
;
2027 struct delayed_work idle_work
;
2029 struct idr context_idr
;
2031 atomic_t rps_wait_boost
;
2032 struct intel_engine_cs
*bsd_ring
;
2036 * A command that requires special handling by the command parser.
2038 struct drm_i915_cmd_descriptor
{
2040 * Flags describing how the command parser processes the command.
2042 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2043 * a length mask if not set
2044 * CMD_DESC_SKIP: The command is allowed but does not follow the
2045 * standard length encoding for the opcode range in
2047 * CMD_DESC_REJECT: The command is never allowed
2048 * CMD_DESC_REGISTER: The command should be checked against the
2049 * register whitelist for the appropriate ring
2050 * CMD_DESC_MASTER: The command is allowed if the submitting process
2054 #define CMD_DESC_FIXED (1<<0)
2055 #define CMD_DESC_SKIP (1<<1)
2056 #define CMD_DESC_REJECT (1<<2)
2057 #define CMD_DESC_REGISTER (1<<3)
2058 #define CMD_DESC_BITMASK (1<<4)
2059 #define CMD_DESC_MASTER (1<<5)
2062 * The command's unique identification bits and the bitmask to get them.
2063 * This isn't strictly the opcode field as defined in the spec and may
2064 * also include type, subtype, and/or subop fields.
2072 * The command's length. The command is either fixed length (i.e. does
2073 * not include a length field) or has a length field mask. The flag
2074 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2075 * a length mask. All command entries in a command table must include
2076 * length information.
2084 * Describes where to find a register address in the command to check
2085 * against the ring's register whitelist. Only valid if flags has the
2086 * CMD_DESC_REGISTER bit set.
2093 #define MAX_CMD_DESC_BITMASKS 3
2095 * Describes command checks where a particular dword is masked and
2096 * compared against an expected value. If the command does not match
2097 * the expected value, the parser rejects it. Only valid if flags has
2098 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2101 * If the check specifies a non-zero condition_mask then the parser
2102 * only performs the check when the bits specified by condition_mask
2109 u32 condition_offset
;
2111 } bits
[MAX_CMD_DESC_BITMASKS
];
2115 * A table of commands requiring special handling by the command parser.
2117 * Each ring has an array of tables. Each table consists of an array of command
2118 * descriptors, which must be sorted with command opcodes in ascending order.
2120 struct drm_i915_cmd_table
{
2121 const struct drm_i915_cmd_descriptor
*table
;
2125 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2126 #define __I915__(p) ({ \
2127 struct drm_i915_private *__p; \
2128 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2129 __p = (struct drm_i915_private *)p; \
2130 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2131 __p = to_i915((struct drm_device *)p); \
2136 #define INTEL_INFO(p) (&__I915__(p)->info)
2137 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2139 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2140 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2141 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2142 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2143 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2144 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2145 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2146 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2147 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2148 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2149 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2150 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2151 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2152 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2153 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2154 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2155 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2156 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2157 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2158 INTEL_DEVID(dev) == 0x0152 || \
2159 INTEL_DEVID(dev) == 0x015a)
2160 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2161 INTEL_DEVID(dev) == 0x0106 || \
2162 INTEL_DEVID(dev) == 0x010A)
2163 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2164 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2165 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2166 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2167 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2168 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2169 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2170 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2171 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2172 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2173 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2174 (INTEL_DEVID(dev) & 0xf) == 0xe))
2175 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2176 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2177 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2178 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2179 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2180 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2181 /* ULX machines are also considered ULT. */
2182 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2183 INTEL_DEVID(dev) == 0x0A1E)
2184 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2187 * The genX designation typically refers to the render engine, so render
2188 * capability related checks should use IS_GEN, while display and other checks
2189 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2192 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2193 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2194 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2195 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2196 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2197 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2198 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2199 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2201 #define RENDER_RING (1<<RCS)
2202 #define BSD_RING (1<<VCS)
2203 #define BLT_RING (1<<BCS)
2204 #define VEBOX_RING (1<<VECS)
2205 #define BSD2_RING (1<<VCS2)
2206 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2207 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2208 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2209 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2210 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2211 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2212 __I915__(dev)->ellc_size)
2213 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2215 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2216 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2217 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2218 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2220 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2221 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2223 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2224 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2226 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2227 * even when in MSI mode. This results in spurious interrupt warnings if the
2228 * legacy irq no. is shared with another device. The kernel then disables that
2229 * interrupt source and so prevents the other device from working properly.
2231 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2232 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2234 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2235 * rows, which changed the alignment requirements and fence programming.
2237 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2239 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2240 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2241 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2242 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2243 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2245 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2246 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2247 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2249 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2251 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2252 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2253 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2254 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2255 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2256 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2257 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2259 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2260 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2261 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2262 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2263 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2264 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2265 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2266 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2268 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2269 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2270 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2271 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2272 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2273 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2274 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2276 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2278 /* DPF == dynamic parity feature */
2279 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2280 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2282 #define GT_FREQUENCY_MULTIPLIER 50
2284 #include "i915_trace.h"
2286 extern const struct drm_ioctl_desc i915_ioctls
[];
2287 extern int i915_max_ioctl
;
2289 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2290 extern int i915_resume_legacy(struct drm_device
*dev
);
2291 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2292 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2295 struct i915_params
{
2297 int panel_ignore_lid
;
2298 unsigned int powersave
;
2300 unsigned int lvds_downclock
;
2301 int lvds_channel_mode
;
2303 int vbt_sdvo_panel_type
;
2307 int enable_execlists
;
2309 unsigned int preliminary_hw_support
;
2310 int disable_power_well
;
2312 int invert_brightness
;
2313 int enable_cmd_parser
;
2314 /* leave bools at the end to not create holes */
2315 bool enable_hangcheck
;
2317 bool prefault_disable
;
2319 bool disable_display
;
2320 bool disable_vtd_wa
;
2324 extern struct i915_params i915 __read_mostly
;
2327 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2328 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2329 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2330 extern int i915_driver_unload(struct drm_device
*);
2331 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2332 extern void i915_driver_lastclose(struct drm_device
* dev
);
2333 extern void i915_driver_preclose(struct drm_device
*dev
,
2334 struct drm_file
*file
);
2335 extern void i915_driver_postclose(struct drm_device
*dev
,
2336 struct drm_file
*file
);
2337 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2338 #ifdef CONFIG_COMPAT
2339 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2342 extern int i915_emit_box(struct drm_device
*dev
,
2343 struct drm_clip_rect
*box
,
2345 extern int intel_gpu_reset(struct drm_device
*dev
);
2346 extern int i915_reset(struct drm_device
*dev
);
2347 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2348 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2349 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2350 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2351 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2352 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2355 void i915_queue_hangcheck(struct drm_device
*dev
);
2357 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2358 const char *fmt
, ...);
2360 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2361 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2362 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2363 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2365 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2366 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2367 bool restore_forcewake
);
2368 extern void intel_uncore_init(struct drm_device
*dev
);
2369 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2370 extern void intel_uncore_fini(struct drm_device
*dev
);
2371 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2374 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2378 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2381 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2382 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2384 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2386 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2387 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2388 uint32_t interrupt_mask
,
2389 uint32_t enabled_irq_mask
);
2390 #define ibx_enable_display_interrupt(dev_priv, bits) \
2391 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2392 #define ibx_disable_display_interrupt(dev_priv, bits) \
2393 ibx_display_interrupt_update((dev_priv), (bits), 0)
2396 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2397 struct drm_file
*file_priv
);
2398 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2399 struct drm_file
*file_priv
);
2400 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2401 struct drm_file
*file_priv
);
2402 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2403 struct drm_file
*file_priv
);
2404 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2405 struct drm_file
*file_priv
);
2406 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2407 struct drm_file
*file_priv
);
2408 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2409 struct drm_file
*file_priv
);
2410 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2411 struct drm_file
*file_priv
);
2412 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2413 struct intel_engine_cs
*ring
);
2414 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2415 struct drm_file
*file
,
2416 struct intel_engine_cs
*ring
,
2417 struct drm_i915_gem_object
*obj
);
2418 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2419 struct drm_file
*file
,
2420 struct intel_engine_cs
*ring
,
2421 struct intel_context
*ctx
,
2422 struct drm_i915_gem_execbuffer2
*args
,
2423 struct list_head
*vmas
,
2424 struct drm_i915_gem_object
*batch_obj
,
2425 u64 exec_start
, u32 flags
);
2426 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2427 struct drm_file
*file_priv
);
2428 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2429 struct drm_file
*file_priv
);
2430 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2431 struct drm_file
*file_priv
);
2432 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2433 struct drm_file
*file_priv
);
2434 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2435 struct drm_file
*file_priv
);
2436 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2437 struct drm_file
*file
);
2438 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2439 struct drm_file
*file
);
2440 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2441 struct drm_file
*file_priv
);
2442 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2443 struct drm_file
*file_priv
);
2444 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2445 struct drm_file
*file_priv
);
2446 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2447 struct drm_file
*file_priv
);
2448 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2449 struct drm_file
*file_priv
);
2450 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2451 struct drm_file
*file_priv
);
2452 int i915_gem_init_userptr(struct drm_device
*dev
);
2453 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2454 struct drm_file
*file
);
2455 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2456 struct drm_file
*file_priv
);
2457 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2458 struct drm_file
*file_priv
);
2459 void i915_gem_load(struct drm_device
*dev
);
2460 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2463 #define I915_SHRINK_PURGEABLE 0x1
2464 #define I915_SHRINK_UNBOUND 0x2
2465 #define I915_SHRINK_BOUND 0x4
2466 void *i915_gem_object_alloc(struct drm_device
*dev
);
2467 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2468 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2469 const struct drm_i915_gem_object_ops
*ops
);
2470 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2472 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2473 struct i915_address_space
*vm
);
2474 void i915_gem_free_object(struct drm_gem_object
*obj
);
2475 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2477 #define PIN_MAPPABLE 0x1
2478 #define PIN_NONBLOCK 0x2
2479 #define PIN_GLOBAL 0x4
2480 #define PIN_OFFSET_BIAS 0x8
2481 #define PIN_OFFSET_MASK (~4095)
2482 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2483 struct i915_address_space
*vm
,
2486 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2487 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2488 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2489 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2490 void i915_gem_lastclose(struct drm_device
*dev
);
2492 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2493 int *needs_clflush
);
2495 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2496 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2498 struct sg_page_iter sg_iter
;
2500 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2501 return sg_page_iter_page(&sg_iter
);
2505 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2507 BUG_ON(obj
->pages
== NULL
);
2508 obj
->pages_pin_count
++;
2510 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2512 BUG_ON(obj
->pages_pin_count
== 0);
2513 obj
->pages_pin_count
--;
2516 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2517 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2518 struct intel_engine_cs
*to
);
2519 void i915_vma_move_to_active(struct i915_vma
*vma
,
2520 struct intel_engine_cs
*ring
);
2521 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2522 struct drm_device
*dev
,
2523 struct drm_mode_create_dumb
*args
);
2524 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2525 uint32_t handle
, uint64_t *offset
);
2527 * Returns true if seq1 is later than seq2.
2530 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2532 return (int32_t)(seq1
- seq2
) >= 0;
2535 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2536 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2537 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2538 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2540 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2541 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2543 struct drm_i915_gem_request
*
2544 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2546 bool i915_gem_retire_requests(struct drm_device
*dev
);
2547 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2548 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2549 bool interruptible
);
2550 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2552 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2554 return unlikely(atomic_read(&error
->reset_counter
)
2555 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2558 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2560 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2563 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2565 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2568 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2570 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2571 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2574 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2576 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2577 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2580 void i915_gem_reset(struct drm_device
*dev
);
2581 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2582 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2583 int __must_check
i915_gem_init(struct drm_device
*dev
);
2584 int i915_gem_init_rings(struct drm_device
*dev
);
2585 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2586 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2587 void i915_gem_init_swizzling(struct drm_device
*dev
);
2588 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2589 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2590 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2591 int __i915_add_request(struct intel_engine_cs
*ring
,
2592 struct drm_file
*file
,
2593 struct drm_i915_gem_object
*batch_obj
,
2595 #define i915_add_request(ring, seqno) \
2596 __i915_add_request(ring, NULL, NULL, seqno)
2597 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2599 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2601 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2604 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2606 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2608 struct intel_engine_cs
*pipelined
);
2609 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2610 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2612 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2613 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2616 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2618 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2619 int tiling_mode
, bool fenced
);
2621 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2622 enum i915_cache_level cache_level
);
2624 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2625 struct dma_buf
*dma_buf
);
2627 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2628 struct drm_gem_object
*gem_obj
, int flags
);
2630 void i915_gem_restore_fences(struct drm_device
*dev
);
2632 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2633 struct i915_address_space
*vm
);
2634 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2635 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2636 struct i915_address_space
*vm
);
2637 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2638 struct i915_address_space
*vm
);
2639 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2640 struct i915_address_space
*vm
);
2642 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2643 struct i915_address_space
*vm
);
2645 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2646 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2647 struct i915_vma
*vma
;
2648 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2649 if (vma
->pin_count
> 0)
2654 /* Some GGTT VM helpers */
2655 #define i915_obj_to_ggtt(obj) \
2656 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2657 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2659 struct i915_address_space
*ggtt
=
2660 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2664 static inline struct i915_hw_ppgtt
*
2665 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2667 WARN_ON(i915_is_ggtt(vm
));
2669 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2673 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2675 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2678 static inline unsigned long
2679 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2681 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2684 static inline unsigned long
2685 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2687 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2690 static inline int __must_check
2691 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2695 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2696 alignment
, flags
| PIN_GLOBAL
);
2700 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2702 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2705 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2707 /* i915_gem_context.c */
2708 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2709 void i915_gem_context_fini(struct drm_device
*dev
);
2710 void i915_gem_context_reset(struct drm_device
*dev
);
2711 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2712 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2713 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2714 int i915_switch_context(struct intel_engine_cs
*ring
,
2715 struct intel_context
*to
);
2716 struct intel_context
*
2717 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2718 void i915_gem_context_free(struct kref
*ctx_ref
);
2719 struct drm_i915_gem_object
*
2720 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2721 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2723 kref_get(&ctx
->ref
);
2726 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2728 kref_put(&ctx
->ref
, i915_gem_context_free
);
2731 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2733 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2736 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2737 struct drm_file
*file
);
2738 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2739 struct drm_file
*file
);
2741 /* i915_gem_evict.c */
2742 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2743 struct i915_address_space
*vm
,
2746 unsigned cache_level
,
2747 unsigned long start
,
2750 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2751 int i915_gem_evict_everything(struct drm_device
*dev
);
2753 /* belongs in i915_gem_gtt.h */
2754 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2756 if (INTEL_INFO(dev
)->gen
< 6)
2757 intel_gtt_chipset_flush();
2760 /* i915_gem_stolen.c */
2761 int i915_gem_init_stolen(struct drm_device
*dev
);
2762 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2763 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2764 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2765 struct drm_i915_gem_object
*
2766 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2767 struct drm_i915_gem_object
*
2768 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2773 /* i915_gem_tiling.c */
2774 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2776 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2778 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2779 obj
->tiling_mode
!= I915_TILING_NONE
;
2782 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2783 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2784 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2786 /* i915_gem_debug.c */
2788 int i915_verify_lists(struct drm_device
*dev
);
2790 #define i915_verify_lists(dev) 0
2793 /* i915_debugfs.c */
2794 int i915_debugfs_init(struct drm_minor
*minor
);
2795 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2796 #ifdef CONFIG_DEBUG_FS
2797 void intel_display_crc_init(struct drm_device
*dev
);
2799 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2802 /* i915_gpu_error.c */
2804 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2805 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2806 const struct i915_error_state_file_priv
*error
);
2807 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2808 struct drm_i915_private
*i915
,
2809 size_t count
, loff_t pos
);
2810 static inline void i915_error_state_buf_release(
2811 struct drm_i915_error_state_buf
*eb
)
2815 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2816 const char *error_msg
);
2817 void i915_error_state_get(struct drm_device
*dev
,
2818 struct i915_error_state_file_priv
*error_priv
);
2819 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2820 void i915_destroy_error_state(struct drm_device
*dev
);
2822 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2823 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
2825 /* i915_cmd_parser.c */
2826 int i915_cmd_parser_get_version(void);
2827 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2828 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2829 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2830 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2831 struct drm_i915_gem_object
*batch_obj
,
2832 u32 batch_start_offset
,
2835 /* i915_suspend.c */
2836 extern int i915_save_state(struct drm_device
*dev
);
2837 extern int i915_restore_state(struct drm_device
*dev
);
2840 void i915_save_display_reg(struct drm_device
*dev
);
2841 void i915_restore_display_reg(struct drm_device
*dev
);
2844 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2845 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2848 extern int intel_setup_gmbus(struct drm_device
*dev
);
2849 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2850 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2852 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2855 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2856 struct drm_i915_private
*dev_priv
, unsigned port
);
2857 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2858 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2859 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2861 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2863 extern void intel_i2c_reset(struct drm_device
*dev
);
2865 /* intel_opregion.c */
2867 extern int intel_opregion_setup(struct drm_device
*dev
);
2868 extern void intel_opregion_init(struct drm_device
*dev
);
2869 extern void intel_opregion_fini(struct drm_device
*dev
);
2870 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2871 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2873 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2876 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2877 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2878 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2879 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2881 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2886 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2894 extern void intel_register_dsm_handler(void);
2895 extern void intel_unregister_dsm_handler(void);
2897 static inline void intel_register_dsm_handler(void) { return; }
2898 static inline void intel_unregister_dsm_handler(void) { return; }
2899 #endif /* CONFIG_ACPI */
2902 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2903 extern void intel_modeset_init(struct drm_device
*dev
);
2904 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2905 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2906 extern void intel_connector_unregister(struct intel_connector
*);
2907 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2908 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2909 bool force_restore
);
2910 extern void i915_redisable_vga(struct drm_device
*dev
);
2911 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2912 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2913 extern void bdw_fbc_sw_flush(struct drm_device
*dev
, u32 value
);
2914 extern void intel_disable_fbc(struct drm_device
*dev
);
2915 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2916 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2917 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2918 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2919 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2921 extern void intel_detect_pch(struct drm_device
*dev
);
2922 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2923 extern int intel_enable_rc6(const struct drm_device
*dev
);
2925 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2926 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2927 struct drm_file
*file
);
2928 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2929 struct drm_file
*file
);
2931 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2934 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2935 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2936 struct intel_overlay_error_state
*error
);
2938 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2939 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2940 struct drm_device
*dev
,
2941 struct intel_display_error_state
*error
);
2943 /* On SNB platform, before reading ring registers forcewake bit
2944 * must be set to prevent GT core from power down and stale values being
2947 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2948 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2949 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2951 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2952 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2954 /* intel_sideband.c */
2955 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2956 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2957 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2958 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2959 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2960 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2961 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2962 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2963 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2964 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2965 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2966 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2967 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2968 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2969 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2970 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2971 enum intel_sbi_destination destination
);
2972 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2973 enum intel_sbi_destination destination
);
2974 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2975 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2977 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2978 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2980 #define FORCEWAKE_RENDER (1 << 0)
2981 #define FORCEWAKE_MEDIA (1 << 1)
2982 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2985 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2986 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2988 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2989 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2990 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2991 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2993 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2994 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2995 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2996 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2998 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2999 * will be implemented using 2 32-bit writes in an arbitrary order with
3000 * an arbitrary delay between them. This can cause the hardware to
3001 * act upon the intermediate value, possibly leading to corruption and
3002 * machine death. You have been warned.
3004 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3005 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3007 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3008 u32 upper = I915_READ(upper_reg); \
3009 u32 lower = I915_READ(lower_reg); \
3010 u32 tmp = I915_READ(upper_reg); \
3011 if (upper != tmp) { \
3013 lower = I915_READ(lower_reg); \
3014 WARN_ON(I915_READ(upper_reg) != upper); \
3016 (u64)upper << 32 | lower; })
3018 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3019 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3021 /* "Broadcast RGB" property */
3022 #define INTEL_BROADCAST_RGB_AUTO 0
3023 #define INTEL_BROADCAST_RGB_FULL 1
3024 #define INTEL_BROADCAST_RGB_LIMITED 2
3026 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3028 if (IS_VALLEYVIEW(dev
))
3029 return VLV_VGACNTRL
;
3030 else if (INTEL_INFO(dev
)->gen
>= 5)
3031 return CPU_VGACNTRL
;
3036 static inline void __user
*to_user_ptr(u64 address
)
3038 return (void __user
*)(uintptr_t)address
;
3041 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3043 unsigned long j
= msecs_to_jiffies(m
);
3045 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3048 static inline unsigned long
3049 timespec_to_jiffies_timeout(const struct timespec
*value
)
3051 unsigned long j
= timespec_to_jiffies(value
);
3053 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3057 * If you need to wait X milliseconds between events A and B, but event B
3058 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3059 * when event A happened, then just before event B you call this function and
3060 * pass the timestamp as the first argument, and X as the second argument.
3063 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3065 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3068 * Don't re-read the value of "jiffies" every time since it may change
3069 * behind our back and break the math.
3071 tmp_jiffies
= jiffies
;
3072 target_jiffies
= timestamp_jiffies
+
3073 msecs_to_jiffies_timeout(to_wait_ms
);
3075 if (time_after(target_jiffies
, tmp_jiffies
)) {
3076 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3077 while (remaining_jiffies
)
3079 schedule_timeout_uninterruptible(remaining_jiffies
);