drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <drm/intel-gtt.h>
  39
  40 /* General customization:
  41  */
  42
  43 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  44
  45 #define DRIVER_NAME             "i915"
  46 #define DRIVER_DESC             "Intel Graphics"
  47 #define DRIVER_DATE             "20080730"
  48
  49 enum pipe {
  50         PIPE_A = 0,
  51         PIPE_B,
  52         PIPE_C,
  53         I915_MAX_PIPES
  54 };
  55 #define pipe_name(p) ((p) + 'A')
  56
  57 enum plane {
  58         PLANE_A = 0,
  59         PLANE_B,
  60         PLANE_C,
  61 };
  62 #define plane_name(p) ((p) + 'A')
  63
  64 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  65
  66 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  67
  68 /* Interface history:
  69  *
  70  * 1.1: Original.
  71  * 1.2: Add Power Management
  72  * 1.3: Add vblank support
  73  * 1.4: Fix cmdbuffer path, add heap destroy
  74  * 1.5: Add vblank pipe configuration
  75  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  76  *      - Support vertical blank on secondary display pipe
  77  */
  78 #define DRIVER_MAJOR            1
  79 #define DRIVER_MINOR            6
  80 #define DRIVER_PATCHLEVEL       0
  81
  82 #define WATCH_COHERENCY 0
  83 #define WATCH_LISTS     0
  84
  85 #define I915_GEM_PHYS_CURSOR_0 1
  86 #define I915_GEM_PHYS_CURSOR_1 2
  87 #define I915_GEM_PHYS_OVERLAY_REGS 3
  88 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  89
  90 struct drm_i915_gem_phys_object {
  91         int id;
  92         struct page **page_list;
  93         drm_dma_handle_t *handle;
  94         struct drm_i915_gem_object *cur_obj;
  95 };
  96
  97 struct mem_block {
  98         struct mem_block *next;
  99         struct mem_block *prev;
 100         int start;
 101         int size;
 102         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 103 };
 104
 105 struct opregion_header;
 106 struct opregion_acpi;
 107 struct opregion_swsci;
 108 struct opregion_asle;
 109
 110 struct intel_opregion {
 111         struct opregion_header *header;
 112         struct opregion_acpi *acpi;
 113         struct opregion_swsci *swsci;
 114         struct opregion_asle *asle;
 115         void *vbt;
 116         u32 __iomem *lid_state;
 117 };
 118 #define OPREGION_SIZE            (8*1024)
 119
 120 struct intel_overlay;
 121 struct intel_overlay_error_state;
 122
 123 struct drm_i915_master_private {
 124         drm_local_map_t *sarea;
 125         struct _drm_i915_sarea *sarea_priv;
 126 };
 127 #define I915_FENCE_REG_NONE -1
 128
 129 struct drm_i915_fence_reg {
 130         struct list_head lru_list;
 131         struct drm_i915_gem_object *obj;
 132         uint32_t setup_seqno;
 133 };
 134
 135 struct sdvo_device_mapping {
 136         u8 initialized;
 137         u8 dvo_port;
 138         u8 slave_addr;
 139         u8 dvo_wiring;
 140         u8 i2c_pin;
 141         u8 i2c_speed;
 142         u8 ddc_pin;
 143 };
 144
 145 struct intel_display_error_state;
 146
 147 struct drm_i915_error_state {
 148         u32 eir;
 149         u32 pgtbl_er;
 150         u32 pipestat[I915_MAX_PIPES];
 151         u32 ipeir;
 152         u32 ipehr;
 153         u32 instdone;
 154         u32 acthd;
 155         u32 error; /* gen6+ */
 156         u32 bcs_acthd; /* gen6+ blt engine */
 157         u32 bcs_ipehr;
 158         u32 bcs_ipeir;
 159         u32 bcs_instdone;
 160         u32 bcs_seqno;
 161         u32 vcs_acthd; /* gen6+ bsd engine */
 162         u32 vcs_ipehr;
 163         u32 vcs_ipeir;
 164         u32 vcs_instdone;
 165         u32 vcs_seqno;
 166         u32 instpm;
 167         u32 instps;
 168         u32 instdone1;
 169         u32 seqno;
 170         u64 bbaddr;
 171         u64 fence[16];
 172         struct timeval time;
 173         struct drm_i915_error_object {
 174                 int page_count;
 175                 u32 gtt_offset;
 176                 u32 *pages[0];
 177         } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
 178         struct drm_i915_error_buffer {
 179                 u32 size;
 180                 u32 name;
 181                 u32 seqno;
 182                 u32 gtt_offset;
 183                 u32 read_domains;
 184                 u32 write_domain;
 185                 s32 fence_reg:5;
 186                 s32 pinned:2;
 187                 u32 tiling:2;
 188                 u32 dirty:1;
 189                 u32 purgeable:1;
 190                 u32 ring:4;
 191                 u32 cache_level:2;
 192         } *active_bo, *pinned_bo;
 193         u32 active_bo_count, pinned_bo_count;
 194         struct intel_overlay_error_state *overlay;
 195         struct intel_display_error_state *display;
 196 };
 197
 198 struct drm_i915_display_funcs {
 199         void (*dpms)(struct drm_crtc *crtc, int mode);
 200         bool (*fbc_enabled)(struct drm_device *dev);
 201         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 202         void (*disable_fbc)(struct drm_device *dev);
 203         int (*get_display_clock_speed)(struct drm_device *dev);
 204         int (*get_fifo_size)(struct drm_device *dev, int plane);
 205         void (*update_wm)(struct drm_device *dev);
 206         int (*crtc_mode_set)(struct drm_crtc *crtc,
 207                              struct drm_display_mode *mode,
 208                              struct drm_display_mode *adjusted_mode,
 209                              int x, int y,
 210                              struct drm_framebuffer *old_fb);
 211         void (*fdi_link_train)(struct drm_crtc *crtc);
 212         void (*init_clock_gating)(struct drm_device *dev);
 213         /* clock updates for mode set */
 214         /* cursor updates */
 215         /* render clock increase/decrease */
 216         /* display clock increase/decrease */
 217         /* pll clock increase/decrease */
 218 };
 219
 220 struct intel_device_info {
 221         u8 gen;
 222         u8 is_mobile : 1;
 223         u8 is_i85x : 1;
 224         u8 is_i915g : 1;
 225         u8 is_i945gm : 1;
 226         u8 is_g33 : 1;
 227         u8 need_gfx_hws : 1;
 228         u8 is_g4x : 1;
 229         u8 is_pineview : 1;
 230         u8 is_broadwater : 1;
 231         u8 is_crestline : 1;
 232         u8 is_ivybridge : 1;
 233         u8 has_fbc : 1;
 234         u8 has_pipe_cxsr : 1;
 235         u8 has_hotplug : 1;
 236         u8 cursor_needs_physical : 1;
 237         u8 has_overlay : 1;
 238         u8 overlay_needs_physical : 1;
 239         u8 supports_tv : 1;
 240         u8 has_bsd_ring : 1;
 241         u8 has_blt_ring : 1;
 242 };
 243
 244 enum no_fbc_reason {
 245         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 246         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 247         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 248         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 249         FBC_BAD_PLANE, /* fbc not supported on plane */
 250         FBC_NOT_TILED, /* buffer not tiled */
 251         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 252 };
 253
 254 enum intel_pch {
 255         PCH_IBX,        /* Ibexpeak PCH */
 256         PCH_CPT,        /* Cougarpoint PCH */
 257 };
 258
 259 #define QUIRK_PIPEA_FORCE (1<<0)
 260
 261 struct intel_fbdev;
 262
 263 typedef struct drm_i915_private {
 264         struct drm_device *dev;
 265
 266         const struct intel_device_info *info;
 267
 268         int has_gem;
 269         int relative_constants_mode;
 270
 271         void __iomem *regs;
 272
 273         struct intel_gmbus {
 274                 struct i2c_adapter adapter;
 275                 struct i2c_adapter *force_bit;
 276                 u32 reg0;
 277         } *gmbus;
 278
 279         struct pci_dev *bridge_dev;
 280         struct intel_ring_buffer ring[I915_NUM_RINGS];
 281         uint32_t next_seqno;
 282
 283         drm_dma_handle_t *status_page_dmah;
 284         uint32_t counter;
 285         drm_local_map_t hws_map;
 286         struct drm_i915_gem_object *pwrctx;
 287         struct drm_i915_gem_object *renderctx;
 288
 289         struct resource mch_res;
 290
 291         unsigned int cpp;
 292         int back_offset;
 293         int front_offset;
 294         int current_page;
 295         int page_flipping;
 296
 297         atomic_t irq_received;
 298
 299         /* protects the irq masks */
 300         spinlock_t irq_lock;
 301         /** Cached value of IMR to avoid reads in updating the bitfield */
 302         u32 pipestat[2];
 303         u32 irq_mask;
 304         u32 gt_irq_mask;
 305         u32 pch_irq_mask;
 306
 307         u32 hotplug_supported_mask;
 308         struct work_struct hotplug_work;
 309
 310         int tex_lru_log_granularity;
 311         int allow_batchbuffer;
 312         struct mem_block *agp_heap;
 313         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 314         int vblank_pipe;
 315         int num_pipe;
 316
 317         /* For hangcheck timer */
 318 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 319         struct timer_list hangcheck_timer;
 320         int hangcheck_count;
 321         uint32_t last_acthd;
 322         uint32_t last_instdone;
 323         uint32_t last_instdone1;
 324
 325         unsigned long cfb_size;
 326         unsigned long cfb_pitch;
 327         unsigned long cfb_offset;
 328         int cfb_fence;
 329         int cfb_plane;
 330         int cfb_y;
 331
 332         struct intel_opregion opregion;
 333
 334         /* overlay */
 335         struct intel_overlay *overlay;
 336
 337         /* LVDS info */
 338         int backlight_level;  /* restore backlight to this value */
 339         bool backlight_enabled;
 340         struct drm_display_mode *panel_fixed_mode;
 341         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 342         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 343
 344         /* Feature bits from the VBIOS */
 345         unsigned int int_tv_support:1;
 346         unsigned int lvds_dither:1;
 347         unsigned int lvds_vbt:1;
 348         unsigned int int_crt_support:1;
 349         unsigned int lvds_use_ssc:1;
 350         int lvds_ssc_freq;
 351         struct {
 352                 int rate;
 353                 int lanes;
 354                 int preemphasis;
 355                 int vswing;
 356
 357                 bool initialized;
 358                 bool support;
 359                 int bpp;
 360                 struct edp_power_seq pps;
 361         } edp;
 362         bool no_aux_handshake;
 363
 364         struct notifier_block lid_notifier;
 365
 366         int crt_ddc_pin;
 367         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 368         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 369         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 370
 371         unsigned int fsb_freq, mem_freq, is_ddr3;
 372
 373         spinlock_t error_lock;
 374         struct drm_i915_error_state *first_error;
 375         struct work_struct error_work;
 376         struct completion error_completion;
 377         struct workqueue_struct *wq;
 378
 379         /* Display functions */
 380         struct drm_i915_display_funcs display;
 381
 382         /* PCH chipset type */
 383         enum intel_pch pch_type;
 384
 385         unsigned long quirks;
 386
 387         /* Register state */
 388         bool modeset_on_lid;
 389         u8 saveLBB;
 390         u32 saveDSPACNTR;
 391         u32 saveDSPBCNTR;
 392         u32 saveDSPARB;
 393         u32 saveHWS;
 394         u32 savePIPEACONF;
 395         u32 savePIPEBCONF;
 396         u32 savePIPEASRC;
 397         u32 savePIPEBSRC;
 398         u32 saveFPA0;
 399         u32 saveFPA1;
 400         u32 saveDPLL_A;
 401         u32 saveDPLL_A_MD;
 402         u32 saveHTOTAL_A;
 403         u32 saveHBLANK_A;
 404         u32 saveHSYNC_A;
 405         u32 saveVTOTAL_A;
 406         u32 saveVBLANK_A;
 407         u32 saveVSYNC_A;
 408         u32 saveBCLRPAT_A;
 409         u32 saveTRANSACONF;
 410         u32 saveTRANS_HTOTAL_A;
 411         u32 saveTRANS_HBLANK_A;
 412         u32 saveTRANS_HSYNC_A;
 413         u32 saveTRANS_VTOTAL_A;
 414         u32 saveTRANS_VBLANK_A;
 415         u32 saveTRANS_VSYNC_A;
 416         u32 savePIPEASTAT;
 417         u32 saveDSPASTRIDE;
 418         u32 saveDSPASIZE;
 419         u32 saveDSPAPOS;
 420         u32 saveDSPAADDR;
 421         u32 saveDSPASURF;
 422         u32 saveDSPATILEOFF;
 423         u32 savePFIT_PGM_RATIOS;
 424         u32 saveBLC_HIST_CTL;
 425         u32 saveBLC_PWM_CTL;
 426         u32 saveBLC_PWM_CTL2;
 427         u32 saveBLC_CPU_PWM_CTL;
 428         u32 saveBLC_CPU_PWM_CTL2;
 429         u32 saveFPB0;
 430         u32 saveFPB1;
 431         u32 saveDPLL_B;
 432         u32 saveDPLL_B_MD;
 433         u32 saveHTOTAL_B;
 434         u32 saveHBLANK_B;
 435         u32 saveHSYNC_B;
 436         u32 saveVTOTAL_B;
 437         u32 saveVBLANK_B;
 438         u32 saveVSYNC_B;
 439         u32 saveBCLRPAT_B;
 440         u32 saveTRANSBCONF;
 441         u32 saveTRANS_HTOTAL_B;
 442         u32 saveTRANS_HBLANK_B;
 443         u32 saveTRANS_HSYNC_B;
 444         u32 saveTRANS_VTOTAL_B;
 445         u32 saveTRANS_VBLANK_B;
 446         u32 saveTRANS_VSYNC_B;
 447         u32 savePIPEBSTAT;
 448         u32 saveDSPBSTRIDE;
 449         u32 saveDSPBSIZE;
 450         u32 saveDSPBPOS;
 451         u32 saveDSPBADDR;
 452         u32 saveDSPBSURF;
 453         u32 saveDSPBTILEOFF;
 454         u32 saveVGA0;
 455         u32 saveVGA1;
 456         u32 saveVGA_PD;
 457         u32 saveVGACNTRL;
 458         u32 saveADPA;
 459         u32 saveLVDS;
 460         u32 savePP_ON_DELAYS;
 461         u32 savePP_OFF_DELAYS;
 462         u32 saveDVOA;
 463         u32 saveDVOB;
 464         u32 saveDVOC;
 465         u32 savePP_ON;
 466         u32 savePP_OFF;
 467         u32 savePP_CONTROL;
 468         u32 savePP_DIVISOR;
 469         u32 savePFIT_CONTROL;
 470         u32 save_palette_a[256];
 471         u32 save_palette_b[256];
 472         u32 saveDPFC_CB_BASE;
 473         u32 saveFBC_CFB_BASE;
 474         u32 saveFBC_LL_BASE;
 475         u32 saveFBC_CONTROL;
 476         u32 saveFBC_CONTROL2;
 477         u32 saveIER;
 478         u32 saveIIR;
 479         u32 saveIMR;
 480         u32 saveDEIER;
 481         u32 saveDEIMR;
 482         u32 saveGTIER;
 483         u32 saveGTIMR;
 484         u32 saveFDI_RXA_IMR;
 485         u32 saveFDI_RXB_IMR;
 486         u32 saveCACHE_MODE_0;
 487         u32 saveMI_ARB_STATE;
 488         u32 saveSWF0[16];
 489         u32 saveSWF1[16];
 490         u32 saveSWF2[3];
 491         u8 saveMSR;
 492         u8 saveSR[8];
 493         u8 saveGR[25];
 494         u8 saveAR_INDEX;
 495         u8 saveAR[21];
 496         u8 saveDACMASK;
 497         u8 saveCR[37];
 498         uint64_t saveFENCE[16];
 499         u32 saveCURACNTR;
 500         u32 saveCURAPOS;
 501         u32 saveCURABASE;
 502         u32 saveCURBCNTR;
 503         u32 saveCURBPOS;
 504         u32 saveCURBBASE;
 505         u32 saveCURSIZE;
 506         u32 saveDP_B;
 507         u32 saveDP_C;
 508         u32 saveDP_D;
 509         u32 savePIPEA_GMCH_DATA_M;
 510         u32 savePIPEB_GMCH_DATA_M;
 511         u32 savePIPEA_GMCH_DATA_N;
 512         u32 savePIPEB_GMCH_DATA_N;
 513         u32 savePIPEA_DP_LINK_M;
 514         u32 savePIPEB_DP_LINK_M;
 515         u32 savePIPEA_DP_LINK_N;
 516         u32 savePIPEB_DP_LINK_N;
 517         u32 saveFDI_RXA_CTL;
 518         u32 saveFDI_TXA_CTL;
 519         u32 saveFDI_RXB_CTL;
 520         u32 saveFDI_TXB_CTL;
 521         u32 savePFA_CTL_1;
 522         u32 savePFB_CTL_1;
 523         u32 savePFA_WIN_SZ;
 524         u32 savePFB_WIN_SZ;
 525         u32 savePFA_WIN_POS;
 526         u32 savePFB_WIN_POS;
 527         u32 savePCH_DREF_CONTROL;
 528         u32 saveDISP_ARB_CTL;
 529         u32 savePIPEA_DATA_M1;
 530         u32 savePIPEA_DATA_N1;
 531         u32 savePIPEA_LINK_M1;
 532         u32 savePIPEA_LINK_N1;
 533         u32 savePIPEB_DATA_M1;
 534         u32 savePIPEB_DATA_N1;
 535         u32 savePIPEB_LINK_M1;
 536         u32 savePIPEB_LINK_N1;
 537         u32 saveMCHBAR_RENDER_STANDBY;
 538
 539         struct {
 540                 /** Bridge to intel-gtt-ko */
 541                 const struct intel_gtt *gtt;
 542                 /** Memory allocator for GTT stolen memory */
 543                 struct drm_mm stolen;
 544                 /** Memory allocator for GTT */
 545                 struct drm_mm gtt_space;
 546                 /** List of all objects in gtt_space. Used to restore gtt
 547                  * mappings on resume */
 548                 struct list_head gtt_list;
 549
 550                 /** Usable portion of the GTT for GEM */
 551                 unsigned long gtt_start;
 552                 unsigned long gtt_mappable_end;
 553                 unsigned long gtt_end;
 554
 555                 struct io_mapping *gtt_mapping;
 556                 int gtt_mtrr;
 557
 558                 struct shrinker inactive_shrinker;
 559
 560                 /**
 561                  * List of objects currently involved in rendering.
 562                  *
 563                  * Includes buffers having the contents of their GPU caches
 564                  * flushed, not necessarily primitives.  last_rendering_seqno
 565                  * represents when the rendering involved will be completed.
 566                  *
 567                  * A reference is held on the buffer while on this list.
 568                  */
 569                 struct list_head active_list;
 570
 571                 /**
 572                  * List of objects which are not in the ringbuffer but which
 573                  * still have a write_domain which needs to be flushed before
 574                  * unbinding.
 575                  *
 576                  * last_rendering_seqno is 0 while an object is in this list.
 577                  *
 578                  * A reference is held on the buffer while on this list.
 579                  */
 580                 struct list_head flushing_list;
 581
 582                 /**
 583                  * LRU list of objects which are not in the ringbuffer and
 584                  * are ready to unbind, but are still in the GTT.
 585                  *
 586                  * last_rendering_seqno is 0 while an object is in this list.
 587                  *
 588                  * A reference is not held on the buffer while on this list,
 589                  * as merely being GTT-bound shouldn't prevent its being
 590                  * freed, and we'll pull it off the list in the free path.
 591                  */
 592                 struct list_head inactive_list;
 593
 594                 /**
 595                  * LRU list of objects which are not in the ringbuffer but
 596                  * are still pinned in the GTT.
 597                  */
 598                 struct list_head pinned_list;
 599
 600                 /** LRU list of objects with fence regs on them. */
 601                 struct list_head fence_list;
 602
 603                 /**
 604                  * List of objects currently pending being freed.
 605                  *
 606                  * These objects are no longer in use, but due to a signal
 607                  * we were prevented from freeing them at the appointed time.
 608                  */
 609                 struct list_head deferred_free_list;
 610
 611                 /**
 612                  * We leave the user IRQ off as much as possible,
 613                  * but this means that requests will finish and never
 614                  * be retired once the system goes idle. Set a timer to
 615                  * fire periodically while the ring is running. When it
 616                  * fires, go retire requests.
 617                  */
 618                 struct delayed_work retire_work;
 619
 620                 /**
 621                  * Are we in a non-interruptible section of code like
 622                  * modesetting?
 623                  */
 624                 bool interruptible;
 625
 626                 /**
 627                  * Flag if the X Server, and thus DRM, is not currently in
 628                  * control of the device.
 629                  *
 630                  * This is set between LeaveVT and EnterVT.  It needs to be
 631                  * replaced with a semaphore.  It also needs to be
 632                  * transitioned away from for kernel modesetting.
 633                  */
 634                 int suspended;
 635
 636                 /**
 637                  * Flag if the hardware appears to be wedged.
 638                  *
 639                  * This is set when attempts to idle the device timeout.
 640                  * It prevents command submission from occurring and makes
 641                  * every pending request fail
 642                  */
 643                 atomic_t wedged;
 644
 645                 /** Bit 6 swizzling required for X tiling */
 646                 uint32_t bit_6_swizzle_x;
 647                 /** Bit 6 swizzling required for Y tiling */
 648                 uint32_t bit_6_swizzle_y;
 649
 650                 /* storage for physical objects */
 651                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 652
 653                 /* accounting, useful for userland debugging */
 654                 size_t gtt_total;
 655                 size_t mappable_gtt_total;
 656                 size_t object_memory;
 657                 u32 object_count;
 658         } mm;
 659         struct sdvo_device_mapping sdvo_mappings[2];
 660         /* indicate whether the LVDS_BORDER should be enabled or not */
 661         unsigned int lvds_border_bits;
 662         /* Panel fitter placement and size for Ironlake+ */
 663         u32 pch_pf_pos, pch_pf_size;
 664         int panel_t3, panel_t12;
 665
 666         struct drm_crtc *plane_to_crtc_mapping[2];
 667         struct drm_crtc *pipe_to_crtc_mapping[2];
 668         wait_queue_head_t pending_flip_queue;
 669         bool flip_pending_is_done;
 670
 671         /* Reclocking support */
 672         bool render_reclock_avail;
 673         bool lvds_downclock_avail;
 674         /* indicates the reduced downclock for LVDS*/
 675         int lvds_downclock;
 676         struct work_struct idle_work;
 677         struct timer_list idle_timer;
 678         bool busy;
 679         u16 orig_clock;
 680         int child_dev_num;
 681         struct child_device_config *child_dev;
 682         struct drm_connector *int_lvds_connector;
 683
 684         bool mchbar_need_disable;
 685
 686         struct work_struct rps_work;
 687         spinlock_t rps_lock;
 688         u32 pm_iir;
 689
 690         u8 cur_delay;
 691         u8 min_delay;
 692         u8 max_delay;
 693         u8 fmax;
 694         u8 fstart;
 695
 696         u64 last_count1;
 697         unsigned long last_time1;
 698         u64 last_count2;
 699         struct timespec last_time2;
 700         unsigned long gfx_power;
 701         int c_m;
 702         int r_t;
 703         u8 corr;
 704         spinlock_t *mchdev_lock;
 705
 706         enum no_fbc_reason no_fbc_reason;
 707
 708         struct drm_mm_node *compressed_fb;
 709         struct drm_mm_node *compressed_llb;
 710
 711         unsigned long last_gpu_reset;
 712
 713         /* list of fbdev register on this device */
 714         struct intel_fbdev *fbdev;
 715
 716         struct drm_property *broadcast_rgb_property;
 717
 718         atomic_t forcewake_count;
 719 } drm_i915_private_t;
 720
 721 enum i915_cache_level {
 722         I915_CACHE_NONE,
 723         I915_CACHE_LLC,
 724         I915_CACHE_LLC_MLC, /* gen6+ */
 725 };
 726
 727 struct drm_i915_gem_object {
 728         struct drm_gem_object base;
 729
 730         /** Current space allocated to this object in the GTT, if any. */
 731         struct drm_mm_node *gtt_space;
 732         struct list_head gtt_list;
 733
 734         /** This object's place on the active/flushing/inactive lists */
 735         struct list_head ring_list;
 736         struct list_head mm_list;
 737         /** This object's place on GPU write list */
 738         struct list_head gpu_write_list;
 739         /** This object's place in the batchbuffer or on the eviction list */
 740         struct list_head exec_list;
 741
 742         /**
 743          * This is set if the object is on the active or flushing lists
 744          * (has pending rendering), and is not set if it's on inactive (ready
 745          * to be unbound).
 746          */
 747         unsigned int active : 1;
 748
 749         /**
 750          * This is set if the object has been written to since last bound
 751          * to the GTT
 752          */
 753         unsigned int dirty : 1;
 754
 755         /**
 756          * This is set if the object has been written to since the last
 757          * GPU flush.
 758          */
 759         unsigned int pending_gpu_write : 1;
 760
 761         /**
 762          * Fence register bits (if any) for this object.  Will be set
 763          * as needed when mapped into the GTT.
 764          * Protected by dev->struct_mutex.
 765          *
 766          * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
 767          */
 768         signed int fence_reg : 5;
 769
 770         /**
 771          * Advice: are the backing pages purgeable?
 772          */
 773         unsigned int madv : 2;
 774
 775         /**
 776          * Current tiling mode for the object.
 777          */
 778         unsigned int tiling_mode : 2;
 779         unsigned int tiling_changed : 1;
 780
 781         /** How many users have pinned this object in GTT space. The following
 782          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 783          * (via user_pin_count), execbuffer (objects are not allowed multiple
 784          * times for the same batchbuffer), and the framebuffer code. When
 785          * switching/pageflipping, the framebuffer code has at most two buffers
 786          * pinned per crtc.
 787          *
 788          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 789          * bits with absolutely no headroom. So use 4 bits. */
 790         unsigned int pin_count : 4;
 791 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 792
 793         /**
 794          * Is the object at the current location in the gtt mappable and
 795          * fenceable? Used to avoid costly recalculations.
 796          */
 797         unsigned int map_and_fenceable : 1;
 798
 799         /**
 800          * Whether the current gtt mapping needs to be mappable (and isn't just
 801          * mappable by accident). Track pin and fault separate for a more
 802          * accurate mappable working set.
 803          */
 804         unsigned int fault_mappable : 1;
 805         unsigned int pin_mappable : 1;
 806
 807         /*
 808          * Is the GPU currently using a fence to access this buffer,
 809          */
 810         unsigned int pending_fenced_gpu_access:1;
 811         unsigned int fenced_gpu_access:1;
 812
 813         unsigned int cache_level:2;
 814
 815         struct page **pages;
 816
 817         /**
 818          * DMAR support
 819          */
 820         struct scatterlist *sg_list;
 821         int num_sg;
 822
 823         /**
 824          * Used for performing relocations during execbuffer insertion.
 825          */
 826         struct hlist_node exec_node;
 827         unsigned long exec_handle;
 828         struct drm_i915_gem_exec_object2 *exec_entry;
 829
 830         /**
 831          * Current offset of the object in GTT space.
 832          *
 833          * This is the same as gtt_space->start
 834          */
 835         uint32_t gtt_offset;
 836
 837         /** Breadcrumb of last rendering to the buffer. */
 838         uint32_t last_rendering_seqno;
 839         struct intel_ring_buffer *ring;
 840
 841         /** Breadcrumb of last fenced GPU access to the buffer. */
 842         uint32_t last_fenced_seqno;
 843         struct intel_ring_buffer *last_fenced_ring;
 844
 845         /** Current tiling stride for the object, if it's tiled. */
 846         uint32_t stride;
 847
 848         /** Record of address bit 17 of each page at last unbind. */
 849         unsigned long *bit_17;
 850
 851
 852         /**
 853          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 854          * flags which individual pages are valid.
 855          */
 856         uint8_t *page_cpu_valid;
 857
 858         /** User space pin count and filp owning the pin */
 859         uint32_t user_pin_count;
 860         struct drm_file *pin_filp;
 861
 862         /** for phy allocated objects */
 863         struct drm_i915_gem_phys_object *phys_obj;
 864
 865         /**
 866          * Number of crtcs where this object is currently the fb, but
 867          * will be page flipped away on the next vblank.  When it
 868          * reaches 0, dev_priv->pending_flip_queue will be woken up.
 869          */
 870         atomic_t pending_flip;
 871 };
 872
 873 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 874
 875 /**
 876  * Request queue structure.
 877  *
 878  * The request queue allows us to note sequence numbers that have been emitted
 879  * and may be associated with active buffers to be retired.
 880  *
 881  * By keeping this list, we can avoid having to do questionable
 882  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 883  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 884  */
 885 struct drm_i915_gem_request {
 886         /** On Which ring this request was generated */
 887         struct intel_ring_buffer *ring;
 888
 889         /** GEM sequence number associated with this request. */
 890         uint32_t seqno;
 891
 892         /** Time at which this request was emitted, in jiffies. */
 893         unsigned long emitted_jiffies;
 894
 895         /** global list entry for this request */
 896         struct list_head list;
 897
 898         struct drm_i915_file_private *file_priv;
 899         /** file_priv list entry for this request */
 900         struct list_head client_list;
 901 };
 902
 903 struct drm_i915_file_private {
 904         struct {
 905                 struct spinlock lock;
 906                 struct list_head request_list;
 907         } mm;
 908 };
 909
 910 enum intel_chip_family {
 911         CHIP_I8XX = 0x01,
 912         CHIP_I9XX = 0x02,
 913         CHIP_I915 = 0x04,
 914         CHIP_I965 = 0x08,
 915 };
 916
 917 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
 918
 919 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
 920 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
 921 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
 922 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
 923 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
 924 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
 925 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
 926 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 927 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
 928 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
 929 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
 930 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
 931 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
 932 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
 933 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
 934 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
 935 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
 936 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
 937 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
 938 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
 939
 940 /*
 941  * The genX designation typically refers to the render engine, so render
 942  * capability related checks should use IS_GEN, while display and other checks
 943  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 944  * chips, etc.).
 945  */
 946 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
 947 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
 948 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
 949 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
 950 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
 951 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
 952
 953 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
 954 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
 955 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
 956
 957 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
 958 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
 959
 960 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 961  * rows, which changed the alignment requirements and fence programming.
 962  */
 963 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
 964                                                       IS_I915GM(dev)))
 965 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
 966 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
 967 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
 968 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
 969 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
 970 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
 971 /* dsparb controlled by hw only */
 972 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 973
 974 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
 975 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 976 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 977
 978 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 979 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 980
 981 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 982 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 983 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 984
 985 #include "i915_trace.h"
 986
 987 extern struct drm_ioctl_desc i915_ioctls[];
 988 extern int i915_max_ioctl;
 989 extern unsigned int i915_fbpercrtc;
 990 extern int i915_panel_ignore_lid;
 991 extern unsigned int i915_powersave;
 992 extern unsigned int i915_semaphores;
 993 extern unsigned int i915_lvds_downclock;
 994 extern unsigned int i915_panel_use_ssc;
 995 extern int i915_vbt_sdvo_panel_type;
 996 extern unsigned int i915_enable_rc6;
 997
 998 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 999 extern int i915_resume(struct drm_device *dev);
1000 extern void i915_save_display(struct drm_device *dev);
1001 extern void i915_restore_display(struct drm_device *dev);
1002 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1003 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1004
1005                                 /* i915_dma.c */
1006 extern void i915_kernel_lost_context(struct drm_device * dev);
1007 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1008 extern int i915_driver_unload(struct drm_device *);
1009 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1010 extern void i915_driver_lastclose(struct drm_device * dev);
1011 extern void i915_driver_preclose(struct drm_device *dev,
1012                                  struct drm_file *file_priv);
1013 extern void i915_driver_postclose(struct drm_device *dev,
1014                                   struct drm_file *file_priv);
1015 extern int i915_driver_device_is_agp(struct drm_device * dev);
1016 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1017                               unsigned long arg);
1018 extern int i915_emit_box(struct drm_device *dev,
1019                          struct drm_clip_rect *box,
1020                          int DR1, int DR4);
1021 extern int i915_reset(struct drm_device *dev, u8 flags);
1022 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1023 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1024 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1025 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1026
1027
1028 /* i915_irq.c */
1029 void i915_hangcheck_elapsed(unsigned long data);
1030 void i915_handle_error(struct drm_device *dev, bool wedged);
1031 extern int i915_irq_emit(struct drm_device *dev, void *data,
1032                          struct drm_file *file_priv);
1033 extern int i915_irq_wait(struct drm_device *dev, void *data,
1034                          struct drm_file *file_priv);
1035
1036 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS);
1037 extern void i915_driver_irq_preinstall(struct drm_device * dev);
1038 extern int i915_driver_irq_postinstall(struct drm_device *dev);
1039 extern void i915_driver_irq_uninstall(struct drm_device * dev);
1040
1041 extern irqreturn_t ironlake_irq_handler(DRM_IRQ_ARGS);
1042 extern void ironlake_irq_preinstall(struct drm_device *dev);
1043 extern int ironlake_irq_postinstall(struct drm_device *dev);
1044 extern void ironlake_irq_uninstall(struct drm_device *dev);
1045
1046 extern irqreturn_t ivybridge_irq_handler(DRM_IRQ_ARGS);
1047 extern void ivybridge_irq_preinstall(struct drm_device *dev);
1048 extern int ivybridge_irq_postinstall(struct drm_device *dev);
1049 extern void ivybridge_irq_uninstall(struct drm_device *dev);
1050
1051 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1052                                 struct drm_file *file_priv);
1053 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1054                                 struct drm_file *file_priv);
1055 extern int i915_enable_vblank(struct drm_device *dev, int crtc);
1056 extern void i915_disable_vblank(struct drm_device *dev, int crtc);
1057 extern int ironlake_enable_vblank(struct drm_device *dev, int crtc);
1058 extern void ironlake_disable_vblank(struct drm_device *dev, int crtc);
1059 extern int ivybridge_enable_vblank(struct drm_device *dev, int crtc);
1060 extern void ivybridge_disable_vblank(struct drm_device *dev, int crtc);
1061 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc);
1062 extern u32 gm45_get_vblank_counter(struct drm_device *dev, int crtc);
1063 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1064                             struct drm_file *file_priv);
1065
1066 void
1067 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1068
1069 void
1070 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1071
1072 void intel_enable_asle (struct drm_device *dev);
1073 int i915_get_vblank_timestamp(struct drm_device *dev, int crtc,
1074                               int *max_error,
1075                               struct timeval *vblank_time,
1076                               unsigned flags);
1077
1078 int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
1079                              int *vpos, int *hpos);
1080
1081 #ifdef CONFIG_DEBUG_FS
1082 extern void i915_destroy_error_state(struct drm_device *dev);
1083 #else
1084 #define i915_destroy_error_state(x)
1085 #endif
1086
1087
1088 /* i915_mem.c */
1089 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1090                           struct drm_file *file_priv);
1091 extern int i915_mem_free(struct drm_device *dev, void *data,
1092                          struct drm_file *file_priv);
1093 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1094                               struct drm_file *file_priv);
1095 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1096                                  struct drm_file *file_priv);
1097 extern void i915_mem_takedown(struct mem_block **heap);
1098 extern void i915_mem_release(struct drm_device * dev,
1099                              struct drm_file *file_priv, struct mem_block *heap);
1100 /* i915_gem.c */
1101 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1102                         struct drm_file *file_priv);
1103 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1104                           struct drm_file *file_priv);
1105 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1106                          struct drm_file *file_priv);
1107 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1108                           struct drm_file *file_priv);
1109 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1110                         struct drm_file *file_priv);
1111 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1112                         struct drm_file *file_priv);
1113 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1114                               struct drm_file *file_priv);
1115 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1116                              struct drm_file *file_priv);
1117 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1118                         struct drm_file *file_priv);
1119 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1120                          struct drm_file *file_priv);
1121 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1122                        struct drm_file *file_priv);
1123 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1124                          struct drm_file *file_priv);
1125 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1126                         struct drm_file *file_priv);
1127 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1128                             struct drm_file *file_priv);
1129 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1130                            struct drm_file *file_priv);
1131 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1132                            struct drm_file *file_priv);
1133 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1134                            struct drm_file *file_priv);
1135 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1136                         struct drm_file *file_priv);
1137 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1138                         struct drm_file *file_priv);
1139 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1140                                 struct drm_file *file_priv);
1141 void i915_gem_load(struct drm_device *dev);
1142 int i915_gem_init_object(struct drm_gem_object *obj);
1143 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1144                                      uint32_t invalidate_domains,
1145                                      uint32_t flush_domains);
1146 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1147                                                   size_t size);
1148 void i915_gem_free_object(struct drm_gem_object *obj);
1149 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1150                                      uint32_t alignment,
1151                                      bool map_and_fenceable);
1152 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1153 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1154 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1155 void i915_gem_lastclose(struct drm_device *dev);
1156
1157 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1158 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1159 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1160                                     struct intel_ring_buffer *ring,
1161                                     u32 seqno);
1162
1163 int i915_gem_dumb_create(struct drm_file *file_priv,
1164                          struct drm_device *dev,
1165                          struct drm_mode_create_dumb *args);
1166 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1167                       uint32_t handle, uint64_t *offset);
1168 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1169                           uint32_t handle);
1170 /**
1171  * Returns true if seq1 is later than seq2.
1172  */
1173 static inline bool
1174 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1175 {
1176         return (int32_t)(seq1 - seq2) >= 0;
1177 }
1178
1179 static inline u32
1180 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1181 {
1182         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1183         return ring->outstanding_lazy_request = dev_priv->next_seqno;
1184 }
1185
1186 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1187                                            struct intel_ring_buffer *pipelined);
1188 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1189
1190 void i915_gem_retire_requests(struct drm_device *dev);
1191 void i915_gem_reset(struct drm_device *dev);
1192 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1193 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1194                                             uint32_t read_domains,
1195                                             uint32_t write_domain);
1196 int __must_check i915_gem_object_flush_gpu(struct drm_i915_gem_object *obj);
1197 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1198 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1199 void i915_gem_do_init(struct drm_device *dev,
1200                       unsigned long start,
1201                       unsigned long mappable_end,
1202                       unsigned long end);
1203 int __must_check i915_gpu_idle(struct drm_device *dev);
1204 int __must_check i915_gem_idle(struct drm_device *dev);
1205 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1206                                   struct drm_file *file,
1207                                   struct drm_i915_gem_request *request);
1208 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1209                                    uint32_t seqno);
1210 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1211 int __must_check
1212 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1213                                   bool write);
1214 int __must_check
1215 i915_gem_object_set_to_display_plane(struct drm_i915_gem_object *obj,
1216                                      struct intel_ring_buffer *pipelined);
1217 int i915_gem_attach_phys_object(struct drm_device *dev,
1218                                 struct drm_i915_gem_object *obj,
1219                                 int id,
1220                                 int align);
1221 void i915_gem_detach_phys_object(struct drm_device *dev,
1222                                  struct drm_i915_gem_object *obj);
1223 void i915_gem_free_all_phys_object(struct drm_device *dev);
1224 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1225
1226 uint32_t
1227 i915_gem_get_unfenced_gtt_alignment(struct drm_i915_gem_object *obj);
1228
1229 /* i915_gem_gtt.c */
1230 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1231 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1232 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1233
1234 /* i915_gem_evict.c */
1235 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1236                                           unsigned alignment, bool mappable);
1237 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1238                                            bool purgeable_only);
1239 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1240                                          bool purgeable_only);
1241
1242 /* i915_gem_tiling.c */
1243 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1244 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1245 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1246
1247 /* i915_gem_debug.c */
1248 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1249                           const char *where, uint32_t mark);
1250 #if WATCH_LISTS
1251 int i915_verify_lists(struct drm_device *dev);
1252 #else
1253 #define i915_verify_lists(dev) 0
1254 #endif
1255 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1256                                      int handle);
1257 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1258                           const char *where, uint32_t mark);
1259
1260 /* i915_debugfs.c */
1261 int i915_debugfs_init(struct drm_minor *minor);
1262 void i915_debugfs_cleanup(struct drm_minor *minor);
1263
1264 /* i915_suspend.c */
1265 extern int i915_save_state(struct drm_device *dev);
1266 extern int i915_restore_state(struct drm_device *dev);
1267
1268 /* i915_suspend.c */
1269 extern int i915_save_state(struct drm_device *dev);
1270 extern int i915_restore_state(struct drm_device *dev);
1271
1272 /* intel_i2c.c */
1273 extern int intel_setup_gmbus(struct drm_device *dev);
1274 extern void intel_teardown_gmbus(struct drm_device *dev);
1275 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1276 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1277 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1278 {
1279         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1280 }
1281 extern void intel_i2c_reset(struct drm_device *dev);
1282
1283 /* intel_opregion.c */
1284 extern int intel_opregion_setup(struct drm_device *dev);
1285 #ifdef CONFIG_ACPI
1286 extern void intel_opregion_init(struct drm_device *dev);
1287 extern void intel_opregion_fini(struct drm_device *dev);
1288 extern void intel_opregion_asle_intr(struct drm_device *dev);
1289 extern void intel_opregion_gse_intr(struct drm_device *dev);
1290 extern void intel_opregion_enable_asle(struct drm_device *dev);
1291 #else
1292 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1293 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1294 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1295 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1296 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1297 #endif
1298
1299 /* intel_acpi.c */
1300 #ifdef CONFIG_ACPI
1301 extern void intel_register_dsm_handler(void);
1302 extern void intel_unregister_dsm_handler(void);
1303 #else
1304 static inline void intel_register_dsm_handler(void) { return; }
1305 static inline void intel_unregister_dsm_handler(void) { return; }
1306 #endif /* CONFIG_ACPI */
1307
1308 /* modesetting */
1309 extern void intel_modeset_init(struct drm_device *dev);
1310 extern void intel_modeset_gem_init(struct drm_device *dev);
1311 extern void intel_modeset_cleanup(struct drm_device *dev);
1312 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1313 extern void i8xx_disable_fbc(struct drm_device *dev);
1314 extern void g4x_disable_fbc(struct drm_device *dev);
1315 extern void ironlake_disable_fbc(struct drm_device *dev);
1316 extern void intel_disable_fbc(struct drm_device *dev);
1317 extern void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval);
1318 extern bool intel_fbc_enabled(struct drm_device *dev);
1319 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1320 extern void ironlake_enable_rc6(struct drm_device *dev);
1321 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1322 extern void intel_detect_pch (struct drm_device *dev);
1323 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1324
1325 /* overlay */
1326 #ifdef CONFIG_DEBUG_FS
1327 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1328 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1329
1330 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1331 extern void intel_display_print_error_state(struct seq_file *m,
1332                                             struct drm_device *dev,
1333                                             struct intel_display_error_state *error);
1334 #endif
1335
1336 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1337
1338 #define BEGIN_LP_RING(n) \
1339         intel_ring_begin(LP_RING(dev_priv), (n))
1340
1341 #define OUT_RING(x) \
1342         intel_ring_emit(LP_RING(dev_priv), x)
1343
1344 #define ADVANCE_LP_RING() \
1345         intel_ring_advance(LP_RING(dev_priv))
1346
1347 /**
1348  * Lock test for when it's just for synchronization of ring access.
1349  *
1350  * In that case, we don't need to do it when GEM is initialized as nobody else
1351  * has access to the ring.
1352  */
1353 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
1354         if (LP_RING(dev->dev_private)->obj == NULL)                     \
1355                 LOCK_TEST_WITH_RETURN(dev, file);                       \
1356 } while (0)
1357
1358 /* On SNB platform, before reading ring registers forcewake bit
1359  * must be set to prevent GT core from power down and stale values being
1360  * returned.
1361  */
1362 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1363 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1364 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1365
1366 /* We give fast paths for the really cool registers */
1367 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1368         (((dev_priv)->info->gen >= 6) && \
1369         ((reg) < 0x40000) && \
1370         ((reg) != FORCEWAKE))
1371
1372 #define __i915_read(x, y) \
1373 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1374         u##x val = 0; \
1375         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1376                 gen6_gt_force_wake_get(dev_priv); \
1377                 val = read##y(dev_priv->regs + reg); \
1378                 gen6_gt_force_wake_put(dev_priv); \
1379         } else { \
1380                 val = read##y(dev_priv->regs + reg); \
1381         } \
1382         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1383         return val; \
1384 }
1385
1386 __i915_read(8, b)
1387 __i915_read(16, w)
1388 __i915_read(32, l)
1389 __i915_read(64, q)
1390 #undef __i915_read
1391
1392 #define __i915_write(x, y) \
1393 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1394         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1395         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1396                 __gen6_gt_wait_for_fifo(dev_priv); \
1397         } \
1398         write##y(val, dev_priv->regs + reg); \
1399 }
1400 __i915_write(8, b)
1401 __i915_write(16, w)
1402 __i915_write(32, l)
1403 __i915_write(64, q)
1404 #undef __i915_write
1405
1406 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1407 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1408
1409 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1410 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1411 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1412 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1413
1414 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1415 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1416 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1417 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1418
1419 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1420 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1421
1422 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1423 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1424
1425
1426 #endif