drm/i915: introduce intel_audio_codec_{enable, disable}
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include "i915_reg.h"
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
52
53 /* General customization:
54 */
55
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141024"
59
60 enum pipe {
61 INVALID_PIPE = -1,
62 PIPE_A = 0,
63 PIPE_B,
64 PIPE_C,
65 _PIPE_EDP,
66 I915_MAX_PIPES = _PIPE_EDP
67 };
68 #define pipe_name(p) ((p) + 'A')
69
70 enum transcoder {
71 TRANSCODER_A = 0,
72 TRANSCODER_B,
73 TRANSCODER_C,
74 TRANSCODER_EDP,
75 I915_MAX_TRANSCODERS
76 };
77 #define transcoder_name(t) ((t) + 'A')
78
79 /*
80 * This is the maximum (across all platforms) number of planes (primary +
81 * sprites) that can be active at the same time on one pipe.
82 *
83 * This value doesn't count the cursor plane.
84 */
85 #define I915_MAX_PLANES 3
86
87 enum plane {
88 PLANE_A = 0,
89 PLANE_B,
90 PLANE_C,
91 };
92 #define plane_name(p) ((p) + 'A')
93
94 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
95
96 enum port {
97 PORT_A = 0,
98 PORT_B,
99 PORT_C,
100 PORT_D,
101 PORT_E,
102 I915_MAX_PORTS
103 };
104 #define port_name(p) ((p) + 'A')
105
106 #define I915_NUM_PHYS_VLV 2
107
108 enum dpio_channel {
109 DPIO_CH0,
110 DPIO_CH1
111 };
112
113 enum dpio_phy {
114 DPIO_PHY0,
115 DPIO_PHY1
116 };
117
118 enum intel_display_power_domain {
119 POWER_DOMAIN_PIPE_A,
120 POWER_DOMAIN_PIPE_B,
121 POWER_DOMAIN_PIPE_C,
122 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
123 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
124 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
125 POWER_DOMAIN_TRANSCODER_A,
126 POWER_DOMAIN_TRANSCODER_B,
127 POWER_DOMAIN_TRANSCODER_C,
128 POWER_DOMAIN_TRANSCODER_EDP,
129 POWER_DOMAIN_PORT_DDI_A_2_LANES,
130 POWER_DOMAIN_PORT_DDI_A_4_LANES,
131 POWER_DOMAIN_PORT_DDI_B_2_LANES,
132 POWER_DOMAIN_PORT_DDI_B_4_LANES,
133 POWER_DOMAIN_PORT_DDI_C_2_LANES,
134 POWER_DOMAIN_PORT_DDI_C_4_LANES,
135 POWER_DOMAIN_PORT_DDI_D_2_LANES,
136 POWER_DOMAIN_PORT_DDI_D_4_LANES,
137 POWER_DOMAIN_PORT_DSI,
138 POWER_DOMAIN_PORT_CRT,
139 POWER_DOMAIN_PORT_OTHER,
140 POWER_DOMAIN_VGA,
141 POWER_DOMAIN_AUDIO,
142 POWER_DOMAIN_PLLS,
143 POWER_DOMAIN_INIT,
144
145 POWER_DOMAIN_NUM,
146 };
147
148 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
149 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
150 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
151 #define POWER_DOMAIN_TRANSCODER(tran) \
152 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
153 (tran) + POWER_DOMAIN_TRANSCODER_A)
154
155 enum hpd_pin {
156 HPD_NONE = 0,
157 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
158 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
159 HPD_CRT,
160 HPD_SDVO_B,
161 HPD_SDVO_C,
162 HPD_PORT_B,
163 HPD_PORT_C,
164 HPD_PORT_D,
165 HPD_NUM_PINS
166 };
167
168 #define I915_GEM_GPU_DOMAINS \
169 (I915_GEM_DOMAIN_RENDER | \
170 I915_GEM_DOMAIN_SAMPLER | \
171 I915_GEM_DOMAIN_COMMAND | \
172 I915_GEM_DOMAIN_INSTRUCTION | \
173 I915_GEM_DOMAIN_VERTEX)
174
175 #define for_each_pipe(__dev_priv, __p) \
176 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
177 #define for_each_plane(pipe, p) \
178 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
179 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
180
181 #define for_each_crtc(dev, crtc) \
182 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
183
184 #define for_each_intel_crtc(dev, intel_crtc) \
185 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
186
187 #define for_each_intel_encoder(dev, intel_encoder) \
188 list_for_each_entry(intel_encoder, \
189 &(dev)->mode_config.encoder_list, \
190 base.head)
191
192 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
193 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
194 if ((intel_encoder)->base.crtc == (__crtc))
195
196 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
197 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
198 if ((intel_connector)->base.encoder == (__encoder))
199
200 #define for_each_power_domain(domain, mask) \
201 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
202 if ((1 << (domain)) & (mask))
203
204 struct drm_i915_private;
205 struct i915_mm_struct;
206 struct i915_mmu_object;
207
208 enum intel_dpll_id {
209 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
210 /* real shared dpll ids must be >= 0 */
211 DPLL_ID_PCH_PLL_A = 0,
212 DPLL_ID_PCH_PLL_B = 1,
213 DPLL_ID_WRPLL1 = 0,
214 DPLL_ID_WRPLL2 = 1,
215 };
216 #define I915_NUM_PLLS 2
217
218 struct intel_dpll_hw_state {
219 /* i9xx, pch plls */
220 uint32_t dpll;
221 uint32_t dpll_md;
222 uint32_t fp0;
223 uint32_t fp1;
224
225 /* hsw, bdw */
226 uint32_t wrpll;
227 };
228
229 struct intel_shared_dpll {
230 int refcount; /* count of number of CRTCs sharing this PLL */
231 int active; /* count of number of active CRTCs (i.e. DPMS on) */
232 bool on; /* is the PLL actually active? Disabled during modeset */
233 const char *name;
234 /* should match the index in the dev_priv->shared_dplls array */
235 enum intel_dpll_id id;
236 struct intel_dpll_hw_state hw_state;
237 /* The mode_set hook is optional and should be used together with the
238 * intel_prepare_shared_dpll function. */
239 void (*mode_set)(struct drm_i915_private *dev_priv,
240 struct intel_shared_dpll *pll);
241 void (*enable)(struct drm_i915_private *dev_priv,
242 struct intel_shared_dpll *pll);
243 void (*disable)(struct drm_i915_private *dev_priv,
244 struct intel_shared_dpll *pll);
245 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
246 struct intel_shared_dpll *pll,
247 struct intel_dpll_hw_state *hw_state);
248 };
249
250 /* Used by dp and fdi links */
251 struct intel_link_m_n {
252 uint32_t tu;
253 uint32_t gmch_m;
254 uint32_t gmch_n;
255 uint32_t link_m;
256 uint32_t link_n;
257 };
258
259 void intel_link_compute_m_n(int bpp, int nlanes,
260 int pixel_clock, int link_clock,
261 struct intel_link_m_n *m_n);
262
263 /* Interface history:
264 *
265 * 1.1: Original.
266 * 1.2: Add Power Management
267 * 1.3: Add vblank support
268 * 1.4: Fix cmdbuffer path, add heap destroy
269 * 1.5: Add vblank pipe configuration
270 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
271 * - Support vertical blank on secondary display pipe
272 */
273 #define DRIVER_MAJOR 1
274 #define DRIVER_MINOR 6
275 #define DRIVER_PATCHLEVEL 0
276
277 #define WATCH_LISTS 0
278 #define WATCH_GTT 0
279
280 struct opregion_header;
281 struct opregion_acpi;
282 struct opregion_swsci;
283 struct opregion_asle;
284
285 struct intel_opregion {
286 struct opregion_header __iomem *header;
287 struct opregion_acpi __iomem *acpi;
288 struct opregion_swsci __iomem *swsci;
289 u32 swsci_gbda_sub_functions;
290 u32 swsci_sbcb_sub_functions;
291 struct opregion_asle __iomem *asle;
292 void __iomem *vbt;
293 u32 __iomem *lid_state;
294 struct work_struct asle_work;
295 };
296 #define OPREGION_SIZE (8*1024)
297
298 struct intel_overlay;
299 struct intel_overlay_error_state;
300
301 struct drm_local_map;
302
303 struct drm_i915_master_private {
304 struct drm_local_map *sarea;
305 struct _drm_i915_sarea *sarea_priv;
306 };
307 #define I915_FENCE_REG_NONE -1
308 #define I915_MAX_NUM_FENCES 32
309 /* 32 fences + sign bit for FENCE_REG_NONE */
310 #define I915_MAX_NUM_FENCE_BITS 6
311
312 struct drm_i915_fence_reg {
313 struct list_head lru_list;
314 struct drm_i915_gem_object *obj;
315 int pin_count;
316 };
317
318 struct sdvo_device_mapping {
319 u8 initialized;
320 u8 dvo_port;
321 u8 slave_addr;
322 u8 dvo_wiring;
323 u8 i2c_pin;
324 u8 ddc_pin;
325 };
326
327 struct intel_display_error_state;
328
329 struct drm_i915_error_state {
330 struct kref ref;
331 struct timeval time;
332
333 char error_msg[128];
334 u32 reset_count;
335 u32 suspend_count;
336
337 /* Generic register state */
338 u32 eir;
339 u32 pgtbl_er;
340 u32 ier;
341 u32 gtier[4];
342 u32 ccid;
343 u32 derrmr;
344 u32 forcewake;
345 u32 error; /* gen6+ */
346 u32 err_int; /* gen7 */
347 u32 done_reg;
348 u32 gac_eco;
349 u32 gam_ecochk;
350 u32 gab_ctl;
351 u32 gfx_mode;
352 u32 extra_instdone[I915_NUM_INSTDONE_REG];
353 u64 fence[I915_MAX_NUM_FENCES];
354 struct intel_overlay_error_state *overlay;
355 struct intel_display_error_state *display;
356 struct drm_i915_error_object *semaphore_obj;
357
358 struct drm_i915_error_ring {
359 bool valid;
360 /* Software tracked state */
361 bool waiting;
362 int hangcheck_score;
363 enum intel_ring_hangcheck_action hangcheck_action;
364 int num_requests;
365
366 /* our own tracking of ring head and tail */
367 u32 cpu_ring_head;
368 u32 cpu_ring_tail;
369
370 u32 semaphore_seqno[I915_NUM_RINGS - 1];
371
372 /* Register state */
373 u32 tail;
374 u32 head;
375 u32 ctl;
376 u32 hws;
377 u32 ipeir;
378 u32 ipehr;
379 u32 instdone;
380 u32 bbstate;
381 u32 instpm;
382 u32 instps;
383 u32 seqno;
384 u64 bbaddr;
385 u64 acthd;
386 u32 fault_reg;
387 u64 faddr;
388 u32 rc_psmi; /* sleep state */
389 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
390
391 struct drm_i915_error_object {
392 int page_count;
393 u32 gtt_offset;
394 u32 *pages[0];
395 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
396
397 struct drm_i915_error_request {
398 long jiffies;
399 u32 seqno;
400 u32 tail;
401 } *requests;
402
403 struct {
404 u32 gfx_mode;
405 union {
406 u64 pdp[4];
407 u32 pp_dir_base;
408 };
409 } vm_info;
410
411 pid_t pid;
412 char comm[TASK_COMM_LEN];
413 } ring[I915_NUM_RINGS];
414
415 struct drm_i915_error_buffer {
416 u32 size;
417 u32 name;
418 u32 rseqno, wseqno;
419 u32 gtt_offset;
420 u32 read_domains;
421 u32 write_domain;
422 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
423 s32 pinned:2;
424 u32 tiling:2;
425 u32 dirty:1;
426 u32 purgeable:1;
427 u32 userptr:1;
428 s32 ring:4;
429 u32 cache_level:3;
430 } **active_bo, **pinned_bo;
431
432 u32 *active_bo_count, *pinned_bo_count;
433 u32 vm_count;
434 };
435
436 struct intel_connector;
437 struct intel_encoder;
438 struct intel_crtc_config;
439 struct intel_plane_config;
440 struct intel_crtc;
441 struct intel_limit;
442 struct dpll;
443
444 struct drm_i915_display_funcs {
445 bool (*fbc_enabled)(struct drm_device *dev);
446 void (*enable_fbc)(struct drm_crtc *crtc);
447 void (*disable_fbc)(struct drm_device *dev);
448 int (*get_display_clock_speed)(struct drm_device *dev);
449 int (*get_fifo_size)(struct drm_device *dev, int plane);
450 /**
451 * find_dpll() - Find the best values for the PLL
452 * @limit: limits for the PLL
453 * @crtc: current CRTC
454 * @target: target frequency in kHz
455 * @refclk: reference clock frequency in kHz
456 * @match_clock: if provided, @best_clock P divider must
457 * match the P divider from @match_clock
458 * used for LVDS downclocking
459 * @best_clock: best PLL values found
460 *
461 * Returns true on success, false on failure.
462 */
463 bool (*find_dpll)(const struct intel_limit *limit,
464 struct intel_crtc *crtc,
465 int target, int refclk,
466 struct dpll *match_clock,
467 struct dpll *best_clock);
468 void (*update_wm)(struct drm_crtc *crtc);
469 void (*update_sprite_wm)(struct drm_plane *plane,
470 struct drm_crtc *crtc,
471 uint32_t sprite_width, uint32_t sprite_height,
472 int pixel_size, bool enable, bool scaled);
473 void (*modeset_global_resources)(struct drm_device *dev);
474 /* Returns the active state of the crtc, and if the crtc is active,
475 * fills out the pipe-config with the hw state. */
476 bool (*get_pipe_config)(struct intel_crtc *,
477 struct intel_crtc_config *);
478 void (*get_plane_config)(struct intel_crtc *,
479 struct intel_plane_config *);
480 int (*crtc_mode_set)(struct intel_crtc *crtc,
481 int x, int y,
482 struct drm_framebuffer *old_fb);
483 void (*crtc_enable)(struct drm_crtc *crtc);
484 void (*crtc_disable)(struct drm_crtc *crtc);
485 void (*off)(struct drm_crtc *crtc);
486 void (*audio_codec_enable)(struct drm_connector *connector,
487 struct intel_encoder *encoder,
488 struct drm_display_mode *mode);
489 void (*audio_codec_disable)(struct intel_encoder *encoder);
490 void (*fdi_link_train)(struct drm_crtc *crtc);
491 void (*init_clock_gating)(struct drm_device *dev);
492 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
493 struct drm_framebuffer *fb,
494 struct drm_i915_gem_object *obj,
495 struct intel_engine_cs *ring,
496 uint32_t flags);
497 void (*update_primary_plane)(struct drm_crtc *crtc,
498 struct drm_framebuffer *fb,
499 int x, int y);
500 void (*hpd_irq_setup)(struct drm_device *dev);
501 /* clock updates for mode set */
502 /* cursor updates */
503 /* render clock increase/decrease */
504 /* display clock increase/decrease */
505 /* pll clock increase/decrease */
506
507 int (*setup_backlight)(struct intel_connector *connector);
508 uint32_t (*get_backlight)(struct intel_connector *connector);
509 void (*set_backlight)(struct intel_connector *connector,
510 uint32_t level);
511 void (*disable_backlight)(struct intel_connector *connector);
512 void (*enable_backlight)(struct intel_connector *connector);
513 };
514
515 struct intel_uncore_funcs {
516 void (*force_wake_get)(struct drm_i915_private *dev_priv,
517 int fw_engine);
518 void (*force_wake_put)(struct drm_i915_private *dev_priv,
519 int fw_engine);
520
521 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
522 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
523 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
524 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
525
526 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
527 uint8_t val, bool trace);
528 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
529 uint16_t val, bool trace);
530 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
531 uint32_t val, bool trace);
532 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
533 uint64_t val, bool trace);
534 };
535
536 struct intel_uncore {
537 spinlock_t lock; /** lock is also taken in irq contexts. */
538
539 struct intel_uncore_funcs funcs;
540
541 unsigned fifo_count;
542 unsigned forcewake_count;
543
544 unsigned fw_rendercount;
545 unsigned fw_mediacount;
546
547 struct timer_list force_wake_timer;
548 };
549
550 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
551 func(is_mobile) sep \
552 func(is_i85x) sep \
553 func(is_i915g) sep \
554 func(is_i945gm) sep \
555 func(is_g33) sep \
556 func(need_gfx_hws) sep \
557 func(is_g4x) sep \
558 func(is_pineview) sep \
559 func(is_broadwater) sep \
560 func(is_crestline) sep \
561 func(is_ivybridge) sep \
562 func(is_valleyview) sep \
563 func(is_haswell) sep \
564 func(is_skylake) sep \
565 func(is_preliminary) sep \
566 func(has_fbc) sep \
567 func(has_pipe_cxsr) sep \
568 func(has_hotplug) sep \
569 func(cursor_needs_physical) sep \
570 func(has_overlay) sep \
571 func(overlay_needs_physical) sep \
572 func(supports_tv) sep \
573 func(has_llc) sep \
574 func(has_ddi) sep \
575 func(has_fpga_dbg)
576
577 #define DEFINE_FLAG(name) u8 name:1
578 #define SEP_SEMICOLON ;
579
580 struct intel_device_info {
581 u32 display_mmio_offset;
582 u16 device_id;
583 u8 num_pipes:3;
584 u8 num_sprites[I915_MAX_PIPES];
585 u8 gen;
586 u8 ring_mask; /* Rings supported by the HW */
587 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
588 /* Register offsets for the various display pipes and transcoders */
589 int pipe_offsets[I915_MAX_TRANSCODERS];
590 int trans_offsets[I915_MAX_TRANSCODERS];
591 int palette_offsets[I915_MAX_PIPES];
592 int cursor_offsets[I915_MAX_PIPES];
593 };
594
595 #undef DEFINE_FLAG
596 #undef SEP_SEMICOLON
597
598 enum i915_cache_level {
599 I915_CACHE_NONE = 0,
600 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
601 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
602 caches, eg sampler/render caches, and the
603 large Last-Level-Cache. LLC is coherent with
604 the CPU, but L3 is only visible to the GPU. */
605 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
606 };
607
608 struct i915_ctx_hang_stats {
609 /* This context had batch pending when hang was declared */
610 unsigned batch_pending;
611
612 /* This context had batch active when hang was declared */
613 unsigned batch_active;
614
615 /* Time when this context was last blamed for a GPU reset */
616 unsigned long guilty_ts;
617
618 /* This context is banned to submit more work */
619 bool banned;
620 };
621
622 /* This must match up with the value previously used for execbuf2.rsvd1. */
623 #define DEFAULT_CONTEXT_HANDLE 0
624 /**
625 * struct intel_context - as the name implies, represents a context.
626 * @ref: reference count.
627 * @user_handle: userspace tracking identity for this context.
628 * @remap_slice: l3 row remapping information.
629 * @file_priv: filp associated with this context (NULL for global default
630 * context).
631 * @hang_stats: information about the role of this context in possible GPU
632 * hangs.
633 * @vm: virtual memory space used by this context.
634 * @legacy_hw_ctx: render context backing object and whether it is correctly
635 * initialized (legacy ring submission mechanism only).
636 * @link: link in the global list of contexts.
637 *
638 * Contexts are memory images used by the hardware to store copies of their
639 * internal state.
640 */
641 struct intel_context {
642 struct kref ref;
643 int user_handle;
644 uint8_t remap_slice;
645 struct drm_i915_file_private *file_priv;
646 struct i915_ctx_hang_stats hang_stats;
647 struct i915_hw_ppgtt *ppgtt;
648
649 /* Legacy ring buffer submission */
650 struct {
651 struct drm_i915_gem_object *rcs_state;
652 bool initialized;
653 } legacy_hw_ctx;
654
655 /* Execlists */
656 bool rcs_initialized;
657 struct {
658 struct drm_i915_gem_object *state;
659 struct intel_ringbuffer *ringbuf;
660 } engine[I915_NUM_RINGS];
661
662 struct list_head link;
663 };
664
665 struct i915_fbc {
666 unsigned long size;
667 unsigned threshold;
668 unsigned int fb_id;
669 enum plane plane;
670 int y;
671
672 struct drm_mm_node compressed_fb;
673 struct drm_mm_node *compressed_llb;
674
675 bool false_color;
676
677 /* Tracks whether the HW is actually enabled, not whether the feature is
678 * possible. */
679 bool enabled;
680
681 /* On gen8 some rings cannont perform fbc clean operation so for now
682 * we are doing this on SW with mmio.
683 * This variable works in the opposite information direction
684 * of ring->fbc_dirty telling software on frontbuffer tracking
685 * to perform the cache clean on sw side.
686 */
687 bool need_sw_cache_clean;
688
689 struct intel_fbc_work {
690 struct delayed_work work;
691 struct drm_crtc *crtc;
692 struct drm_framebuffer *fb;
693 } *fbc_work;
694
695 enum no_fbc_reason {
696 FBC_OK, /* FBC is enabled */
697 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
698 FBC_NO_OUTPUT, /* no outputs enabled to compress */
699 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
700 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
701 FBC_MODE_TOO_LARGE, /* mode too large for compression */
702 FBC_BAD_PLANE, /* fbc not supported on plane */
703 FBC_NOT_TILED, /* buffer not tiled */
704 FBC_MULTIPLE_PIPES, /* more than one pipe active */
705 FBC_MODULE_PARAM,
706 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
707 } no_fbc_reason;
708 };
709
710 struct i915_drrs {
711 struct intel_connector *connector;
712 };
713
714 struct intel_dp;
715 struct i915_psr {
716 struct mutex lock;
717 bool sink_support;
718 bool source_ok;
719 struct intel_dp *enabled;
720 bool active;
721 struct delayed_work work;
722 unsigned busy_frontbuffer_bits;
723 };
724
725 enum intel_pch {
726 PCH_NONE = 0, /* No PCH present */
727 PCH_IBX, /* Ibexpeak PCH */
728 PCH_CPT, /* Cougarpoint PCH */
729 PCH_LPT, /* Lynxpoint PCH */
730 PCH_SPT, /* Sunrisepoint PCH */
731 PCH_NOP,
732 };
733
734 enum intel_sbi_destination {
735 SBI_ICLK,
736 SBI_MPHY,
737 };
738
739 #define QUIRK_PIPEA_FORCE (1<<0)
740 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
741 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
742 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
743 #define QUIRK_PIPEB_FORCE (1<<4)
744
745 struct intel_fbdev;
746 struct intel_fbc_work;
747
748 struct intel_gmbus {
749 struct i2c_adapter adapter;
750 u32 force_bit;
751 u32 reg0;
752 u32 gpio_reg;
753 struct i2c_algo_bit_data bit_algo;
754 struct drm_i915_private *dev_priv;
755 };
756
757 struct i915_suspend_saved_registers {
758 u8 saveLBB;
759 u32 saveDSPACNTR;
760 u32 saveDSPBCNTR;
761 u32 saveDSPARB;
762 u32 savePIPEACONF;
763 u32 savePIPEBCONF;
764 u32 savePIPEASRC;
765 u32 savePIPEBSRC;
766 u32 saveFPA0;
767 u32 saveFPA1;
768 u32 saveDPLL_A;
769 u32 saveDPLL_A_MD;
770 u32 saveHTOTAL_A;
771 u32 saveHBLANK_A;
772 u32 saveHSYNC_A;
773 u32 saveVTOTAL_A;
774 u32 saveVBLANK_A;
775 u32 saveVSYNC_A;
776 u32 saveBCLRPAT_A;
777 u32 saveTRANSACONF;
778 u32 saveTRANS_HTOTAL_A;
779 u32 saveTRANS_HBLANK_A;
780 u32 saveTRANS_HSYNC_A;
781 u32 saveTRANS_VTOTAL_A;
782 u32 saveTRANS_VBLANK_A;
783 u32 saveTRANS_VSYNC_A;
784 u32 savePIPEASTAT;
785 u32 saveDSPASTRIDE;
786 u32 saveDSPASIZE;
787 u32 saveDSPAPOS;
788 u32 saveDSPAADDR;
789 u32 saveDSPASURF;
790 u32 saveDSPATILEOFF;
791 u32 savePFIT_PGM_RATIOS;
792 u32 saveBLC_HIST_CTL;
793 u32 saveBLC_PWM_CTL;
794 u32 saveBLC_PWM_CTL2;
795 u32 saveBLC_HIST_CTL_B;
796 u32 saveBLC_CPU_PWM_CTL;
797 u32 saveBLC_CPU_PWM_CTL2;
798 u32 saveFPB0;
799 u32 saveFPB1;
800 u32 saveDPLL_B;
801 u32 saveDPLL_B_MD;
802 u32 saveHTOTAL_B;
803 u32 saveHBLANK_B;
804 u32 saveHSYNC_B;
805 u32 saveVTOTAL_B;
806 u32 saveVBLANK_B;
807 u32 saveVSYNC_B;
808 u32 saveBCLRPAT_B;
809 u32 saveTRANSBCONF;
810 u32 saveTRANS_HTOTAL_B;
811 u32 saveTRANS_HBLANK_B;
812 u32 saveTRANS_HSYNC_B;
813 u32 saveTRANS_VTOTAL_B;
814 u32 saveTRANS_VBLANK_B;
815 u32 saveTRANS_VSYNC_B;
816 u32 savePIPEBSTAT;
817 u32 saveDSPBSTRIDE;
818 u32 saveDSPBSIZE;
819 u32 saveDSPBPOS;
820 u32 saveDSPBADDR;
821 u32 saveDSPBSURF;
822 u32 saveDSPBTILEOFF;
823 u32 saveVGA0;
824 u32 saveVGA1;
825 u32 saveVGA_PD;
826 u32 saveVGACNTRL;
827 u32 saveADPA;
828 u32 saveLVDS;
829 u32 savePP_ON_DELAYS;
830 u32 savePP_OFF_DELAYS;
831 u32 saveDVOA;
832 u32 saveDVOB;
833 u32 saveDVOC;
834 u32 savePP_ON;
835 u32 savePP_OFF;
836 u32 savePP_CONTROL;
837 u32 savePP_DIVISOR;
838 u32 savePFIT_CONTROL;
839 u32 save_palette_a[256];
840 u32 save_palette_b[256];
841 u32 saveFBC_CONTROL;
842 u32 saveIER;
843 u32 saveIIR;
844 u32 saveIMR;
845 u32 saveDEIER;
846 u32 saveDEIMR;
847 u32 saveGTIER;
848 u32 saveGTIMR;
849 u32 saveFDI_RXA_IMR;
850 u32 saveFDI_RXB_IMR;
851 u32 saveCACHE_MODE_0;
852 u32 saveMI_ARB_STATE;
853 u32 saveSWF0[16];
854 u32 saveSWF1[16];
855 u32 saveSWF2[3];
856 u8 saveMSR;
857 u8 saveSR[8];
858 u8 saveGR[25];
859 u8 saveAR_INDEX;
860 u8 saveAR[21];
861 u8 saveDACMASK;
862 u8 saveCR[37];
863 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
864 u32 saveCURACNTR;
865 u32 saveCURAPOS;
866 u32 saveCURABASE;
867 u32 saveCURBCNTR;
868 u32 saveCURBPOS;
869 u32 saveCURBBASE;
870 u32 saveCURSIZE;
871 u32 saveDP_B;
872 u32 saveDP_C;
873 u32 saveDP_D;
874 u32 savePIPEA_GMCH_DATA_M;
875 u32 savePIPEB_GMCH_DATA_M;
876 u32 savePIPEA_GMCH_DATA_N;
877 u32 savePIPEB_GMCH_DATA_N;
878 u32 savePIPEA_DP_LINK_M;
879 u32 savePIPEB_DP_LINK_M;
880 u32 savePIPEA_DP_LINK_N;
881 u32 savePIPEB_DP_LINK_N;
882 u32 saveFDI_RXA_CTL;
883 u32 saveFDI_TXA_CTL;
884 u32 saveFDI_RXB_CTL;
885 u32 saveFDI_TXB_CTL;
886 u32 savePFA_CTL_1;
887 u32 savePFB_CTL_1;
888 u32 savePFA_WIN_SZ;
889 u32 savePFB_WIN_SZ;
890 u32 savePFA_WIN_POS;
891 u32 savePFB_WIN_POS;
892 u32 savePCH_DREF_CONTROL;
893 u32 saveDISP_ARB_CTL;
894 u32 savePIPEA_DATA_M1;
895 u32 savePIPEA_DATA_N1;
896 u32 savePIPEA_LINK_M1;
897 u32 savePIPEA_LINK_N1;
898 u32 savePIPEB_DATA_M1;
899 u32 savePIPEB_DATA_N1;
900 u32 savePIPEB_LINK_M1;
901 u32 savePIPEB_LINK_N1;
902 u32 saveMCHBAR_RENDER_STANDBY;
903 u32 savePCH_PORT_HOTPLUG;
904 };
905
906 struct vlv_s0ix_state {
907 /* GAM */
908 u32 wr_watermark;
909 u32 gfx_prio_ctrl;
910 u32 arb_mode;
911 u32 gfx_pend_tlb0;
912 u32 gfx_pend_tlb1;
913 u32 lra_limits[GEN7_LRA_LIMITS_REG_NUM];
914 u32 media_max_req_count;
915 u32 gfx_max_req_count;
916 u32 render_hwsp;
917 u32 ecochk;
918 u32 bsd_hwsp;
919 u32 blt_hwsp;
920 u32 tlb_rd_addr;
921
922 /* MBC */
923 u32 g3dctl;
924 u32 gsckgctl;
925 u32 mbctl;
926
927 /* GCP */
928 u32 ucgctl1;
929 u32 ucgctl3;
930 u32 rcgctl1;
931 u32 rcgctl2;
932 u32 rstctl;
933 u32 misccpctl;
934
935 /* GPM */
936 u32 gfxpause;
937 u32 rpdeuhwtc;
938 u32 rpdeuc;
939 u32 ecobus;
940 u32 pwrdwnupctl;
941 u32 rp_down_timeout;
942 u32 rp_deucsw;
943 u32 rcubmabdtmr;
944 u32 rcedata;
945 u32 spare2gh;
946
947 /* Display 1 CZ domain */
948 u32 gt_imr;
949 u32 gt_ier;
950 u32 pm_imr;
951 u32 pm_ier;
952 u32 gt_scratch[GEN7_GT_SCRATCH_REG_NUM];
953
954 /* GT SA CZ domain */
955 u32 tilectl;
956 u32 gt_fifoctl;
957 u32 gtlc_wake_ctrl;
958 u32 gtlc_survive;
959 u32 pmwgicz;
960
961 /* Display 2 CZ domain */
962 u32 gu_ctl0;
963 u32 gu_ctl1;
964 u32 clock_gate_dis2;
965 };
966
967 struct intel_rps_ei {
968 u32 cz_clock;
969 u32 render_c0;
970 u32 media_c0;
971 };
972
973 struct intel_gen6_power_mgmt {
974 /* work and pm_iir are protected by dev_priv->irq_lock */
975 struct work_struct work;
976 u32 pm_iir;
977
978 /* Frequencies are stored in potentially platform dependent multiples.
979 * In other words, *_freq needs to be multiplied by X to be interesting.
980 * Soft limits are those which are used for the dynamic reclocking done
981 * by the driver (raise frequencies under heavy loads, and lower for
982 * lighter loads). Hard limits are those imposed by the hardware.
983 *
984 * A distinction is made for overclocking, which is never enabled by
985 * default, and is considered to be above the hard limit if it's
986 * possible at all.
987 */
988 u8 cur_freq; /* Current frequency (cached, may not == HW) */
989 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
990 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
991 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
992 u8 min_freq; /* AKA RPn. Minimum frequency */
993 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
994 u8 rp1_freq; /* "less than" RP0 power/freqency */
995 u8 rp0_freq; /* Non-overclocked max frequency. */
996 u32 cz_freq;
997
998 u32 ei_interrupt_count;
999
1000 int last_adj;
1001 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
1002
1003 bool enabled;
1004 struct delayed_work delayed_resume_work;
1005
1006 /* manual wa residency calculations */
1007 struct intel_rps_ei up_ei, down_ei;
1008
1009 /*
1010 * Protects RPS/RC6 register access and PCU communication.
1011 * Must be taken after struct_mutex if nested.
1012 */
1013 struct mutex hw_lock;
1014 };
1015
1016 /* defined intel_pm.c */
1017 extern spinlock_t mchdev_lock;
1018
1019 struct intel_ilk_power_mgmt {
1020 u8 cur_delay;
1021 u8 min_delay;
1022 u8 max_delay;
1023 u8 fmax;
1024 u8 fstart;
1025
1026 u64 last_count1;
1027 unsigned long last_time1;
1028 unsigned long chipset_power;
1029 u64 last_count2;
1030 u64 last_time2;
1031 unsigned long gfx_power;
1032 u8 corr;
1033
1034 int c_m;
1035 int r_t;
1036
1037 struct drm_i915_gem_object *pwrctx;
1038 struct drm_i915_gem_object *renderctx;
1039 };
1040
1041 struct drm_i915_private;
1042 struct i915_power_well;
1043
1044 struct i915_power_well_ops {
1045 /*
1046 * Synchronize the well's hw state to match the current sw state, for
1047 * example enable/disable it based on the current refcount. Called
1048 * during driver init and resume time, possibly after first calling
1049 * the enable/disable handlers.
1050 */
1051 void (*sync_hw)(struct drm_i915_private *dev_priv,
1052 struct i915_power_well *power_well);
1053 /*
1054 * Enable the well and resources that depend on it (for example
1055 * interrupts located on the well). Called after the 0->1 refcount
1056 * transition.
1057 */
1058 void (*enable)(struct drm_i915_private *dev_priv,
1059 struct i915_power_well *power_well);
1060 /*
1061 * Disable the well and resources that depend on it. Called after
1062 * the 1->0 refcount transition.
1063 */
1064 void (*disable)(struct drm_i915_private *dev_priv,
1065 struct i915_power_well *power_well);
1066 /* Returns the hw enabled state. */
1067 bool (*is_enabled)(struct drm_i915_private *dev_priv,
1068 struct i915_power_well *power_well);
1069 };
1070
1071 /* Power well structure for haswell */
1072 struct i915_power_well {
1073 const char *name;
1074 bool always_on;
1075 /* power well enable/disable usage count */
1076 int count;
1077 /* cached hw enabled state */
1078 bool hw_enabled;
1079 unsigned long domains;
1080 unsigned long data;
1081 const struct i915_power_well_ops *ops;
1082 };
1083
1084 struct i915_power_domains {
1085 /*
1086 * Power wells needed for initialization at driver init and suspend
1087 * time are on. They are kept on until after the first modeset.
1088 */
1089 bool init_power_on;
1090 bool initializing;
1091 int power_well_count;
1092
1093 struct mutex lock;
1094 int domain_use_count[POWER_DOMAIN_NUM];
1095 struct i915_power_well *power_wells;
1096 };
1097
1098 struct i915_dri1_state {
1099 unsigned allow_batchbuffer : 1;
1100 u32 __iomem *gfx_hws_cpu_addr;
1101
1102 unsigned int cpp;
1103 int back_offset;
1104 int front_offset;
1105 int current_page;
1106 int page_flipping;
1107
1108 uint32_t counter;
1109 };
1110
1111 struct i915_ums_state {
1112 /**
1113 * Flag if the X Server, and thus DRM, is not currently in
1114 * control of the device.
1115 *
1116 * This is set between LeaveVT and EnterVT. It needs to be
1117 * replaced with a semaphore. It also needs to be
1118 * transitioned away from for kernel modesetting.
1119 */
1120 int mm_suspended;
1121 };
1122
1123 #define MAX_L3_SLICES 2
1124 struct intel_l3_parity {
1125 u32 *remap_info[MAX_L3_SLICES];
1126 struct work_struct error_work;
1127 int which_slice;
1128 };
1129
1130 struct i915_gem_mm {
1131 /** Memory allocator for GTT stolen memory */
1132 struct drm_mm stolen;
1133 /** List of all objects in gtt_space. Used to restore gtt
1134 * mappings on resume */
1135 struct list_head bound_list;
1136 /**
1137 * List of objects which are not bound to the GTT (thus
1138 * are idle and not used by the GPU) but still have
1139 * (presumably uncached) pages still attached.
1140 */
1141 struct list_head unbound_list;
1142
1143 /** Usable portion of the GTT for GEM */
1144 unsigned long stolen_base; /* limited to low memory (32-bit) */
1145
1146 /** PPGTT used for aliasing the PPGTT with the GTT */
1147 struct i915_hw_ppgtt *aliasing_ppgtt;
1148
1149 struct notifier_block oom_notifier;
1150 struct shrinker shrinker;
1151 bool shrinker_no_lock_stealing;
1152
1153 /** LRU list of objects with fence regs on them. */
1154 struct list_head fence_list;
1155
1156 /**
1157 * We leave the user IRQ off as much as possible,
1158 * but this means that requests will finish and never
1159 * be retired once the system goes idle. Set a timer to
1160 * fire periodically while the ring is running. When it
1161 * fires, go retire requests.
1162 */
1163 struct delayed_work retire_work;
1164
1165 /**
1166 * When we detect an idle GPU, we want to turn on
1167 * powersaving features. So once we see that there
1168 * are no more requests outstanding and no more
1169 * arrive within a small period of time, we fire
1170 * off the idle_work.
1171 */
1172 struct delayed_work idle_work;
1173
1174 /**
1175 * Are we in a non-interruptible section of code like
1176 * modesetting?
1177 */
1178 bool interruptible;
1179
1180 /**
1181 * Is the GPU currently considered idle, or busy executing userspace
1182 * requests? Whilst idle, we attempt to power down the hardware and
1183 * display clocks. In order to reduce the effect on performance, there
1184 * is a slight delay before we do so.
1185 */
1186 bool busy;
1187
1188 /* the indicator for dispatch video commands on two BSD rings */
1189 int bsd_ring_dispatch_index;
1190
1191 /** Bit 6 swizzling required for X tiling */
1192 uint32_t bit_6_swizzle_x;
1193 /** Bit 6 swizzling required for Y tiling */
1194 uint32_t bit_6_swizzle_y;
1195
1196 /* accounting, useful for userland debugging */
1197 spinlock_t object_stat_lock;
1198 size_t object_memory;
1199 u32 object_count;
1200 };
1201
1202 struct drm_i915_error_state_buf {
1203 struct drm_i915_private *i915;
1204 unsigned bytes;
1205 unsigned size;
1206 int err;
1207 u8 *buf;
1208 loff_t start;
1209 loff_t pos;
1210 };
1211
1212 struct i915_error_state_file_priv {
1213 struct drm_device *dev;
1214 struct drm_i915_error_state *error;
1215 };
1216
1217 struct i915_gpu_error {
1218 /* For hangcheck timer */
1219 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1220 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1221 /* Hang gpu twice in this window and your context gets banned */
1222 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1223
1224 struct timer_list hangcheck_timer;
1225
1226 /* For reset and error_state handling. */
1227 spinlock_t lock;
1228 /* Protected by the above dev->gpu_error.lock. */
1229 struct drm_i915_error_state *first_error;
1230 struct work_struct work;
1231
1232
1233 unsigned long missed_irq_rings;
1234
1235 /**
1236 * State variable controlling the reset flow and count
1237 *
1238 * This is a counter which gets incremented when reset is triggered,
1239 * and again when reset has been handled. So odd values (lowest bit set)
1240 * means that reset is in progress and even values that
1241 * (reset_counter >> 1):th reset was successfully completed.
1242 *
1243 * If reset is not completed succesfully, the I915_WEDGE bit is
1244 * set meaning that hardware is terminally sour and there is no
1245 * recovery. All waiters on the reset_queue will be woken when
1246 * that happens.
1247 *
1248 * This counter is used by the wait_seqno code to notice that reset
1249 * event happened and it needs to restart the entire ioctl (since most
1250 * likely the seqno it waited for won't ever signal anytime soon).
1251 *
1252 * This is important for lock-free wait paths, where no contended lock
1253 * naturally enforces the correct ordering between the bail-out of the
1254 * waiter and the gpu reset work code.
1255 */
1256 atomic_t reset_counter;
1257
1258 #define I915_RESET_IN_PROGRESS_FLAG 1
1259 #define I915_WEDGED (1 << 31)
1260
1261 /**
1262 * Waitqueue to signal when the reset has completed. Used by clients
1263 * that wait for dev_priv->mm.wedged to settle.
1264 */
1265 wait_queue_head_t reset_queue;
1266
1267 /* Userspace knobs for gpu hang simulation;
1268 * combines both a ring mask, and extra flags
1269 */
1270 u32 stop_rings;
1271 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1272 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1273
1274 /* For missed irq/seqno simulation. */
1275 unsigned int test_irq_rings;
1276
1277 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1278 bool reload_in_reset;
1279 };
1280
1281 enum modeset_restore {
1282 MODESET_ON_LID_OPEN,
1283 MODESET_DONE,
1284 MODESET_SUSPENDED,
1285 };
1286
1287 struct ddi_vbt_port_info {
1288 /*
1289 * This is an index in the HDMI/DVI DDI buffer translation table.
1290 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1291 * populate this field.
1292 */
1293 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1294 uint8_t hdmi_level_shift;
1295
1296 uint8_t supports_dvi:1;
1297 uint8_t supports_hdmi:1;
1298 uint8_t supports_dp:1;
1299 };
1300
1301 enum drrs_support_type {
1302 DRRS_NOT_SUPPORTED = 0,
1303 STATIC_DRRS_SUPPORT = 1,
1304 SEAMLESS_DRRS_SUPPORT = 2
1305 };
1306
1307 struct intel_vbt_data {
1308 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1309 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1310
1311 /* Feature bits */
1312 unsigned int int_tv_support:1;
1313 unsigned int lvds_dither:1;
1314 unsigned int lvds_vbt:1;
1315 unsigned int int_crt_support:1;
1316 unsigned int lvds_use_ssc:1;
1317 unsigned int display_clock_mode:1;
1318 unsigned int fdi_rx_polarity_inverted:1;
1319 unsigned int has_mipi:1;
1320 int lvds_ssc_freq;
1321 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1322
1323 enum drrs_support_type drrs_type;
1324
1325 /* eDP */
1326 int edp_rate;
1327 int edp_lanes;
1328 int edp_preemphasis;
1329 int edp_vswing;
1330 bool edp_initialized;
1331 bool edp_support;
1332 int edp_bpp;
1333 struct edp_power_seq edp_pps;
1334
1335 struct {
1336 u16 pwm_freq_hz;
1337 bool present;
1338 bool active_low_pwm;
1339 u8 min_brightness; /* min_brightness/255 of max */
1340 } backlight;
1341
1342 /* MIPI DSI */
1343 struct {
1344 u16 port;
1345 u16 panel_id;
1346 struct mipi_config *config;
1347 struct mipi_pps_data *pps;
1348 u8 seq_version;
1349 u32 size;
1350 u8 *data;
1351 u8 *sequence[MIPI_SEQ_MAX];
1352 } dsi;
1353
1354 int crt_ddc_pin;
1355
1356 int child_dev_num;
1357 union child_device_config *child_dev;
1358
1359 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1360 };
1361
1362 enum intel_ddb_partitioning {
1363 INTEL_DDB_PART_1_2,
1364 INTEL_DDB_PART_5_6, /* IVB+ */
1365 };
1366
1367 struct intel_wm_level {
1368 bool enable;
1369 uint32_t pri_val;
1370 uint32_t spr_val;
1371 uint32_t cur_val;
1372 uint32_t fbc_val;
1373 };
1374
1375 struct ilk_wm_values {
1376 uint32_t wm_pipe[3];
1377 uint32_t wm_lp[3];
1378 uint32_t wm_lp_spr[3];
1379 uint32_t wm_linetime[3];
1380 bool enable_fbc_wm;
1381 enum intel_ddb_partitioning partitioning;
1382 };
1383
1384 /*
1385 * This struct helps tracking the state needed for runtime PM, which puts the
1386 * device in PCI D3 state. Notice that when this happens, nothing on the
1387 * graphics device works, even register access, so we don't get interrupts nor
1388 * anything else.
1389 *
1390 * Every piece of our code that needs to actually touch the hardware needs to
1391 * either call intel_runtime_pm_get or call intel_display_power_get with the
1392 * appropriate power domain.
1393 *
1394 * Our driver uses the autosuspend delay feature, which means we'll only really
1395 * suspend if we stay with zero refcount for a certain amount of time. The
1396 * default value is currently very conservative (see intel_runtime_pm_enable), but
1397 * it can be changed with the standard runtime PM files from sysfs.
1398 *
1399 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1400 * goes back to false exactly before we reenable the IRQs. We use this variable
1401 * to check if someone is trying to enable/disable IRQs while they're supposed
1402 * to be disabled. This shouldn't happen and we'll print some error messages in
1403 * case it happens.
1404 *
1405 * For more, read the Documentation/power/runtime_pm.txt.
1406 */
1407 struct i915_runtime_pm {
1408 bool suspended;
1409 bool irqs_enabled;
1410 };
1411
1412 enum intel_pipe_crc_source {
1413 INTEL_PIPE_CRC_SOURCE_NONE,
1414 INTEL_PIPE_CRC_SOURCE_PLANE1,
1415 INTEL_PIPE_CRC_SOURCE_PLANE2,
1416 INTEL_PIPE_CRC_SOURCE_PF,
1417 INTEL_PIPE_CRC_SOURCE_PIPE,
1418 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1419 INTEL_PIPE_CRC_SOURCE_TV,
1420 INTEL_PIPE_CRC_SOURCE_DP_B,
1421 INTEL_PIPE_CRC_SOURCE_DP_C,
1422 INTEL_PIPE_CRC_SOURCE_DP_D,
1423 INTEL_PIPE_CRC_SOURCE_AUTO,
1424 INTEL_PIPE_CRC_SOURCE_MAX,
1425 };
1426
1427 struct intel_pipe_crc_entry {
1428 uint32_t frame;
1429 uint32_t crc[5];
1430 };
1431
1432 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1433 struct intel_pipe_crc {
1434 spinlock_t lock;
1435 bool opened; /* exclusive access to the result file */
1436 struct intel_pipe_crc_entry *entries;
1437 enum intel_pipe_crc_source source;
1438 int head, tail;
1439 wait_queue_head_t wq;
1440 };
1441
1442 struct i915_frontbuffer_tracking {
1443 struct mutex lock;
1444
1445 /*
1446 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1447 * scheduled flips.
1448 */
1449 unsigned busy_bits;
1450 unsigned flip_bits;
1451 };
1452
1453 struct i915_wa_reg {
1454 u32 addr;
1455 u32 value;
1456 /* bitmask representing WA bits */
1457 u32 mask;
1458 };
1459
1460 #define I915_MAX_WA_REGS 16
1461
1462 struct i915_workarounds {
1463 struct i915_wa_reg reg[I915_MAX_WA_REGS];
1464 u32 count;
1465 };
1466
1467 struct drm_i915_private {
1468 struct drm_device *dev;
1469 struct kmem_cache *slab;
1470
1471 const struct intel_device_info info;
1472
1473 int relative_constants_mode;
1474
1475 void __iomem *regs;
1476
1477 struct intel_uncore uncore;
1478
1479 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1480
1481
1482 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1483 * controller on different i2c buses. */
1484 struct mutex gmbus_mutex;
1485
1486 /**
1487 * Base address of the gmbus and gpio block.
1488 */
1489 uint32_t gpio_mmio_base;
1490
1491 /* MMIO base address for MIPI regs */
1492 uint32_t mipi_mmio_base;
1493
1494 wait_queue_head_t gmbus_wait_queue;
1495
1496 struct pci_dev *bridge_dev;
1497 struct intel_engine_cs ring[I915_NUM_RINGS];
1498 struct drm_i915_gem_object *semaphore_obj;
1499 uint32_t last_seqno, next_seqno;
1500
1501 struct drm_dma_handle *status_page_dmah;
1502 struct resource mch_res;
1503
1504 /* protects the irq masks */
1505 spinlock_t irq_lock;
1506
1507 /* protects the mmio flip data */
1508 spinlock_t mmio_flip_lock;
1509
1510 bool display_irqs_enabled;
1511
1512 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1513 struct pm_qos_request pm_qos;
1514
1515 /* DPIO indirect register protection */
1516 struct mutex dpio_lock;
1517
1518 /** Cached value of IMR to avoid reads in updating the bitfield */
1519 union {
1520 u32 irq_mask;
1521 u32 de_irq_mask[I915_MAX_PIPES];
1522 };
1523 u32 gt_irq_mask;
1524 u32 pm_irq_mask;
1525 u32 pm_rps_events;
1526 u32 pipestat_irq_mask[I915_MAX_PIPES];
1527
1528 struct work_struct hotplug_work;
1529 struct {
1530 unsigned long hpd_last_jiffies;
1531 int hpd_cnt;
1532 enum {
1533 HPD_ENABLED = 0,
1534 HPD_DISABLED = 1,
1535 HPD_MARK_DISABLED = 2
1536 } hpd_mark;
1537 } hpd_stats[HPD_NUM_PINS];
1538 u32 hpd_event_bits;
1539 struct delayed_work hotplug_reenable_work;
1540
1541 struct i915_fbc fbc;
1542 struct i915_drrs drrs;
1543 struct intel_opregion opregion;
1544 struct intel_vbt_data vbt;
1545
1546 bool preserve_bios_swizzle;
1547
1548 /* overlay */
1549 struct intel_overlay *overlay;
1550
1551 /* backlight registers and fields in struct intel_panel */
1552 struct mutex backlight_lock;
1553
1554 /* LVDS info */
1555 bool no_aux_handshake;
1556
1557 /* protects panel power sequencer state */
1558 struct mutex pps_mutex;
1559
1560 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1561 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1562 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1563
1564 unsigned int fsb_freq, mem_freq, is_ddr3;
1565 unsigned int vlv_cdclk_freq;
1566
1567 /**
1568 * wq - Driver workqueue for GEM.
1569 *
1570 * NOTE: Work items scheduled here are not allowed to grab any modeset
1571 * locks, for otherwise the flushing done in the pageflip code will
1572 * result in deadlocks.
1573 */
1574 struct workqueue_struct *wq;
1575
1576 /* Display functions */
1577 struct drm_i915_display_funcs display;
1578
1579 /* PCH chipset type */
1580 enum intel_pch pch_type;
1581 unsigned short pch_id;
1582
1583 unsigned long quirks;
1584
1585 enum modeset_restore modeset_restore;
1586 struct mutex modeset_restore_lock;
1587
1588 struct list_head vm_list; /* Global list of all address spaces */
1589 struct i915_gtt gtt; /* VM representing the global address space */
1590
1591 struct i915_gem_mm mm;
1592 DECLARE_HASHTABLE(mm_structs, 7);
1593 struct mutex mm_lock;
1594
1595 /* Kernel Modesetting */
1596
1597 struct sdvo_device_mapping sdvo_mappings[2];
1598
1599 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1600 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1601 wait_queue_head_t pending_flip_queue;
1602
1603 #ifdef CONFIG_DEBUG_FS
1604 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1605 #endif
1606
1607 int num_shared_dpll;
1608 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1609 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1610
1611 struct i915_workarounds workarounds;
1612
1613 /* Reclocking support */
1614 bool render_reclock_avail;
1615 bool lvds_downclock_avail;
1616 /* indicates the reduced downclock for LVDS*/
1617 int lvds_downclock;
1618
1619 struct i915_frontbuffer_tracking fb_tracking;
1620
1621 u16 orig_clock;
1622
1623 bool mchbar_need_disable;
1624
1625 struct intel_l3_parity l3_parity;
1626
1627 /* Cannot be determined by PCIID. You must always read a register. */
1628 size_t ellc_size;
1629
1630 /* gen6+ rps state */
1631 struct intel_gen6_power_mgmt rps;
1632
1633 /* ilk-only ips/rps state. Everything in here is protected by the global
1634 * mchdev_lock in intel_pm.c */
1635 struct intel_ilk_power_mgmt ips;
1636
1637 struct i915_power_domains power_domains;
1638
1639 struct i915_psr psr;
1640
1641 struct i915_gpu_error gpu_error;
1642
1643 struct drm_i915_gem_object *vlv_pctx;
1644
1645 #ifdef CONFIG_DRM_I915_FBDEV
1646 /* list of fbdev register on this device */
1647 struct intel_fbdev *fbdev;
1648 struct work_struct fbdev_suspend_work;
1649 #endif
1650
1651 struct drm_property *broadcast_rgb_property;
1652 struct drm_property *force_audio_property;
1653
1654 uint32_t hw_context_size;
1655 struct list_head context_list;
1656
1657 u32 fdi_rx_config;
1658
1659 u32 suspend_count;
1660 struct i915_suspend_saved_registers regfile;
1661 struct vlv_s0ix_state vlv_s0ix_state;
1662
1663 struct {
1664 /*
1665 * Raw watermark latency values:
1666 * in 0.1us units for WM0,
1667 * in 0.5us units for WM1+.
1668 */
1669 /* primary */
1670 uint16_t pri_latency[5];
1671 /* sprite */
1672 uint16_t spr_latency[5];
1673 /* cursor */
1674 uint16_t cur_latency[5];
1675
1676 /* current hardware state */
1677 struct ilk_wm_values hw;
1678 } wm;
1679
1680 struct i915_runtime_pm pm;
1681
1682 struct intel_digital_port *hpd_irq_port[I915_MAX_PORTS];
1683 u32 long_hpd_port_mask;
1684 u32 short_hpd_port_mask;
1685 struct work_struct dig_port_work;
1686
1687 /*
1688 * if we get a HPD irq from DP and a HPD irq from non-DP
1689 * the non-DP HPD could block the workqueue on a mode config
1690 * mutex getting, that userspace may have taken. However
1691 * userspace is waiting on the DP workqueue to run which is
1692 * blocked behind the non-DP one.
1693 */
1694 struct workqueue_struct *dp_wq;
1695
1696 uint32_t bios_vgacntr;
1697
1698 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1699 * here! */
1700 struct i915_dri1_state dri1;
1701 /* Old ums support infrastructure, same warning applies. */
1702 struct i915_ums_state ums;
1703
1704 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1705 struct {
1706 int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
1707 struct intel_engine_cs *ring,
1708 struct intel_context *ctx,
1709 struct drm_i915_gem_execbuffer2 *args,
1710 struct list_head *vmas,
1711 struct drm_i915_gem_object *batch_obj,
1712 u64 exec_start, u32 flags);
1713 int (*init_rings)(struct drm_device *dev);
1714 void (*cleanup_ring)(struct intel_engine_cs *ring);
1715 void (*stop_ring)(struct intel_engine_cs *ring);
1716 } gt;
1717
1718 /*
1719 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1720 * will be rejected. Instead look for a better place.
1721 */
1722 };
1723
1724 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1725 {
1726 return dev->dev_private;
1727 }
1728
1729 /* Iterate over initialised rings */
1730 #define for_each_ring(ring__, dev_priv__, i__) \
1731 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1732 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1733
1734 enum hdmi_force_audio {
1735 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1736 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1737 HDMI_AUDIO_AUTO, /* trust EDID */
1738 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1739 };
1740
1741 #define I915_GTT_OFFSET_NONE ((u32)-1)
1742
1743 struct drm_i915_gem_object_ops {
1744 /* Interface between the GEM object and its backing storage.
1745 * get_pages() is called once prior to the use of the associated set
1746 * of pages before to binding them into the GTT, and put_pages() is
1747 * called after we no longer need them. As we expect there to be
1748 * associated cost with migrating pages between the backing storage
1749 * and making them available for the GPU (e.g. clflush), we may hold
1750 * onto the pages after they are no longer referenced by the GPU
1751 * in case they may be used again shortly (for example migrating the
1752 * pages to a different memory domain within the GTT). put_pages()
1753 * will therefore most likely be called when the object itself is
1754 * being released or under memory pressure (where we attempt to
1755 * reap pages for the shrinker).
1756 */
1757 int (*get_pages)(struct drm_i915_gem_object *);
1758 void (*put_pages)(struct drm_i915_gem_object *);
1759 int (*dmabuf_export)(struct drm_i915_gem_object *);
1760 void (*release)(struct drm_i915_gem_object *);
1761 };
1762
1763 /*
1764 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1765 * considered to be the frontbuffer for the given plane interface-vise. This
1766 * doesn't mean that the hw necessarily already scans it out, but that any
1767 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1768 *
1769 * We have one bit per pipe and per scanout plane type.
1770 */
1771 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1772 #define INTEL_FRONTBUFFER_BITS \
1773 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1774 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1775 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1776 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1777 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1778 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1779 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1780 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1781 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1782 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1783 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1784
1785 struct drm_i915_gem_object {
1786 struct drm_gem_object base;
1787
1788 const struct drm_i915_gem_object_ops *ops;
1789
1790 /** List of VMAs backed by this object */
1791 struct list_head vma_list;
1792
1793 /** Stolen memory for this object, instead of being backed by shmem. */
1794 struct drm_mm_node *stolen;
1795 struct list_head global_list;
1796
1797 struct list_head ring_list;
1798 /** Used in execbuf to temporarily hold a ref */
1799 struct list_head obj_exec_link;
1800
1801 /**
1802 * This is set if the object is on the active lists (has pending
1803 * rendering and so a non-zero seqno), and is not set if it i s on
1804 * inactive (ready to be unbound) list.
1805 */
1806 unsigned int active:1;
1807
1808 /**
1809 * This is set if the object has been written to since last bound
1810 * to the GTT
1811 */
1812 unsigned int dirty:1;
1813
1814 /**
1815 * Fence register bits (if any) for this object. Will be set
1816 * as needed when mapped into the GTT.
1817 * Protected by dev->struct_mutex.
1818 */
1819 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1820
1821 /**
1822 * Advice: are the backing pages purgeable?
1823 */
1824 unsigned int madv:2;
1825
1826 /**
1827 * Current tiling mode for the object.
1828 */
1829 unsigned int tiling_mode:2;
1830 /**
1831 * Whether the tiling parameters for the currently associated fence
1832 * register have changed. Note that for the purposes of tracking
1833 * tiling changes we also treat the unfenced register, the register
1834 * slot that the object occupies whilst it executes a fenced
1835 * command (such as BLT on gen2/3), as a "fence".
1836 */
1837 unsigned int fence_dirty:1;
1838
1839 /**
1840 * Is the object at the current location in the gtt mappable and
1841 * fenceable? Used to avoid costly recalculations.
1842 */
1843 unsigned int map_and_fenceable:1;
1844
1845 /**
1846 * Whether the current gtt mapping needs to be mappable (and isn't just
1847 * mappable by accident). Track pin and fault separate for a more
1848 * accurate mappable working set.
1849 */
1850 unsigned int fault_mappable:1;
1851 unsigned int pin_mappable:1;
1852 unsigned int pin_display:1;
1853
1854 /*
1855 * Is the object to be mapped as read-only to the GPU
1856 * Only honoured if hardware has relevant pte bit
1857 */
1858 unsigned long gt_ro:1;
1859 unsigned int cache_level:3;
1860
1861 unsigned int has_dma_mapping:1;
1862
1863 unsigned int frontbuffer_bits:INTEL_FRONTBUFFER_BITS;
1864
1865 struct sg_table *pages;
1866 int pages_pin_count;
1867
1868 /* prime dma-buf support */
1869 void *dma_buf_vmapping;
1870 int vmapping_count;
1871
1872 struct intel_engine_cs *ring;
1873
1874 /** Breadcrumb of last rendering to the buffer. */
1875 uint32_t last_read_seqno;
1876 uint32_t last_write_seqno;
1877 /** Breadcrumb of last fenced GPU access to the buffer. */
1878 uint32_t last_fenced_seqno;
1879
1880 /** Current tiling stride for the object, if it's tiled. */
1881 uint32_t stride;
1882
1883 /** References from framebuffers, locks out tiling changes. */
1884 unsigned long framebuffer_references;
1885
1886 /** Record of address bit 17 of each page at last unbind. */
1887 unsigned long *bit_17;
1888
1889 /** User space pin count and filp owning the pin */
1890 unsigned long user_pin_count;
1891 struct drm_file *pin_filp;
1892
1893 /** for phy allocated objects */
1894 struct drm_dma_handle *phys_handle;
1895
1896 union {
1897 struct i915_gem_userptr {
1898 uintptr_t ptr;
1899 unsigned read_only :1;
1900 unsigned workers :4;
1901 #define I915_GEM_USERPTR_MAX_WORKERS 15
1902
1903 struct i915_mm_struct *mm;
1904 struct i915_mmu_object *mmu_object;
1905 struct work_struct *work;
1906 } userptr;
1907 };
1908 };
1909 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1910
1911 void i915_gem_track_fb(struct drm_i915_gem_object *old,
1912 struct drm_i915_gem_object *new,
1913 unsigned frontbuffer_bits);
1914
1915 /**
1916 * Request queue structure.
1917 *
1918 * The request queue allows us to note sequence numbers that have been emitted
1919 * and may be associated with active buffers to be retired.
1920 *
1921 * By keeping this list, we can avoid having to do questionable
1922 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1923 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1924 */
1925 struct drm_i915_gem_request {
1926 /** On Which ring this request was generated */
1927 struct intel_engine_cs *ring;
1928
1929 /** GEM sequence number associated with this request. */
1930 uint32_t seqno;
1931
1932 /** Position in the ringbuffer of the start of the request */
1933 u32 head;
1934
1935 /** Position in the ringbuffer of the end of the request */
1936 u32 tail;
1937
1938 /** Context related to this request */
1939 struct intel_context *ctx;
1940
1941 /** Batch buffer related to this request if any */
1942 struct drm_i915_gem_object *batch_obj;
1943
1944 /** Time at which this request was emitted, in jiffies. */
1945 unsigned long emitted_jiffies;
1946
1947 /** global list entry for this request */
1948 struct list_head list;
1949
1950 struct drm_i915_file_private *file_priv;
1951 /** file_priv list entry for this request */
1952 struct list_head client_list;
1953 };
1954
1955 struct drm_i915_file_private {
1956 struct drm_i915_private *dev_priv;
1957 struct drm_file *file;
1958
1959 struct {
1960 spinlock_t lock;
1961 struct list_head request_list;
1962 struct delayed_work idle_work;
1963 } mm;
1964 struct idr context_idr;
1965
1966 atomic_t rps_wait_boost;
1967 struct intel_engine_cs *bsd_ring;
1968 };
1969
1970 /*
1971 * A command that requires special handling by the command parser.
1972 */
1973 struct drm_i915_cmd_descriptor {
1974 /*
1975 * Flags describing how the command parser processes the command.
1976 *
1977 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1978 * a length mask if not set
1979 * CMD_DESC_SKIP: The command is allowed but does not follow the
1980 * standard length encoding for the opcode range in
1981 * which it falls
1982 * CMD_DESC_REJECT: The command is never allowed
1983 * CMD_DESC_REGISTER: The command should be checked against the
1984 * register whitelist for the appropriate ring
1985 * CMD_DESC_MASTER: The command is allowed if the submitting process
1986 * is the DRM master
1987 */
1988 u32 flags;
1989 #define CMD_DESC_FIXED (1<<0)
1990 #define CMD_DESC_SKIP (1<<1)
1991 #define CMD_DESC_REJECT (1<<2)
1992 #define CMD_DESC_REGISTER (1<<3)
1993 #define CMD_DESC_BITMASK (1<<4)
1994 #define CMD_DESC_MASTER (1<<5)
1995
1996 /*
1997 * The command's unique identification bits and the bitmask to get them.
1998 * This isn't strictly the opcode field as defined in the spec and may
1999 * also include type, subtype, and/or subop fields.
2000 */
2001 struct {
2002 u32 value;
2003 u32 mask;
2004 } cmd;
2005
2006 /*
2007 * The command's length. The command is either fixed length (i.e. does
2008 * not include a length field) or has a length field mask. The flag
2009 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2010 * a length mask. All command entries in a command table must include
2011 * length information.
2012 */
2013 union {
2014 u32 fixed;
2015 u32 mask;
2016 } length;
2017
2018 /*
2019 * Describes where to find a register address in the command to check
2020 * against the ring's register whitelist. Only valid if flags has the
2021 * CMD_DESC_REGISTER bit set.
2022 */
2023 struct {
2024 u32 offset;
2025 u32 mask;
2026 } reg;
2027
2028 #define MAX_CMD_DESC_BITMASKS 3
2029 /*
2030 * Describes command checks where a particular dword is masked and
2031 * compared against an expected value. If the command does not match
2032 * the expected value, the parser rejects it. Only valid if flags has
2033 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2034 * are valid.
2035 *
2036 * If the check specifies a non-zero condition_mask then the parser
2037 * only performs the check when the bits specified by condition_mask
2038 * are non-zero.
2039 */
2040 struct {
2041 u32 offset;
2042 u32 mask;
2043 u32 expected;
2044 u32 condition_offset;
2045 u32 condition_mask;
2046 } bits[MAX_CMD_DESC_BITMASKS];
2047 };
2048
2049 /*
2050 * A table of commands requiring special handling by the command parser.
2051 *
2052 * Each ring has an array of tables. Each table consists of an array of command
2053 * descriptors, which must be sorted with command opcodes in ascending order.
2054 */
2055 struct drm_i915_cmd_table {
2056 const struct drm_i915_cmd_descriptor *table;
2057 int count;
2058 };
2059
2060 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2061 #define __I915__(p) ({ \
2062 struct drm_i915_private *__p; \
2063 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2064 __p = (struct drm_i915_private *)p; \
2065 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2066 __p = to_i915((struct drm_device *)p); \
2067 else \
2068 BUILD_BUG(); \
2069 __p; \
2070 })
2071 #define INTEL_INFO(p) (&__I915__(p)->info)
2072 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2073
2074 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2075 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2076 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2077 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2078 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2079 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2080 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2081 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2082 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2083 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2084 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2085 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2086 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2087 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2088 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2089 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2090 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2091 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2092 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2093 INTEL_DEVID(dev) == 0x0152 || \
2094 INTEL_DEVID(dev) == 0x015a)
2095 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2096 INTEL_DEVID(dev) == 0x0106 || \
2097 INTEL_DEVID(dev) == 0x010A)
2098 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2099 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2100 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2101 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2102 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2103 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2104 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2105 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2106 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2107 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2108 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2109 (INTEL_DEVID(dev) & 0xf) == 0xe))
2110 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2111 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2112 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2113 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2114 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2115 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2116 /* ULX machines are also considered ULT. */
2117 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2118 INTEL_DEVID(dev) == 0x0A1E)
2119 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2120
2121 /*
2122 * The genX designation typically refers to the render engine, so render
2123 * capability related checks should use IS_GEN, while display and other checks
2124 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2125 * chips, etc.).
2126 */
2127 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2128 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2129 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2130 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2131 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2132 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2133 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2134 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2135
2136 #define RENDER_RING (1<<RCS)
2137 #define BSD_RING (1<<VCS)
2138 #define BLT_RING (1<<BCS)
2139 #define VEBOX_RING (1<<VECS)
2140 #define BSD2_RING (1<<VCS2)
2141 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2142 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2143 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2144 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2145 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2146 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2147 __I915__(dev)->ellc_size)
2148 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2149
2150 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2151 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2152 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2153 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2154
2155 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2156 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2157
2158 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2159 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2160 /*
2161 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2162 * even when in MSI mode. This results in spurious interrupt warnings if the
2163 * legacy irq no. is shared with another device. The kernel then disables that
2164 * interrupt source and so prevents the other device from working properly.
2165 */
2166 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2167 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2168
2169 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2170 * rows, which changed the alignment requirements and fence programming.
2171 */
2172 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2173 IS_I915GM(dev)))
2174 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2175 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2176 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2177 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2178 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2179
2180 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2181 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2182 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2183
2184 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2185
2186 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2187 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2188 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2189 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2190 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2191 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2192 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2193
2194 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2195 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2196 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2197 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2198 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2199 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2200 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2201 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2202
2203 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2204 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2205 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2206 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2207 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2208 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2209 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2210
2211 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2212
2213 /* DPF == dynamic parity feature */
2214 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2215 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2216
2217 #define GT_FREQUENCY_MULTIPLIER 50
2218
2219 #include "i915_trace.h"
2220
2221 extern const struct drm_ioctl_desc i915_ioctls[];
2222 extern int i915_max_ioctl;
2223
2224 extern int i915_suspend_legacy(struct drm_device *dev, pm_message_t state);
2225 extern int i915_resume_legacy(struct drm_device *dev);
2226 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
2227 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
2228
2229 /* i915_params.c */
2230 struct i915_params {
2231 int modeset;
2232 int panel_ignore_lid;
2233 unsigned int powersave;
2234 int semaphores;
2235 unsigned int lvds_downclock;
2236 int lvds_channel_mode;
2237 int panel_use_ssc;
2238 int vbt_sdvo_panel_type;
2239 int enable_rc6;
2240 int enable_fbc;
2241 int enable_ppgtt;
2242 int enable_execlists;
2243 int enable_psr;
2244 unsigned int preliminary_hw_support;
2245 int disable_power_well;
2246 int enable_ips;
2247 int invert_brightness;
2248 int enable_cmd_parser;
2249 /* leave bools at the end to not create holes */
2250 bool enable_hangcheck;
2251 bool fastboot;
2252 bool prefault_disable;
2253 bool reset;
2254 bool disable_display;
2255 bool disable_vtd_wa;
2256 int use_mmio_flip;
2257 bool mmio_debug;
2258 };
2259 extern struct i915_params i915 __read_mostly;
2260
2261 /* i915_dma.c */
2262 void i915_update_dri1_breadcrumb(struct drm_device *dev);
2263 extern void i915_kernel_lost_context(struct drm_device * dev);
2264 extern int i915_driver_load(struct drm_device *, unsigned long flags);
2265 extern int i915_driver_unload(struct drm_device *);
2266 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
2267 extern void i915_driver_lastclose(struct drm_device * dev);
2268 extern void i915_driver_preclose(struct drm_device *dev,
2269 struct drm_file *file);
2270 extern void i915_driver_postclose(struct drm_device *dev,
2271 struct drm_file *file);
2272 extern int i915_driver_device_is_agp(struct drm_device * dev);
2273 #ifdef CONFIG_COMPAT
2274 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
2275 unsigned long arg);
2276 #endif
2277 extern int i915_emit_box(struct drm_device *dev,
2278 struct drm_clip_rect *box,
2279 int DR1, int DR4);
2280 extern int intel_gpu_reset(struct drm_device *dev);
2281 extern int i915_reset(struct drm_device *dev);
2282 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
2283 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
2284 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
2285 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
2286 int vlv_force_gfx_clock(struct drm_i915_private *dev_priv, bool on);
2287 void intel_hpd_cancel_work(struct drm_i915_private *dev_priv);
2288
2289 /* i915_irq.c */
2290 void i915_queue_hangcheck(struct drm_device *dev);
2291 __printf(3, 4)
2292 void i915_handle_error(struct drm_device *dev, bool wedged,
2293 const char *fmt, ...);
2294
2295 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
2296 int new_delay);
2297 extern void intel_irq_init(struct drm_i915_private *dev_priv);
2298 extern void intel_hpd_init(struct drm_i915_private *dev_priv);
2299 int intel_irq_install(struct drm_i915_private *dev_priv);
2300 void intel_irq_uninstall(struct drm_i915_private *dev_priv);
2301
2302 extern void intel_uncore_sanitize(struct drm_device *dev);
2303 extern void intel_uncore_early_sanitize(struct drm_device *dev,
2304 bool restore_forcewake);
2305 extern void intel_uncore_init(struct drm_device *dev);
2306 extern void intel_uncore_check_errors(struct drm_device *dev);
2307 extern void intel_uncore_fini(struct drm_device *dev);
2308 extern void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore);
2309
2310 void
2311 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2312 u32 status_mask);
2313
2314 void
2315 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2316 u32 status_mask);
2317
2318 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2319 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2320 void
2321 ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2322 void
2323 ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask);
2324 void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
2325 uint32_t interrupt_mask,
2326 uint32_t enabled_irq_mask);
2327 #define ibx_enable_display_interrupt(dev_priv, bits) \
2328 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2329 #define ibx_disable_display_interrupt(dev_priv, bits) \
2330 ibx_display_interrupt_update((dev_priv), (bits), 0)
2331
2332 /* i915_gem.c */
2333 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2334 struct drm_file *file_priv);
2335 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2336 struct drm_file *file_priv);
2337 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2338 struct drm_file *file_priv);
2339 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2340 struct drm_file *file_priv);
2341 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2342 struct drm_file *file_priv);
2343 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2344 struct drm_file *file_priv);
2345 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2346 struct drm_file *file_priv);
2347 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2348 struct drm_file *file_priv);
2349 void i915_gem_execbuffer_move_to_active(struct list_head *vmas,
2350 struct intel_engine_cs *ring);
2351 void i915_gem_execbuffer_retire_commands(struct drm_device *dev,
2352 struct drm_file *file,
2353 struct intel_engine_cs *ring,
2354 struct drm_i915_gem_object *obj);
2355 int i915_gem_ringbuffer_submission(struct drm_device *dev,
2356 struct drm_file *file,
2357 struct intel_engine_cs *ring,
2358 struct intel_context *ctx,
2359 struct drm_i915_gem_execbuffer2 *args,
2360 struct list_head *vmas,
2361 struct drm_i915_gem_object *batch_obj,
2362 u64 exec_start, u32 flags);
2363 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2364 struct drm_file *file_priv);
2365 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2366 struct drm_file *file_priv);
2367 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2368 struct drm_file *file_priv);
2369 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2370 struct drm_file *file_priv);
2371 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2372 struct drm_file *file_priv);
2373 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2374 struct drm_file *file);
2375 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2376 struct drm_file *file);
2377 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2378 struct drm_file *file_priv);
2379 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2380 struct drm_file *file_priv);
2381 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2382 struct drm_file *file_priv);
2383 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2384 struct drm_file *file_priv);
2385 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2386 struct drm_file *file_priv);
2387 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2388 struct drm_file *file_priv);
2389 int i915_gem_init_userptr(struct drm_device *dev);
2390 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data,
2391 struct drm_file *file);
2392 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2393 struct drm_file *file_priv);
2394 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2395 struct drm_file *file_priv);
2396 void i915_gem_load(struct drm_device *dev);
2397 unsigned long i915_gem_shrink(struct drm_i915_private *dev_priv,
2398 long target,
2399 unsigned flags);
2400 #define I915_SHRINK_PURGEABLE 0x1
2401 #define I915_SHRINK_UNBOUND 0x2
2402 #define I915_SHRINK_BOUND 0x4
2403 void *i915_gem_object_alloc(struct drm_device *dev);
2404 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2405 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2406 const struct drm_i915_gem_object_ops *ops);
2407 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2408 size_t size);
2409 void i915_init_vm(struct drm_i915_private *dev_priv,
2410 struct i915_address_space *vm);
2411 void i915_gem_free_object(struct drm_gem_object *obj);
2412 void i915_gem_vma_destroy(struct i915_vma *vma);
2413
2414 #define PIN_MAPPABLE 0x1
2415 #define PIN_NONBLOCK 0x2
2416 #define PIN_GLOBAL 0x4
2417 #define PIN_OFFSET_BIAS 0x8
2418 #define PIN_OFFSET_MASK (~4095)
2419 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2420 struct i915_address_space *vm,
2421 uint32_t alignment,
2422 uint64_t flags);
2423 int __must_check i915_vma_unbind(struct i915_vma *vma);
2424 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2425 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2426 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2427 void i915_gem_lastclose(struct drm_device *dev);
2428
2429 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2430 int *needs_clflush);
2431
2432 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2433 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2434 {
2435 struct sg_page_iter sg_iter;
2436
2437 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2438 return sg_page_iter_page(&sg_iter);
2439
2440 return NULL;
2441 }
2442 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2443 {
2444 BUG_ON(obj->pages == NULL);
2445 obj->pages_pin_count++;
2446 }
2447 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2448 {
2449 BUG_ON(obj->pages_pin_count == 0);
2450 obj->pages_pin_count--;
2451 }
2452
2453 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2454 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2455 struct intel_engine_cs *to);
2456 void i915_vma_move_to_active(struct i915_vma *vma,
2457 struct intel_engine_cs *ring);
2458 int i915_gem_dumb_create(struct drm_file *file_priv,
2459 struct drm_device *dev,
2460 struct drm_mode_create_dumb *args);
2461 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2462 uint32_t handle, uint64_t *offset);
2463 /**
2464 * Returns true if seq1 is later than seq2.
2465 */
2466 static inline bool
2467 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2468 {
2469 return (int32_t)(seq1 - seq2) >= 0;
2470 }
2471
2472 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2473 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2474 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2475 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2476
2477 bool i915_gem_object_pin_fence(struct drm_i915_gem_object *obj);
2478 void i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj);
2479
2480 struct drm_i915_gem_request *
2481 i915_gem_find_active_request(struct intel_engine_cs *ring);
2482
2483 bool i915_gem_retire_requests(struct drm_device *dev);
2484 void i915_gem_retire_requests_ring(struct intel_engine_cs *ring);
2485 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2486 bool interruptible);
2487 int __must_check i915_gem_check_olr(struct intel_engine_cs *ring, u32 seqno);
2488
2489 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2490 {
2491 return unlikely(atomic_read(&error->reset_counter)
2492 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2493 }
2494
2495 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2496 {
2497 return atomic_read(&error->reset_counter) & I915_WEDGED;
2498 }
2499
2500 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2501 {
2502 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2503 }
2504
2505 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2506 {
2507 return dev_priv->gpu_error.stop_rings == 0 ||
2508 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2509 }
2510
2511 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2512 {
2513 return dev_priv->gpu_error.stop_rings == 0 ||
2514 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2515 }
2516
2517 void i915_gem_reset(struct drm_device *dev);
2518 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2519 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2520 int __must_check i915_gem_init(struct drm_device *dev);
2521 int i915_gem_init_rings(struct drm_device *dev);
2522 int __must_check i915_gem_init_hw(struct drm_device *dev);
2523 int i915_gem_l3_remap(struct intel_engine_cs *ring, int slice);
2524 void i915_gem_init_swizzling(struct drm_device *dev);
2525 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2526 int __must_check i915_gpu_idle(struct drm_device *dev);
2527 int __must_check i915_gem_suspend(struct drm_device *dev);
2528 int __i915_add_request(struct intel_engine_cs *ring,
2529 struct drm_file *file,
2530 struct drm_i915_gem_object *batch_obj,
2531 u32 *seqno);
2532 #define i915_add_request(ring, seqno) \
2533 __i915_add_request(ring, NULL, NULL, seqno)
2534 int __must_check i915_wait_seqno(struct intel_engine_cs *ring,
2535 uint32_t seqno);
2536 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2537 int __must_check
2538 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2539 bool write);
2540 int __must_check
2541 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2542 int __must_check
2543 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2544 u32 alignment,
2545 struct intel_engine_cs *pipelined);
2546 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2547 int i915_gem_object_attach_phys(struct drm_i915_gem_object *obj,
2548 int align);
2549 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2550 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2551
2552 uint32_t
2553 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2554 uint32_t
2555 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2556 int tiling_mode, bool fenced);
2557
2558 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2559 enum i915_cache_level cache_level);
2560
2561 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2562 struct dma_buf *dma_buf);
2563
2564 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2565 struct drm_gem_object *gem_obj, int flags);
2566
2567 void i915_gem_restore_fences(struct drm_device *dev);
2568
2569 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2570 struct i915_address_space *vm);
2571 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2572 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2573 struct i915_address_space *vm);
2574 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2575 struct i915_address_space *vm);
2576 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2577 struct i915_address_space *vm);
2578 struct i915_vma *
2579 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2580 struct i915_address_space *vm);
2581
2582 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2583 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2584 struct i915_vma *vma;
2585 list_for_each_entry(vma, &obj->vma_list, vma_link)
2586 if (vma->pin_count > 0)
2587 return true;
2588 return false;
2589 }
2590
2591 /* Some GGTT VM helpers */
2592 #define i915_obj_to_ggtt(obj) \
2593 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2594 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2595 {
2596 struct i915_address_space *ggtt =
2597 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2598 return vm == ggtt;
2599 }
2600
2601 static inline struct i915_hw_ppgtt *
2602 i915_vm_to_ppgtt(struct i915_address_space *vm)
2603 {
2604 WARN_ON(i915_is_ggtt(vm));
2605
2606 return container_of(vm, struct i915_hw_ppgtt, base);
2607 }
2608
2609
2610 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2611 {
2612 return i915_gem_obj_bound(obj, i915_obj_to_ggtt(obj));
2613 }
2614
2615 static inline unsigned long
2616 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2617 {
2618 return i915_gem_obj_offset(obj, i915_obj_to_ggtt(obj));
2619 }
2620
2621 static inline unsigned long
2622 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2623 {
2624 return i915_gem_obj_size(obj, i915_obj_to_ggtt(obj));
2625 }
2626
2627 static inline int __must_check
2628 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2629 uint32_t alignment,
2630 unsigned flags)
2631 {
2632 return i915_gem_object_pin(obj, i915_obj_to_ggtt(obj),
2633 alignment, flags | PIN_GLOBAL);
2634 }
2635
2636 static inline int
2637 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2638 {
2639 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2640 }
2641
2642 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2643
2644 /* i915_gem_context.c */
2645 int __must_check i915_gem_context_init(struct drm_device *dev);
2646 void i915_gem_context_fini(struct drm_device *dev);
2647 void i915_gem_context_reset(struct drm_device *dev);
2648 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2649 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2650 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2651 int i915_switch_context(struct intel_engine_cs *ring,
2652 struct intel_context *to);
2653 struct intel_context *
2654 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2655 void i915_gem_context_free(struct kref *ctx_ref);
2656 struct drm_i915_gem_object *
2657 i915_gem_alloc_context_obj(struct drm_device *dev, size_t size);
2658 static inline void i915_gem_context_reference(struct intel_context *ctx)
2659 {
2660 kref_get(&ctx->ref);
2661 }
2662
2663 static inline void i915_gem_context_unreference(struct intel_context *ctx)
2664 {
2665 kref_put(&ctx->ref, i915_gem_context_free);
2666 }
2667
2668 static inline bool i915_gem_context_is_default(const struct intel_context *c)
2669 {
2670 return c->user_handle == DEFAULT_CONTEXT_HANDLE;
2671 }
2672
2673 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2674 struct drm_file *file);
2675 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2676 struct drm_file *file);
2677
2678 /* i915_gem_evict.c */
2679 int __must_check i915_gem_evict_something(struct drm_device *dev,
2680 struct i915_address_space *vm,
2681 int min_size,
2682 unsigned alignment,
2683 unsigned cache_level,
2684 unsigned long start,
2685 unsigned long end,
2686 unsigned flags);
2687 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2688 int i915_gem_evict_everything(struct drm_device *dev);
2689
2690 /* belongs in i915_gem_gtt.h */
2691 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2692 {
2693 if (INTEL_INFO(dev)->gen < 6)
2694 intel_gtt_chipset_flush();
2695 }
2696
2697 /* i915_gem_stolen.c */
2698 int i915_gem_init_stolen(struct drm_device *dev);
2699 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size, int fb_cpp);
2700 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2701 void i915_gem_cleanup_stolen(struct drm_device *dev);
2702 struct drm_i915_gem_object *
2703 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2704 struct drm_i915_gem_object *
2705 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2706 u32 stolen_offset,
2707 u32 gtt_offset,
2708 u32 size);
2709
2710 /* i915_gem_tiling.c */
2711 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2712 {
2713 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2714
2715 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2716 obj->tiling_mode != I915_TILING_NONE;
2717 }
2718
2719 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2720 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2721 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2722
2723 /* i915_gem_debug.c */
2724 #if WATCH_LISTS
2725 int i915_verify_lists(struct drm_device *dev);
2726 #else
2727 #define i915_verify_lists(dev) 0
2728 #endif
2729
2730 /* i915_debugfs.c */
2731 int i915_debugfs_init(struct drm_minor *minor);
2732 void i915_debugfs_cleanup(struct drm_minor *minor);
2733 #ifdef CONFIG_DEBUG_FS
2734 void intel_display_crc_init(struct drm_device *dev);
2735 #else
2736 static inline void intel_display_crc_init(struct drm_device *dev) {}
2737 #endif
2738
2739 /* i915_gpu_error.c */
2740 __printf(2, 3)
2741 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2742 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2743 const struct i915_error_state_file_priv *error);
2744 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2745 struct drm_i915_private *i915,
2746 size_t count, loff_t pos);
2747 static inline void i915_error_state_buf_release(
2748 struct drm_i915_error_state_buf *eb)
2749 {
2750 kfree(eb->buf);
2751 }
2752 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2753 const char *error_msg);
2754 void i915_error_state_get(struct drm_device *dev,
2755 struct i915_error_state_file_priv *error_priv);
2756 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2757 void i915_destroy_error_state(struct drm_device *dev);
2758
2759 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2760 const char *i915_cache_level_str(struct drm_i915_private *i915, int type);
2761
2762 /* i915_cmd_parser.c */
2763 int i915_cmd_parser_get_version(void);
2764 int i915_cmd_parser_init_ring(struct intel_engine_cs *ring);
2765 void i915_cmd_parser_fini_ring(struct intel_engine_cs *ring);
2766 bool i915_needs_cmd_parser(struct intel_engine_cs *ring);
2767 int i915_parse_cmds(struct intel_engine_cs *ring,
2768 struct drm_i915_gem_object *batch_obj,
2769 u32 batch_start_offset,
2770 bool is_master);
2771
2772 /* i915_suspend.c */
2773 extern int i915_save_state(struct drm_device *dev);
2774 extern int i915_restore_state(struct drm_device *dev);
2775
2776 /* i915_ums.c */
2777 void i915_save_display_reg(struct drm_device *dev);
2778 void i915_restore_display_reg(struct drm_device *dev);
2779
2780 /* i915_sysfs.c */
2781 void i915_setup_sysfs(struct drm_device *dev_priv);
2782 void i915_teardown_sysfs(struct drm_device *dev_priv);
2783
2784 /* intel_i2c.c */
2785 extern int intel_setup_gmbus(struct drm_device *dev);
2786 extern void intel_teardown_gmbus(struct drm_device *dev);
2787 static inline bool intel_gmbus_is_port_valid(unsigned port)
2788 {
2789 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2790 }
2791
2792 extern struct i2c_adapter *intel_gmbus_get_adapter(
2793 struct drm_i915_private *dev_priv, unsigned port);
2794 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2795 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2796 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2797 {
2798 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2799 }
2800 extern void intel_i2c_reset(struct drm_device *dev);
2801
2802 /* intel_opregion.c */
2803 #ifdef CONFIG_ACPI
2804 extern int intel_opregion_setup(struct drm_device *dev);
2805 extern void intel_opregion_init(struct drm_device *dev);
2806 extern void intel_opregion_fini(struct drm_device *dev);
2807 extern void intel_opregion_asle_intr(struct drm_device *dev);
2808 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2809 bool enable);
2810 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2811 pci_power_t state);
2812 #else
2813 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2814 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2815 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2816 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2817 static inline int
2818 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2819 {
2820 return 0;
2821 }
2822 static inline int
2823 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2824 {
2825 return 0;
2826 }
2827 #endif
2828
2829 /* intel_acpi.c */
2830 #ifdef CONFIG_ACPI
2831 extern void intel_register_dsm_handler(void);
2832 extern void intel_unregister_dsm_handler(void);
2833 #else
2834 static inline void intel_register_dsm_handler(void) { return; }
2835 static inline void intel_unregister_dsm_handler(void) { return; }
2836 #endif /* CONFIG_ACPI */
2837
2838 /* modesetting */
2839 extern void intel_modeset_init_hw(struct drm_device *dev);
2840 extern void intel_modeset_init(struct drm_device *dev);
2841 extern void intel_modeset_gem_init(struct drm_device *dev);
2842 extern void intel_modeset_cleanup(struct drm_device *dev);
2843 extern void intel_connector_unregister(struct intel_connector *);
2844 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2845 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2846 bool force_restore);
2847 extern void i915_redisable_vga(struct drm_device *dev);
2848 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2849 extern bool intel_fbc_enabled(struct drm_device *dev);
2850 extern void bdw_fbc_sw_flush(struct drm_device *dev, u32 value);
2851 extern void intel_disable_fbc(struct drm_device *dev);
2852 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2853 extern void intel_init_pch_refclk(struct drm_device *dev);
2854 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2855 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2856 extern void intel_set_memory_cxsr(struct drm_i915_private *dev_priv,
2857 bool enable);
2858 extern void intel_detect_pch(struct drm_device *dev);
2859 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2860 extern int intel_enable_rc6(const struct drm_device *dev);
2861
2862 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2863 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2864 struct drm_file *file);
2865 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2866 struct drm_file *file);
2867
2868 void intel_notify_mmio_flip(struct intel_engine_cs *ring);
2869
2870 /* overlay */
2871 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2872 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2873 struct intel_overlay_error_state *error);
2874
2875 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2876 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2877 struct drm_device *dev,
2878 struct intel_display_error_state *error);
2879
2880 /* On SNB platform, before reading ring registers forcewake bit
2881 * must be set to prevent GT core from power down and stale values being
2882 * returned.
2883 */
2884 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2885 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2886 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2887
2888 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2889 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2890
2891 /* intel_sideband.c */
2892 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2893 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2894 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2895 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2896 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2897 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2898 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2899 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2900 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2901 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2902 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2903 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2904 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2905 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2906 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2907 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2908 enum intel_sbi_destination destination);
2909 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2910 enum intel_sbi_destination destination);
2911 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2912 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2913
2914 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2915 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2916
2917 #define FORCEWAKE_RENDER (1 << 0)
2918 #define FORCEWAKE_MEDIA (1 << 1)
2919 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2920
2921
2922 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2923 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2924
2925 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2926 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2927 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2928 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2929
2930 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2931 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2932 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2933 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2934
2935 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2936 * will be implemented using 2 32-bit writes in an arbitrary order with
2937 * an arbitrary delay between them. This can cause the hardware to
2938 * act upon the intermediate value, possibly leading to corruption and
2939 * machine death. You have been warned.
2940 */
2941 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2942 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2943
2944 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2945 u32 upper = I915_READ(upper_reg); \
2946 u32 lower = I915_READ(lower_reg); \
2947 u32 tmp = I915_READ(upper_reg); \
2948 if (upper != tmp) { \
2949 upper = tmp; \
2950 lower = I915_READ(lower_reg); \
2951 WARN_ON(I915_READ(upper_reg) != upper); \
2952 } \
2953 (u64)upper << 32 | lower; })
2954
2955 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2956 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2957
2958 /* "Broadcast RGB" property */
2959 #define INTEL_BROADCAST_RGB_AUTO 0
2960 #define INTEL_BROADCAST_RGB_FULL 1
2961 #define INTEL_BROADCAST_RGB_LIMITED 2
2962
2963 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2964 {
2965 if (IS_VALLEYVIEW(dev))
2966 return VLV_VGACNTRL;
2967 else if (INTEL_INFO(dev)->gen >= 5)
2968 return CPU_VGACNTRL;
2969 else
2970 return VGACNTRL;
2971 }
2972
2973 static inline void __user *to_user_ptr(u64 address)
2974 {
2975 return (void __user *)(uintptr_t)address;
2976 }
2977
2978 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2979 {
2980 unsigned long j = msecs_to_jiffies(m);
2981
2982 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2983 }
2984
2985 static inline unsigned long
2986 timespec_to_jiffies_timeout(const struct timespec *value)
2987 {
2988 unsigned long j = timespec_to_jiffies(value);
2989
2990 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2991 }
2992
2993 /*
2994 * If you need to wait X milliseconds between events A and B, but event B
2995 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2996 * when event A happened, then just before event B you call this function and
2997 * pass the timestamp as the first argument, and X as the second argument.
2998 */
2999 static inline void
3000 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
3001 {
3002 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
3003
3004 /*
3005 * Don't re-read the value of "jiffies" every time since it may change
3006 * behind our back and break the math.
3007 */
3008 tmp_jiffies = jiffies;
3009 target_jiffies = timestamp_jiffies +
3010 msecs_to_jiffies_timeout(to_wait_ms);
3011
3012 if (time_after(target_jiffies, tmp_jiffies)) {
3013 remaining_jiffies = target_jiffies - tmp_jiffies;
3014 while (remaining_jiffies)
3015 remaining_jiffies =
3016 schedule_timeout_uninterruptible(remaining_jiffies);
3017 }
3018 }
3019
3020 #endif
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