drivers/gpu/drm/i915/i915_drv.h

   1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #ifndef _I915_DRV_H_
  31 #define _I915_DRV_H_
  32
  33 #include "i915_reg.h"
  34 #include "intel_bios.h"
  35 #include "intel_ringbuffer.h"
  36 #include <linux/io-mapping.h>
  37 #include <linux/i2c.h>
  38 #include <drm/intel-gtt.h>
  39
  40 /* General customization:
  41  */
  42
  43 #define DRIVER_AUTHOR           "Tungsten Graphics, Inc."
  44
  45 #define DRIVER_NAME             "i915"
  46 #define DRIVER_DESC             "Intel Graphics"
  47 #define DRIVER_DATE             "20080730"
  48
  49 enum pipe {
  50         PIPE_A = 0,
  51         PIPE_B,
  52         PIPE_C,
  53         I915_MAX_PIPES
  54 };
  55 #define pipe_name(p) ((p) + 'A')
  56
  57 enum plane {
  58         PLANE_A = 0,
  59         PLANE_B,
  60         PLANE_C,
  61 };
  62 #define plane_name(p) ((p) + 'A')
  63
  64 #define I915_GEM_GPU_DOMAINS    (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT))
  65
  66 #define for_each_pipe(p) for ((p) = 0; (p) < dev_priv->num_pipe; (p)++)
  67
  68 /* Interface history:
  69  *
  70  * 1.1: Original.
  71  * 1.2: Add Power Management
  72  * 1.3: Add vblank support
  73  * 1.4: Fix cmdbuffer path, add heap destroy
  74  * 1.5: Add vblank pipe configuration
  75  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
  76  *      - Support vertical blank on secondary display pipe
  77  */
  78 #define DRIVER_MAJOR            1
  79 #define DRIVER_MINOR            6
  80 #define DRIVER_PATCHLEVEL       0
  81
  82 #define WATCH_COHERENCY 0
  83 #define WATCH_LISTS     0
  84
  85 #define I915_GEM_PHYS_CURSOR_0 1
  86 #define I915_GEM_PHYS_CURSOR_1 2
  87 #define I915_GEM_PHYS_OVERLAY_REGS 3
  88 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
  89
  90 struct drm_i915_gem_phys_object {
  91         int id;
  92         struct page **page_list;
  93         drm_dma_handle_t *handle;
  94         struct drm_i915_gem_object *cur_obj;
  95 };
  96
  97 struct mem_block {
  98         struct mem_block *next;
  99         struct mem_block *prev;
 100         int start;
 101         int size;
 102         struct drm_file *file_priv; /* NULL: free, -1: heap, other: real files */
 103 };
 104
 105 struct opregion_header;
 106 struct opregion_acpi;
 107 struct opregion_swsci;
 108 struct opregion_asle;
 109
 110 struct intel_opregion {
 111         struct opregion_header *header;
 112         struct opregion_acpi *acpi;
 113         struct opregion_swsci *swsci;
 114         struct opregion_asle *asle;
 115         void *vbt;
 116         u32 __iomem *lid_state;
 117 };
 118 #define OPREGION_SIZE            (8*1024)
 119
 120 struct intel_overlay;
 121 struct intel_overlay_error_state;
 122
 123 struct drm_i915_master_private {
 124         drm_local_map_t *sarea;
 125         struct _drm_i915_sarea *sarea_priv;
 126 };
 127 #define I915_FENCE_REG_NONE -1
 128
 129 struct drm_i915_fence_reg {
 130         struct list_head lru_list;
 131         struct drm_i915_gem_object *obj;
 132         uint32_t setup_seqno;
 133 };
 134
 135 struct sdvo_device_mapping {
 136         u8 initialized;
 137         u8 dvo_port;
 138         u8 slave_addr;
 139         u8 dvo_wiring;
 140         u8 i2c_pin;
 141         u8 i2c_speed;
 142         u8 ddc_pin;
 143 };
 144
 145 struct intel_display_error_state;
 146
 147 struct drm_i915_error_state {
 148         u32 eir;
 149         u32 pgtbl_er;
 150         u32 pipestat[I915_MAX_PIPES];
 151         u32 ipeir;
 152         u32 ipehr;
 153         u32 instdone;
 154         u32 acthd;
 155         u32 error; /* gen6+ */
 156         u32 bcs_acthd; /* gen6+ blt engine */
 157         u32 bcs_ipehr;
 158         u32 bcs_ipeir;
 159         u32 bcs_instdone;
 160         u32 bcs_seqno;
 161         u32 vcs_acthd; /* gen6+ bsd engine */
 162         u32 vcs_ipehr;
 163         u32 vcs_ipeir;
 164         u32 vcs_instdone;
 165         u32 vcs_seqno;
 166         u32 instpm;
 167         u32 instps;
 168         u32 instdone1;
 169         u32 seqno;
 170         u64 bbaddr;
 171         u64 fence[16];
 172         struct timeval time;
 173         struct drm_i915_error_object {
 174                 int page_count;
 175                 u32 gtt_offset;
 176                 u32 *pages[0];
 177         } *ringbuffer[I915_NUM_RINGS], *batchbuffer[I915_NUM_RINGS];
 178         struct drm_i915_error_buffer {
 179                 u32 size;
 180                 u32 name;
 181                 u32 seqno;
 182                 u32 gtt_offset;
 183                 u32 read_domains;
 184                 u32 write_domain;
 185                 s32 fence_reg:5;
 186                 s32 pinned:2;
 187                 u32 tiling:2;
 188                 u32 dirty:1;
 189                 u32 purgeable:1;
 190                 u32 ring:4;
 191                 u32 cache_level:2;
 192         } *active_bo, *pinned_bo;
 193         u32 active_bo_count, pinned_bo_count;
 194         struct intel_overlay_error_state *overlay;
 195         struct intel_display_error_state *display;
 196 };
 197
 198 struct drm_i915_display_funcs {
 199         void (*dpms)(struct drm_crtc *crtc, int mode);
 200         bool (*fbc_enabled)(struct drm_device *dev);
 201         void (*enable_fbc)(struct drm_crtc *crtc, unsigned long interval);
 202         void (*disable_fbc)(struct drm_device *dev);
 203         int (*get_display_clock_speed)(struct drm_device *dev);
 204         int (*get_fifo_size)(struct drm_device *dev, int plane);
 205         void (*update_wm)(struct drm_device *dev);
 206         int (*crtc_mode_set)(struct drm_crtc *crtc,
 207                              struct drm_display_mode *mode,
 208                              struct drm_display_mode *adjusted_mode,
 209                              int x, int y,
 210                              struct drm_framebuffer *old_fb);
 211         void (*fdi_link_train)(struct drm_crtc *crtc);
 212         void (*init_clock_gating)(struct drm_device *dev);
 213         void (*init_pch_clock_gating)(struct drm_device *dev);
 214         int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
 215                           struct drm_framebuffer *fb,
 216                           struct drm_i915_gem_object *obj);
 217         int (*update_plane)(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 218                             int x, int y);
 219         /* clock updates for mode set */
 220         /* cursor updates */
 221         /* render clock increase/decrease */
 222         /* display clock increase/decrease */
 223         /* pll clock increase/decrease */
 224 };
 225
 226 struct intel_device_info {
 227         u8 gen;
 228         u8 is_mobile : 1;
 229         u8 is_i85x : 1;
 230         u8 is_i915g : 1;
 231         u8 is_i945gm : 1;
 232         u8 is_g33 : 1;
 233         u8 need_gfx_hws : 1;
 234         u8 is_g4x : 1;
 235         u8 is_pineview : 1;
 236         u8 is_broadwater : 1;
 237         u8 is_crestline : 1;
 238         u8 is_ivybridge : 1;
 239         u8 has_fbc : 1;
 240         u8 has_pipe_cxsr : 1;
 241         u8 has_hotplug : 1;
 242         u8 cursor_needs_physical : 1;
 243         u8 has_overlay : 1;
 244         u8 overlay_needs_physical : 1;
 245         u8 supports_tv : 1;
 246         u8 has_bsd_ring : 1;
 247         u8 has_blt_ring : 1;
 248 };
 249
 250 enum no_fbc_reason {
 251         FBC_NO_OUTPUT, /* no outputs enabled to compress */
 252         FBC_STOLEN_TOO_SMALL, /* not enough space to hold compressed buffers */
 253         FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
 254         FBC_MODE_TOO_LARGE, /* mode too large for compression */
 255         FBC_BAD_PLANE, /* fbc not supported on plane */
 256         FBC_NOT_TILED, /* buffer not tiled */
 257         FBC_MULTIPLE_PIPES, /* more than one pipe active */
 258         FBC_MODULE_PARAM,
 259 };
 260
 261 enum intel_pch {
 262         PCH_IBX,        /* Ibexpeak PCH */
 263         PCH_CPT,        /* Cougarpoint PCH */
 264 };
 265
 266 #define QUIRK_PIPEA_FORCE (1<<0)
 267 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
 268
 269 struct intel_fbdev;
 270 struct intel_fbc_work;
 271
 272 typedef struct drm_i915_private {
 273         struct drm_device *dev;
 274
 275         const struct intel_device_info *info;
 276
 277         int has_gem;
 278         int relative_constants_mode;
 279
 280         void __iomem *regs;
 281         u32 gt_fifo_count;
 282
 283         struct intel_gmbus {
 284                 struct i2c_adapter adapter;
 285                 struct i2c_adapter *force_bit;
 286                 u32 reg0;
 287         } *gmbus;
 288
 289         struct pci_dev *bridge_dev;
 290         struct intel_ring_buffer ring[I915_NUM_RINGS];
 291         uint32_t next_seqno;
 292
 293         drm_dma_handle_t *status_page_dmah;
 294         uint32_t counter;
 295         drm_local_map_t hws_map;
 296         struct drm_i915_gem_object *pwrctx;
 297         struct drm_i915_gem_object *renderctx;
 298
 299         struct resource mch_res;
 300
 301         unsigned int cpp;
 302         int back_offset;
 303         int front_offset;
 304         int current_page;
 305         int page_flipping;
 306
 307         atomic_t irq_received;
 308
 309         /* protects the irq masks */
 310         spinlock_t irq_lock;
 311         /** Cached value of IMR to avoid reads in updating the bitfield */
 312         u32 pipestat[2];
 313         u32 irq_mask;
 314         u32 gt_irq_mask;
 315         u32 pch_irq_mask;
 316
 317         u32 hotplug_supported_mask;
 318         struct work_struct hotplug_work;
 319
 320         int tex_lru_log_granularity;
 321         int allow_batchbuffer;
 322         struct mem_block *agp_heap;
 323         unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds;
 324         int vblank_pipe;
 325         int num_pipe;
 326
 327         /* For hangcheck timer */
 328 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
 329         struct timer_list hangcheck_timer;
 330         int hangcheck_count;
 331         uint32_t last_acthd;
 332         uint32_t last_instdone;
 333         uint32_t last_instdone1;
 334
 335         unsigned long cfb_size;
 336         unsigned int cfb_fb;
 337         enum plane cfb_plane;
 338         int cfb_y;
 339         struct intel_fbc_work *fbc_work;
 340
 341         struct intel_opregion opregion;
 342
 343         /* overlay */
 344         struct intel_overlay *overlay;
 345
 346         /* LVDS info */
 347         int backlight_level;  /* restore backlight to this value */
 348         bool backlight_enabled;
 349         struct drm_display_mode *panel_fixed_mode;
 350         struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
 351         struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
 352
 353         /* Feature bits from the VBIOS */
 354         unsigned int int_tv_support:1;
 355         unsigned int lvds_dither:1;
 356         unsigned int lvds_vbt:1;
 357         unsigned int int_crt_support:1;
 358         unsigned int lvds_use_ssc:1;
 359         int lvds_ssc_freq;
 360         struct {
 361                 int rate;
 362                 int lanes;
 363                 int preemphasis;
 364                 int vswing;
 365
 366                 bool initialized;
 367                 bool support;
 368                 int bpp;
 369                 struct edp_power_seq pps;
 370         } edp;
 371         bool no_aux_handshake;
 372
 373         struct notifier_block lid_notifier;
 374
 375         int crt_ddc_pin;
 376         struct drm_i915_fence_reg fence_regs[16]; /* assume 965 */
 377         int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
 378         int num_fence_regs; /* 8 on pre-965, 16 otherwise */
 379
 380         unsigned int fsb_freq, mem_freq, is_ddr3;
 381
 382         spinlock_t error_lock;
 383         struct drm_i915_error_state *first_error;
 384         struct work_struct error_work;
 385         struct completion error_completion;
 386         struct workqueue_struct *wq;
 387
 388         /* Display functions */
 389         struct drm_i915_display_funcs display;
 390
 391         /* PCH chipset type */
 392         enum intel_pch pch_type;
 393
 394         unsigned long quirks;
 395
 396         /* Register state */
 397         bool modeset_on_lid;
 398         u8 saveLBB;
 399         u32 saveDSPACNTR;
 400         u32 saveDSPBCNTR;
 401         u32 saveDSPARB;
 402         u32 saveHWS;
 403         u32 savePIPEACONF;
 404         u32 savePIPEBCONF;
 405         u32 savePIPEASRC;
 406         u32 savePIPEBSRC;
 407         u32 saveFPA0;
 408         u32 saveFPA1;
 409         u32 saveDPLL_A;
 410         u32 saveDPLL_A_MD;
 411         u32 saveHTOTAL_A;
 412         u32 saveHBLANK_A;
 413         u32 saveHSYNC_A;
 414         u32 saveVTOTAL_A;
 415         u32 saveVBLANK_A;
 416         u32 saveVSYNC_A;
 417         u32 saveBCLRPAT_A;
 418         u32 saveTRANSACONF;
 419         u32 saveTRANS_HTOTAL_A;
 420         u32 saveTRANS_HBLANK_A;
 421         u32 saveTRANS_HSYNC_A;
 422         u32 saveTRANS_VTOTAL_A;
 423         u32 saveTRANS_VBLANK_A;
 424         u32 saveTRANS_VSYNC_A;
 425         u32 savePIPEASTAT;
 426         u32 saveDSPASTRIDE;
 427         u32 saveDSPASIZE;
 428         u32 saveDSPAPOS;
 429         u32 saveDSPAADDR;
 430         u32 saveDSPASURF;
 431         u32 saveDSPATILEOFF;
 432         u32 savePFIT_PGM_RATIOS;
 433         u32 saveBLC_HIST_CTL;
 434         u32 saveBLC_PWM_CTL;
 435         u32 saveBLC_PWM_CTL2;
 436         u32 saveBLC_CPU_PWM_CTL;
 437         u32 saveBLC_CPU_PWM_CTL2;
 438         u32 saveFPB0;
 439         u32 saveFPB1;
 440         u32 saveDPLL_B;
 441         u32 saveDPLL_B_MD;
 442         u32 saveHTOTAL_B;
 443         u32 saveHBLANK_B;
 444         u32 saveHSYNC_B;
 445         u32 saveVTOTAL_B;
 446         u32 saveVBLANK_B;
 447         u32 saveVSYNC_B;
 448         u32 saveBCLRPAT_B;
 449         u32 saveTRANSBCONF;
 450         u32 saveTRANS_HTOTAL_B;
 451         u32 saveTRANS_HBLANK_B;
 452         u32 saveTRANS_HSYNC_B;
 453         u32 saveTRANS_VTOTAL_B;
 454         u32 saveTRANS_VBLANK_B;
 455         u32 saveTRANS_VSYNC_B;
 456         u32 savePIPEBSTAT;
 457         u32 saveDSPBSTRIDE;
 458         u32 saveDSPBSIZE;
 459         u32 saveDSPBPOS;
 460         u32 saveDSPBADDR;
 461         u32 saveDSPBSURF;
 462         u32 saveDSPBTILEOFF;
 463         u32 saveVGA0;
 464         u32 saveVGA1;
 465         u32 saveVGA_PD;
 466         u32 saveVGACNTRL;
 467         u32 saveADPA;
 468         u32 saveLVDS;
 469         u32 savePP_ON_DELAYS;
 470         u32 savePP_OFF_DELAYS;
 471         u32 saveDVOA;
 472         u32 saveDVOB;
 473         u32 saveDVOC;
 474         u32 savePP_ON;
 475         u32 savePP_OFF;
 476         u32 savePP_CONTROL;
 477         u32 savePP_DIVISOR;
 478         u32 savePFIT_CONTROL;
 479         u32 save_palette_a[256];
 480         u32 save_palette_b[256];
 481         u32 saveDPFC_CB_BASE;
 482         u32 saveFBC_CFB_BASE;
 483         u32 saveFBC_LL_BASE;
 484         u32 saveFBC_CONTROL;
 485         u32 saveFBC_CONTROL2;
 486         u32 saveIER;
 487         u32 saveIIR;
 488         u32 saveIMR;
 489         u32 saveDEIER;
 490         u32 saveDEIMR;
 491         u32 saveGTIER;
 492         u32 saveGTIMR;
 493         u32 saveFDI_RXA_IMR;
 494         u32 saveFDI_RXB_IMR;
 495         u32 saveCACHE_MODE_0;
 496         u32 saveMI_ARB_STATE;
 497         u32 saveSWF0[16];
 498         u32 saveSWF1[16];
 499         u32 saveSWF2[3];
 500         u8 saveMSR;
 501         u8 saveSR[8];
 502         u8 saveGR[25];
 503         u8 saveAR_INDEX;
 504         u8 saveAR[21];
 505         u8 saveDACMASK;
 506         u8 saveCR[37];
 507         uint64_t saveFENCE[16];
 508         u32 saveCURACNTR;
 509         u32 saveCURAPOS;
 510         u32 saveCURABASE;
 511         u32 saveCURBCNTR;
 512         u32 saveCURBPOS;
 513         u32 saveCURBBASE;
 514         u32 saveCURSIZE;
 515         u32 saveDP_B;
 516         u32 saveDP_C;
 517         u32 saveDP_D;
 518         u32 savePIPEA_GMCH_DATA_M;
 519         u32 savePIPEB_GMCH_DATA_M;
 520         u32 savePIPEA_GMCH_DATA_N;
 521         u32 savePIPEB_GMCH_DATA_N;
 522         u32 savePIPEA_DP_LINK_M;
 523         u32 savePIPEB_DP_LINK_M;
 524         u32 savePIPEA_DP_LINK_N;
 525         u32 savePIPEB_DP_LINK_N;
 526         u32 saveFDI_RXA_CTL;
 527         u32 saveFDI_TXA_CTL;
 528         u32 saveFDI_RXB_CTL;
 529         u32 saveFDI_TXB_CTL;
 530         u32 savePFA_CTL_1;
 531         u32 savePFB_CTL_1;
 532         u32 savePFA_WIN_SZ;
 533         u32 savePFB_WIN_SZ;
 534         u32 savePFA_WIN_POS;
 535         u32 savePFB_WIN_POS;
 536         u32 savePCH_DREF_CONTROL;
 537         u32 saveDISP_ARB_CTL;
 538         u32 savePIPEA_DATA_M1;
 539         u32 savePIPEA_DATA_N1;
 540         u32 savePIPEA_LINK_M1;
 541         u32 savePIPEA_LINK_N1;
 542         u32 savePIPEB_DATA_M1;
 543         u32 savePIPEB_DATA_N1;
 544         u32 savePIPEB_LINK_M1;
 545         u32 savePIPEB_LINK_N1;
 546         u32 saveMCHBAR_RENDER_STANDBY;
 547
 548         struct {
 549                 /** Bridge to intel-gtt-ko */
 550                 const struct intel_gtt *gtt;
 551                 /** Memory allocator for GTT stolen memory */
 552                 struct drm_mm stolen;
 553                 /** Memory allocator for GTT */
 554                 struct drm_mm gtt_space;
 555                 /** List of all objects in gtt_space. Used to restore gtt
 556                  * mappings on resume */
 557                 struct list_head gtt_list;
 558
 559                 /** Usable portion of the GTT for GEM */
 560                 unsigned long gtt_start;
 561                 unsigned long gtt_mappable_end;
 562                 unsigned long gtt_end;
 563
 564                 struct io_mapping *gtt_mapping;
 565                 int gtt_mtrr;
 566
 567                 struct shrinker inactive_shrinker;
 568
 569                 /**
 570                  * List of objects currently involved in rendering.
 571                  *
 572                  * Includes buffers having the contents of their GPU caches
 573                  * flushed, not necessarily primitives.  last_rendering_seqno
 574                  * represents when the rendering involved will be completed.
 575                  *
 576                  * A reference is held on the buffer while on this list.
 577                  */
 578                 struct list_head active_list;
 579
 580                 /**
 581                  * List of objects which are not in the ringbuffer but which
 582                  * still have a write_domain which needs to be flushed before
 583                  * unbinding.
 584                  *
 585                  * last_rendering_seqno is 0 while an object is in this list.
 586                  *
 587                  * A reference is held on the buffer while on this list.
 588                  */
 589                 struct list_head flushing_list;
 590
 591                 /**
 592                  * LRU list of objects which are not in the ringbuffer and
 593                  * are ready to unbind, but are still in the GTT.
 594                  *
 595                  * last_rendering_seqno is 0 while an object is in this list.
 596                  *
 597                  * A reference is not held on the buffer while on this list,
 598                  * as merely being GTT-bound shouldn't prevent its being
 599                  * freed, and we'll pull it off the list in the free path.
 600                  */
 601                 struct list_head inactive_list;
 602
 603                 /**
 604                  * LRU list of objects which are not in the ringbuffer but
 605                  * are still pinned in the GTT.
 606                  */
 607                 struct list_head pinned_list;
 608
 609                 /** LRU list of objects with fence regs on them. */
 610                 struct list_head fence_list;
 611
 612                 /**
 613                  * List of objects currently pending being freed.
 614                  *
 615                  * These objects are no longer in use, but due to a signal
 616                  * we were prevented from freeing them at the appointed time.
 617                  */
 618                 struct list_head deferred_free_list;
 619
 620                 /**
 621                  * We leave the user IRQ off as much as possible,
 622                  * but this means that requests will finish and never
 623                  * be retired once the system goes idle. Set a timer to
 624                  * fire periodically while the ring is running. When it
 625                  * fires, go retire requests.
 626                  */
 627                 struct delayed_work retire_work;
 628
 629                 /**
 630                  * Are we in a non-interruptible section of code like
 631                  * modesetting?
 632                  */
 633                 bool interruptible;
 634
 635                 /**
 636                  * Flag if the X Server, and thus DRM, is not currently in
 637                  * control of the device.
 638                  *
 639                  * This is set between LeaveVT and EnterVT.  It needs to be
 640                  * replaced with a semaphore.  It also needs to be
 641                  * transitioned away from for kernel modesetting.
 642                  */
 643                 int suspended;
 644
 645                 /**
 646                  * Flag if the hardware appears to be wedged.
 647                  *
 648                  * This is set when attempts to idle the device timeout.
 649                  * It prevents command submission from occurring and makes
 650                  * every pending request fail
 651                  */
 652                 atomic_t wedged;
 653
 654                 /** Bit 6 swizzling required for X tiling */
 655                 uint32_t bit_6_swizzle_x;
 656                 /** Bit 6 swizzling required for Y tiling */
 657                 uint32_t bit_6_swizzle_y;
 658
 659                 /* storage for physical objects */
 660                 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
 661
 662                 /* accounting, useful for userland debugging */
 663                 size_t gtt_total;
 664                 size_t mappable_gtt_total;
 665                 size_t object_memory;
 666                 u32 object_count;
 667         } mm;
 668         struct sdvo_device_mapping sdvo_mappings[2];
 669         /* indicate whether the LVDS_BORDER should be enabled or not */
 670         unsigned int lvds_border_bits;
 671         /* Panel fitter placement and size for Ironlake+ */
 672         u32 pch_pf_pos, pch_pf_size;
 673         int panel_t3, panel_t12;
 674
 675         struct drm_crtc *plane_to_crtc_mapping[2];
 676         struct drm_crtc *pipe_to_crtc_mapping[2];
 677         wait_queue_head_t pending_flip_queue;
 678         bool flip_pending_is_done;
 679
 680         /* Reclocking support */
 681         bool render_reclock_avail;
 682         bool lvds_downclock_avail;
 683         /* indicates the reduced downclock for LVDS*/
 684         int lvds_downclock;
 685         struct work_struct idle_work;
 686         struct timer_list idle_timer;
 687         bool busy;
 688         u16 orig_clock;
 689         int child_dev_num;
 690         struct child_device_config *child_dev;
 691         struct drm_connector *int_lvds_connector;
 692
 693         bool mchbar_need_disable;
 694
 695         struct work_struct rps_work;
 696         spinlock_t rps_lock;
 697         u32 pm_iir;
 698
 699         u8 cur_delay;
 700         u8 min_delay;
 701         u8 max_delay;
 702         u8 fmax;
 703         u8 fstart;
 704
 705         u64 last_count1;
 706         unsigned long last_time1;
 707         u64 last_count2;
 708         struct timespec last_time2;
 709         unsigned long gfx_power;
 710         int c_m;
 711         int r_t;
 712         u8 corr;
 713         spinlock_t *mchdev_lock;
 714
 715         enum no_fbc_reason no_fbc_reason;
 716
 717         struct drm_mm_node *compressed_fb;
 718         struct drm_mm_node *compressed_llb;
 719
 720         unsigned long last_gpu_reset;
 721
 722         /* list of fbdev register on this device */
 723         struct intel_fbdev *fbdev;
 724
 725         struct drm_property *broadcast_rgb_property;
 726         struct drm_property *force_audio_property;
 727
 728         atomic_t forcewake_count;
 729 } drm_i915_private_t;
 730
 731 enum i915_cache_level {
 732         I915_CACHE_NONE,
 733         I915_CACHE_LLC,
 734         I915_CACHE_LLC_MLC, /* gen6+ */
 735 };
 736
 737 struct drm_i915_gem_object {
 738         struct drm_gem_object base;
 739
 740         /** Current space allocated to this object in the GTT, if any. */
 741         struct drm_mm_node *gtt_space;
 742         struct list_head gtt_list;
 743
 744         /** This object's place on the active/flushing/inactive lists */
 745         struct list_head ring_list;
 746         struct list_head mm_list;
 747         /** This object's place on GPU write list */
 748         struct list_head gpu_write_list;
 749         /** This object's place in the batchbuffer or on the eviction list */
 750         struct list_head exec_list;
 751
 752         /**
 753          * This is set if the object is on the active or flushing lists
 754          * (has pending rendering), and is not set if it's on inactive (ready
 755          * to be unbound).
 756          */
 757         unsigned int active : 1;
 758
 759         /**
 760          * This is set if the object has been written to since last bound
 761          * to the GTT
 762          */
 763         unsigned int dirty : 1;
 764
 765         /**
 766          * This is set if the object has been written to since the last
 767          * GPU flush.
 768          */
 769         unsigned int pending_gpu_write : 1;
 770
 771         /**
 772          * Fence register bits (if any) for this object.  Will be set
 773          * as needed when mapped into the GTT.
 774          * Protected by dev->struct_mutex.
 775          *
 776          * Size: 4 bits for 16 fences + sign (for FENCE_REG_NONE)
 777          */
 778         signed int fence_reg : 5;
 779
 780         /**
 781          * Advice: are the backing pages purgeable?
 782          */
 783         unsigned int madv : 2;
 784
 785         /**
 786          * Current tiling mode for the object.
 787          */
 788         unsigned int tiling_mode : 2;
 789         unsigned int tiling_changed : 1;
 790
 791         /** How many users have pinned this object in GTT space. The following
 792          * users can each hold at most one reference: pwrite/pread, pin_ioctl
 793          * (via user_pin_count), execbuffer (objects are not allowed multiple
 794          * times for the same batchbuffer), and the framebuffer code. When
 795          * switching/pageflipping, the framebuffer code has at most two buffers
 796          * pinned per crtc.
 797          *
 798          * In the worst case this is 1 + 1 + 1 + 2*2 = 7. That would fit into 3
 799          * bits with absolutely no headroom. So use 4 bits. */
 800         unsigned int pin_count : 4;
 801 #define DRM_I915_GEM_OBJECT_MAX_PIN_COUNT 0xf
 802
 803         /**
 804          * Is the object at the current location in the gtt mappable and
 805          * fenceable? Used to avoid costly recalculations.
 806          */
 807         unsigned int map_and_fenceable : 1;
 808
 809         /**
 810          * Whether the current gtt mapping needs to be mappable (and isn't just
 811          * mappable by accident). Track pin and fault separate for a more
 812          * accurate mappable working set.
 813          */
 814         unsigned int fault_mappable : 1;
 815         unsigned int pin_mappable : 1;
 816
 817         /*
 818          * Is the GPU currently using a fence to access this buffer,
 819          */
 820         unsigned int pending_fenced_gpu_access:1;
 821         unsigned int fenced_gpu_access:1;
 822
 823         unsigned int cache_level:2;
 824
 825         struct page **pages;
 826
 827         /**
 828          * DMAR support
 829          */
 830         struct scatterlist *sg_list;
 831         int num_sg;
 832
 833         /**
 834          * Used for performing relocations during execbuffer insertion.
 835          */
 836         struct hlist_node exec_node;
 837         unsigned long exec_handle;
 838         struct drm_i915_gem_exec_object2 *exec_entry;
 839
 840         /**
 841          * Current offset of the object in GTT space.
 842          *
 843          * This is the same as gtt_space->start
 844          */
 845         uint32_t gtt_offset;
 846
 847         /** Breadcrumb of last rendering to the buffer. */
 848         uint32_t last_rendering_seqno;
 849         struct intel_ring_buffer *ring;
 850
 851         /** Breadcrumb of last fenced GPU access to the buffer. */
 852         uint32_t last_fenced_seqno;
 853         struct intel_ring_buffer *last_fenced_ring;
 854
 855         /** Current tiling stride for the object, if it's tiled. */
 856         uint32_t stride;
 857
 858         /** Record of address bit 17 of each page at last unbind. */
 859         unsigned long *bit_17;
 860
 861
 862         /**
 863          * If present, while GEM_DOMAIN_CPU is in the read domain this array
 864          * flags which individual pages are valid.
 865          */
 866         uint8_t *page_cpu_valid;
 867
 868         /** User space pin count and filp owning the pin */
 869         uint32_t user_pin_count;
 870         struct drm_file *pin_filp;
 871
 872         /** for phy allocated objects */
 873         struct drm_i915_gem_phys_object *phys_obj;
 874
 875         /**
 876          * Number of crtcs where this object is currently the fb, but
 877          * will be page flipped away on the next vblank.  When it
 878          * reaches 0, dev_priv->pending_flip_queue will be woken up.
 879          */
 880         atomic_t pending_flip;
 881 };
 882
 883 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
 884
 885 /**
 886  * Request queue structure.
 887  *
 888  * The request queue allows us to note sequence numbers that have been emitted
 889  * and may be associated with active buffers to be retired.
 890  *
 891  * By keeping this list, we can avoid having to do questionable
 892  * sequence-number comparisons on buffer last_rendering_seqnos, and associate
 893  * an emission time with seqnos for tracking how far ahead of the GPU we are.
 894  */
 895 struct drm_i915_gem_request {
 896         /** On Which ring this request was generated */
 897         struct intel_ring_buffer *ring;
 898
 899         /** GEM sequence number associated with this request. */
 900         uint32_t seqno;
 901
 902         /** Time at which this request was emitted, in jiffies. */
 903         unsigned long emitted_jiffies;
 904
 905         /** global list entry for this request */
 906         struct list_head list;
 907
 908         struct drm_i915_file_private *file_priv;
 909         /** file_priv list entry for this request */
 910         struct list_head client_list;
 911 };
 912
 913 struct drm_i915_file_private {
 914         struct {
 915                 struct spinlock lock;
 916                 struct list_head request_list;
 917         } mm;
 918 };
 919
 920 #define INTEL_INFO(dev) (((struct drm_i915_private *) (dev)->dev_private)->info)
 921
 922 #define IS_I830(dev)            ((dev)->pci_device == 0x3577)
 923 #define IS_845G(dev)            ((dev)->pci_device == 0x2562)
 924 #define IS_I85X(dev)            (INTEL_INFO(dev)->is_i85x)
 925 #define IS_I865G(dev)           ((dev)->pci_device == 0x2572)
 926 #define IS_I915G(dev)           (INTEL_INFO(dev)->is_i915g)
 927 #define IS_I915GM(dev)          ((dev)->pci_device == 0x2592)
 928 #define IS_I945G(dev)           ((dev)->pci_device == 0x2772)
 929 #define IS_I945GM(dev)          (INTEL_INFO(dev)->is_i945gm)
 930 #define IS_BROADWATER(dev)      (INTEL_INFO(dev)->is_broadwater)
 931 #define IS_CRESTLINE(dev)       (INTEL_INFO(dev)->is_crestline)
 932 #define IS_GM45(dev)            ((dev)->pci_device == 0x2A42)
 933 #define IS_G4X(dev)             (INTEL_INFO(dev)->is_g4x)
 934 #define IS_PINEVIEW_G(dev)      ((dev)->pci_device == 0xa001)
 935 #define IS_PINEVIEW_M(dev)      ((dev)->pci_device == 0xa011)
 936 #define IS_PINEVIEW(dev)        (INTEL_INFO(dev)->is_pineview)
 937 #define IS_G33(dev)             (INTEL_INFO(dev)->is_g33)
 938 #define IS_IRONLAKE_D(dev)      ((dev)->pci_device == 0x0042)
 939 #define IS_IRONLAKE_M(dev)      ((dev)->pci_device == 0x0046)
 940 #define IS_IVYBRIDGE(dev)       (INTEL_INFO(dev)->is_ivybridge)
 941 #define IS_MOBILE(dev)          (INTEL_INFO(dev)->is_mobile)
 942
 943 /*
 944  * The genX designation typically refers to the render engine, so render
 945  * capability related checks should use IS_GEN, while display and other checks
 946  * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
 947  * chips, etc.).
 948  */
 949 #define IS_GEN2(dev)    (INTEL_INFO(dev)->gen == 2)
 950 #define IS_GEN3(dev)    (INTEL_INFO(dev)->gen == 3)
 951 #define IS_GEN4(dev)    (INTEL_INFO(dev)->gen == 4)
 952 #define IS_GEN5(dev)    (INTEL_INFO(dev)->gen == 5)
 953 #define IS_GEN6(dev)    (INTEL_INFO(dev)->gen == 6)
 954 #define IS_GEN7(dev)    (INTEL_INFO(dev)->gen == 7)
 955
 956 #define HAS_BSD(dev)            (INTEL_INFO(dev)->has_bsd_ring)
 957 #define HAS_BLT(dev)            (INTEL_INFO(dev)->has_blt_ring)
 958 #define I915_NEED_GFX_HWS(dev)  (INTEL_INFO(dev)->need_gfx_hws)
 959
 960 #define HAS_OVERLAY(dev)                (INTEL_INFO(dev)->has_overlay)
 961 #define OVERLAY_NEEDS_PHYSICAL(dev)     (INTEL_INFO(dev)->overlay_needs_physical)
 962
 963 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
 964  * rows, which changed the alignment requirements and fence programming.
 965  */
 966 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
 967                                                       IS_I915GM(dev)))
 968 #define SUPPORTS_DIGITAL_OUTPUTS(dev)   (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
 969 #define SUPPORTS_INTEGRATED_HDMI(dev)   (IS_G4X(dev) || IS_GEN5(dev))
 970 #define SUPPORTS_INTEGRATED_DP(dev)     (IS_G4X(dev) || IS_GEN5(dev))
 971 #define SUPPORTS_EDP(dev)               (IS_IRONLAKE_M(dev))
 972 #define SUPPORTS_TV(dev)                (INTEL_INFO(dev)->supports_tv)
 973 #define I915_HAS_HOTPLUG(dev)            (INTEL_INFO(dev)->has_hotplug)
 974 /* dsparb controlled by hw only */
 975 #define DSPARB_HWCONTROL(dev) (IS_G4X(dev) || IS_IRONLAKE(dev))
 976
 977 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
 978 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
 979 #define I915_HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
 980
 981 #define HAS_PCH_SPLIT(dev) (IS_GEN5(dev) || IS_GEN6(dev) || IS_IVYBRIDGE(dev))
 982 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 983
 984 #define INTEL_PCH_TYPE(dev) (((struct drm_i915_private *)(dev)->dev_private)->pch_type)
 985 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
 986 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
 987
 988 #include "i915_trace.h"
 989
 990 extern struct drm_ioctl_desc i915_ioctls[];
 991 extern int i915_max_ioctl;
 992 extern unsigned int i915_fbpercrtc __always_unused;
 993 extern int i915_panel_ignore_lid __read_mostly;
 994 extern unsigned int i915_powersave __read_mostly;
 995 extern unsigned int i915_semaphores __read_mostly;
 996 extern unsigned int i915_lvds_downclock __read_mostly;
 997 extern unsigned int i915_panel_use_ssc __read_mostly;
 998 extern int i915_vbt_sdvo_panel_type __read_mostly;
 999 extern unsigned int i915_enable_rc6 __read_mostly;
1000 extern unsigned int i915_enable_fbc __read_mostly;
1001 extern bool i915_enable_hangcheck __read_mostly;
1002
1003 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1004 extern int i915_resume(struct drm_device *dev);
1005 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1006 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1007
1008                                 /* i915_dma.c */
1009 extern void i915_kernel_lost_context(struct drm_device * dev);
1010 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1011 extern int i915_driver_unload(struct drm_device *);
1012 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1013 extern void i915_driver_lastclose(struct drm_device * dev);
1014 extern void i915_driver_preclose(struct drm_device *dev,
1015                                  struct drm_file *file_priv);
1016 extern void i915_driver_postclose(struct drm_device *dev,
1017                                   struct drm_file *file_priv);
1018 extern int i915_driver_device_is_agp(struct drm_device * dev);
1019 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1020                               unsigned long arg);
1021 extern int i915_emit_box(struct drm_device *dev,
1022                          struct drm_clip_rect *box,
1023                          int DR1, int DR4);
1024 extern int i915_reset(struct drm_device *dev, u8 flags);
1025 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1026 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1027 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1028 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1029
1030
1031 /* i915_irq.c */
1032 void i915_hangcheck_elapsed(unsigned long data);
1033 void i915_handle_error(struct drm_device *dev, bool wedged);
1034 extern int i915_irq_emit(struct drm_device *dev, void *data,
1035                          struct drm_file *file_priv);
1036 extern int i915_irq_wait(struct drm_device *dev, void *data,
1037                          struct drm_file *file_priv);
1038
1039 extern void intel_irq_init(struct drm_device *dev);
1040
1041 extern int i915_vblank_pipe_set(struct drm_device *dev, void *data,
1042                                 struct drm_file *file_priv);
1043 extern int i915_vblank_pipe_get(struct drm_device *dev, void *data,
1044                                 struct drm_file *file_priv);
1045 extern int i915_vblank_swap(struct drm_device *dev, void *data,
1046                             struct drm_file *file_priv);
1047
1048 void
1049 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1050
1051 void
1052 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask);
1053
1054 void intel_enable_asle (struct drm_device *dev);
1055
1056 #ifdef CONFIG_DEBUG_FS
1057 extern void i915_destroy_error_state(struct drm_device *dev);
1058 #else
1059 #define i915_destroy_error_state(x)
1060 #endif
1061
1062
1063 /* i915_mem.c */
1064 extern int i915_mem_alloc(struct drm_device *dev, void *data,
1065                           struct drm_file *file_priv);
1066 extern int i915_mem_free(struct drm_device *dev, void *data,
1067                          struct drm_file *file_priv);
1068 extern int i915_mem_init_heap(struct drm_device *dev, void *data,
1069                               struct drm_file *file_priv);
1070 extern int i915_mem_destroy_heap(struct drm_device *dev, void *data,
1071                                  struct drm_file *file_priv);
1072 extern void i915_mem_takedown(struct mem_block **heap);
1073 extern void i915_mem_release(struct drm_device * dev,
1074                              struct drm_file *file_priv, struct mem_block *heap);
1075 /* i915_gem.c */
1076 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
1077                         struct drm_file *file_priv);
1078 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
1079                           struct drm_file *file_priv);
1080 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
1081                          struct drm_file *file_priv);
1082 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
1083                           struct drm_file *file_priv);
1084 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
1085                         struct drm_file *file_priv);
1086 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
1087                         struct drm_file *file_priv);
1088 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
1089                               struct drm_file *file_priv);
1090 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
1091                              struct drm_file *file_priv);
1092 int i915_gem_execbuffer(struct drm_device *dev, void *data,
1093                         struct drm_file *file_priv);
1094 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
1095                          struct drm_file *file_priv);
1096 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
1097                        struct drm_file *file_priv);
1098 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
1099                          struct drm_file *file_priv);
1100 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
1101                         struct drm_file *file_priv);
1102 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
1103                             struct drm_file *file_priv);
1104 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
1105                            struct drm_file *file_priv);
1106 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
1107                            struct drm_file *file_priv);
1108 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
1109                            struct drm_file *file_priv);
1110 int i915_gem_set_tiling(struct drm_device *dev, void *data,
1111                         struct drm_file *file_priv);
1112 int i915_gem_get_tiling(struct drm_device *dev, void *data,
1113                         struct drm_file *file_priv);
1114 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
1115                                 struct drm_file *file_priv);
1116 void i915_gem_load(struct drm_device *dev);
1117 int i915_gem_init_object(struct drm_gem_object *obj);
1118 int __must_check i915_gem_flush_ring(struct intel_ring_buffer *ring,
1119                                      uint32_t invalidate_domains,
1120                                      uint32_t flush_domains);
1121 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
1122                                                   size_t size);
1123 void i915_gem_free_object(struct drm_gem_object *obj);
1124 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
1125                                      uint32_t alignment,
1126                                      bool map_and_fenceable);
1127 void i915_gem_object_unpin(struct drm_i915_gem_object *obj);
1128 int __must_check i915_gem_object_unbind(struct drm_i915_gem_object *obj);
1129 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
1130 void i915_gem_lastclose(struct drm_device *dev);
1131
1132 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
1133 int __must_check i915_gem_object_wait_rendering(struct drm_i915_gem_object *obj);
1134 void i915_gem_object_move_to_active(struct drm_i915_gem_object *obj,
1135                                     struct intel_ring_buffer *ring,
1136                                     u32 seqno);
1137
1138 int i915_gem_dumb_create(struct drm_file *file_priv,
1139                          struct drm_device *dev,
1140                          struct drm_mode_create_dumb *args);
1141 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
1142                       uint32_t handle, uint64_t *offset);
1143 int i915_gem_dumb_destroy(struct drm_file *file_priv, struct drm_device *dev,
1144                           uint32_t handle);
1145 /**
1146  * Returns true if seq1 is later than seq2.
1147  */
1148 static inline bool
1149 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
1150 {
1151         return (int32_t)(seq1 - seq2) >= 0;
1152 }
1153
1154 static inline u32
1155 i915_gem_next_request_seqno(struct intel_ring_buffer *ring)
1156 {
1157         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1158         return ring->outstanding_lazy_request = dev_priv->next_seqno;
1159 }
1160
1161 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj,
1162                                            struct intel_ring_buffer *pipelined);
1163 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
1164
1165 void i915_gem_retire_requests(struct drm_device *dev);
1166 void i915_gem_reset(struct drm_device *dev);
1167 void i915_gem_clflush_object(struct drm_i915_gem_object *obj);
1168 int __must_check i915_gem_object_set_domain(struct drm_i915_gem_object *obj,
1169                                             uint32_t read_domains,
1170                                             uint32_t write_domain);
1171 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
1172 int __must_check i915_gem_init_ringbuffer(struct drm_device *dev);
1173 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
1174 void i915_gem_do_init(struct drm_device *dev,
1175                       unsigned long start,
1176                       unsigned long mappable_end,
1177                       unsigned long end);
1178 int __must_check i915_gpu_idle(struct drm_device *dev);
1179 int __must_check i915_gem_idle(struct drm_device *dev);
1180 int __must_check i915_add_request(struct intel_ring_buffer *ring,
1181                                   struct drm_file *file,
1182                                   struct drm_i915_gem_request *request);
1183 int __must_check i915_wait_request(struct intel_ring_buffer *ring,
1184                                    uint32_t seqno);
1185 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
1186 int __must_check
1187 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
1188                                   bool write);
1189 int __must_check
1190 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
1191                                      u32 alignment,
1192                                      struct intel_ring_buffer *pipelined);
1193 int i915_gem_attach_phys_object(struct drm_device *dev,
1194                                 struct drm_i915_gem_object *obj,
1195                                 int id,
1196                                 int align);
1197 void i915_gem_detach_phys_object(struct drm_device *dev,
1198                                  struct drm_i915_gem_object *obj);
1199 void i915_gem_free_all_phys_object(struct drm_device *dev);
1200 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
1201
1202 uint32_t
1203 i915_gem_get_unfenced_gtt_alignment(struct drm_device *dev,
1204                                     uint32_t size,
1205                                     int tiling_mode);
1206
1207 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
1208                                     enum i915_cache_level cache_level);
1209
1210 /* i915_gem_gtt.c */
1211 void i915_gem_restore_gtt_mappings(struct drm_device *dev);
1212 int __must_check i915_gem_gtt_bind_object(struct drm_i915_gem_object *obj);
1213 void i915_gem_gtt_rebind_object(struct drm_i915_gem_object *obj,
1214                                 enum i915_cache_level cache_level);
1215 void i915_gem_gtt_unbind_object(struct drm_i915_gem_object *obj);
1216
1217 /* i915_gem_evict.c */
1218 int __must_check i915_gem_evict_something(struct drm_device *dev, int min_size,
1219                                           unsigned alignment, bool mappable);
1220 int __must_check i915_gem_evict_everything(struct drm_device *dev,
1221                                            bool purgeable_only);
1222 int __must_check i915_gem_evict_inactive(struct drm_device *dev,
1223                                          bool purgeable_only);
1224
1225 /* i915_gem_tiling.c */
1226 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
1227 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
1228 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
1229
1230 /* i915_gem_debug.c */
1231 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1232                           const char *where, uint32_t mark);
1233 #if WATCH_LISTS
1234 int i915_verify_lists(struct drm_device *dev);
1235 #else
1236 #define i915_verify_lists(dev) 0
1237 #endif
1238 void i915_gem_object_check_coherency(struct drm_i915_gem_object *obj,
1239                                      int handle);
1240 void i915_gem_dump_object(struct drm_i915_gem_object *obj, int len,
1241                           const char *where, uint32_t mark);
1242
1243 /* i915_debugfs.c */
1244 int i915_debugfs_init(struct drm_minor *minor);
1245 void i915_debugfs_cleanup(struct drm_minor *minor);
1246
1247 /* i915_suspend.c */
1248 extern int i915_save_state(struct drm_device *dev);
1249 extern int i915_restore_state(struct drm_device *dev);
1250
1251 /* i915_suspend.c */
1252 extern int i915_save_state(struct drm_device *dev);
1253 extern int i915_restore_state(struct drm_device *dev);
1254
1255 /* intel_i2c.c */
1256 extern int intel_setup_gmbus(struct drm_device *dev);
1257 extern void intel_teardown_gmbus(struct drm_device *dev);
1258 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
1259 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
1260 extern inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
1261 {
1262         return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
1263 }
1264 extern void intel_i2c_reset(struct drm_device *dev);
1265
1266 /* intel_opregion.c */
1267 extern int intel_opregion_setup(struct drm_device *dev);
1268 #ifdef CONFIG_ACPI
1269 extern void intel_opregion_init(struct drm_device *dev);
1270 extern void intel_opregion_fini(struct drm_device *dev);
1271 extern void intel_opregion_asle_intr(struct drm_device *dev);
1272 extern void intel_opregion_gse_intr(struct drm_device *dev);
1273 extern void intel_opregion_enable_asle(struct drm_device *dev);
1274 #else
1275 static inline void intel_opregion_init(struct drm_device *dev) { return; }
1276 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
1277 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
1278 static inline void intel_opregion_gse_intr(struct drm_device *dev) { return; }
1279 static inline void intel_opregion_enable_asle(struct drm_device *dev) { return; }
1280 #endif
1281
1282 /* intel_acpi.c */
1283 #ifdef CONFIG_ACPI
1284 extern void intel_register_dsm_handler(void);
1285 extern void intel_unregister_dsm_handler(void);
1286 #else
1287 static inline void intel_register_dsm_handler(void) { return; }
1288 static inline void intel_unregister_dsm_handler(void) { return; }
1289 #endif /* CONFIG_ACPI */
1290
1291 /* modesetting */
1292 extern void intel_modeset_init(struct drm_device *dev);
1293 extern void intel_modeset_gem_init(struct drm_device *dev);
1294 extern void intel_modeset_cleanup(struct drm_device *dev);
1295 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
1296 extern bool intel_fbc_enabled(struct drm_device *dev);
1297 extern void intel_disable_fbc(struct drm_device *dev);
1298 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
1299 extern void ironlake_enable_rc6(struct drm_device *dev);
1300 extern void gen6_set_rps(struct drm_device *dev, u8 val);
1301 extern void intel_detect_pch (struct drm_device *dev);
1302 extern int intel_trans_dp_port_sel (struct drm_crtc *crtc);
1303
1304 /* overlay */
1305 #ifdef CONFIG_DEBUG_FS
1306 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
1307 extern void intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error);
1308
1309 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
1310 extern void intel_display_print_error_state(struct seq_file *m,
1311                                             struct drm_device *dev,
1312                                             struct intel_display_error_state *error);
1313 #endif
1314
1315 #define LP_RING(d) (&((struct drm_i915_private *)(d))->ring[RCS])
1316
1317 #define BEGIN_LP_RING(n) \
1318         intel_ring_begin(LP_RING(dev_priv), (n))
1319
1320 #define OUT_RING(x) \
1321         intel_ring_emit(LP_RING(dev_priv), x)
1322
1323 #define ADVANCE_LP_RING() \
1324         intel_ring_advance(LP_RING(dev_priv))
1325
1326 /**
1327  * Lock test for when it's just for synchronization of ring access.
1328  *
1329  * In that case, we don't need to do it when GEM is initialized as nobody else
1330  * has access to the ring.
1331  */
1332 #define RING_LOCK_TEST_WITH_RETURN(dev, file) do {                      \
1333         if (LP_RING(dev->dev_private)->obj == NULL)                     \
1334                 LOCK_TEST_WITH_RETURN(dev, file);                       \
1335 } while (0)
1336
1337 /* On SNB platform, before reading ring registers forcewake bit
1338  * must be set to prevent GT core from power down and stale values being
1339  * returned.
1340  */
1341 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv);
1342 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv);
1343 void __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv);
1344
1345 /* We give fast paths for the really cool registers */
1346 #define NEEDS_FORCE_WAKE(dev_priv, reg) \
1347         (((dev_priv)->info->gen >= 6) && \
1348         ((reg) < 0x40000) && \
1349         ((reg) != FORCEWAKE))
1350
1351 #define __i915_read(x, y) \
1352 static inline u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
1353         u##x val = 0; \
1354         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1355                 gen6_gt_force_wake_get(dev_priv); \
1356                 val = read##y(dev_priv->regs + reg); \
1357                 gen6_gt_force_wake_put(dev_priv); \
1358         } else { \
1359                 val = read##y(dev_priv->regs + reg); \
1360         } \
1361         trace_i915_reg_rw(false, reg, val, sizeof(val)); \
1362         return val; \
1363 }
1364
1365 __i915_read(8, b)
1366 __i915_read(16, w)
1367 __i915_read(32, l)
1368 __i915_read(64, q)
1369 #undef __i915_read
1370
1371 #define __i915_write(x, y) \
1372 static inline void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
1373         trace_i915_reg_rw(true, reg, val, sizeof(val)); \
1374         if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
1375                 __gen6_gt_wait_for_fifo(dev_priv); \
1376         } \
1377         write##y(val, dev_priv->regs + reg); \
1378 }
1379 __i915_write(8, b)
1380 __i915_write(16, w)
1381 __i915_write(32, l)
1382 __i915_write(64, q)
1383 #undef __i915_write
1384
1385 #define I915_READ8(reg)         i915_read8(dev_priv, (reg))
1386 #define I915_WRITE8(reg, val)   i915_write8(dev_priv, (reg), (val))
1387
1388 #define I915_READ16(reg)        i915_read16(dev_priv, (reg))
1389 #define I915_WRITE16(reg, val)  i915_write16(dev_priv, (reg), (val))
1390 #define I915_READ16_NOTRACE(reg)        readw(dev_priv->regs + (reg))
1391 #define I915_WRITE16_NOTRACE(reg, val)  writew(val, dev_priv->regs + (reg))
1392
1393 #define I915_READ(reg)          i915_read32(dev_priv, (reg))
1394 #define I915_WRITE(reg, val)    i915_write32(dev_priv, (reg), (val))
1395 #define I915_READ_NOTRACE(reg)          readl(dev_priv->regs + (reg))
1396 #define I915_WRITE_NOTRACE(reg, val)    writel(val, dev_priv->regs + (reg))
1397
1398 #define I915_WRITE64(reg, val)  i915_write64(dev_priv, (reg), (val))
1399 #define I915_READ64(reg)        i915_read64(dev_priv, (reg))
1400
1401 #define POSTING_READ(reg)       (void)I915_READ_NOTRACE(reg)
1402 #define POSTING_READ16(reg)     (void)I915_READ16_NOTRACE(reg)
1403
1404
1405 #endif