1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
34 #include <uapi/drm/drm_fourcc.h>
37 #include "intel_bios.h"
38 #include "intel_ringbuffer.h"
39 #include "intel_lrc.h"
40 #include "i915_gem_gtt.h"
41 #include "i915_gem_render_state.h"
42 #include <linux/io-mapping.h>
43 #include <linux/i2c.h>
44 #include <linux/i2c-algo-bit.h>
45 #include <drm/intel-gtt.h>
46 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
47 #include <drm/drm_gem.h>
48 #include <linux/backlight.h>
49 #include <linux/hashtable.h>
50 #include <linux/intel-iommu.h>
51 #include <linux/kref.h>
52 #include <linux/pm_qos.h>
54 /* General customization:
57 #define DRIVER_NAME "i915"
58 #define DRIVER_DESC "Intel Graphics"
59 #define DRIVER_DATE "20150423"
62 /* Many gcc seem to no see through this and fall over :( */
64 #define WARN_ON(x) ({ \
65 bool __i915_warn_cond = (x); \
66 if (__builtin_constant_p(__i915_warn_cond)) \
67 BUILD_BUG_ON(__i915_warn_cond); \
68 WARN(__i915_warn_cond, "WARN_ON(" #x ")"); })
70 #define WARN_ON(x) WARN((x), "WARN_ON(" #x ")")
74 #define WARN_ON_ONCE(x) WARN_ONCE((x), "WARN_ON_ONCE(" #x ")")
76 #define MISSING_CASE(x) WARN(1, "Missing switch case (%lu) in %s\n", \
77 (long) (x), __func__);
79 /* Use I915_STATE_WARN(x) and I915_STATE_WARN_ON() (rather than WARN() and
80 * WARN_ON()) for hw state sanity checks to check for unexpected conditions
81 * which may not necessarily be a user visible problem. This will either
82 * WARN() or DRM_ERROR() depending on the verbose_checks moduleparam, to
83 * enable distros and users to tailor their preferred amount of i915 abrt
86 #define I915_STATE_WARN(condition, format...) ({ \
87 int __ret_warn_on = !!(condition); \
88 if (unlikely(__ret_warn_on)) { \
89 if (i915.verbose_state_checks) \
94 unlikely(__ret_warn_on); \
97 #define I915_STATE_WARN_ON(condition) ({ \
98 int __ret_warn_on = !!(condition); \
99 if (unlikely(__ret_warn_on)) { \
100 if (i915.verbose_state_checks) \
101 WARN(1, "WARN_ON(" #condition ")\n"); \
103 DRM_ERROR("WARN_ON(" #condition ")\n"); \
105 unlikely(__ret_warn_on); \
114 I915_MAX_PIPES
= _PIPE_EDP
116 #define pipe_name(p) ((p) + 'A')
125 #define transcoder_name(t) ((t) + 'A')
128 * This is the maximum (across all platforms) number of planes (primary +
129 * sprites) that can be active at the same time on one pipe.
131 * This value doesn't count the cursor plane.
133 #define I915_MAX_PLANES 4
140 #define plane_name(p) ((p) + 'A')
142 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
152 #define port_name(p) ((p) + 'A')
154 #define I915_NUM_PHYS_VLV 2
166 enum intel_display_power_domain
{
170 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
171 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
172 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
173 POWER_DOMAIN_TRANSCODER_A
,
174 POWER_DOMAIN_TRANSCODER_B
,
175 POWER_DOMAIN_TRANSCODER_C
,
176 POWER_DOMAIN_TRANSCODER_EDP
,
177 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
178 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
179 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
180 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
181 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
182 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
183 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
184 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
185 POWER_DOMAIN_PORT_DSI
,
186 POWER_DOMAIN_PORT_CRT
,
187 POWER_DOMAIN_PORT_OTHER
,
200 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
201 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
202 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
203 #define POWER_DOMAIN_TRANSCODER(tran) \
204 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
205 (tran) + POWER_DOMAIN_TRANSCODER_A)
209 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
210 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
220 #define I915_GEM_GPU_DOMAINS \
221 (I915_GEM_DOMAIN_RENDER | \
222 I915_GEM_DOMAIN_SAMPLER | \
223 I915_GEM_DOMAIN_COMMAND | \
224 I915_GEM_DOMAIN_INSTRUCTION | \
225 I915_GEM_DOMAIN_VERTEX)
227 #define for_each_pipe(__dev_priv, __p) \
228 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
229 #define for_each_plane(__dev_priv, __pipe, __p) \
231 (__p) < INTEL_INFO(__dev_priv)->num_sprites[(__pipe)] + 1; \
233 #define for_each_sprite(__dev_priv, __p, __s) \
235 (__s) < INTEL_INFO(__dev_priv)->num_sprites[(__p)]; \
238 #define for_each_crtc(dev, crtc) \
239 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
241 #define for_each_intel_plane(dev, intel_plane) \
242 list_for_each_entry(intel_plane, \
243 &dev->mode_config.plane_list, \
246 #define for_each_intel_crtc(dev, intel_crtc) \
247 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
249 #define for_each_intel_encoder(dev, intel_encoder) \
250 list_for_each_entry(intel_encoder, \
251 &(dev)->mode_config.encoder_list, \
254 #define for_each_intel_connector(dev, intel_connector) \
255 list_for_each_entry(intel_connector, \
256 &dev->mode_config.connector_list, \
259 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
260 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
261 if ((intel_encoder)->base.crtc == (__crtc))
263 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
264 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
265 if ((intel_connector)->base.encoder == (__encoder))
267 #define for_each_power_domain(domain, mask) \
268 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
269 if ((1 << (domain)) & (mask))
271 struct drm_i915_private
;
272 struct i915_mm_struct
;
273 struct i915_mmu_object
;
276 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
277 /* real shared dpll ids must be >= 0 */
278 DPLL_ID_PCH_PLL_A
= 0,
279 DPLL_ID_PCH_PLL_B
= 1,
284 DPLL_ID_SKL_DPLL1
= 0,
285 DPLL_ID_SKL_DPLL2
= 1,
286 DPLL_ID_SKL_DPLL3
= 2,
288 #define I915_NUM_PLLS 3
290 struct intel_dpll_hw_state
{
302 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
303 * lower part of ctrl1 and they get shifted into position when writing
304 * the register. This allows us to easily compare the state to share
308 /* HDMI only, 0 when used for DP */
309 uint32_t cfgcr1
, cfgcr2
;
312 uint32_t ebb0
, pll0
, pll1
, pll2
, pll3
, pll6
, pll8
, pcsdw12
;
315 struct intel_shared_dpll_config
{
316 unsigned crtc_mask
; /* mask of CRTCs sharing this PLL */
317 struct intel_dpll_hw_state hw_state
;
320 struct intel_shared_dpll
{
321 struct intel_shared_dpll_config config
;
322 struct intel_shared_dpll_config
*new_config
;
324 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
325 bool on
; /* is the PLL actually active? Disabled during modeset */
327 /* should match the index in the dev_priv->shared_dplls array */
328 enum intel_dpll_id id
;
329 /* The mode_set hook is optional and should be used together with the
330 * intel_prepare_shared_dpll function. */
331 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
332 struct intel_shared_dpll
*pll
);
333 void (*enable
)(struct drm_i915_private
*dev_priv
,
334 struct intel_shared_dpll
*pll
);
335 void (*disable
)(struct drm_i915_private
*dev_priv
,
336 struct intel_shared_dpll
*pll
);
337 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
338 struct intel_shared_dpll
*pll
,
339 struct intel_dpll_hw_state
*hw_state
);
347 /* Used by dp and fdi links */
348 struct intel_link_m_n
{
356 void intel_link_compute_m_n(int bpp
, int nlanes
,
357 int pixel_clock
, int link_clock
,
358 struct intel_link_m_n
*m_n
);
360 /* Interface history:
363 * 1.2: Add Power Management
364 * 1.3: Add vblank support
365 * 1.4: Fix cmdbuffer path, add heap destroy
366 * 1.5: Add vblank pipe configuration
367 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
368 * - Support vertical blank on secondary display pipe
370 #define DRIVER_MAJOR 1
371 #define DRIVER_MINOR 6
372 #define DRIVER_PATCHLEVEL 0
374 #define WATCH_LISTS 0
376 struct opregion_header
;
377 struct opregion_acpi
;
378 struct opregion_swsci
;
379 struct opregion_asle
;
381 struct intel_opregion
{
382 struct opregion_header __iomem
*header
;
383 struct opregion_acpi __iomem
*acpi
;
384 struct opregion_swsci __iomem
*swsci
;
385 u32 swsci_gbda_sub_functions
;
386 u32 swsci_sbcb_sub_functions
;
387 struct opregion_asle __iomem
*asle
;
389 u32 __iomem
*lid_state
;
390 struct work_struct asle_work
;
392 #define OPREGION_SIZE (8*1024)
394 struct intel_overlay
;
395 struct intel_overlay_error_state
;
397 #define I915_FENCE_REG_NONE -1
398 #define I915_MAX_NUM_FENCES 32
399 /* 32 fences + sign bit for FENCE_REG_NONE */
400 #define I915_MAX_NUM_FENCE_BITS 6
402 struct drm_i915_fence_reg
{
403 struct list_head lru_list
;
404 struct drm_i915_gem_object
*obj
;
408 struct sdvo_device_mapping
{
417 struct intel_display_error_state
;
419 struct drm_i915_error_state
{
427 /* Generic register state */
435 u32 error
; /* gen6+ */
436 u32 err_int
; /* gen7 */
437 u32 fault_data0
; /* gen8, gen9 */
438 u32 fault_data1
; /* gen8, gen9 */
444 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
445 u64 fence
[I915_MAX_NUM_FENCES
];
446 struct intel_overlay_error_state
*overlay
;
447 struct intel_display_error_state
*display
;
448 struct drm_i915_error_object
*semaphore_obj
;
450 struct drm_i915_error_ring
{
452 /* Software tracked state */
455 enum intel_ring_hangcheck_action hangcheck_action
;
458 /* our own tracking of ring head and tail */
462 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
481 u32 rc_psmi
; /* sleep state */
482 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
484 struct drm_i915_error_object
{
488 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
490 struct drm_i915_error_request
{
505 char comm
[TASK_COMM_LEN
];
506 } ring
[I915_NUM_RINGS
];
508 struct drm_i915_error_buffer
{
515 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
523 } **active_bo
, **pinned_bo
;
525 u32
*active_bo_count
, *pinned_bo_count
;
529 struct intel_connector
;
530 struct intel_encoder
;
531 struct intel_crtc_state
;
532 struct intel_initial_plane_config
;
537 struct drm_i915_display_funcs
{
538 bool (*fbc_enabled
)(struct drm_device
*dev
);
539 void (*enable_fbc
)(struct drm_crtc
*crtc
);
540 void (*disable_fbc
)(struct drm_device
*dev
);
541 int (*get_display_clock_speed
)(struct drm_device
*dev
);
542 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
544 * find_dpll() - Find the best values for the PLL
545 * @limit: limits for the PLL
546 * @crtc: current CRTC
547 * @target: target frequency in kHz
548 * @refclk: reference clock frequency in kHz
549 * @match_clock: if provided, @best_clock P divider must
550 * match the P divider from @match_clock
551 * used for LVDS downclocking
552 * @best_clock: best PLL values found
554 * Returns true on success, false on failure.
556 bool (*find_dpll
)(const struct intel_limit
*limit
,
557 struct intel_crtc_state
*crtc_state
,
558 int target
, int refclk
,
559 struct dpll
*match_clock
,
560 struct dpll
*best_clock
);
561 void (*update_wm
)(struct drm_crtc
*crtc
);
562 void (*update_sprite_wm
)(struct drm_plane
*plane
,
563 struct drm_crtc
*crtc
,
564 uint32_t sprite_width
, uint32_t sprite_height
,
565 int pixel_size
, bool enable
, bool scaled
);
566 void (*modeset_global_resources
)(struct drm_atomic_state
*state
);
567 /* Returns the active state of the crtc, and if the crtc is active,
568 * fills out the pipe-config with the hw state. */
569 bool (*get_pipe_config
)(struct intel_crtc
*,
570 struct intel_crtc_state
*);
571 void (*get_initial_plane_config
)(struct intel_crtc
*,
572 struct intel_initial_plane_config
*);
573 int (*crtc_compute_clock
)(struct intel_crtc
*crtc
,
574 struct intel_crtc_state
*crtc_state
);
575 void (*crtc_enable
)(struct drm_crtc
*crtc
);
576 void (*crtc_disable
)(struct drm_crtc
*crtc
);
577 void (*off
)(struct drm_crtc
*crtc
);
578 void (*audio_codec_enable
)(struct drm_connector
*connector
,
579 struct intel_encoder
*encoder
,
580 struct drm_display_mode
*mode
);
581 void (*audio_codec_disable
)(struct intel_encoder
*encoder
);
582 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
583 void (*init_clock_gating
)(struct drm_device
*dev
);
584 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
585 struct drm_framebuffer
*fb
,
586 struct drm_i915_gem_object
*obj
,
587 struct intel_engine_cs
*ring
,
589 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
590 struct drm_framebuffer
*fb
,
592 void (*hpd_irq_setup
)(struct drm_device
*dev
);
593 /* clock updates for mode set */
595 /* render clock increase/decrease */
596 /* display clock increase/decrease */
597 /* pll clock increase/decrease */
599 int (*setup_backlight
)(struct intel_connector
*connector
, enum pipe pipe
);
600 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
601 void (*set_backlight
)(struct intel_connector
*connector
,
603 void (*disable_backlight
)(struct intel_connector
*connector
);
604 void (*enable_backlight
)(struct intel_connector
*connector
);
607 enum forcewake_domain_id
{
608 FW_DOMAIN_ID_RENDER
= 0,
609 FW_DOMAIN_ID_BLITTER
,
615 enum forcewake_domains
{
616 FORCEWAKE_RENDER
= (1 << FW_DOMAIN_ID_RENDER
),
617 FORCEWAKE_BLITTER
= (1 << FW_DOMAIN_ID_BLITTER
),
618 FORCEWAKE_MEDIA
= (1 << FW_DOMAIN_ID_MEDIA
),
619 FORCEWAKE_ALL
= (FORCEWAKE_RENDER
|
624 struct intel_uncore_funcs
{
625 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
626 enum forcewake_domains domains
);
627 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
628 enum forcewake_domains domains
);
630 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
631 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
632 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
633 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
635 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
636 uint8_t val
, bool trace
);
637 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
638 uint16_t val
, bool trace
);
639 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
640 uint32_t val
, bool trace
);
641 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
642 uint64_t val
, bool trace
);
645 struct intel_uncore
{
646 spinlock_t lock
; /** lock is also taken in irq contexts. */
648 struct intel_uncore_funcs funcs
;
651 enum forcewake_domains fw_domains
;
653 struct intel_uncore_forcewake_domain
{
654 struct drm_i915_private
*i915
;
655 enum forcewake_domain_id id
;
657 struct timer_list timer
;
664 } fw_domain
[FW_DOMAIN_ID_COUNT
];
667 /* Iterate over initialised fw domains */
668 #define for_each_fw_domain_mask(domain__, mask__, dev_priv__, i__) \
669 for ((i__) = 0, (domain__) = &(dev_priv__)->uncore.fw_domain[0]; \
670 (i__) < FW_DOMAIN_ID_COUNT; \
671 (i__)++, (domain__) = &(dev_priv__)->uncore.fw_domain[i__]) \
672 if (((mask__) & (dev_priv__)->uncore.fw_domains) & (1 << (i__)))
674 #define for_each_fw_domain(domain__, dev_priv__, i__) \
675 for_each_fw_domain_mask(domain__, FORCEWAKE_ALL, dev_priv__, i__)
678 FW_UNINITIALIZED
= 0,
686 uint32_t dmc_fw_size
;
688 uint32_t mmioaddr
[8];
689 uint32_t mmiodata
[8];
690 enum csr_state state
;
693 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
694 func(is_mobile) sep \
697 func(is_i945gm) sep \
699 func(need_gfx_hws) sep \
701 func(is_pineview) sep \
702 func(is_broadwater) sep \
703 func(is_crestline) sep \
704 func(is_ivybridge) sep \
705 func(is_valleyview) sep \
706 func(is_haswell) sep \
707 func(is_skylake) sep \
708 func(is_preliminary) sep \
710 func(has_pipe_cxsr) sep \
711 func(has_hotplug) sep \
712 func(cursor_needs_physical) sep \
713 func(has_overlay) sep \
714 func(overlay_needs_physical) sep \
715 func(supports_tv) sep \
720 #define DEFINE_FLAG(name) u8 name:1
721 #define SEP_SEMICOLON ;
723 struct intel_device_info
{
724 u32 display_mmio_offset
;
727 u8 num_sprites
[I915_MAX_PIPES
];
729 u8 ring_mask
; /* Rings supported by the HW */
730 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
731 /* Register offsets for the various display pipes and transcoders */
732 int pipe_offsets
[I915_MAX_TRANSCODERS
];
733 int trans_offsets
[I915_MAX_TRANSCODERS
];
734 int palette_offsets
[I915_MAX_PIPES
];
735 int cursor_offsets
[I915_MAX_PIPES
];
737 /* Slice/subslice/EU info */
740 u8 subslice_per_slice
;
743 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
746 u8 has_subslice_pg
:1;
753 enum i915_cache_level
{
755 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
756 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
757 caches, eg sampler/render caches, and the
758 large Last-Level-Cache. LLC is coherent with
759 the CPU, but L3 is only visible to the GPU. */
760 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
763 struct i915_ctx_hang_stats
{
764 /* This context had batch pending when hang was declared */
765 unsigned batch_pending
;
767 /* This context had batch active when hang was declared */
768 unsigned batch_active
;
770 /* Time when this context was last blamed for a GPU reset */
771 unsigned long guilty_ts
;
773 /* If the contexts causes a second GPU hang within this time,
774 * it is permanently banned from submitting any more work.
776 unsigned long ban_period_seconds
;
778 /* This context is banned to submit more work */
782 /* This must match up with the value previously used for execbuf2.rsvd1. */
783 #define DEFAULT_CONTEXT_HANDLE 0
785 * struct intel_context - as the name implies, represents a context.
786 * @ref: reference count.
787 * @user_handle: userspace tracking identity for this context.
788 * @remap_slice: l3 row remapping information.
789 * @file_priv: filp associated with this context (NULL for global default
791 * @hang_stats: information about the role of this context in possible GPU
793 * @ppgtt: virtual memory space used by this context.
794 * @legacy_hw_ctx: render context backing object and whether it is correctly
795 * initialized (legacy ring submission mechanism only).
796 * @link: link in the global list of contexts.
798 * Contexts are memory images used by the hardware to store copies of their
801 struct intel_context
{
805 struct drm_i915_file_private
*file_priv
;
806 struct i915_ctx_hang_stats hang_stats
;
807 struct i915_hw_ppgtt
*ppgtt
;
809 /* Legacy ring buffer submission */
811 struct drm_i915_gem_object
*rcs_state
;
816 bool rcs_initialized
;
818 struct drm_i915_gem_object
*state
;
819 struct intel_ringbuffer
*ringbuf
;
821 } engine
[I915_NUM_RINGS
];
823 struct list_head link
;
834 unsigned long uncompressed_size
;
837 unsigned int possible_framebuffer_bits
;
838 unsigned int busy_bits
;
839 struct intel_crtc
*crtc
;
842 struct drm_mm_node compressed_fb
;
843 struct drm_mm_node
*compressed_llb
;
847 /* Tracks whether the HW is actually enabled, not whether the feature is
851 struct intel_fbc_work
{
852 struct delayed_work work
;
853 struct drm_crtc
*crtc
;
854 struct drm_framebuffer
*fb
;
858 FBC_OK
, /* FBC is enabled */
859 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
860 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
861 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
862 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
863 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
864 FBC_BAD_PLANE
, /* fbc not supported on plane */
865 FBC_NOT_TILED
, /* buffer not tiled */
866 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
868 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
873 * HIGH_RR is the highest eDP panel refresh rate read from EDID
874 * LOW_RR is the lowest eDP panel refresh rate found from EDID
875 * parsing for same resolution.
877 enum drrs_refresh_rate_type
{
880 DRRS_MAX_RR
, /* RR count */
883 enum drrs_support_type
{
884 DRRS_NOT_SUPPORTED
= 0,
885 STATIC_DRRS_SUPPORT
= 1,
886 SEAMLESS_DRRS_SUPPORT
= 2
892 struct delayed_work work
;
894 unsigned busy_frontbuffer_bits
;
895 enum drrs_refresh_rate_type refresh_rate_type
;
896 enum drrs_support_type type
;
903 struct intel_dp
*enabled
;
905 struct delayed_work work
;
906 unsigned busy_frontbuffer_bits
;
912 PCH_NONE
= 0, /* No PCH present */
913 PCH_IBX
, /* Ibexpeak PCH */
914 PCH_CPT
, /* Cougarpoint PCH */
915 PCH_LPT
, /* Lynxpoint PCH */
916 PCH_SPT
, /* Sunrisepoint PCH */
920 enum intel_sbi_destination
{
925 #define QUIRK_PIPEA_FORCE (1<<0)
926 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
927 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
928 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
929 #define QUIRK_PIPEB_FORCE (1<<4)
930 #define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
933 struct intel_fbc_work
;
936 struct i2c_adapter adapter
;
940 struct i2c_algo_bit_data bit_algo
;
941 struct drm_i915_private
*dev_priv
;
944 struct i915_suspend_saved_registers
{
947 u32 savePP_ON_DELAYS
;
948 u32 savePP_OFF_DELAYS
;
954 u32 saveCACHE_MODE_0
;
955 u32 saveMI_ARB_STATE
;
959 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
960 u32 savePCH_PORT_HOTPLUG
;
964 struct vlv_s0ix_state
{
971 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
972 u32 media_max_req_count
;
973 u32 gfx_max_req_count
;
1005 /* Display 1 CZ domain */
1010 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
1012 /* GT SA CZ domain */
1019 /* Display 2 CZ domain */
1023 u32 clock_gate_dis2
;
1026 struct intel_rps_ei
{
1032 struct intel_gen6_power_mgmt
{
1034 * work, interrupts_enabled and pm_iir are protected by
1035 * dev_priv->irq_lock
1037 struct work_struct work
;
1038 bool interrupts_enabled
;
1041 /* Frequencies are stored in potentially platform dependent multiples.
1042 * In other words, *_freq needs to be multiplied by X to be interesting.
1043 * Soft limits are those which are used for the dynamic reclocking done
1044 * by the driver (raise frequencies under heavy loads, and lower for
1045 * lighter loads). Hard limits are those imposed by the hardware.
1047 * A distinction is made for overclocking, which is never enabled by
1048 * default, and is considered to be above the hard limit if it's
1051 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
1052 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
1053 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
1054 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
1055 u8 min_freq
; /* AKA RPn. Minimum frequency */
1056 u8 idle_freq
; /* Frequency to request when we are idle */
1057 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
1058 u8 rp1_freq
; /* "less than" RP0 power/freqency */
1059 u8 rp0_freq
; /* Non-overclocked max frequency. */
1062 u8 up_threshold
; /* Current %busy required to uplock */
1063 u8 down_threshold
; /* Current %busy required to downclock */
1066 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1069 struct delayed_work delayed_resume_work
;
1070 struct list_head clients
;
1073 /* manual wa residency calculations */
1074 struct intel_rps_ei up_ei
, down_ei
;
1077 * Protects RPS/RC6 register access and PCU communication.
1078 * Must be taken after struct_mutex if nested.
1080 struct mutex hw_lock
;
1083 /* defined intel_pm.c */
1084 extern spinlock_t mchdev_lock
;
1086 struct intel_ilk_power_mgmt
{
1094 unsigned long last_time1
;
1095 unsigned long chipset_power
;
1098 unsigned long gfx_power
;
1105 struct drm_i915_private
;
1106 struct i915_power_well
;
1108 struct i915_power_well_ops
{
1110 * Synchronize the well's hw state to match the current sw state, for
1111 * example enable/disable it based on the current refcount. Called
1112 * during driver init and resume time, possibly after first calling
1113 * the enable/disable handlers.
1115 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1116 struct i915_power_well
*power_well
);
1118 * Enable the well and resources that depend on it (for example
1119 * interrupts located on the well). Called after the 0->1 refcount
1122 void (*enable
)(struct drm_i915_private
*dev_priv
,
1123 struct i915_power_well
*power_well
);
1125 * Disable the well and resources that depend on it. Called after
1126 * the 1->0 refcount transition.
1128 void (*disable
)(struct drm_i915_private
*dev_priv
,
1129 struct i915_power_well
*power_well
);
1130 /* Returns the hw enabled state. */
1131 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1132 struct i915_power_well
*power_well
);
1135 /* Power well structure for haswell */
1136 struct i915_power_well
{
1139 /* power well enable/disable usage count */
1141 /* cached hw enabled state */
1143 unsigned long domains
;
1145 const struct i915_power_well_ops
*ops
;
1148 struct i915_power_domains
{
1150 * Power wells needed for initialization at driver init and suspend
1151 * time are on. They are kept on until after the first modeset.
1155 int power_well_count
;
1158 int domain_use_count
[POWER_DOMAIN_NUM
];
1159 struct i915_power_well
*power_wells
;
1162 #define MAX_L3_SLICES 2
1163 struct intel_l3_parity
{
1164 u32
*remap_info
[MAX_L3_SLICES
];
1165 struct work_struct error_work
;
1169 struct i915_gem_mm
{
1170 /** Memory allocator for GTT stolen memory */
1171 struct drm_mm stolen
;
1172 /** List of all objects in gtt_space. Used to restore gtt
1173 * mappings on resume */
1174 struct list_head bound_list
;
1176 * List of objects which are not bound to the GTT (thus
1177 * are idle and not used by the GPU) but still have
1178 * (presumably uncached) pages still attached.
1180 struct list_head unbound_list
;
1182 /** Usable portion of the GTT for GEM */
1183 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1185 /** PPGTT used for aliasing the PPGTT with the GTT */
1186 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1188 struct notifier_block oom_notifier
;
1189 struct shrinker shrinker
;
1190 bool shrinker_no_lock_stealing
;
1192 /** LRU list of objects with fence regs on them. */
1193 struct list_head fence_list
;
1196 * We leave the user IRQ off as much as possible,
1197 * but this means that requests will finish and never
1198 * be retired once the system goes idle. Set a timer to
1199 * fire periodically while the ring is running. When it
1200 * fires, go retire requests.
1202 struct delayed_work retire_work
;
1205 * When we detect an idle GPU, we want to turn on
1206 * powersaving features. So once we see that there
1207 * are no more requests outstanding and no more
1208 * arrive within a small period of time, we fire
1209 * off the idle_work.
1211 struct delayed_work idle_work
;
1214 * Are we in a non-interruptible section of code like
1220 * Is the GPU currently considered idle, or busy executing userspace
1221 * requests? Whilst idle, we attempt to power down the hardware and
1222 * display clocks. In order to reduce the effect on performance, there
1223 * is a slight delay before we do so.
1227 /* the indicator for dispatch video commands on two BSD rings */
1228 int bsd_ring_dispatch_index
;
1230 /** Bit 6 swizzling required for X tiling */
1231 uint32_t bit_6_swizzle_x
;
1232 /** Bit 6 swizzling required for Y tiling */
1233 uint32_t bit_6_swizzle_y
;
1235 /* accounting, useful for userland debugging */
1236 spinlock_t object_stat_lock
;
1237 size_t object_memory
;
1241 struct drm_i915_error_state_buf
{
1242 struct drm_i915_private
*i915
;
1251 struct i915_error_state_file_priv
{
1252 struct drm_device
*dev
;
1253 struct drm_i915_error_state
*error
;
1256 struct i915_gpu_error
{
1257 /* For hangcheck timer */
1258 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1259 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1260 /* Hang gpu twice in this window and your context gets banned */
1261 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1263 struct workqueue_struct
*hangcheck_wq
;
1264 struct delayed_work hangcheck_work
;
1266 /* For reset and error_state handling. */
1268 /* Protected by the above dev->gpu_error.lock. */
1269 struct drm_i915_error_state
*first_error
;
1271 unsigned long missed_irq_rings
;
1274 * State variable controlling the reset flow and count
1276 * This is a counter which gets incremented when reset is triggered,
1277 * and again when reset has been handled. So odd values (lowest bit set)
1278 * means that reset is in progress and even values that
1279 * (reset_counter >> 1):th reset was successfully completed.
1281 * If reset is not completed succesfully, the I915_WEDGE bit is
1282 * set meaning that hardware is terminally sour and there is no
1283 * recovery. All waiters on the reset_queue will be woken when
1286 * This counter is used by the wait_seqno code to notice that reset
1287 * event happened and it needs to restart the entire ioctl (since most
1288 * likely the seqno it waited for won't ever signal anytime soon).
1290 * This is important for lock-free wait paths, where no contended lock
1291 * naturally enforces the correct ordering between the bail-out of the
1292 * waiter and the gpu reset work code.
1294 atomic_t reset_counter
;
1296 #define I915_RESET_IN_PROGRESS_FLAG 1
1297 #define I915_WEDGED (1 << 31)
1300 * Waitqueue to signal when the reset has completed. Used by clients
1301 * that wait for dev_priv->mm.wedged to settle.
1303 wait_queue_head_t reset_queue
;
1305 /* Userspace knobs for gpu hang simulation;
1306 * combines both a ring mask, and extra flags
1309 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1310 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1312 /* For missed irq/seqno simulation. */
1313 unsigned int test_irq_rings
;
1315 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1316 bool reload_in_reset
;
1319 enum modeset_restore
{
1320 MODESET_ON_LID_OPEN
,
1325 struct ddi_vbt_port_info
{
1327 * This is an index in the HDMI/DVI DDI buffer translation table.
1328 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1329 * populate this field.
1331 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1332 uint8_t hdmi_level_shift
;
1334 uint8_t supports_dvi
:1;
1335 uint8_t supports_hdmi
:1;
1336 uint8_t supports_dp
:1;
1339 enum psr_lines_to_wait
{
1340 PSR_0_LINES_TO_WAIT
= 0,
1342 PSR_4_LINES_TO_WAIT
,
1346 struct intel_vbt_data
{
1347 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1348 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1351 unsigned int int_tv_support
:1;
1352 unsigned int lvds_dither
:1;
1353 unsigned int lvds_vbt
:1;
1354 unsigned int int_crt_support
:1;
1355 unsigned int lvds_use_ssc
:1;
1356 unsigned int display_clock_mode
:1;
1357 unsigned int fdi_rx_polarity_inverted
:1;
1358 unsigned int has_mipi
:1;
1360 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1362 enum drrs_support_type drrs_type
;
1367 int edp_preemphasis
;
1369 bool edp_initialized
;
1372 struct edp_power_seq edp_pps
;
1376 bool require_aux_wakeup
;
1378 enum psr_lines_to_wait lines_to_wait
;
1379 int tp1_wakeup_time
;
1380 int tp2_tp3_wakeup_time
;
1386 bool active_low_pwm
;
1387 u8 min_brightness
; /* min_brightness/255 of max */
1394 struct mipi_config
*config
;
1395 struct mipi_pps_data
*pps
;
1399 u8
*sequence
[MIPI_SEQ_MAX
];
1405 union child_device_config
*child_dev
;
1407 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1410 enum intel_ddb_partitioning
{
1412 INTEL_DDB_PART_5_6
, /* IVB+ */
1415 struct intel_wm_level
{
1423 struct ilk_wm_values
{
1424 uint32_t wm_pipe
[3];
1426 uint32_t wm_lp_spr
[3];
1427 uint32_t wm_linetime
[3];
1429 enum intel_ddb_partitioning partitioning
;
1432 struct vlv_wm_values
{
1451 struct skl_ddb_entry
{
1452 uint16_t start
, end
; /* in number of blocks, 'end' is exclusive */
1455 static inline uint16_t skl_ddb_entry_size(const struct skl_ddb_entry
*entry
)
1457 return entry
->end
- entry
->start
;
1460 static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry
*e1
,
1461 const struct skl_ddb_entry
*e2
)
1463 if (e1
->start
== e2
->start
&& e1
->end
== e2
->end
)
1469 struct skl_ddb_allocation
{
1470 struct skl_ddb_entry pipe
[I915_MAX_PIPES
];
1471 struct skl_ddb_entry plane
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1472 struct skl_ddb_entry cursor
[I915_MAX_PIPES
];
1475 struct skl_wm_values
{
1476 bool dirty
[I915_MAX_PIPES
];
1477 struct skl_ddb_allocation ddb
;
1478 uint32_t wm_linetime
[I915_MAX_PIPES
];
1479 uint32_t plane
[I915_MAX_PIPES
][I915_MAX_PLANES
][8];
1480 uint32_t cursor
[I915_MAX_PIPES
][8];
1481 uint32_t plane_trans
[I915_MAX_PIPES
][I915_MAX_PLANES
];
1482 uint32_t cursor_trans
[I915_MAX_PIPES
];
1485 struct skl_wm_level
{
1486 bool plane_en
[I915_MAX_PLANES
];
1488 uint16_t plane_res_b
[I915_MAX_PLANES
];
1489 uint8_t plane_res_l
[I915_MAX_PLANES
];
1490 uint16_t cursor_res_b
;
1491 uint8_t cursor_res_l
;
1495 * This struct helps tracking the state needed for runtime PM, which puts the
1496 * device in PCI D3 state. Notice that when this happens, nothing on the
1497 * graphics device works, even register access, so we don't get interrupts nor
1500 * Every piece of our code that needs to actually touch the hardware needs to
1501 * either call intel_runtime_pm_get or call intel_display_power_get with the
1502 * appropriate power domain.
1504 * Our driver uses the autosuspend delay feature, which means we'll only really
1505 * suspend if we stay with zero refcount for a certain amount of time. The
1506 * default value is currently very conservative (see intel_runtime_pm_enable), but
1507 * it can be changed with the standard runtime PM files from sysfs.
1509 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1510 * goes back to false exactly before we reenable the IRQs. We use this variable
1511 * to check if someone is trying to enable/disable IRQs while they're supposed
1512 * to be disabled. This shouldn't happen and we'll print some error messages in
1515 * For more, read the Documentation/power/runtime_pm.txt.
1517 struct i915_runtime_pm
{
1522 enum intel_pipe_crc_source
{
1523 INTEL_PIPE_CRC_SOURCE_NONE
,
1524 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1525 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1526 INTEL_PIPE_CRC_SOURCE_PF
,
1527 INTEL_PIPE_CRC_SOURCE_PIPE
,
1528 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1529 INTEL_PIPE_CRC_SOURCE_TV
,
1530 INTEL_PIPE_CRC_SOURCE_DP_B
,
1531 INTEL_PIPE_CRC_SOURCE_DP_C
,
1532 INTEL_PIPE_CRC_SOURCE_DP_D
,
1533 INTEL_PIPE_CRC_SOURCE_AUTO
,
1534 INTEL_PIPE_CRC_SOURCE_MAX
,
1537 struct intel_pipe_crc_entry
{
1542 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1543 struct intel_pipe_crc
{
1545 bool opened
; /* exclusive access to the result file */
1546 struct intel_pipe_crc_entry
*entries
;
1547 enum intel_pipe_crc_source source
;
1549 wait_queue_head_t wq
;
1552 struct i915_frontbuffer_tracking
{
1556 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1563 struct i915_wa_reg
{
1566 /* bitmask representing WA bits */
1570 #define I915_MAX_WA_REGS 16
1572 struct i915_workarounds
{
1573 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1577 struct i915_virtual_gpu
{
1581 struct drm_i915_private
{
1582 struct drm_device
*dev
;
1583 struct kmem_cache
*objects
;
1584 struct kmem_cache
*vmas
;
1585 struct kmem_cache
*requests
;
1587 const struct intel_device_info info
;
1589 int relative_constants_mode
;
1593 struct intel_uncore uncore
;
1595 struct i915_virtual_gpu vgpu
;
1597 struct intel_csr csr
;
1599 /* Display CSR-related protection */
1600 struct mutex csr_lock
;
1602 struct intel_gmbus gmbus
[GMBUS_NUM_PINS
];
1604 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1605 * controller on different i2c buses. */
1606 struct mutex gmbus_mutex
;
1609 * Base address of the gmbus and gpio block.
1611 uint32_t gpio_mmio_base
;
1613 /* MMIO base address for MIPI regs */
1614 uint32_t mipi_mmio_base
;
1616 wait_queue_head_t gmbus_wait_queue
;
1618 struct pci_dev
*bridge_dev
;
1619 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1620 struct drm_i915_gem_object
*semaphore_obj
;
1621 uint32_t last_seqno
, next_seqno
;
1623 struct drm_dma_handle
*status_page_dmah
;
1624 struct resource mch_res
;
1626 /* protects the irq masks */
1627 spinlock_t irq_lock
;
1629 /* protects the mmio flip data */
1630 spinlock_t mmio_flip_lock
;
1632 bool display_irqs_enabled
;
1634 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1635 struct pm_qos_request pm_qos
;
1637 /* DPIO indirect register protection */
1638 struct mutex dpio_lock
;
1640 /** Cached value of IMR to avoid reads in updating the bitfield */
1643 u32 de_irq_mask
[I915_MAX_PIPES
];
1648 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1650 struct work_struct hotplug_work
;
1652 unsigned long hpd_last_jiffies
;
1657 HPD_MARK_DISABLED
= 2
1659 } hpd_stats
[HPD_NUM_PINS
];
1661 struct delayed_work hotplug_reenable_work
;
1663 struct i915_fbc fbc
;
1664 struct i915_drrs drrs
;
1665 struct intel_opregion opregion
;
1666 struct intel_vbt_data vbt
;
1668 bool preserve_bios_swizzle
;
1671 struct intel_overlay
*overlay
;
1673 /* backlight registers and fields in struct intel_panel */
1674 struct mutex backlight_lock
;
1677 bool no_aux_handshake
;
1679 /* protects panel power sequencer state */
1680 struct mutex pps_mutex
;
1682 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1683 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1684 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1686 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1687 unsigned int cdclk_freq
;
1688 unsigned int hpll_freq
;
1691 * wq - Driver workqueue for GEM.
1693 * NOTE: Work items scheduled here are not allowed to grab any modeset
1694 * locks, for otherwise the flushing done in the pageflip code will
1695 * result in deadlocks.
1697 struct workqueue_struct
*wq
;
1699 /* Display functions */
1700 struct drm_i915_display_funcs display
;
1702 /* PCH chipset type */
1703 enum intel_pch pch_type
;
1704 unsigned short pch_id
;
1706 unsigned long quirks
;
1708 enum modeset_restore modeset_restore
;
1709 struct mutex modeset_restore_lock
;
1711 struct list_head vm_list
; /* Global list of all address spaces */
1712 struct i915_gtt gtt
; /* VM representing the global address space */
1714 struct i915_gem_mm mm
;
1715 DECLARE_HASHTABLE(mm_structs
, 7);
1716 struct mutex mm_lock
;
1718 /* Kernel Modesetting */
1720 struct sdvo_device_mapping sdvo_mappings
[2];
1722 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1723 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1724 wait_queue_head_t pending_flip_queue
;
1726 #ifdef CONFIG_DEBUG_FS
1727 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1730 int num_shared_dpll
;
1731 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1732 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1734 struct i915_workarounds workarounds
;
1736 /* Reclocking support */
1737 bool render_reclock_avail
;
1738 bool lvds_downclock_avail
;
1739 /* indicates the reduced downclock for LVDS*/
1742 struct i915_frontbuffer_tracking fb_tracking
;
1746 bool mchbar_need_disable
;
1748 struct intel_l3_parity l3_parity
;
1750 /* Cannot be determined by PCIID. You must always read a register. */
1753 /* gen6+ rps state */
1754 struct intel_gen6_power_mgmt rps
;
1756 /* ilk-only ips/rps state. Everything in here is protected by the global
1757 * mchdev_lock in intel_pm.c */
1758 struct intel_ilk_power_mgmt ips
;
1760 struct i915_power_domains power_domains
;
1762 struct i915_psr psr
;
1764 struct i915_gpu_error gpu_error
;
1766 struct drm_i915_gem_object
*vlv_pctx
;
1768 #ifdef CONFIG_DRM_I915_FBDEV
1769 /* list of fbdev register on this device */
1770 struct intel_fbdev
*fbdev
;
1771 struct work_struct fbdev_suspend_work
;
1774 struct drm_property
*broadcast_rgb_property
;
1775 struct drm_property
*force_audio_property
;
1777 /* hda/i915 audio component */
1778 bool audio_component_registered
;
1780 uint32_t hw_context_size
;
1781 struct list_head context_list
;
1785 u32 chv_phy_control
;
1788 struct i915_suspend_saved_registers regfile
;
1789 struct vlv_s0ix_state vlv_s0ix_state
;
1793 * Raw watermark latency values:
1794 * in 0.1us units for WM0,
1795 * in 0.5us units for WM1+.
1798 uint16_t pri_latency
[5];
1800 uint16_t spr_latency
[5];
1802 uint16_t cur_latency
[5];
1804 * Raw watermark memory latency values
1805 * for SKL for all 8 levels
1808 uint16_t skl_latency
[8];
1811 * The skl_wm_values structure is a bit too big for stack
1812 * allocation, so we keep the staging struct where we store
1813 * intermediate results here instead.
1815 struct skl_wm_values skl_results
;
1817 /* current hardware state */
1819 struct ilk_wm_values hw
;
1820 struct skl_wm_values skl_hw
;
1821 struct vlv_wm_values vlv
;
1825 struct i915_runtime_pm pm
;
1827 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1828 u32 long_hpd_port_mask
;
1829 u32 short_hpd_port_mask
;
1830 struct work_struct dig_port_work
;
1833 * if we get a HPD irq from DP and a HPD irq from non-DP
1834 * the non-DP HPD could block the workqueue on a mode config
1835 * mutex getting, that userspace may have taken. However
1836 * userspace is waiting on the DP workqueue to run which is
1837 * blocked behind the non-DP one.
1839 struct workqueue_struct
*dp_wq
;
1841 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1843 int (*execbuf_submit
)(struct drm_device
*dev
, struct drm_file
*file
,
1844 struct intel_engine_cs
*ring
,
1845 struct intel_context
*ctx
,
1846 struct drm_i915_gem_execbuffer2
*args
,
1847 struct list_head
*vmas
,
1848 struct drm_i915_gem_object
*batch_obj
,
1849 u64 exec_start
, u32 flags
);
1850 int (*init_rings
)(struct drm_device
*dev
);
1851 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1852 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1855 bool edp_low_vswing
;
1858 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1859 * will be rejected. Instead look for a better place.
1863 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1865 return dev
->dev_private
;
1868 static inline struct drm_i915_private
*dev_to_i915(struct device
*dev
)
1870 return to_i915(dev_get_drvdata(dev
));
1873 /* Iterate over initialised rings */
1874 #define for_each_ring(ring__, dev_priv__, i__) \
1875 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1876 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1878 enum hdmi_force_audio
{
1879 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1880 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1881 HDMI_AUDIO_AUTO
, /* trust EDID */
1882 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1885 #define I915_GTT_OFFSET_NONE ((u32)-1)
1887 struct drm_i915_gem_object_ops
{
1888 /* Interface between the GEM object and its backing storage.
1889 * get_pages() is called once prior to the use of the associated set
1890 * of pages before to binding them into the GTT, and put_pages() is
1891 * called after we no longer need them. As we expect there to be
1892 * associated cost with migrating pages between the backing storage
1893 * and making them available for the GPU (e.g. clflush), we may hold
1894 * onto the pages after they are no longer referenced by the GPU
1895 * in case they may be used again shortly (for example migrating the
1896 * pages to a different memory domain within the GTT). put_pages()
1897 * will therefore most likely be called when the object itself is
1898 * being released or under memory pressure (where we attempt to
1899 * reap pages for the shrinker).
1901 int (*get_pages
)(struct drm_i915_gem_object
*);
1902 void (*put_pages
)(struct drm_i915_gem_object
*);
1903 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1904 void (*release
)(struct drm_i915_gem_object
*);
1908 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1909 * considered to be the frontbuffer for the given plane interface-vise. This
1910 * doesn't mean that the hw necessarily already scans it out, but that any
1911 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1913 * We have one bit per pipe and per scanout plane type.
1915 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1916 #define INTEL_FRONTBUFFER_BITS \
1917 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1918 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1919 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1920 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1921 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1922 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1923 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1924 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1925 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1926 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1927 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1929 struct drm_i915_gem_object
{
1930 struct drm_gem_object base
;
1932 const struct drm_i915_gem_object_ops
*ops
;
1934 /** List of VMAs backed by this object */
1935 struct list_head vma_list
;
1937 /** Stolen memory for this object, instead of being backed by shmem. */
1938 struct drm_mm_node
*stolen
;
1939 struct list_head global_list
;
1941 struct list_head ring_list
;
1942 /** Used in execbuf to temporarily hold a ref */
1943 struct list_head obj_exec_link
;
1945 struct list_head batch_pool_link
;
1948 * This is set if the object is on the active lists (has pending
1949 * rendering and so a non-zero seqno), and is not set if it i s on
1950 * inactive (ready to be unbound) list.
1952 unsigned int active
:1;
1955 * This is set if the object has been written to since last bound
1958 unsigned int dirty
:1;
1961 * Fence register bits (if any) for this object. Will be set
1962 * as needed when mapped into the GTT.
1963 * Protected by dev->struct_mutex.
1965 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1968 * Advice: are the backing pages purgeable?
1970 unsigned int madv
:2;
1973 * Current tiling mode for the object.
1975 unsigned int tiling_mode
:2;
1977 * Whether the tiling parameters for the currently associated fence
1978 * register have changed. Note that for the purposes of tracking
1979 * tiling changes we also treat the unfenced register, the register
1980 * slot that the object occupies whilst it executes a fenced
1981 * command (such as BLT on gen2/3), as a "fence".
1983 unsigned int fence_dirty
:1;
1986 * Is the object at the current location in the gtt mappable and
1987 * fenceable? Used to avoid costly recalculations.
1989 unsigned int map_and_fenceable
:1;
1992 * Whether the current gtt mapping needs to be mappable (and isn't just
1993 * mappable by accident). Track pin and fault separate for a more
1994 * accurate mappable working set.
1996 unsigned int fault_mappable
:1;
1999 * Is the object to be mapped as read-only to the GPU
2000 * Only honoured if hardware has relevant pte bit
2002 unsigned long gt_ro
:1;
2003 unsigned int cache_level
:3;
2004 unsigned int cache_dirty
:1;
2006 unsigned int has_dma_mapping
:1;
2008 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
2010 unsigned int pin_display
;
2012 struct sg_table
*pages
;
2013 int pages_pin_count
;
2015 struct scatterlist
*sg
;
2019 /* prime dma-buf support */
2020 void *dma_buf_vmapping
;
2023 /** Breadcrumb of last rendering to the buffer. */
2024 struct drm_i915_gem_request
*last_read_req
;
2025 struct drm_i915_gem_request
*last_write_req
;
2026 /** Breadcrumb of last fenced GPU access to the buffer. */
2027 struct drm_i915_gem_request
*last_fenced_req
;
2029 /** Current tiling stride for the object, if it's tiled. */
2032 /** References from framebuffers, locks out tiling changes. */
2033 unsigned long framebuffer_references
;
2035 /** Record of address bit 17 of each page at last unbind. */
2036 unsigned long *bit_17
;
2039 /** for phy allocated objects */
2040 struct drm_dma_handle
*phys_handle
;
2042 struct i915_gem_userptr
{
2044 unsigned read_only
:1;
2045 unsigned workers
:4;
2046 #define I915_GEM_USERPTR_MAX_WORKERS 15
2048 struct i915_mm_struct
*mm
;
2049 struct i915_mmu_object
*mmu_object
;
2050 struct work_struct
*work
;
2054 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
2056 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
2057 struct drm_i915_gem_object
*new,
2058 unsigned frontbuffer_bits
);
2061 * Request queue structure.
2063 * The request queue allows us to note sequence numbers that have been emitted
2064 * and may be associated with active buffers to be retired.
2066 * By keeping this list, we can avoid having to do questionable sequence
2067 * number comparisons on buffer last_read|write_seqno. It also allows an
2068 * emission time to be associated with the request for tracking how far ahead
2069 * of the GPU the submission is.
2071 * The requests are reference counted, so upon creation they should have an
2072 * initial reference taken using kref_init
2074 struct drm_i915_gem_request
{
2077 /** On Which ring this request was generated */
2078 struct drm_i915_private
*i915
;
2079 struct intel_engine_cs
*ring
;
2081 /** GEM sequence number associated with this request. */
2084 /** Position in the ringbuffer of the start of the request */
2088 * Position in the ringbuffer of the start of the postfix.
2089 * This is required to calculate the maximum available ringbuffer
2090 * space without overwriting the postfix.
2094 /** Position in the ringbuffer of the end of the whole request */
2098 * Context and ring buffer related to this request
2099 * Contexts are refcounted, so when this request is associated with a
2100 * context, we must increment the context's refcount, to guarantee that
2101 * it persists while any request is linked to it. Requests themselves
2102 * are also refcounted, so the request will only be freed when the last
2103 * reference to it is dismissed, and the code in
2104 * i915_gem_request_free() will then decrement the refcount on the
2107 struct intel_context
*ctx
;
2108 struct intel_ringbuffer
*ringbuf
;
2110 /** Batch buffer related to this request if any */
2111 struct drm_i915_gem_object
*batch_obj
;
2113 /** Time at which this request was emitted, in jiffies. */
2114 unsigned long emitted_jiffies
;
2116 /** global list entry for this request */
2117 struct list_head list
;
2119 struct drm_i915_file_private
*file_priv
;
2120 /** file_priv list entry for this request */
2121 struct list_head client_list
;
2123 /** process identifier submitting this request */
2127 * The ELSP only accepts two elements at a time, so we queue
2128 * context/tail pairs on a given queue (ring->execlist_queue) until the
2129 * hardware is available. The queue serves a double purpose: we also use
2130 * it to keep track of the up to 2 contexts currently in the hardware
2131 * (usually one in execution and the other queued up by the GPU): We
2132 * only remove elements from the head of the queue when the hardware
2133 * informs us that an element has been completed.
2135 * All accesses to the queue are mediated by a spinlock
2136 * (ring->execlist_lock).
2139 /** Execlist link in the submission queue.*/
2140 struct list_head execlist_link
;
2142 /** Execlists no. of times this request has been sent to the ELSP */
2147 int i915_gem_request_alloc(struct intel_engine_cs
*ring
,
2148 struct intel_context
*ctx
);
2149 void i915_gem_request_free(struct kref
*req_ref
);
2151 static inline uint32_t
2152 i915_gem_request_get_seqno(struct drm_i915_gem_request
*req
)
2154 return req
? req
->seqno
: 0;
2157 static inline struct intel_engine_cs
*
2158 i915_gem_request_get_ring(struct drm_i915_gem_request
*req
)
2160 return req
? req
->ring
: NULL
;
2164 i915_gem_request_reference(struct drm_i915_gem_request
*req
)
2166 kref_get(&req
->ref
);
2170 i915_gem_request_unreference(struct drm_i915_gem_request
*req
)
2172 WARN_ON(!mutex_is_locked(&req
->ring
->dev
->struct_mutex
));
2173 kref_put(&req
->ref
, i915_gem_request_free
);
2177 i915_gem_request_unreference__unlocked(struct drm_i915_gem_request
*req
)
2179 struct drm_device
*dev
;
2184 dev
= req
->ring
->dev
;
2185 if (kref_put_mutex(&req
->ref
, i915_gem_request_free
, &dev
->struct_mutex
))
2186 mutex_unlock(&dev
->struct_mutex
);
2189 static inline void i915_gem_request_assign(struct drm_i915_gem_request
**pdst
,
2190 struct drm_i915_gem_request
*src
)
2193 i915_gem_request_reference(src
);
2196 i915_gem_request_unreference(*pdst
);
2202 * XXX: i915_gem_request_completed should be here but currently needs the
2203 * definition of i915_seqno_passed() which is below. It will be moved in
2204 * a later patch when the call to i915_seqno_passed() is obsoleted...
2207 struct drm_i915_file_private
{
2208 struct drm_i915_private
*dev_priv
;
2209 struct drm_file
*file
;
2213 struct list_head request_list
;
2215 struct idr context_idr
;
2217 struct list_head rps_boost
;
2218 struct intel_engine_cs
*bsd_ring
;
2220 unsigned rps_boosts
;
2224 * A command that requires special handling by the command parser.
2226 struct drm_i915_cmd_descriptor
{
2228 * Flags describing how the command parser processes the command.
2230 * CMD_DESC_FIXED: The command has a fixed length if this is set,
2231 * a length mask if not set
2232 * CMD_DESC_SKIP: The command is allowed but does not follow the
2233 * standard length encoding for the opcode range in
2235 * CMD_DESC_REJECT: The command is never allowed
2236 * CMD_DESC_REGISTER: The command should be checked against the
2237 * register whitelist for the appropriate ring
2238 * CMD_DESC_MASTER: The command is allowed if the submitting process
2242 #define CMD_DESC_FIXED (1<<0)
2243 #define CMD_DESC_SKIP (1<<1)
2244 #define CMD_DESC_REJECT (1<<2)
2245 #define CMD_DESC_REGISTER (1<<3)
2246 #define CMD_DESC_BITMASK (1<<4)
2247 #define CMD_DESC_MASTER (1<<5)
2250 * The command's unique identification bits and the bitmask to get them.
2251 * This isn't strictly the opcode field as defined in the spec and may
2252 * also include type, subtype, and/or subop fields.
2260 * The command's length. The command is either fixed length (i.e. does
2261 * not include a length field) or has a length field mask. The flag
2262 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2263 * a length mask. All command entries in a command table must include
2264 * length information.
2272 * Describes where to find a register address in the command to check
2273 * against the ring's register whitelist. Only valid if flags has the
2274 * CMD_DESC_REGISTER bit set.
2281 #define MAX_CMD_DESC_BITMASKS 3
2283 * Describes command checks where a particular dword is masked and
2284 * compared against an expected value. If the command does not match
2285 * the expected value, the parser rejects it. Only valid if flags has
2286 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2289 * If the check specifies a non-zero condition_mask then the parser
2290 * only performs the check when the bits specified by condition_mask
2297 u32 condition_offset
;
2299 } bits
[MAX_CMD_DESC_BITMASKS
];
2303 * A table of commands requiring special handling by the command parser.
2305 * Each ring has an array of tables. Each table consists of an array of command
2306 * descriptors, which must be sorted with command opcodes in ascending order.
2308 struct drm_i915_cmd_table
{
2309 const struct drm_i915_cmd_descriptor
*table
;
2313 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2314 #define __I915__(p) ({ \
2315 struct drm_i915_private *__p; \
2316 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2317 __p = (struct drm_i915_private *)p; \
2318 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2319 __p = to_i915((struct drm_device *)p); \
2324 #define INTEL_INFO(p) (&__I915__(p)->info)
2325 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2326 #define INTEL_REVID(p) (__I915__(p)->dev->pdev->revision)
2328 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2329 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2330 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2331 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2332 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2333 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2334 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2335 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2336 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2337 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2338 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2339 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2340 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2341 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2342 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2343 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2344 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2345 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2346 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2347 INTEL_DEVID(dev) == 0x0152 || \
2348 INTEL_DEVID(dev) == 0x015a)
2349 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2350 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2351 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2352 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2353 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2354 #define IS_BROXTON(dev) (!INTEL_INFO(dev)->is_skylake && IS_GEN9(dev))
2355 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2356 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2357 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2358 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2359 ((INTEL_DEVID(dev) & 0xf) == 0x6 || \
2360 (INTEL_DEVID(dev) & 0xf) == 0xb || \
2361 (INTEL_DEVID(dev) & 0xf) == 0xe))
2362 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2363 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2364 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2365 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2366 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2367 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2368 /* ULX machines are also considered ULT. */
2369 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2370 INTEL_DEVID(dev) == 0x0A1E)
2371 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2373 #define SKL_REVID_A0 (0x0)
2374 #define SKL_REVID_B0 (0x1)
2375 #define SKL_REVID_C0 (0x2)
2376 #define SKL_REVID_D0 (0x3)
2377 #define SKL_REVID_E0 (0x4)
2379 #define BXT_REVID_A0 (0x0)
2380 #define BXT_REVID_B0 (0x3)
2381 #define BXT_REVID_C0 (0x6)
2384 * The genX designation typically refers to the render engine, so render
2385 * capability related checks should use IS_GEN, while display and other checks
2386 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2389 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2390 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2391 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2392 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2393 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2394 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2395 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2396 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2398 #define RENDER_RING (1<<RCS)
2399 #define BSD_RING (1<<VCS)
2400 #define BLT_RING (1<<BCS)
2401 #define VEBOX_RING (1<<VECS)
2402 #define BSD2_RING (1<<VCS2)
2403 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2404 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2405 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2406 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2407 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2408 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2409 __I915__(dev)->ellc_size)
2410 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2412 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2413 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2414 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2415 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2417 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2418 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2420 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2421 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2423 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2424 * even when in MSI mode. This results in spurious interrupt warnings if the
2425 * legacy irq no. is shared with another device. The kernel then disables that
2426 * interrupt source and so prevents the other device from working properly.
2428 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2429 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2431 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2432 * rows, which changed the alignment requirements and fence programming.
2434 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2436 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2437 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2438 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2439 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2440 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2442 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2443 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2444 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2446 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2448 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2449 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2450 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev) || \
2451 IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev) || \
2453 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2454 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev) || \
2456 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2457 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2459 #define HAS_CSR(dev) (IS_SKYLAKE(dev))
2461 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2462 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2463 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2464 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2465 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2466 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2467 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2468 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2470 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2471 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2472 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2473 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2474 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2475 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2476 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2478 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2480 /* DPF == dynamic parity feature */
2481 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2482 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2484 #define GT_FREQUENCY_MULTIPLIER 50
2485 #define GEN9_FREQ_SCALER 3
2487 #include "i915_trace.h"
2489 extern const struct drm_ioctl_desc i915_ioctls
[];
2490 extern int i915_max_ioctl
;
2492 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2493 extern int i915_resume_legacy(struct drm_device
*dev
);
2496 struct i915_params
{
2498 int panel_ignore_lid
;
2500 unsigned int lvds_downclock
;
2501 int lvds_channel_mode
;
2503 int vbt_sdvo_panel_type
;
2507 int enable_execlists
;
2509 unsigned int preliminary_hw_support
;
2510 int disable_power_well
;
2512 int invert_brightness
;
2513 int enable_cmd_parser
;
2514 /* leave bools at the end to not create holes */
2515 bool enable_hangcheck
;
2517 bool prefault_disable
;
2518 bool load_detect_test
;
2520 bool disable_display
;
2521 bool disable_vtd_wa
;
2524 bool verbose_state_checks
;
2525 bool nuclear_pageflip
;
2528 extern struct i915_params i915 __read_mostly
;
2531 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2532 extern int i915_driver_unload(struct drm_device
*);
2533 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2534 extern void i915_driver_lastclose(struct drm_device
* dev
);
2535 extern void i915_driver_preclose(struct drm_device
*dev
,
2536 struct drm_file
*file
);
2537 extern void i915_driver_postclose(struct drm_device
*dev
,
2538 struct drm_file
*file
);
2539 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2540 #ifdef CONFIG_COMPAT
2541 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2544 extern int intel_gpu_reset(struct drm_device
*dev
);
2545 extern int i915_reset(struct drm_device
*dev
);
2546 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2547 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2548 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2549 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2550 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2551 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2552 void i915_firmware_load_error_print(const char *fw_path
, int err
);
2555 void i915_queue_hangcheck(struct drm_device
*dev
);
2557 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2558 const char *fmt
, ...);
2560 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2561 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2562 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2563 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2565 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2566 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2567 bool restore_forcewake
);
2568 extern void intel_uncore_init(struct drm_device
*dev
);
2569 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2570 extern void intel_uncore_fini(struct drm_device
*dev
);
2571 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2572 const char *intel_uncore_forcewake_domain_to_str(const enum forcewake_domain_id id
);
2573 void intel_uncore_forcewake_get(struct drm_i915_private
*dev_priv
,
2574 enum forcewake_domains domains
);
2575 void intel_uncore_forcewake_put(struct drm_i915_private
*dev_priv
,
2576 enum forcewake_domains domains
);
2577 /* Like above but the caller must manage the uncore.lock itself.
2578 * Must be used with I915_READ_FW and friends.
2580 void intel_uncore_forcewake_get__locked(struct drm_i915_private
*dev_priv
,
2581 enum forcewake_domains domains
);
2582 void intel_uncore_forcewake_put__locked(struct drm_i915_private
*dev_priv
,
2583 enum forcewake_domains domains
);
2584 void assert_forcewakes_inactive(struct drm_i915_private
*dev_priv
);
2585 static inline bool intel_vgpu_active(struct drm_device
*dev
)
2587 return to_i915(dev
)->vgpu
.active
;
2591 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2595 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2598 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2599 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2601 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2603 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2604 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2605 uint32_t interrupt_mask
,
2606 uint32_t enabled_irq_mask
);
2607 #define ibx_enable_display_interrupt(dev_priv, bits) \
2608 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2609 #define ibx_disable_display_interrupt(dev_priv, bits) \
2610 ibx_display_interrupt_update((dev_priv), (bits), 0)
2613 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2614 struct drm_file
*file_priv
);
2615 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2616 struct drm_file
*file_priv
);
2617 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2618 struct drm_file
*file_priv
);
2619 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2620 struct drm_file
*file_priv
);
2621 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2622 struct drm_file
*file_priv
);
2623 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2624 struct drm_file
*file_priv
);
2625 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2626 struct drm_file
*file_priv
);
2627 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2628 struct intel_engine_cs
*ring
);
2629 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2630 struct drm_file
*file
,
2631 struct intel_engine_cs
*ring
,
2632 struct drm_i915_gem_object
*obj
);
2633 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2634 struct drm_file
*file
,
2635 struct intel_engine_cs
*ring
,
2636 struct intel_context
*ctx
,
2637 struct drm_i915_gem_execbuffer2
*args
,
2638 struct list_head
*vmas
,
2639 struct drm_i915_gem_object
*batch_obj
,
2640 u64 exec_start
, u32 flags
);
2641 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2642 struct drm_file
*file_priv
);
2643 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2644 struct drm_file
*file_priv
);
2645 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2646 struct drm_file
*file_priv
);
2647 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2648 struct drm_file
*file
);
2649 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2650 struct drm_file
*file
);
2651 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2652 struct drm_file
*file_priv
);
2653 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2654 struct drm_file
*file_priv
);
2655 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2656 struct drm_file
*file_priv
);
2657 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2658 struct drm_file
*file_priv
);
2659 int i915_gem_init_userptr(struct drm_device
*dev
);
2660 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2661 struct drm_file
*file
);
2662 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2663 struct drm_file
*file_priv
);
2664 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2665 struct drm_file
*file_priv
);
2666 void i915_gem_load(struct drm_device
*dev
);
2667 void *i915_gem_object_alloc(struct drm_device
*dev
);
2668 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2669 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2670 const struct drm_i915_gem_object_ops
*ops
);
2671 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2673 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2674 struct i915_address_space
*vm
);
2675 void i915_gem_free_object(struct drm_gem_object
*obj
);
2676 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2678 /* Flags used by pin/bind&friends. */
2679 #define PIN_MAPPABLE (1<<0)
2680 #define PIN_NONBLOCK (1<<1)
2681 #define PIN_GLOBAL (1<<2)
2682 #define PIN_OFFSET_BIAS (1<<3)
2683 #define PIN_USER (1<<4)
2684 #define PIN_UPDATE (1<<5)
2685 #define PIN_OFFSET_MASK (~4095)
2687 i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2688 struct i915_address_space
*vm
,
2692 i915_gem_object_ggtt_pin(struct drm_i915_gem_object
*obj
,
2693 const struct i915_ggtt_view
*view
,
2697 int i915_vma_bind(struct i915_vma
*vma
, enum i915_cache_level cache_level
,
2699 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2700 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2701 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2702 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2704 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2705 int *needs_clflush
);
2707 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2709 static inline int __sg_page_count(struct scatterlist
*sg
)
2711 return sg
->length
>> PAGE_SHIFT
;
2714 static inline struct page
*
2715 i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2717 if (WARN_ON(n
>= obj
->base
.size
>> PAGE_SHIFT
))
2720 if (n
< obj
->get_page
.last
) {
2721 obj
->get_page
.sg
= obj
->pages
->sgl
;
2722 obj
->get_page
.last
= 0;
2725 while (obj
->get_page
.last
+ __sg_page_count(obj
->get_page
.sg
) <= n
) {
2726 obj
->get_page
.last
+= __sg_page_count(obj
->get_page
.sg
++);
2727 if (unlikely(sg_is_chain(obj
->get_page
.sg
)))
2728 obj
->get_page
.sg
= sg_chain_ptr(obj
->get_page
.sg
);
2731 return nth_page(sg_page(obj
->get_page
.sg
), n
- obj
->get_page
.last
);
2734 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2736 BUG_ON(obj
->pages
== NULL
);
2737 obj
->pages_pin_count
++;
2739 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2741 BUG_ON(obj
->pages_pin_count
== 0);
2742 obj
->pages_pin_count
--;
2745 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2746 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2747 struct intel_engine_cs
*to
);
2748 void i915_vma_move_to_active(struct i915_vma
*vma
,
2749 struct intel_engine_cs
*ring
);
2750 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2751 struct drm_device
*dev
,
2752 struct drm_mode_create_dumb
*args
);
2753 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2754 uint32_t handle
, uint64_t *offset
);
2756 * Returns true if seq1 is later than seq2.
2759 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2761 return (int32_t)(seq1
- seq2
) >= 0;
2764 static inline bool i915_gem_request_completed(struct drm_i915_gem_request
*req
,
2765 bool lazy_coherency
)
2769 BUG_ON(req
== NULL
);
2771 seqno
= req
->ring
->get_seqno(req
->ring
, lazy_coherency
);
2773 return i915_seqno_passed(seqno
, req
->seqno
);
2776 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2777 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2778 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2779 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2781 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2782 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2784 struct drm_i915_gem_request
*
2785 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2787 bool i915_gem_retire_requests(struct drm_device
*dev
);
2788 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2789 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2790 bool interruptible
);
2791 int __must_check
i915_gem_check_olr(struct drm_i915_gem_request
*req
);
2793 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2795 return unlikely(atomic_read(&error
->reset_counter
)
2796 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2799 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2801 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2804 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2806 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2809 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2811 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2812 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2815 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2817 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2818 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2821 void i915_gem_reset(struct drm_device
*dev
);
2822 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2823 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2824 int __must_check
i915_gem_init(struct drm_device
*dev
);
2825 int i915_gem_init_rings(struct drm_device
*dev
);
2826 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2827 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2828 void i915_gem_init_swizzling(struct drm_device
*dev
);
2829 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2830 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2831 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2832 int __i915_add_request(struct intel_engine_cs
*ring
,
2833 struct drm_file
*file
,
2834 struct drm_i915_gem_object
*batch_obj
);
2835 #define i915_add_request(ring) \
2836 __i915_add_request(ring, NULL, NULL)
2837 int __i915_wait_request(struct drm_i915_gem_request
*req
,
2838 unsigned reset_counter
,
2841 struct drm_i915_file_private
*file_priv
);
2842 int __must_check
i915_wait_request(struct drm_i915_gem_request
*req
);
2843 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2845 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2848 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2850 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2852 struct intel_engine_cs
*pipelined
,
2853 const struct i915_ggtt_view
*view
);
2854 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
,
2855 const struct i915_ggtt_view
*view
);
2856 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2858 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2859 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2862 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2864 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2865 int tiling_mode
, bool fenced
);
2867 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2868 enum i915_cache_level cache_level
);
2870 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2871 struct dma_buf
*dma_buf
);
2873 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2874 struct drm_gem_object
*gem_obj
, int flags
);
2876 void i915_gem_restore_fences(struct drm_device
*dev
);
2879 i915_gem_obj_ggtt_offset_view(struct drm_i915_gem_object
*o
,
2880 const struct i915_ggtt_view
*view
);
2882 i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2883 struct i915_address_space
*vm
);
2884 static inline unsigned long
2885 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*o
)
2887 return i915_gem_obj_ggtt_offset_view(o
, &i915_ggtt_view_normal
);
2890 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2891 bool i915_gem_obj_ggtt_bound_view(struct drm_i915_gem_object
*o
,
2892 const struct i915_ggtt_view
*view
);
2893 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2894 struct i915_address_space
*vm
);
2896 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2897 struct i915_address_space
*vm
);
2899 i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2900 struct i915_address_space
*vm
);
2902 i915_gem_obj_to_ggtt_view(struct drm_i915_gem_object
*obj
,
2903 const struct i915_ggtt_view
*view
);
2906 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2907 struct i915_address_space
*vm
);
2909 i915_gem_obj_lookup_or_create_ggtt_vma(struct drm_i915_gem_object
*obj
,
2910 const struct i915_ggtt_view
*view
);
2912 static inline struct i915_vma
*
2913 i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
)
2915 return i915_gem_obj_to_ggtt_view(obj
, &i915_ggtt_view_normal
);
2917 bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
);
2919 /* Some GGTT VM helpers */
2920 #define i915_obj_to_ggtt(obj) \
2921 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2922 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2924 struct i915_address_space
*ggtt
=
2925 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2929 static inline struct i915_hw_ppgtt
*
2930 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2932 WARN_ON(i915_is_ggtt(vm
));
2934 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2938 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2940 return i915_gem_obj_ggtt_bound_view(obj
, &i915_ggtt_view_normal
);
2943 static inline unsigned long
2944 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2946 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2949 static inline int __must_check
2950 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2954 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2955 alignment
, flags
| PIN_GLOBAL
);
2959 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2961 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2964 void i915_gem_object_ggtt_unpin_view(struct drm_i915_gem_object
*obj
,
2965 const struct i915_ggtt_view
*view
);
2967 i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
)
2969 i915_gem_object_ggtt_unpin_view(obj
, &i915_ggtt_view_normal
);
2972 /* i915_gem_context.c */
2973 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2974 void i915_gem_context_fini(struct drm_device
*dev
);
2975 void i915_gem_context_reset(struct drm_device
*dev
);
2976 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2977 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2978 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2979 int i915_switch_context(struct intel_engine_cs
*ring
,
2980 struct intel_context
*to
);
2981 struct intel_context
*
2982 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2983 void i915_gem_context_free(struct kref
*ctx_ref
);
2984 struct drm_i915_gem_object
*
2985 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2986 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2988 kref_get(&ctx
->ref
);
2991 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2993 kref_put(&ctx
->ref
, i915_gem_context_free
);
2996 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2998 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
3001 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
3002 struct drm_file
*file
);
3003 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
3004 struct drm_file
*file
);
3005 int i915_gem_context_getparam_ioctl(struct drm_device
*dev
, void *data
,
3006 struct drm_file
*file_priv
);
3007 int i915_gem_context_setparam_ioctl(struct drm_device
*dev
, void *data
,
3008 struct drm_file
*file_priv
);
3010 /* i915_gem_evict.c */
3011 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
3012 struct i915_address_space
*vm
,
3015 unsigned cache_level
,
3016 unsigned long start
,
3019 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
3020 int i915_gem_evict_everything(struct drm_device
*dev
);
3022 /* belongs in i915_gem_gtt.h */
3023 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
3025 if (INTEL_INFO(dev
)->gen
< 6)
3026 intel_gtt_chipset_flush();
3029 /* i915_gem_stolen.c */
3030 int i915_gem_init_stolen(struct drm_device
*dev
);
3031 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
3032 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
3033 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
3034 struct drm_i915_gem_object
*
3035 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
3036 struct drm_i915_gem_object
*
3037 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
3042 /* i915_gem_shrinker.c */
3043 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
3046 #define I915_SHRINK_PURGEABLE 0x1
3047 #define I915_SHRINK_UNBOUND 0x2
3048 #define I915_SHRINK_BOUND 0x4
3049 unsigned long i915_gem_shrink_all(struct drm_i915_private
*dev_priv
);
3050 void i915_gem_shrinker_init(struct drm_i915_private
*dev_priv
);
3053 /* i915_gem_tiling.c */
3054 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
3056 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
3058 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
3059 obj
->tiling_mode
!= I915_TILING_NONE
;
3062 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
3063 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3064 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
3066 /* i915_gem_debug.c */
3068 int i915_verify_lists(struct drm_device
*dev
);
3070 #define i915_verify_lists(dev) 0
3073 /* i915_debugfs.c */
3074 int i915_debugfs_init(struct drm_minor
*minor
);
3075 void i915_debugfs_cleanup(struct drm_minor
*minor
);
3076 #ifdef CONFIG_DEBUG_FS
3077 int i915_debugfs_connector_add(struct drm_connector
*connector
);
3078 void intel_display_crc_init(struct drm_device
*dev
);
3080 static inline int i915_debugfs_connector_add(struct drm_connector
*connector
) {}
3081 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
3084 /* i915_gpu_error.c */
3086 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
3087 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
3088 const struct i915_error_state_file_priv
*error
);
3089 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
3090 struct drm_i915_private
*i915
,
3091 size_t count
, loff_t pos
);
3092 static inline void i915_error_state_buf_release(
3093 struct drm_i915_error_state_buf
*eb
)
3097 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
3098 const char *error_msg
);
3099 void i915_error_state_get(struct drm_device
*dev
,
3100 struct i915_error_state_file_priv
*error_priv
);
3101 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
3102 void i915_destroy_error_state(struct drm_device
*dev
);
3104 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
3105 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
3107 /* i915_cmd_parser.c */
3108 int i915_cmd_parser_get_version(void);
3109 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
3110 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
3111 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
3112 int i915_parse_cmds(struct intel_engine_cs
*ring
,
3113 struct drm_i915_gem_object
*batch_obj
,
3114 struct drm_i915_gem_object
*shadow_batch_obj
,
3115 u32 batch_start_offset
,
3119 /* i915_suspend.c */
3120 extern int i915_save_state(struct drm_device
*dev
);
3121 extern int i915_restore_state(struct drm_device
*dev
);
3124 void i915_setup_sysfs(struct drm_device
*dev_priv
);
3125 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
3128 extern int intel_setup_gmbus(struct drm_device
*dev
);
3129 extern void intel_teardown_gmbus(struct drm_device
*dev
);
3130 extern bool intel_gmbus_is_valid_pin(struct drm_i915_private
*dev_priv
,
3133 extern struct i2c_adapter
*
3134 intel_gmbus_get_adapter(struct drm_i915_private
*dev_priv
, unsigned int pin
);
3135 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
3136 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
3137 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
3139 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
3141 extern void intel_i2c_reset(struct drm_device
*dev
);
3143 /* intel_opregion.c */
3145 extern int intel_opregion_setup(struct drm_device
*dev
);
3146 extern void intel_opregion_init(struct drm_device
*dev
);
3147 extern void intel_opregion_fini(struct drm_device
*dev
);
3148 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
3149 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
3151 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
3154 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
3155 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
3156 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
3157 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
3159 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
3164 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
3172 extern void intel_register_dsm_handler(void);
3173 extern void intel_unregister_dsm_handler(void);
3175 static inline void intel_register_dsm_handler(void) { return; }
3176 static inline void intel_unregister_dsm_handler(void) { return; }
3177 #endif /* CONFIG_ACPI */
3180 extern void intel_modeset_init_hw(struct drm_device
*dev
);
3181 extern void intel_modeset_init(struct drm_device
*dev
);
3182 extern void intel_modeset_gem_init(struct drm_device
*dev
);
3183 extern void intel_modeset_cleanup(struct drm_device
*dev
);
3184 extern void intel_connector_unregister(struct intel_connector
*);
3185 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
3186 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
3187 bool force_restore
);
3188 extern void i915_redisable_vga(struct drm_device
*dev
);
3189 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
3190 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
3191 extern void intel_init_pch_refclk(struct drm_device
*dev
);
3192 extern void intel_set_rps(struct drm_device
*dev
, u8 val
);
3193 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
3195 extern void intel_detect_pch(struct drm_device
*dev
);
3196 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
3197 extern int intel_enable_rc6(const struct drm_device
*dev
);
3199 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
3200 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
3201 struct drm_file
*file
);
3202 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
3203 struct drm_file
*file
);
3206 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
3207 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
3208 struct intel_overlay_error_state
*error
);
3210 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
3211 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
3212 struct drm_device
*dev
,
3213 struct intel_display_error_state
*error
);
3215 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u32 mbox
, u32
*val
);
3216 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u32 mbox
, u32 val
);
3218 /* intel_sideband.c */
3219 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u32 addr
);
3220 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u32 addr
, u32 val
);
3221 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
3222 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3223 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3224 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3225 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3226 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3227 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3228 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3229 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3230 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3231 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3232 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
3233 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
3234 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
3235 enum intel_sbi_destination destination
);
3236 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
3237 enum intel_sbi_destination destination
);
3238 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
3239 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
3241 int intel_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
3242 int intel_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
3244 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
3245 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
3247 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
3248 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
3249 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
3250 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
3252 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
3253 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
3254 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
3255 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
3257 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
3258 * will be implemented using 2 32-bit writes in an arbitrary order with
3259 * an arbitrary delay between them. This can cause the hardware to
3260 * act upon the intermediate value, possibly leading to corruption and
3261 * machine death. You have been warned.
3263 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
3264 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
3266 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
3267 u32 upper = I915_READ(upper_reg); \
3268 u32 lower = I915_READ(lower_reg); \
3269 u32 tmp = I915_READ(upper_reg); \
3270 if (upper != tmp) { \
3272 lower = I915_READ(lower_reg); \
3273 WARN_ON(I915_READ(upper_reg) != upper); \
3275 (u64)upper << 32 | lower; })
3277 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
3278 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
3280 /* These are untraced mmio-accessors that are only valid to be used inside
3281 * criticial sections inside IRQ handlers where forcewake is explicitly
3283 * Think twice, and think again, before using these.
3284 * Note: Should only be used between intel_uncore_forcewake_irqlock() and
3285 * intel_uncore_forcewake_irqunlock().
3287 #define I915_READ_FW(reg__) readl(dev_priv->regs + (reg__))
3288 #define I915_WRITE_FW(reg__, val__) writel(val__, dev_priv->regs + (reg__))
3289 #define POSTING_READ_FW(reg__) (void)I915_READ_FW(reg__)
3291 /* "Broadcast RGB" property */
3292 #define INTEL_BROADCAST_RGB_AUTO 0
3293 #define INTEL_BROADCAST_RGB_FULL 1
3294 #define INTEL_BROADCAST_RGB_LIMITED 2
3296 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
3298 if (IS_VALLEYVIEW(dev
))
3299 return VLV_VGACNTRL
;
3300 else if (INTEL_INFO(dev
)->gen
>= 5)
3301 return CPU_VGACNTRL
;
3306 static inline void __user
*to_user_ptr(u64 address
)
3308 return (void __user
*)(uintptr_t)address
;
3311 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
3313 unsigned long j
= msecs_to_jiffies(m
);
3315 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3318 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n
)
3320 return min_t(u64
, MAX_JIFFY_OFFSET
, nsecs_to_jiffies64(n
) + 1);
3323 static inline unsigned long
3324 timespec_to_jiffies_timeout(const struct timespec
*value
)
3326 unsigned long j
= timespec_to_jiffies(value
);
3328 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
3332 * If you need to wait X milliseconds between events A and B, but event B
3333 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
3334 * when event A happened, then just before event B you call this function and
3335 * pass the timestamp as the first argument, and X as the second argument.
3338 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3340 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3343 * Don't re-read the value of "jiffies" every time since it may change
3344 * behind our back and break the math.
3346 tmp_jiffies
= jiffies
;
3347 target_jiffies
= timestamp_jiffies
+
3348 msecs_to_jiffies_timeout(to_wait_ms
);
3350 if (time_after(target_jiffies
, tmp_jiffies
)) {
3351 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3352 while (remaining_jiffies
)
3354 schedule_timeout_uninterruptible(remaining_jiffies
);
3358 static inline void i915_trace_irq_get(struct intel_engine_cs
*ring
,
3359 struct drm_i915_gem_request
*req
)
3361 if (ring
->trace_irq_req
== NULL
&& ring
->irq_get(ring
))
3362 i915_gem_request_assign(&ring
->trace_irq_req
, req
);