1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "intel_lrc.h"
39 #include "i915_gem_gtt.h"
40 #include "i915_gem_render_state.h"
41 #include <linux/io-mapping.h>
42 #include <linux/i2c.h>
43 #include <linux/i2c-algo-bit.h>
44 #include <drm/intel-gtt.h>
45 #include <drm/drm_legacy.h> /* for struct drm_dma_handle */
46 #include <drm/drm_gem.h>
47 #include <linux/backlight.h>
48 #include <linux/hashtable.h>
49 #include <linux/intel-iommu.h>
50 #include <linux/kref.h>
51 #include <linux/pm_qos.h>
53 /* General customization:
56 #define DRIVER_NAME "i915"
57 #define DRIVER_DESC "Intel Graphics"
58 #define DRIVER_DATE "20141024"
66 I915_MAX_PIPES
= _PIPE_EDP
68 #define pipe_name(p) ((p) + 'A')
77 #define transcoder_name(t) ((t) + 'A')
80 * This is the maximum (across all platforms) number of planes (primary +
81 * sprites) that can be active at the same time on one pipe.
83 * This value doesn't count the cursor plane.
85 #define I915_MAX_PLANES 3
92 #define plane_name(p) ((p) + 'A')
94 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
104 #define port_name(p) ((p) + 'A')
106 #define I915_NUM_PHYS_VLV 2
118 enum intel_display_power_domain
{
122 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
123 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
124 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
125 POWER_DOMAIN_TRANSCODER_A
,
126 POWER_DOMAIN_TRANSCODER_B
,
127 POWER_DOMAIN_TRANSCODER_C
,
128 POWER_DOMAIN_TRANSCODER_EDP
,
129 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
130 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
131 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
132 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
133 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
134 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
135 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
136 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
137 POWER_DOMAIN_PORT_DSI
,
138 POWER_DOMAIN_PORT_CRT
,
139 POWER_DOMAIN_PORT_OTHER
,
148 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
149 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
150 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
151 #define POWER_DOMAIN_TRANSCODER(tran) \
152 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
153 (tran) + POWER_DOMAIN_TRANSCODER_A)
157 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
158 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
168 #define I915_GEM_GPU_DOMAINS \
169 (I915_GEM_DOMAIN_RENDER | \
170 I915_GEM_DOMAIN_SAMPLER | \
171 I915_GEM_DOMAIN_COMMAND | \
172 I915_GEM_DOMAIN_INSTRUCTION | \
173 I915_GEM_DOMAIN_VERTEX)
175 #define for_each_pipe(__dev_priv, __p) \
176 for ((__p) = 0; (__p) < INTEL_INFO(__dev_priv)->num_pipes; (__p)++)
177 #define for_each_plane(pipe, p) \
178 for ((p) = 0; (p) < INTEL_INFO(dev)->num_sprites[(pipe)] + 1; (p)++)
179 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
181 #define for_each_crtc(dev, crtc) \
182 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
184 #define for_each_intel_crtc(dev, intel_crtc) \
185 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
187 #define for_each_intel_encoder(dev, intel_encoder) \
188 list_for_each_entry(intel_encoder, \
189 &(dev)->mode_config.encoder_list, \
192 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
193 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
194 if ((intel_encoder)->base.crtc == (__crtc))
196 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
197 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
198 if ((intel_connector)->base.encoder == (__encoder))
200 #define for_each_power_domain(domain, mask) \
201 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
202 if ((1 << (domain)) & (mask))
204 struct drm_i915_private
;
205 struct i915_mm_struct
;
206 struct i915_mmu_object
;
209 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
210 /* real shared dpll ids must be >= 0 */
211 DPLL_ID_PCH_PLL_A
= 0,
212 DPLL_ID_PCH_PLL_B
= 1,
216 #define I915_NUM_PLLS 2
218 struct intel_dpll_hw_state
{
229 struct intel_shared_dpll
{
230 int refcount
; /* count of number of CRTCs sharing this PLL */
231 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
232 bool on
; /* is the PLL actually active? Disabled during modeset */
234 /* should match the index in the dev_priv->shared_dplls array */
235 enum intel_dpll_id id
;
236 struct intel_dpll_hw_state hw_state
;
237 /* The mode_set hook is optional and should be used together with the
238 * intel_prepare_shared_dpll function. */
239 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
240 struct intel_shared_dpll
*pll
);
241 void (*enable
)(struct drm_i915_private
*dev_priv
,
242 struct intel_shared_dpll
*pll
);
243 void (*disable
)(struct drm_i915_private
*dev_priv
,
244 struct intel_shared_dpll
*pll
);
245 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
246 struct intel_shared_dpll
*pll
,
247 struct intel_dpll_hw_state
*hw_state
);
250 /* Used by dp and fdi links */
251 struct intel_link_m_n
{
259 void intel_link_compute_m_n(int bpp
, int nlanes
,
260 int pixel_clock
, int link_clock
,
261 struct intel_link_m_n
*m_n
);
263 /* Interface history:
266 * 1.2: Add Power Management
267 * 1.3: Add vblank support
268 * 1.4: Fix cmdbuffer path, add heap destroy
269 * 1.5: Add vblank pipe configuration
270 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
271 * - Support vertical blank on secondary display pipe
273 #define DRIVER_MAJOR 1
274 #define DRIVER_MINOR 6
275 #define DRIVER_PATCHLEVEL 0
277 #define WATCH_LISTS 0
280 struct opregion_header
;
281 struct opregion_acpi
;
282 struct opregion_swsci
;
283 struct opregion_asle
;
285 struct intel_opregion
{
286 struct opregion_header __iomem
*header
;
287 struct opregion_acpi __iomem
*acpi
;
288 struct opregion_swsci __iomem
*swsci
;
289 u32 swsci_gbda_sub_functions
;
290 u32 swsci_sbcb_sub_functions
;
291 struct opregion_asle __iomem
*asle
;
293 u32 __iomem
*lid_state
;
294 struct work_struct asle_work
;
296 #define OPREGION_SIZE (8*1024)
298 struct intel_overlay
;
299 struct intel_overlay_error_state
;
301 struct drm_local_map
;
303 struct drm_i915_master_private
{
304 struct drm_local_map
*sarea
;
305 struct _drm_i915_sarea
*sarea_priv
;
307 #define I915_FENCE_REG_NONE -1
308 #define I915_MAX_NUM_FENCES 32
309 /* 32 fences + sign bit for FENCE_REG_NONE */
310 #define I915_MAX_NUM_FENCE_BITS 6
312 struct drm_i915_fence_reg
{
313 struct list_head lru_list
;
314 struct drm_i915_gem_object
*obj
;
318 struct sdvo_device_mapping
{
327 struct intel_display_error_state
;
329 struct drm_i915_error_state
{
337 /* Generic register state */
345 u32 error
; /* gen6+ */
346 u32 err_int
; /* gen7 */
352 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
353 u64 fence
[I915_MAX_NUM_FENCES
];
354 struct intel_overlay_error_state
*overlay
;
355 struct intel_display_error_state
*display
;
356 struct drm_i915_error_object
*semaphore_obj
;
358 struct drm_i915_error_ring
{
360 /* Software tracked state */
363 enum intel_ring_hangcheck_action hangcheck_action
;
366 /* our own tracking of ring head and tail */
370 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
388 u32 rc_psmi
; /* sleep state */
389 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
391 struct drm_i915_error_object
{
395 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
397 struct drm_i915_error_request
{
412 char comm
[TASK_COMM_LEN
];
413 } ring
[I915_NUM_RINGS
];
415 struct drm_i915_error_buffer
{
422 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
430 } **active_bo
, **pinned_bo
;
432 u32
*active_bo_count
, *pinned_bo_count
;
436 struct intel_connector
;
437 struct intel_encoder
;
438 struct intel_crtc_config
;
439 struct intel_plane_config
;
444 struct drm_i915_display_funcs
{
445 bool (*fbc_enabled
)(struct drm_device
*dev
);
446 void (*enable_fbc
)(struct drm_crtc
*crtc
);
447 void (*disable_fbc
)(struct drm_device
*dev
);
448 int (*get_display_clock_speed
)(struct drm_device
*dev
);
449 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
451 * find_dpll() - Find the best values for the PLL
452 * @limit: limits for the PLL
453 * @crtc: current CRTC
454 * @target: target frequency in kHz
455 * @refclk: reference clock frequency in kHz
456 * @match_clock: if provided, @best_clock P divider must
457 * match the P divider from @match_clock
458 * used for LVDS downclocking
459 * @best_clock: best PLL values found
461 * Returns true on success, false on failure.
463 bool (*find_dpll
)(const struct intel_limit
*limit
,
464 struct intel_crtc
*crtc
,
465 int target
, int refclk
,
466 struct dpll
*match_clock
,
467 struct dpll
*best_clock
);
468 void (*update_wm
)(struct drm_crtc
*crtc
);
469 void (*update_sprite_wm
)(struct drm_plane
*plane
,
470 struct drm_crtc
*crtc
,
471 uint32_t sprite_width
, uint32_t sprite_height
,
472 int pixel_size
, bool enable
, bool scaled
);
473 void (*modeset_global_resources
)(struct drm_device
*dev
);
474 /* Returns the active state of the crtc, and if the crtc is active,
475 * fills out the pipe-config with the hw state. */
476 bool (*get_pipe_config
)(struct intel_crtc
*,
477 struct intel_crtc_config
*);
478 void (*get_plane_config
)(struct intel_crtc
*,
479 struct intel_plane_config
*);
480 int (*crtc_mode_set
)(struct intel_crtc
*crtc
,
482 struct drm_framebuffer
*old_fb
);
483 void (*crtc_enable
)(struct drm_crtc
*crtc
);
484 void (*crtc_disable
)(struct drm_crtc
*crtc
);
485 void (*off
)(struct drm_crtc
*crtc
);
486 void (*write_eld
)(struct drm_connector
*connector
,
487 struct intel_encoder
*encoder
,
488 struct drm_display_mode
*mode
);
489 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
490 void (*init_clock_gating
)(struct drm_device
*dev
);
491 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
492 struct drm_framebuffer
*fb
,
493 struct drm_i915_gem_object
*obj
,
494 struct intel_engine_cs
*ring
,
496 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
497 struct drm_framebuffer
*fb
,
499 void (*hpd_irq_setup
)(struct drm_device
*dev
);
500 /* clock updates for mode set */
502 /* render clock increase/decrease */
503 /* display clock increase/decrease */
504 /* pll clock increase/decrease */
506 int (*setup_backlight
)(struct intel_connector
*connector
);
507 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
508 void (*set_backlight
)(struct intel_connector
*connector
,
510 void (*disable_backlight
)(struct intel_connector
*connector
);
511 void (*enable_backlight
)(struct intel_connector
*connector
);
514 struct intel_uncore_funcs
{
515 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
517 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
520 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
521 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
522 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
523 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
525 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
526 uint8_t val
, bool trace
);
527 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
528 uint16_t val
, bool trace
);
529 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
530 uint32_t val
, bool trace
);
531 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
532 uint64_t val
, bool trace
);
535 struct intel_uncore
{
536 spinlock_t lock
; /** lock is also taken in irq contexts. */
538 struct intel_uncore_funcs funcs
;
541 unsigned forcewake_count
;
543 unsigned fw_rendercount
;
544 unsigned fw_mediacount
;
546 struct timer_list force_wake_timer
;
549 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
550 func(is_mobile) sep \
553 func(is_i945gm) sep \
555 func(need_gfx_hws) sep \
557 func(is_pineview) sep \
558 func(is_broadwater) sep \
559 func(is_crestline) sep \
560 func(is_ivybridge) sep \
561 func(is_valleyview) sep \
562 func(is_haswell) sep \
563 func(is_skylake) sep \
564 func(is_preliminary) sep \
566 func(has_pipe_cxsr) sep \
567 func(has_hotplug) sep \
568 func(cursor_needs_physical) sep \
569 func(has_overlay) sep \
570 func(overlay_needs_physical) sep \
571 func(supports_tv) sep \
576 #define DEFINE_FLAG(name) u8 name:1
577 #define SEP_SEMICOLON ;
579 struct intel_device_info
{
580 u32 display_mmio_offset
;
583 u8 num_sprites
[I915_MAX_PIPES
];
585 u8 ring_mask
; /* Rings supported by the HW */
586 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
587 /* Register offsets for the various display pipes and transcoders */
588 int pipe_offsets
[I915_MAX_TRANSCODERS
];
589 int trans_offsets
[I915_MAX_TRANSCODERS
];
590 int palette_offsets
[I915_MAX_PIPES
];
591 int cursor_offsets
[I915_MAX_PIPES
];
597 enum i915_cache_level
{
599 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
600 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
601 caches, eg sampler/render caches, and the
602 large Last-Level-Cache. LLC is coherent with
603 the CPU, but L3 is only visible to the GPU. */
604 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
607 struct i915_ctx_hang_stats
{
608 /* This context had batch pending when hang was declared */
609 unsigned batch_pending
;
611 /* This context had batch active when hang was declared */
612 unsigned batch_active
;
614 /* Time when this context was last blamed for a GPU reset */
615 unsigned long guilty_ts
;
617 /* This context is banned to submit more work */
621 /* This must match up with the value previously used for execbuf2.rsvd1. */
622 #define DEFAULT_CONTEXT_HANDLE 0
624 * struct intel_context - as the name implies, represents a context.
625 * @ref: reference count.
626 * @user_handle: userspace tracking identity for this context.
627 * @remap_slice: l3 row remapping information.
628 * @file_priv: filp associated with this context (NULL for global default
630 * @hang_stats: information about the role of this context in possible GPU
632 * @vm: virtual memory space used by this context.
633 * @legacy_hw_ctx: render context backing object and whether it is correctly
634 * initialized (legacy ring submission mechanism only).
635 * @link: link in the global list of contexts.
637 * Contexts are memory images used by the hardware to store copies of their
640 struct intel_context
{
644 struct drm_i915_file_private
*file_priv
;
645 struct i915_ctx_hang_stats hang_stats
;
646 struct i915_hw_ppgtt
*ppgtt
;
648 /* Legacy ring buffer submission */
650 struct drm_i915_gem_object
*rcs_state
;
655 bool rcs_initialized
;
657 struct drm_i915_gem_object
*state
;
658 struct intel_ringbuffer
*ringbuf
;
659 } engine
[I915_NUM_RINGS
];
661 struct list_head link
;
671 struct drm_mm_node compressed_fb
;
672 struct drm_mm_node
*compressed_llb
;
676 /* Tracks whether the HW is actually enabled, not whether the feature is
680 /* On gen8 some rings cannont perform fbc clean operation so for now
681 * we are doing this on SW with mmio.
682 * This variable works in the opposite information direction
683 * of ring->fbc_dirty telling software on frontbuffer tracking
684 * to perform the cache clean on sw side.
686 bool need_sw_cache_clean
;
688 struct intel_fbc_work
{
689 struct delayed_work work
;
690 struct drm_crtc
*crtc
;
691 struct drm_framebuffer
*fb
;
695 FBC_OK
, /* FBC is enabled */
696 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
697 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
698 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
699 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
700 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
701 FBC_BAD_PLANE
, /* fbc not supported on plane */
702 FBC_NOT_TILED
, /* buffer not tiled */
703 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
705 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
710 struct intel_connector
*connector
;
718 struct intel_dp
*enabled
;
720 struct delayed_work work
;
721 unsigned busy_frontbuffer_bits
;
725 PCH_NONE
= 0, /* No PCH present */
726 PCH_IBX
, /* Ibexpeak PCH */
727 PCH_CPT
, /* Cougarpoint PCH */
728 PCH_LPT
, /* Lynxpoint PCH */
729 PCH_SPT
, /* Sunrisepoint PCH */
733 enum intel_sbi_destination
{
738 #define QUIRK_PIPEA_FORCE (1<<0)
739 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
740 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
741 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
742 #define QUIRK_PIPEB_FORCE (1<<4)
745 struct intel_fbc_work
;
748 struct i2c_adapter adapter
;
752 struct i2c_algo_bit_data bit_algo
;
753 struct drm_i915_private
*dev_priv
;
756 struct i915_suspend_saved_registers
{
777 u32 saveTRANS_HTOTAL_A
;
778 u32 saveTRANS_HBLANK_A
;
779 u32 saveTRANS_HSYNC_A
;
780 u32 saveTRANS_VTOTAL_A
;
781 u32 saveTRANS_VBLANK_A
;
782 u32 saveTRANS_VSYNC_A
;
790 u32 savePFIT_PGM_RATIOS
;
791 u32 saveBLC_HIST_CTL
;
793 u32 saveBLC_PWM_CTL2
;
794 u32 saveBLC_HIST_CTL_B
;
795 u32 saveBLC_CPU_PWM_CTL
;
796 u32 saveBLC_CPU_PWM_CTL2
;
809 u32 saveTRANS_HTOTAL_B
;
810 u32 saveTRANS_HBLANK_B
;
811 u32 saveTRANS_HSYNC_B
;
812 u32 saveTRANS_VTOTAL_B
;
813 u32 saveTRANS_VBLANK_B
;
814 u32 saveTRANS_VSYNC_B
;
828 u32 savePP_ON_DELAYS
;
829 u32 savePP_OFF_DELAYS
;
837 u32 savePFIT_CONTROL
;
838 u32 save_palette_a
[256];
839 u32 save_palette_b
[256];
850 u32 saveCACHE_MODE_0
;
851 u32 saveMI_ARB_STATE
;
862 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
873 u32 savePIPEA_GMCH_DATA_M
;
874 u32 savePIPEB_GMCH_DATA_M
;
875 u32 savePIPEA_GMCH_DATA_N
;
876 u32 savePIPEB_GMCH_DATA_N
;
877 u32 savePIPEA_DP_LINK_M
;
878 u32 savePIPEB_DP_LINK_M
;
879 u32 savePIPEA_DP_LINK_N
;
880 u32 savePIPEB_DP_LINK_N
;
891 u32 savePCH_DREF_CONTROL
;
892 u32 saveDISP_ARB_CTL
;
893 u32 savePIPEA_DATA_M1
;
894 u32 savePIPEA_DATA_N1
;
895 u32 savePIPEA_LINK_M1
;
896 u32 savePIPEA_LINK_N1
;
897 u32 savePIPEB_DATA_M1
;
898 u32 savePIPEB_DATA_N1
;
899 u32 savePIPEB_LINK_M1
;
900 u32 savePIPEB_LINK_N1
;
901 u32 saveMCHBAR_RENDER_STANDBY
;
902 u32 savePCH_PORT_HOTPLUG
;
905 struct vlv_s0ix_state
{
912 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
913 u32 media_max_req_count
;
914 u32 gfx_max_req_count
;
946 /* Display 1 CZ domain */
951 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
953 /* GT SA CZ domain */
960 /* Display 2 CZ domain */
966 struct intel_rps_ei
{
972 struct intel_gen6_power_mgmt
{
973 /* work and pm_iir are protected by dev_priv->irq_lock */
974 struct work_struct work
;
977 /* Frequencies are stored in potentially platform dependent multiples.
978 * In other words, *_freq needs to be multiplied by X to be interesting.
979 * Soft limits are those which are used for the dynamic reclocking done
980 * by the driver (raise frequencies under heavy loads, and lower for
981 * lighter loads). Hard limits are those imposed by the hardware.
983 * A distinction is made for overclocking, which is never enabled by
984 * default, and is considered to be above the hard limit if it's
987 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
988 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
989 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
990 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
991 u8 min_freq
; /* AKA RPn. Minimum frequency */
992 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
993 u8 rp1_freq
; /* "less than" RP0 power/freqency */
994 u8 rp0_freq
; /* Non-overclocked max frequency. */
997 u32 ei_interrupt_count
;
1000 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
1003 struct delayed_work delayed_resume_work
;
1005 /* manual wa residency calculations */
1006 struct intel_rps_ei up_ei
, down_ei
;
1009 * Protects RPS/RC6 register access and PCU communication.
1010 * Must be taken after struct_mutex if nested.
1012 struct mutex hw_lock
;
1015 /* defined intel_pm.c */
1016 extern spinlock_t mchdev_lock
;
1018 struct intel_ilk_power_mgmt
{
1026 unsigned long last_time1
;
1027 unsigned long chipset_power
;
1030 unsigned long gfx_power
;
1036 struct drm_i915_gem_object
*pwrctx
;
1037 struct drm_i915_gem_object
*renderctx
;
1040 struct drm_i915_private
;
1041 struct i915_power_well
;
1043 struct i915_power_well_ops
{
1045 * Synchronize the well's hw state to match the current sw state, for
1046 * example enable/disable it based on the current refcount. Called
1047 * during driver init and resume time, possibly after first calling
1048 * the enable/disable handlers.
1050 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
1051 struct i915_power_well
*power_well
);
1053 * Enable the well and resources that depend on it (for example
1054 * interrupts located on the well). Called after the 0->1 refcount
1057 void (*enable
)(struct drm_i915_private
*dev_priv
,
1058 struct i915_power_well
*power_well
);
1060 * Disable the well and resources that depend on it. Called after
1061 * the 1->0 refcount transition.
1063 void (*disable
)(struct drm_i915_private
*dev_priv
,
1064 struct i915_power_well
*power_well
);
1065 /* Returns the hw enabled state. */
1066 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1067 struct i915_power_well
*power_well
);
1070 /* Power well structure for haswell */
1071 struct i915_power_well
{
1074 /* power well enable/disable usage count */
1076 /* cached hw enabled state */
1078 unsigned long domains
;
1080 const struct i915_power_well_ops
*ops
;
1083 struct i915_power_domains
{
1085 * Power wells needed for initialization at driver init and suspend
1086 * time are on. They are kept on until after the first modeset.
1090 int power_well_count
;
1093 int domain_use_count
[POWER_DOMAIN_NUM
];
1094 struct i915_power_well
*power_wells
;
1097 struct i915_dri1_state
{
1098 unsigned allow_batchbuffer
: 1;
1099 u32 __iomem
*gfx_hws_cpu_addr
;
1110 struct i915_ums_state
{
1112 * Flag if the X Server, and thus DRM, is not currently in
1113 * control of the device.
1115 * This is set between LeaveVT and EnterVT. It needs to be
1116 * replaced with a semaphore. It also needs to be
1117 * transitioned away from for kernel modesetting.
1122 #define MAX_L3_SLICES 2
1123 struct intel_l3_parity
{
1124 u32
*remap_info
[MAX_L3_SLICES
];
1125 struct work_struct error_work
;
1129 struct i915_gem_mm
{
1130 /** Memory allocator for GTT stolen memory */
1131 struct drm_mm stolen
;
1132 /** List of all objects in gtt_space. Used to restore gtt
1133 * mappings on resume */
1134 struct list_head bound_list
;
1136 * List of objects which are not bound to the GTT (thus
1137 * are idle and not used by the GPU) but still have
1138 * (presumably uncached) pages still attached.
1140 struct list_head unbound_list
;
1142 /** Usable portion of the GTT for GEM */
1143 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1145 /** PPGTT used for aliasing the PPGTT with the GTT */
1146 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1148 struct notifier_block oom_notifier
;
1149 struct shrinker shrinker
;
1150 bool shrinker_no_lock_stealing
;
1152 /** LRU list of objects with fence regs on them. */
1153 struct list_head fence_list
;
1156 * We leave the user IRQ off as much as possible,
1157 * but this means that requests will finish and never
1158 * be retired once the system goes idle. Set a timer to
1159 * fire periodically while the ring is running. When it
1160 * fires, go retire requests.
1162 struct delayed_work retire_work
;
1165 * When we detect an idle GPU, we want to turn on
1166 * powersaving features. So once we see that there
1167 * are no more requests outstanding and no more
1168 * arrive within a small period of time, we fire
1169 * off the idle_work.
1171 struct delayed_work idle_work
;
1174 * Are we in a non-interruptible section of code like
1180 * Is the GPU currently considered idle, or busy executing userspace
1181 * requests? Whilst idle, we attempt to power down the hardware and
1182 * display clocks. In order to reduce the effect on performance, there
1183 * is a slight delay before we do so.
1187 /* the indicator for dispatch video commands on two BSD rings */
1188 int bsd_ring_dispatch_index
;
1190 /** Bit 6 swizzling required for X tiling */
1191 uint32_t bit_6_swizzle_x
;
1192 /** Bit 6 swizzling required for Y tiling */
1193 uint32_t bit_6_swizzle_y
;
1195 /* accounting, useful for userland debugging */
1196 spinlock_t object_stat_lock
;
1197 size_t object_memory
;
1201 struct drm_i915_error_state_buf
{
1202 struct drm_i915_private
*i915
;
1211 struct i915_error_state_file_priv
{
1212 struct drm_device
*dev
;
1213 struct drm_i915_error_state
*error
;
1216 struct i915_gpu_error
{
1217 /* For hangcheck timer */
1218 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1219 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1220 /* Hang gpu twice in this window and your context gets banned */
1221 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1223 struct timer_list hangcheck_timer
;
1225 /* For reset and error_state handling. */
1227 /* Protected by the above dev->gpu_error.lock. */
1228 struct drm_i915_error_state
*first_error
;
1229 struct work_struct work
;
1232 unsigned long missed_irq_rings
;
1235 * State variable controlling the reset flow and count
1237 * This is a counter which gets incremented when reset is triggered,
1238 * and again when reset has been handled. So odd values (lowest bit set)
1239 * means that reset is in progress and even values that
1240 * (reset_counter >> 1):th reset was successfully completed.
1242 * If reset is not completed succesfully, the I915_WEDGE bit is
1243 * set meaning that hardware is terminally sour and there is no
1244 * recovery. All waiters on the reset_queue will be woken when
1247 * This counter is used by the wait_seqno code to notice that reset
1248 * event happened and it needs to restart the entire ioctl (since most
1249 * likely the seqno it waited for won't ever signal anytime soon).
1251 * This is important for lock-free wait paths, where no contended lock
1252 * naturally enforces the correct ordering between the bail-out of the
1253 * waiter and the gpu reset work code.
1255 atomic_t reset_counter
;
1257 #define I915_RESET_IN_PROGRESS_FLAG 1
1258 #define I915_WEDGED (1 << 31)
1261 * Waitqueue to signal when the reset has completed. Used by clients
1262 * that wait for dev_priv->mm.wedged to settle.
1264 wait_queue_head_t reset_queue
;
1266 /* Userspace knobs for gpu hang simulation;
1267 * combines both a ring mask, and extra flags
1270 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1271 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1273 /* For missed irq/seqno simulation. */
1274 unsigned int test_irq_rings
;
1276 /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
1277 bool reload_in_reset
;
1280 enum modeset_restore
{
1281 MODESET_ON_LID_OPEN
,
1286 struct ddi_vbt_port_info
{
1288 * This is an index in the HDMI/DVI DDI buffer translation table.
1289 * The special value HDMI_LEVEL_SHIFT_UNKNOWN means the VBT didn't
1290 * populate this field.
1292 #define HDMI_LEVEL_SHIFT_UNKNOWN 0xff
1293 uint8_t hdmi_level_shift
;
1295 uint8_t supports_dvi
:1;
1296 uint8_t supports_hdmi
:1;
1297 uint8_t supports_dp
:1;
1300 enum drrs_support_type
{
1301 DRRS_NOT_SUPPORTED
= 0,
1302 STATIC_DRRS_SUPPORT
= 1,
1303 SEAMLESS_DRRS_SUPPORT
= 2
1306 struct intel_vbt_data
{
1307 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1308 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1311 unsigned int int_tv_support
:1;
1312 unsigned int lvds_dither
:1;
1313 unsigned int lvds_vbt
:1;
1314 unsigned int int_crt_support
:1;
1315 unsigned int lvds_use_ssc
:1;
1316 unsigned int display_clock_mode
:1;
1317 unsigned int fdi_rx_polarity_inverted
:1;
1318 unsigned int has_mipi
:1;
1320 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1322 enum drrs_support_type drrs_type
;
1327 int edp_preemphasis
;
1329 bool edp_initialized
;
1332 struct edp_power_seq edp_pps
;
1337 bool active_low_pwm
;
1338 u8 min_brightness
; /* min_brightness/255 of max */
1345 struct mipi_config
*config
;
1346 struct mipi_pps_data
*pps
;
1350 u8
*sequence
[MIPI_SEQ_MAX
];
1356 union child_device_config
*child_dev
;
1358 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1361 enum intel_ddb_partitioning
{
1363 INTEL_DDB_PART_5_6
, /* IVB+ */
1366 struct intel_wm_level
{
1374 struct ilk_wm_values
{
1375 uint32_t wm_pipe
[3];
1377 uint32_t wm_lp_spr
[3];
1378 uint32_t wm_linetime
[3];
1380 enum intel_ddb_partitioning partitioning
;
1384 * This struct helps tracking the state needed for runtime PM, which puts the
1385 * device in PCI D3 state. Notice that when this happens, nothing on the
1386 * graphics device works, even register access, so we don't get interrupts nor
1389 * Every piece of our code that needs to actually touch the hardware needs to
1390 * either call intel_runtime_pm_get or call intel_display_power_get with the
1391 * appropriate power domain.
1393 * Our driver uses the autosuspend delay feature, which means we'll only really
1394 * suspend if we stay with zero refcount for a certain amount of time. The
1395 * default value is currently very conservative (see intel_runtime_pm_enable), but
1396 * it can be changed with the standard runtime PM files from sysfs.
1398 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1399 * goes back to false exactly before we reenable the IRQs. We use this variable
1400 * to check if someone is trying to enable/disable IRQs while they're supposed
1401 * to be disabled. This shouldn't happen and we'll print some error messages in
1404 * For more, read the Documentation/power/runtime_pm.txt.
1406 struct i915_runtime_pm
{
1411 enum intel_pipe_crc_source
{
1412 INTEL_PIPE_CRC_SOURCE_NONE
,
1413 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1414 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1415 INTEL_PIPE_CRC_SOURCE_PF
,
1416 INTEL_PIPE_CRC_SOURCE_PIPE
,
1417 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1418 INTEL_PIPE_CRC_SOURCE_TV
,
1419 INTEL_PIPE_CRC_SOURCE_DP_B
,
1420 INTEL_PIPE_CRC_SOURCE_DP_C
,
1421 INTEL_PIPE_CRC_SOURCE_DP_D
,
1422 INTEL_PIPE_CRC_SOURCE_AUTO
,
1423 INTEL_PIPE_CRC_SOURCE_MAX
,
1426 struct intel_pipe_crc_entry
{
1431 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1432 struct intel_pipe_crc
{
1434 bool opened
; /* exclusive access to the result file */
1435 struct intel_pipe_crc_entry
*entries
;
1436 enum intel_pipe_crc_source source
;
1438 wait_queue_head_t wq
;
1441 struct i915_frontbuffer_tracking
{
1445 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1452 struct i915_wa_reg
{
1455 /* bitmask representing WA bits */
1459 #define I915_MAX_WA_REGS 16
1461 struct i915_workarounds
{
1462 struct i915_wa_reg reg
[I915_MAX_WA_REGS
];
1466 struct drm_i915_private
{
1467 struct drm_device
*dev
;
1468 struct kmem_cache
*slab
;
1470 const struct intel_device_info info
;
1472 int relative_constants_mode
;
1476 struct intel_uncore uncore
;
1478 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1481 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1482 * controller on different i2c buses. */
1483 struct mutex gmbus_mutex
;
1486 * Base address of the gmbus and gpio block.
1488 uint32_t gpio_mmio_base
;
1490 /* MMIO base address for MIPI regs */
1491 uint32_t mipi_mmio_base
;
1493 wait_queue_head_t gmbus_wait_queue
;
1495 struct pci_dev
*bridge_dev
;
1496 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1497 struct drm_i915_gem_object
*semaphore_obj
;
1498 uint32_t last_seqno
, next_seqno
;
1500 struct drm_dma_handle
*status_page_dmah
;
1501 struct resource mch_res
;
1503 /* protects the irq masks */
1504 spinlock_t irq_lock
;
1506 /* protects the mmio flip data */
1507 spinlock_t mmio_flip_lock
;
1509 bool display_irqs_enabled
;
1511 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1512 struct pm_qos_request pm_qos
;
1514 /* DPIO indirect register protection */
1515 struct mutex dpio_lock
;
1517 /** Cached value of IMR to avoid reads in updating the bitfield */
1520 u32 de_irq_mask
[I915_MAX_PIPES
];
1525 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1527 struct work_struct hotplug_work
;
1529 unsigned long hpd_last_jiffies
;
1534 HPD_MARK_DISABLED
= 2
1536 } hpd_stats
[HPD_NUM_PINS
];
1538 struct delayed_work hotplug_reenable_work
;
1540 struct i915_fbc fbc
;
1541 struct i915_drrs drrs
;
1542 struct intel_opregion opregion
;
1543 struct intel_vbt_data vbt
;
1545 bool preserve_bios_swizzle
;
1548 struct intel_overlay
*overlay
;
1550 /* backlight registers and fields in struct intel_panel */
1551 struct mutex backlight_lock
;
1554 bool no_aux_handshake
;
1556 /* protects panel power sequencer state */
1557 struct mutex pps_mutex
;
1559 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1560 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1561 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1563 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1564 unsigned int vlv_cdclk_freq
;
1567 * wq - Driver workqueue for GEM.
1569 * NOTE: Work items scheduled here are not allowed to grab any modeset
1570 * locks, for otherwise the flushing done in the pageflip code will
1571 * result in deadlocks.
1573 struct workqueue_struct
*wq
;
1575 /* Display functions */
1576 struct drm_i915_display_funcs display
;
1578 /* PCH chipset type */
1579 enum intel_pch pch_type
;
1580 unsigned short pch_id
;
1582 unsigned long quirks
;
1584 enum modeset_restore modeset_restore
;
1585 struct mutex modeset_restore_lock
;
1587 struct list_head vm_list
; /* Global list of all address spaces */
1588 struct i915_gtt gtt
; /* VM representing the global address space */
1590 struct i915_gem_mm mm
;
1591 DECLARE_HASHTABLE(mm_structs
, 7);
1592 struct mutex mm_lock
;
1594 /* Kernel Modesetting */
1596 struct sdvo_device_mapping sdvo_mappings
[2];
1598 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1599 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1600 wait_queue_head_t pending_flip_queue
;
1602 #ifdef CONFIG_DEBUG_FS
1603 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1606 int num_shared_dpll
;
1607 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1608 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1610 struct i915_workarounds workarounds
;
1612 /* Reclocking support */
1613 bool render_reclock_avail
;
1614 bool lvds_downclock_avail
;
1615 /* indicates the reduced downclock for LVDS*/
1618 struct i915_frontbuffer_tracking fb_tracking
;
1622 bool mchbar_need_disable
;
1624 struct intel_l3_parity l3_parity
;
1626 /* Cannot be determined by PCIID. You must always read a register. */
1629 /* gen6+ rps state */
1630 struct intel_gen6_power_mgmt rps
;
1632 /* ilk-only ips/rps state. Everything in here is protected by the global
1633 * mchdev_lock in intel_pm.c */
1634 struct intel_ilk_power_mgmt ips
;
1636 struct i915_power_domains power_domains
;
1638 struct i915_psr psr
;
1640 struct i915_gpu_error gpu_error
;
1642 struct drm_i915_gem_object
*vlv_pctx
;
1644 #ifdef CONFIG_DRM_I915_FBDEV
1645 /* list of fbdev register on this device */
1646 struct intel_fbdev
*fbdev
;
1647 struct work_struct fbdev_suspend_work
;
1650 struct drm_property
*broadcast_rgb_property
;
1651 struct drm_property
*force_audio_property
;
1653 uint32_t hw_context_size
;
1654 struct list_head context_list
;
1659 struct i915_suspend_saved_registers regfile
;
1660 struct vlv_s0ix_state vlv_s0ix_state
;
1664 * Raw watermark latency values:
1665 * in 0.1us units for WM0,
1666 * in 0.5us units for WM1+.
1669 uint16_t pri_latency
[5];
1671 uint16_t spr_latency
[5];
1673 uint16_t cur_latency
[5];
1675 /* current hardware state */
1676 struct ilk_wm_values hw
;
1679 struct i915_runtime_pm pm
;
1681 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1682 u32 long_hpd_port_mask
;
1683 u32 short_hpd_port_mask
;
1684 struct work_struct dig_port_work
;
1687 * if we get a HPD irq from DP and a HPD irq from non-DP
1688 * the non-DP HPD could block the workqueue on a mode config
1689 * mutex getting, that userspace may have taken. However
1690 * userspace is waiting on the DP workqueue to run which is
1691 * blocked behind the non-DP one.
1693 struct workqueue_struct
*dp_wq
;
1695 uint32_t bios_vgacntr
;
1697 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1699 struct i915_dri1_state dri1
;
1700 /* Old ums support infrastructure, same warning applies. */
1701 struct i915_ums_state ums
;
1703 /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
1705 int (*do_execbuf
)(struct drm_device
*dev
, struct drm_file
*file
,
1706 struct intel_engine_cs
*ring
,
1707 struct intel_context
*ctx
,
1708 struct drm_i915_gem_execbuffer2
*args
,
1709 struct list_head
*vmas
,
1710 struct drm_i915_gem_object
*batch_obj
,
1711 u64 exec_start
, u32 flags
);
1712 int (*init_rings
)(struct drm_device
*dev
);
1713 void (*cleanup_ring
)(struct intel_engine_cs
*ring
);
1714 void (*stop_ring
)(struct intel_engine_cs
*ring
);
1718 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1719 * will be rejected. Instead look for a better place.
1723 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1725 return dev
->dev_private
;
1728 /* Iterate over initialised rings */
1729 #define for_each_ring(ring__, dev_priv__, i__) \
1730 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1731 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1733 enum hdmi_force_audio
{
1734 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1735 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1736 HDMI_AUDIO_AUTO
, /* trust EDID */
1737 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1740 #define I915_GTT_OFFSET_NONE ((u32)-1)
1742 struct drm_i915_gem_object_ops
{
1743 /* Interface between the GEM object and its backing storage.
1744 * get_pages() is called once prior to the use of the associated set
1745 * of pages before to binding them into the GTT, and put_pages() is
1746 * called after we no longer need them. As we expect there to be
1747 * associated cost with migrating pages between the backing storage
1748 * and making them available for the GPU (e.g. clflush), we may hold
1749 * onto the pages after they are no longer referenced by the GPU
1750 * in case they may be used again shortly (for example migrating the
1751 * pages to a different memory domain within the GTT). put_pages()
1752 * will therefore most likely be called when the object itself is
1753 * being released or under memory pressure (where we attempt to
1754 * reap pages for the shrinker).
1756 int (*get_pages
)(struct drm_i915_gem_object
*);
1757 void (*put_pages
)(struct drm_i915_gem_object
*);
1758 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1759 void (*release
)(struct drm_i915_gem_object
*);
1763 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1764 * considered to be the frontbuffer for the given plane interface-vise. This
1765 * doesn't mean that the hw necessarily already scans it out, but that any
1766 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1768 * We have one bit per pipe and per scanout plane type.
1770 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1771 #define INTEL_FRONTBUFFER_BITS \
1772 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1773 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1774 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1775 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1776 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1777 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1778 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1779 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1780 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1781 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1782 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1784 struct drm_i915_gem_object
{
1785 struct drm_gem_object base
;
1787 const struct drm_i915_gem_object_ops
*ops
;
1789 /** List of VMAs backed by this object */
1790 struct list_head vma_list
;
1792 /** Stolen memory for this object, instead of being backed by shmem. */
1793 struct drm_mm_node
*stolen
;
1794 struct list_head global_list
;
1796 struct list_head ring_list
;
1797 /** Used in execbuf to temporarily hold a ref */
1798 struct list_head obj_exec_link
;
1801 * This is set if the object is on the active lists (has pending
1802 * rendering and so a non-zero seqno), and is not set if it i s on
1803 * inactive (ready to be unbound) list.
1805 unsigned int active
:1;
1808 * This is set if the object has been written to since last bound
1811 unsigned int dirty
:1;
1814 * Fence register bits (if any) for this object. Will be set
1815 * as needed when mapped into the GTT.
1816 * Protected by dev->struct_mutex.
1818 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1821 * Advice: are the backing pages purgeable?
1823 unsigned int madv
:2;
1826 * Current tiling mode for the object.
1828 unsigned int tiling_mode
:2;
1830 * Whether the tiling parameters for the currently associated fence
1831 * register have changed. Note that for the purposes of tracking
1832 * tiling changes we also treat the unfenced register, the register
1833 * slot that the object occupies whilst it executes a fenced
1834 * command (such as BLT on gen2/3), as a "fence".
1836 unsigned int fence_dirty
:1;
1839 * Is the object at the current location in the gtt mappable and
1840 * fenceable? Used to avoid costly recalculations.
1842 unsigned int map_and_fenceable
:1;
1845 * Whether the current gtt mapping needs to be mappable (and isn't just
1846 * mappable by accident). Track pin and fault separate for a more
1847 * accurate mappable working set.
1849 unsigned int fault_mappable
:1;
1850 unsigned int pin_mappable
:1;
1851 unsigned int pin_display
:1;
1854 * Is the object to be mapped as read-only to the GPU
1855 * Only honoured if hardware has relevant pte bit
1857 unsigned long gt_ro
:1;
1858 unsigned int cache_level
:3;
1860 unsigned int has_dma_mapping
:1;
1862 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1864 struct sg_table
*pages
;
1865 int pages_pin_count
;
1867 /* prime dma-buf support */
1868 void *dma_buf_vmapping
;
1871 struct intel_engine_cs
*ring
;
1873 /** Breadcrumb of last rendering to the buffer. */
1874 uint32_t last_read_seqno
;
1875 uint32_t last_write_seqno
;
1876 /** Breadcrumb of last fenced GPU access to the buffer. */
1877 uint32_t last_fenced_seqno
;
1879 /** Current tiling stride for the object, if it's tiled. */
1882 /** References from framebuffers, locks out tiling changes. */
1883 unsigned long framebuffer_references
;
1885 /** Record of address bit 17 of each page at last unbind. */
1886 unsigned long *bit_17
;
1888 /** User space pin count and filp owning the pin */
1889 unsigned long user_pin_count
;
1890 struct drm_file
*pin_filp
;
1892 /** for phy allocated objects */
1893 struct drm_dma_handle
*phys_handle
;
1896 struct i915_gem_userptr
{
1898 unsigned read_only
:1;
1899 unsigned workers
:4;
1900 #define I915_GEM_USERPTR_MAX_WORKERS 15
1902 struct i915_mm_struct
*mm
;
1903 struct i915_mmu_object
*mmu_object
;
1904 struct work_struct
*work
;
1908 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1910 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1911 struct drm_i915_gem_object
*new,
1912 unsigned frontbuffer_bits
);
1915 * Request queue structure.
1917 * The request queue allows us to note sequence numbers that have been emitted
1918 * and may be associated with active buffers to be retired.
1920 * By keeping this list, we can avoid having to do questionable
1921 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1922 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1924 struct drm_i915_gem_request
{
1925 /** On Which ring this request was generated */
1926 struct intel_engine_cs
*ring
;
1928 /** GEM sequence number associated with this request. */
1931 /** Position in the ringbuffer of the start of the request */
1934 /** Position in the ringbuffer of the end of the request */
1937 /** Context related to this request */
1938 struct intel_context
*ctx
;
1940 /** Batch buffer related to this request if any */
1941 struct drm_i915_gem_object
*batch_obj
;
1943 /** Time at which this request was emitted, in jiffies. */
1944 unsigned long emitted_jiffies
;
1946 /** global list entry for this request */
1947 struct list_head list
;
1949 struct drm_i915_file_private
*file_priv
;
1950 /** file_priv list entry for this request */
1951 struct list_head client_list
;
1954 struct drm_i915_file_private
{
1955 struct drm_i915_private
*dev_priv
;
1956 struct drm_file
*file
;
1960 struct list_head request_list
;
1961 struct delayed_work idle_work
;
1963 struct idr context_idr
;
1965 atomic_t rps_wait_boost
;
1966 struct intel_engine_cs
*bsd_ring
;
1970 * A command that requires special handling by the command parser.
1972 struct drm_i915_cmd_descriptor
{
1974 * Flags describing how the command parser processes the command.
1976 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1977 * a length mask if not set
1978 * CMD_DESC_SKIP: The command is allowed but does not follow the
1979 * standard length encoding for the opcode range in
1981 * CMD_DESC_REJECT: The command is never allowed
1982 * CMD_DESC_REGISTER: The command should be checked against the
1983 * register whitelist for the appropriate ring
1984 * CMD_DESC_MASTER: The command is allowed if the submitting process
1988 #define CMD_DESC_FIXED (1<<0)
1989 #define CMD_DESC_SKIP (1<<1)
1990 #define CMD_DESC_REJECT (1<<2)
1991 #define CMD_DESC_REGISTER (1<<3)
1992 #define CMD_DESC_BITMASK (1<<4)
1993 #define CMD_DESC_MASTER (1<<5)
1996 * The command's unique identification bits and the bitmask to get them.
1997 * This isn't strictly the opcode field as defined in the spec and may
1998 * also include type, subtype, and/or subop fields.
2006 * The command's length. The command is either fixed length (i.e. does
2007 * not include a length field) or has a length field mask. The flag
2008 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
2009 * a length mask. All command entries in a command table must include
2010 * length information.
2018 * Describes where to find a register address in the command to check
2019 * against the ring's register whitelist. Only valid if flags has the
2020 * CMD_DESC_REGISTER bit set.
2027 #define MAX_CMD_DESC_BITMASKS 3
2029 * Describes command checks where a particular dword is masked and
2030 * compared against an expected value. If the command does not match
2031 * the expected value, the parser rejects it. Only valid if flags has
2032 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
2035 * If the check specifies a non-zero condition_mask then the parser
2036 * only performs the check when the bits specified by condition_mask
2043 u32 condition_offset
;
2045 } bits
[MAX_CMD_DESC_BITMASKS
];
2049 * A table of commands requiring special handling by the command parser.
2051 * Each ring has an array of tables. Each table consists of an array of command
2052 * descriptors, which must be sorted with command opcodes in ascending order.
2054 struct drm_i915_cmd_table
{
2055 const struct drm_i915_cmd_descriptor
*table
;
2059 /* Note that the (struct drm_i915_private *) cast is just to shut up gcc. */
2060 #define __I915__(p) ({ \
2061 struct drm_i915_private *__p; \
2062 if (__builtin_types_compatible_p(typeof(*p), struct drm_i915_private)) \
2063 __p = (struct drm_i915_private *)p; \
2064 else if (__builtin_types_compatible_p(typeof(*p), struct drm_device)) \
2065 __p = to_i915((struct drm_device *)p); \
2070 #define INTEL_INFO(p) (&__I915__(p)->info)
2071 #define INTEL_DEVID(p) (INTEL_INFO(p)->device_id)
2073 #define IS_I830(dev) (INTEL_DEVID(dev) == 0x3577)
2074 #define IS_845G(dev) (INTEL_DEVID(dev) == 0x2562)
2075 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
2076 #define IS_I865G(dev) (INTEL_DEVID(dev) == 0x2572)
2077 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
2078 #define IS_I915GM(dev) (INTEL_DEVID(dev) == 0x2592)
2079 #define IS_I945G(dev) (INTEL_DEVID(dev) == 0x2772)
2080 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
2081 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
2082 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
2083 #define IS_GM45(dev) (INTEL_DEVID(dev) == 0x2A42)
2084 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
2085 #define IS_PINEVIEW_G(dev) (INTEL_DEVID(dev) == 0xa001)
2086 #define IS_PINEVIEW_M(dev) (INTEL_DEVID(dev) == 0xa011)
2087 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
2088 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
2089 #define IS_IRONLAKE_M(dev) (INTEL_DEVID(dev) == 0x0046)
2090 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
2091 #define IS_IVB_GT1(dev) (INTEL_DEVID(dev) == 0x0156 || \
2092 INTEL_DEVID(dev) == 0x0152 || \
2093 INTEL_DEVID(dev) == 0x015a)
2094 #define IS_SNB_GT1(dev) (INTEL_DEVID(dev) == 0x0102 || \
2095 INTEL_DEVID(dev) == 0x0106 || \
2096 INTEL_DEVID(dev) == 0x010A)
2097 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2098 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2099 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2100 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2101 #define IS_SKYLAKE(dev) (INTEL_INFO(dev)->is_skylake)
2102 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2103 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2104 (INTEL_DEVID(dev) & 0xFF00) == 0x0C00)
2105 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2106 ((INTEL_DEVID(dev) & 0xf) == 0x2 || \
2107 (INTEL_DEVID(dev) & 0xf) == 0x6 || \
2108 (INTEL_DEVID(dev) & 0xf) == 0xe))
2109 #define IS_BDW_GT3(dev) (IS_BROADWELL(dev) && \
2110 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2111 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2112 (INTEL_DEVID(dev) & 0xFF00) == 0x0A00)
2113 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2114 (INTEL_DEVID(dev) & 0x00F0) == 0x0020)
2115 /* ULX machines are also considered ULT. */
2116 #define IS_HSW_ULX(dev) (INTEL_DEVID(dev) == 0x0A0E || \
2117 INTEL_DEVID(dev) == 0x0A1E)
2118 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2121 * The genX designation typically refers to the render engine, so render
2122 * capability related checks should use IS_GEN, while display and other checks
2123 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2126 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2127 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2128 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2129 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2130 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2131 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2132 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2133 #define IS_GEN9(dev) (INTEL_INFO(dev)->gen == 9)
2135 #define RENDER_RING (1<<RCS)
2136 #define BSD_RING (1<<VCS)
2137 #define BLT_RING (1<<BCS)
2138 #define VEBOX_RING (1<<VECS)
2139 #define BSD2_RING (1<<VCS2)
2140 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2141 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2142 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2143 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2144 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2145 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2146 __I915__(dev)->ellc_size)
2147 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2149 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2150 #define HAS_LOGICAL_RING_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 8)
2151 #define USES_PPGTT(dev) (i915.enable_ppgtt)
2152 #define USES_FULL_PPGTT(dev) (i915.enable_ppgtt == 2)
2154 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2155 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2157 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2158 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2160 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2161 * even when in MSI mode. This results in spurious interrupt warnings if the
2162 * legacy irq no. is shared with another device. The kernel then disables that
2163 * interrupt source and so prevents the other device from working properly.
2165 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2166 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2168 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2169 * rows, which changed the alignment requirements and fence programming.
2171 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2173 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2174 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2175 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2176 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2177 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2179 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2180 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2181 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2183 #define HAS_IPS(dev) (IS_HSW_ULT(dev) || IS_BROADWELL(dev))
2185 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2186 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2187 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2188 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2189 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2190 #define HAS_RC6(dev) (INTEL_INFO(dev)->gen >= 6)
2191 #define HAS_RC6p(dev) (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev))
2193 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2194 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2195 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2196 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2197 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2198 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2199 #define INTEL_PCH_SPT_DEVICE_ID_TYPE 0xA100
2200 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE 0x9D00
2202 #define INTEL_PCH_TYPE(dev) (__I915__(dev)->pch_type)
2203 #define HAS_PCH_SPT(dev) (INTEL_PCH_TYPE(dev) == PCH_SPT)
2204 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2205 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2206 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2207 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2208 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2210 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2212 /* DPF == dynamic parity feature */
2213 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2214 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2216 #define GT_FREQUENCY_MULTIPLIER 50
2218 #include "i915_trace.h"
2220 extern const struct drm_ioctl_desc i915_ioctls
[];
2221 extern int i915_max_ioctl
;
2223 extern int i915_suspend_legacy(struct drm_device
*dev
, pm_message_t state
);
2224 extern int i915_resume_legacy(struct drm_device
*dev
);
2225 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2226 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2229 struct i915_params
{
2231 int panel_ignore_lid
;
2232 unsigned int powersave
;
2234 unsigned int lvds_downclock
;
2235 int lvds_channel_mode
;
2237 int vbt_sdvo_panel_type
;
2241 int enable_execlists
;
2243 unsigned int preliminary_hw_support
;
2244 int disable_power_well
;
2246 int invert_brightness
;
2247 int enable_cmd_parser
;
2248 /* leave bools at the end to not create holes */
2249 bool enable_hangcheck
;
2251 bool prefault_disable
;
2253 bool disable_display
;
2254 bool disable_vtd_wa
;
2258 extern struct i915_params i915 __read_mostly
;
2261 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2262 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2263 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2264 extern int i915_driver_unload(struct drm_device
*);
2265 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2266 extern void i915_driver_lastclose(struct drm_device
* dev
);
2267 extern void i915_driver_preclose(struct drm_device
*dev
,
2268 struct drm_file
*file
);
2269 extern void i915_driver_postclose(struct drm_device
*dev
,
2270 struct drm_file
*file
);
2271 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2272 #ifdef CONFIG_COMPAT
2273 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2276 extern int i915_emit_box(struct drm_device
*dev
,
2277 struct drm_clip_rect
*box
,
2279 extern int intel_gpu_reset(struct drm_device
*dev
);
2280 extern int i915_reset(struct drm_device
*dev
);
2281 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2282 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2283 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2284 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2285 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2286 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2289 void i915_queue_hangcheck(struct drm_device
*dev
);
2291 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2292 const char *fmt
, ...);
2294 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2296 extern void intel_irq_init(struct drm_i915_private
*dev_priv
);
2297 extern void intel_hpd_init(struct drm_i915_private
*dev_priv
);
2298 int intel_irq_install(struct drm_i915_private
*dev_priv
);
2299 void intel_irq_uninstall(struct drm_i915_private
*dev_priv
);
2301 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2302 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2303 bool restore_forcewake
);
2304 extern void intel_uncore_init(struct drm_device
*dev
);
2305 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2306 extern void intel_uncore_fini(struct drm_device
*dev
);
2307 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2310 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2314 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2317 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2318 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2320 ironlake_enable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2322 ironlake_disable_display_irq(struct drm_i915_private
*dev_priv
, u32 mask
);
2323 void ibx_display_interrupt_update(struct drm_i915_private
*dev_priv
,
2324 uint32_t interrupt_mask
,
2325 uint32_t enabled_irq_mask
);
2326 #define ibx_enable_display_interrupt(dev_priv, bits) \
2327 ibx_display_interrupt_update((dev_priv), (bits), (bits))
2328 #define ibx_disable_display_interrupt(dev_priv, bits) \
2329 ibx_display_interrupt_update((dev_priv), (bits), 0)
2332 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2333 struct drm_file
*file_priv
);
2334 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2335 struct drm_file
*file_priv
);
2336 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2337 struct drm_file
*file_priv
);
2338 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2339 struct drm_file
*file_priv
);
2340 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2341 struct drm_file
*file_priv
);
2342 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2343 struct drm_file
*file_priv
);
2344 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2345 struct drm_file
*file_priv
);
2346 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2347 struct drm_file
*file_priv
);
2348 void i915_gem_execbuffer_move_to_active(struct list_head
*vmas
,
2349 struct intel_engine_cs
*ring
);
2350 void i915_gem_execbuffer_retire_commands(struct drm_device
*dev
,
2351 struct drm_file
*file
,
2352 struct intel_engine_cs
*ring
,
2353 struct drm_i915_gem_object
*obj
);
2354 int i915_gem_ringbuffer_submission(struct drm_device
*dev
,
2355 struct drm_file
*file
,
2356 struct intel_engine_cs
*ring
,
2357 struct intel_context
*ctx
,
2358 struct drm_i915_gem_execbuffer2
*args
,
2359 struct list_head
*vmas
,
2360 struct drm_i915_gem_object
*batch_obj
,
2361 u64 exec_start
, u32 flags
);
2362 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2363 struct drm_file
*file_priv
);
2364 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2365 struct drm_file
*file_priv
);
2366 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2367 struct drm_file
*file_priv
);
2368 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2369 struct drm_file
*file_priv
);
2370 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2371 struct drm_file
*file_priv
);
2372 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2373 struct drm_file
*file
);
2374 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2375 struct drm_file
*file
);
2376 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2377 struct drm_file
*file_priv
);
2378 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2379 struct drm_file
*file_priv
);
2380 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2381 struct drm_file
*file_priv
);
2382 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2383 struct drm_file
*file_priv
);
2384 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2385 struct drm_file
*file_priv
);
2386 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2387 struct drm_file
*file_priv
);
2388 int i915_gem_init_userptr(struct drm_device
*dev
);
2389 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2390 struct drm_file
*file
);
2391 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2392 struct drm_file
*file_priv
);
2393 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2394 struct drm_file
*file_priv
);
2395 void i915_gem_load(struct drm_device
*dev
);
2396 unsigned long i915_gem_shrink(struct drm_i915_private
*dev_priv
,
2399 #define I915_SHRINK_PURGEABLE 0x1
2400 #define I915_SHRINK_UNBOUND 0x2
2401 #define I915_SHRINK_BOUND 0x4
2402 void *i915_gem_object_alloc(struct drm_device
*dev
);
2403 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2404 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2405 const struct drm_i915_gem_object_ops
*ops
);
2406 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2408 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2409 struct i915_address_space
*vm
);
2410 void i915_gem_free_object(struct drm_gem_object
*obj
);
2411 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2413 #define PIN_MAPPABLE 0x1
2414 #define PIN_NONBLOCK 0x2
2415 #define PIN_GLOBAL 0x4
2416 #define PIN_OFFSET_BIAS 0x8
2417 #define PIN_OFFSET_MASK (~4095)
2418 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2419 struct i915_address_space
*vm
,
2422 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2423 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2424 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2425 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2426 void i915_gem_lastclose(struct drm_device
*dev
);
2428 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2429 int *needs_clflush
);
2431 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2432 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2434 struct sg_page_iter sg_iter
;
2436 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2437 return sg_page_iter_page(&sg_iter
);
2441 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2443 BUG_ON(obj
->pages
== NULL
);
2444 obj
->pages_pin_count
++;
2446 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2448 BUG_ON(obj
->pages_pin_count
== 0);
2449 obj
->pages_pin_count
--;
2452 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2453 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2454 struct intel_engine_cs
*to
);
2455 void i915_vma_move_to_active(struct i915_vma
*vma
,
2456 struct intel_engine_cs
*ring
);
2457 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2458 struct drm_device
*dev
,
2459 struct drm_mode_create_dumb
*args
);
2460 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2461 uint32_t handle
, uint64_t *offset
);
2463 * Returns true if seq1 is later than seq2.
2466 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2468 return (int32_t)(seq1
- seq2
) >= 0;
2471 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2472 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2473 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2474 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2476 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2477 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2479 struct drm_i915_gem_request
*
2480 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2482 bool i915_gem_retire_requests(struct drm_device
*dev
);
2483 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2484 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2485 bool interruptible
);
2486 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2488 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2490 return unlikely(atomic_read(&error
->reset_counter
)
2491 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2494 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2496 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2499 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2501 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2504 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2506 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2507 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2510 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2512 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2513 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2516 void i915_gem_reset(struct drm_device
*dev
);
2517 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2518 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2519 int __must_check
i915_gem_init(struct drm_device
*dev
);
2520 int i915_gem_init_rings(struct drm_device
*dev
);
2521 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2522 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2523 void i915_gem_init_swizzling(struct drm_device
*dev
);
2524 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2525 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2526 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2527 int __i915_add_request(struct intel_engine_cs
*ring
,
2528 struct drm_file
*file
,
2529 struct drm_i915_gem_object
*batch_obj
,
2531 #define i915_add_request(ring, seqno) \
2532 __i915_add_request(ring, NULL, NULL, seqno)
2533 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2535 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2537 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2540 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2542 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2544 struct intel_engine_cs
*pipelined
);
2545 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2546 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2548 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2549 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2552 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2554 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2555 int tiling_mode
, bool fenced
);
2557 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2558 enum i915_cache_level cache_level
);
2560 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2561 struct dma_buf
*dma_buf
);
2563 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2564 struct drm_gem_object
*gem_obj
, int flags
);
2566 void i915_gem_restore_fences(struct drm_device
*dev
);
2568 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2569 struct i915_address_space
*vm
);
2570 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2571 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2572 struct i915_address_space
*vm
);
2573 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2574 struct i915_address_space
*vm
);
2575 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2576 struct i915_address_space
*vm
);
2578 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2579 struct i915_address_space
*vm
);
2581 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2582 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2583 struct i915_vma
*vma
;
2584 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2585 if (vma
->pin_count
> 0)
2590 /* Some GGTT VM helpers */
2591 #define i915_obj_to_ggtt(obj) \
2592 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2593 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2595 struct i915_address_space
*ggtt
=
2596 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2600 static inline struct i915_hw_ppgtt
*
2601 i915_vm_to_ppgtt(struct i915_address_space
*vm
)
2603 WARN_ON(i915_is_ggtt(vm
));
2605 return container_of(vm
, struct i915_hw_ppgtt
, base
);
2609 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2611 return i915_gem_obj_bound(obj
, i915_obj_to_ggtt(obj
));
2614 static inline unsigned long
2615 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2617 return i915_gem_obj_offset(obj
, i915_obj_to_ggtt(obj
));
2620 static inline unsigned long
2621 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2623 return i915_gem_obj_size(obj
, i915_obj_to_ggtt(obj
));
2626 static inline int __must_check
2627 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2631 return i915_gem_object_pin(obj
, i915_obj_to_ggtt(obj
),
2632 alignment
, flags
| PIN_GLOBAL
);
2636 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2638 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2641 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2643 /* i915_gem_context.c */
2644 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2645 void i915_gem_context_fini(struct drm_device
*dev
);
2646 void i915_gem_context_reset(struct drm_device
*dev
);
2647 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2648 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2649 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2650 int i915_switch_context(struct intel_engine_cs
*ring
,
2651 struct intel_context
*to
);
2652 struct intel_context
*
2653 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2654 void i915_gem_context_free(struct kref
*ctx_ref
);
2655 struct drm_i915_gem_object
*
2656 i915_gem_alloc_context_obj(struct drm_device
*dev
, size_t size
);
2657 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2659 kref_get(&ctx
->ref
);
2662 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2664 kref_put(&ctx
->ref
, i915_gem_context_free
);
2667 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2669 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2672 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2673 struct drm_file
*file
);
2674 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2675 struct drm_file
*file
);
2677 /* i915_gem_evict.c */
2678 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2679 struct i915_address_space
*vm
,
2682 unsigned cache_level
,
2683 unsigned long start
,
2686 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2687 int i915_gem_evict_everything(struct drm_device
*dev
);
2689 /* belongs in i915_gem_gtt.h */
2690 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2692 if (INTEL_INFO(dev
)->gen
< 6)
2693 intel_gtt_chipset_flush();
2696 /* i915_gem_stolen.c */
2697 int i915_gem_init_stolen(struct drm_device
*dev
);
2698 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2699 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2700 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2701 struct drm_i915_gem_object
*
2702 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2703 struct drm_i915_gem_object
*
2704 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2709 /* i915_gem_tiling.c */
2710 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2712 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2714 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2715 obj
->tiling_mode
!= I915_TILING_NONE
;
2718 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2719 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2720 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2722 /* i915_gem_debug.c */
2724 int i915_verify_lists(struct drm_device
*dev
);
2726 #define i915_verify_lists(dev) 0
2729 /* i915_debugfs.c */
2730 int i915_debugfs_init(struct drm_minor
*minor
);
2731 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2732 #ifdef CONFIG_DEBUG_FS
2733 void intel_display_crc_init(struct drm_device
*dev
);
2735 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2738 /* i915_gpu_error.c */
2740 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2741 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2742 const struct i915_error_state_file_priv
*error
);
2743 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2744 struct drm_i915_private
*i915
,
2745 size_t count
, loff_t pos
);
2746 static inline void i915_error_state_buf_release(
2747 struct drm_i915_error_state_buf
*eb
)
2751 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2752 const char *error_msg
);
2753 void i915_error_state_get(struct drm_device
*dev
,
2754 struct i915_error_state_file_priv
*error_priv
);
2755 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2756 void i915_destroy_error_state(struct drm_device
*dev
);
2758 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2759 const char *i915_cache_level_str(struct drm_i915_private
*i915
, int type
);
2761 /* i915_cmd_parser.c */
2762 int i915_cmd_parser_get_version(void);
2763 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2764 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2765 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2766 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2767 struct drm_i915_gem_object
*batch_obj
,
2768 u32 batch_start_offset
,
2771 /* i915_suspend.c */
2772 extern int i915_save_state(struct drm_device
*dev
);
2773 extern int i915_restore_state(struct drm_device
*dev
);
2776 void i915_save_display_reg(struct drm_device
*dev
);
2777 void i915_restore_display_reg(struct drm_device
*dev
);
2780 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2781 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2784 extern int intel_setup_gmbus(struct drm_device
*dev
);
2785 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2786 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2788 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2791 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2792 struct drm_i915_private
*dev_priv
, unsigned port
);
2793 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2794 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2795 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2797 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2799 extern void intel_i2c_reset(struct drm_device
*dev
);
2801 /* intel_opregion.c */
2803 extern int intel_opregion_setup(struct drm_device
*dev
);
2804 extern void intel_opregion_init(struct drm_device
*dev
);
2805 extern void intel_opregion_fini(struct drm_device
*dev
);
2806 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2807 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2809 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2812 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2813 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2814 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2815 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2817 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2822 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2830 extern void intel_register_dsm_handler(void);
2831 extern void intel_unregister_dsm_handler(void);
2833 static inline void intel_register_dsm_handler(void) { return; }
2834 static inline void intel_unregister_dsm_handler(void) { return; }
2835 #endif /* CONFIG_ACPI */
2838 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2839 extern void intel_modeset_init(struct drm_device
*dev
);
2840 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2841 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2842 extern void intel_connector_unregister(struct intel_connector
*);
2843 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2844 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2845 bool force_restore
);
2846 extern void i915_redisable_vga(struct drm_device
*dev
);
2847 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2848 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2849 extern void bdw_fbc_sw_flush(struct drm_device
*dev
, u32 value
);
2850 extern void intel_disable_fbc(struct drm_device
*dev
);
2851 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2852 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2853 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2854 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2855 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2857 extern void intel_detect_pch(struct drm_device
*dev
);
2858 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2859 extern int intel_enable_rc6(const struct drm_device
*dev
);
2861 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2862 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2863 struct drm_file
*file
);
2864 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2865 struct drm_file
*file
);
2867 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2870 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2871 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2872 struct intel_overlay_error_state
*error
);
2874 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2875 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2876 struct drm_device
*dev
,
2877 struct intel_display_error_state
*error
);
2879 /* On SNB platform, before reading ring registers forcewake bit
2880 * must be set to prevent GT core from power down and stale values being
2883 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2884 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2885 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2887 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2888 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2890 /* intel_sideband.c */
2891 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2892 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2893 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2894 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2895 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2896 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2897 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2898 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2899 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2900 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2901 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2902 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2903 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2904 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2905 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2906 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2907 enum intel_sbi_destination destination
);
2908 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2909 enum intel_sbi_destination destination
);
2910 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2911 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2913 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2914 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2916 #define FORCEWAKE_RENDER (1 << 0)
2917 #define FORCEWAKE_MEDIA (1 << 1)
2918 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2921 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2922 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2924 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2925 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2926 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2927 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2929 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2930 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2931 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2932 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2934 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2935 * will be implemented using 2 32-bit writes in an arbitrary order with
2936 * an arbitrary delay between them. This can cause the hardware to
2937 * act upon the intermediate value, possibly leading to corruption and
2938 * machine death. You have been warned.
2940 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2941 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2943 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2944 u32 upper = I915_READ(upper_reg); \
2945 u32 lower = I915_READ(lower_reg); \
2946 u32 tmp = I915_READ(upper_reg); \
2947 if (upper != tmp) { \
2949 lower = I915_READ(lower_reg); \
2950 WARN_ON(I915_READ(upper_reg) != upper); \
2952 (u64)upper << 32 | lower; })
2954 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2955 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2957 /* "Broadcast RGB" property */
2958 #define INTEL_BROADCAST_RGB_AUTO 0
2959 #define INTEL_BROADCAST_RGB_FULL 1
2960 #define INTEL_BROADCAST_RGB_LIMITED 2
2962 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2964 if (IS_VALLEYVIEW(dev
))
2965 return VLV_VGACNTRL
;
2966 else if (INTEL_INFO(dev
)->gen
>= 5)
2967 return CPU_VGACNTRL
;
2972 static inline void __user
*to_user_ptr(u64 address
)
2974 return (void __user
*)(uintptr_t)address
;
2977 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2979 unsigned long j
= msecs_to_jiffies(m
);
2981 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2984 static inline unsigned long
2985 timespec_to_jiffies_timeout(const struct timespec
*value
)
2987 unsigned long j
= timespec_to_jiffies(value
);
2989 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2993 * If you need to wait X milliseconds between events A and B, but event B
2994 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2995 * when event A happened, then just before event B you call this function and
2996 * pass the timestamp as the first argument, and X as the second argument.
2999 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
3001 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
3004 * Don't re-read the value of "jiffies" every time since it may change
3005 * behind our back and break the math.
3007 tmp_jiffies
= jiffies
;
3008 target_jiffies
= timestamp_jiffies
+
3009 msecs_to_jiffies_timeout(to_wait_ms
);
3011 if (time_after(target_jiffies
, tmp_jiffies
)) {
3012 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
3013 while (remaining_jiffies
)
3015 schedule_timeout_uninterruptible(remaining_jiffies
);