1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
33 #include <uapi/drm/i915_drm.h>
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "i915_gem_gtt.h"
39 #include <linux/io-mapping.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 #include <drm/intel-gtt.h>
43 #include <linux/backlight.h>
44 #include <linux/hashtable.h>
45 #include <linux/intel-iommu.h>
46 #include <linux/kref.h>
47 #include <linux/pm_qos.h>
49 /* General customization:
52 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
54 #define DRIVER_NAME "i915"
55 #define DRIVER_DESC "Intel Graphics"
56 #define DRIVER_DATE "20140725"
64 I915_MAX_PIPES
= _PIPE_EDP
66 #define pipe_name(p) ((p) + 'A')
75 #define transcoder_name(t) ((t) + 'A')
82 #define plane_name(p) ((p) + 'A')
84 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
94 #define port_name(p) ((p) + 'A')
96 #define I915_NUM_PHYS_VLV 2
108 enum intel_display_power_domain
{
112 POWER_DOMAIN_PIPE_A_PANEL_FITTER
,
113 POWER_DOMAIN_PIPE_B_PANEL_FITTER
,
114 POWER_DOMAIN_PIPE_C_PANEL_FITTER
,
115 POWER_DOMAIN_TRANSCODER_A
,
116 POWER_DOMAIN_TRANSCODER_B
,
117 POWER_DOMAIN_TRANSCODER_C
,
118 POWER_DOMAIN_TRANSCODER_EDP
,
119 POWER_DOMAIN_PORT_DDI_A_2_LANES
,
120 POWER_DOMAIN_PORT_DDI_A_4_LANES
,
121 POWER_DOMAIN_PORT_DDI_B_2_LANES
,
122 POWER_DOMAIN_PORT_DDI_B_4_LANES
,
123 POWER_DOMAIN_PORT_DDI_C_2_LANES
,
124 POWER_DOMAIN_PORT_DDI_C_4_LANES
,
125 POWER_DOMAIN_PORT_DDI_D_2_LANES
,
126 POWER_DOMAIN_PORT_DDI_D_4_LANES
,
127 POWER_DOMAIN_PORT_DSI
,
128 POWER_DOMAIN_PORT_CRT
,
129 POWER_DOMAIN_PORT_OTHER
,
138 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
139 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
140 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
141 #define POWER_DOMAIN_TRANSCODER(tran) \
142 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
143 (tran) + POWER_DOMAIN_TRANSCODER_A)
147 HPD_PORT_A
= HPD_NONE
, /* PORT_A is internal */
148 HPD_TV
= HPD_NONE
, /* TV is known to be unreliable */
158 #define I915_GEM_GPU_DOMAINS \
159 (I915_GEM_DOMAIN_RENDER | \
160 I915_GEM_DOMAIN_SAMPLER | \
161 I915_GEM_DOMAIN_COMMAND | \
162 I915_GEM_DOMAIN_INSTRUCTION | \
163 I915_GEM_DOMAIN_VERTEX)
165 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
166 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
168 #define for_each_crtc(dev, crtc) \
169 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
171 #define for_each_intel_crtc(dev, intel_crtc) \
172 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head)
174 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
175 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
176 if ((intel_encoder)->base.crtc == (__crtc))
178 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
179 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
180 if ((intel_connector)->base.encoder == (__encoder))
182 #define for_each_power_domain(domain, mask) \
183 for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
184 if ((1 << (domain)) & (mask))
186 struct drm_i915_private
;
187 struct i915_mm_struct
;
188 struct i915_mmu_object
;
191 DPLL_ID_PRIVATE
= -1, /* non-shared dpll in use */
192 /* real shared dpll ids must be >= 0 */
193 DPLL_ID_PCH_PLL_A
= 0,
194 DPLL_ID_PCH_PLL_B
= 1,
198 #define I915_NUM_PLLS 2
200 struct intel_dpll_hw_state
{
208 struct intel_shared_dpll
{
209 int refcount
; /* count of number of CRTCs sharing this PLL */
210 int active
; /* count of number of active CRTCs (i.e. DPMS on) */
211 bool on
; /* is the PLL actually active? Disabled during modeset */
213 /* should match the index in the dev_priv->shared_dplls array */
214 enum intel_dpll_id id
;
215 struct intel_dpll_hw_state hw_state
;
216 /* The mode_set hook is optional and should be used together with the
217 * intel_prepare_shared_dpll function. */
218 void (*mode_set
)(struct drm_i915_private
*dev_priv
,
219 struct intel_shared_dpll
*pll
);
220 void (*enable
)(struct drm_i915_private
*dev_priv
,
221 struct intel_shared_dpll
*pll
);
222 void (*disable
)(struct drm_i915_private
*dev_priv
,
223 struct intel_shared_dpll
*pll
);
224 bool (*get_hw_state
)(struct drm_i915_private
*dev_priv
,
225 struct intel_shared_dpll
*pll
,
226 struct intel_dpll_hw_state
*hw_state
);
229 /* Used by dp and fdi links */
230 struct intel_link_m_n
{
238 void intel_link_compute_m_n(int bpp
, int nlanes
,
239 int pixel_clock
, int link_clock
,
240 struct intel_link_m_n
*m_n
);
242 /* Interface history:
245 * 1.2: Add Power Management
246 * 1.3: Add vblank support
247 * 1.4: Fix cmdbuffer path, add heap destroy
248 * 1.5: Add vblank pipe configuration
249 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
250 * - Support vertical blank on secondary display pipe
252 #define DRIVER_MAJOR 1
253 #define DRIVER_MINOR 6
254 #define DRIVER_PATCHLEVEL 0
256 #define WATCH_LISTS 0
259 struct opregion_header
;
260 struct opregion_acpi
;
261 struct opregion_swsci
;
262 struct opregion_asle
;
264 struct intel_opregion
{
265 struct opregion_header __iomem
*header
;
266 struct opregion_acpi __iomem
*acpi
;
267 struct opregion_swsci __iomem
*swsci
;
268 u32 swsci_gbda_sub_functions
;
269 u32 swsci_sbcb_sub_functions
;
270 struct opregion_asle __iomem
*asle
;
272 u32 __iomem
*lid_state
;
273 struct work_struct asle_work
;
275 #define OPREGION_SIZE (8*1024)
277 struct intel_overlay
;
278 struct intel_overlay_error_state
;
280 struct drm_i915_master_private
{
281 drm_local_map_t
*sarea
;
282 struct _drm_i915_sarea
*sarea_priv
;
284 #define I915_FENCE_REG_NONE -1
285 #define I915_MAX_NUM_FENCES 32
286 /* 32 fences + sign bit for FENCE_REG_NONE */
287 #define I915_MAX_NUM_FENCE_BITS 6
289 struct drm_i915_fence_reg
{
290 struct list_head lru_list
;
291 struct drm_i915_gem_object
*obj
;
295 struct sdvo_device_mapping
{
304 struct intel_display_error_state
;
306 struct drm_i915_error_state
{
314 /* Generic register state */
322 u32 error
; /* gen6+ */
323 u32 err_int
; /* gen7 */
329 u32 extra_instdone
[I915_NUM_INSTDONE_REG
];
330 u64 fence
[I915_MAX_NUM_FENCES
];
331 struct intel_overlay_error_state
*overlay
;
332 struct intel_display_error_state
*display
;
333 struct drm_i915_error_object
*semaphore_obj
;
335 struct drm_i915_error_ring
{
337 /* Software tracked state */
340 enum intel_ring_hangcheck_action hangcheck_action
;
343 /* our own tracking of ring head and tail */
347 u32 semaphore_seqno
[I915_NUM_RINGS
- 1];
365 u32 rc_psmi
; /* sleep state */
366 u32 semaphore_mboxes
[I915_NUM_RINGS
- 1];
368 struct drm_i915_error_object
{
372 } *ringbuffer
, *batchbuffer
, *wa_batchbuffer
, *ctx
, *hws_page
;
374 struct drm_i915_error_request
{
389 char comm
[TASK_COMM_LEN
];
390 } ring
[I915_NUM_RINGS
];
391 struct drm_i915_error_buffer
{
398 s32 fence_reg
:I915_MAX_NUM_FENCE_BITS
;
406 } **active_bo
, **pinned_bo
;
408 u32
*active_bo_count
, *pinned_bo_count
;
411 struct intel_connector
;
412 struct intel_crtc_config
;
413 struct intel_plane_config
;
418 struct drm_i915_display_funcs
{
419 bool (*fbc_enabled
)(struct drm_device
*dev
);
420 void (*enable_fbc
)(struct drm_crtc
*crtc
);
421 void (*disable_fbc
)(struct drm_device
*dev
);
422 int (*get_display_clock_speed
)(struct drm_device
*dev
);
423 int (*get_fifo_size
)(struct drm_device
*dev
, int plane
);
425 * find_dpll() - Find the best values for the PLL
426 * @limit: limits for the PLL
427 * @crtc: current CRTC
428 * @target: target frequency in kHz
429 * @refclk: reference clock frequency in kHz
430 * @match_clock: if provided, @best_clock P divider must
431 * match the P divider from @match_clock
432 * used for LVDS downclocking
433 * @best_clock: best PLL values found
435 * Returns true on success, false on failure.
437 bool (*find_dpll
)(const struct intel_limit
*limit
,
438 struct drm_crtc
*crtc
,
439 int target
, int refclk
,
440 struct dpll
*match_clock
,
441 struct dpll
*best_clock
);
442 void (*update_wm
)(struct drm_crtc
*crtc
);
443 void (*update_sprite_wm
)(struct drm_plane
*plane
,
444 struct drm_crtc
*crtc
,
445 uint32_t sprite_width
, uint32_t sprite_height
,
446 int pixel_size
, bool enable
, bool scaled
);
447 void (*modeset_global_resources
)(struct drm_device
*dev
);
448 /* Returns the active state of the crtc, and if the crtc is active,
449 * fills out the pipe-config with the hw state. */
450 bool (*get_pipe_config
)(struct intel_crtc
*,
451 struct intel_crtc_config
*);
452 void (*get_plane_config
)(struct intel_crtc
*,
453 struct intel_plane_config
*);
454 int (*crtc_mode_set
)(struct drm_crtc
*crtc
,
456 struct drm_framebuffer
*old_fb
);
457 void (*crtc_enable
)(struct drm_crtc
*crtc
);
458 void (*crtc_disable
)(struct drm_crtc
*crtc
);
459 void (*off
)(struct drm_crtc
*crtc
);
460 void (*write_eld
)(struct drm_connector
*connector
,
461 struct drm_crtc
*crtc
,
462 struct drm_display_mode
*mode
);
463 void (*fdi_link_train
)(struct drm_crtc
*crtc
);
464 void (*init_clock_gating
)(struct drm_device
*dev
);
465 int (*queue_flip
)(struct drm_device
*dev
, struct drm_crtc
*crtc
,
466 struct drm_framebuffer
*fb
,
467 struct drm_i915_gem_object
*obj
,
468 struct intel_engine_cs
*ring
,
470 void (*update_primary_plane
)(struct drm_crtc
*crtc
,
471 struct drm_framebuffer
*fb
,
473 void (*hpd_irq_setup
)(struct drm_device
*dev
);
474 /* clock updates for mode set */
476 /* render clock increase/decrease */
477 /* display clock increase/decrease */
478 /* pll clock increase/decrease */
480 int (*setup_backlight
)(struct intel_connector
*connector
);
481 uint32_t (*get_backlight
)(struct intel_connector
*connector
);
482 void (*set_backlight
)(struct intel_connector
*connector
,
484 void (*disable_backlight
)(struct intel_connector
*connector
);
485 void (*enable_backlight
)(struct intel_connector
*connector
);
488 struct intel_uncore_funcs
{
489 void (*force_wake_get
)(struct drm_i915_private
*dev_priv
,
491 void (*force_wake_put
)(struct drm_i915_private
*dev_priv
,
494 uint8_t (*mmio_readb
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
495 uint16_t (*mmio_readw
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
496 uint32_t (*mmio_readl
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
497 uint64_t (*mmio_readq
)(struct drm_i915_private
*dev_priv
, off_t offset
, bool trace
);
499 void (*mmio_writeb
)(struct drm_i915_private
*dev_priv
, off_t offset
,
500 uint8_t val
, bool trace
);
501 void (*mmio_writew
)(struct drm_i915_private
*dev_priv
, off_t offset
,
502 uint16_t val
, bool trace
);
503 void (*mmio_writel
)(struct drm_i915_private
*dev_priv
, off_t offset
,
504 uint32_t val
, bool trace
);
505 void (*mmio_writeq
)(struct drm_i915_private
*dev_priv
, off_t offset
,
506 uint64_t val
, bool trace
);
509 struct intel_uncore
{
510 spinlock_t lock
; /** lock is also taken in irq contexts. */
512 struct intel_uncore_funcs funcs
;
515 unsigned forcewake_count
;
517 unsigned fw_rendercount
;
518 unsigned fw_mediacount
;
520 struct timer_list force_wake_timer
;
523 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
524 func(is_mobile) sep \
527 func(is_i945gm) sep \
529 func(need_gfx_hws) sep \
531 func(is_pineview) sep \
532 func(is_broadwater) sep \
533 func(is_crestline) sep \
534 func(is_ivybridge) sep \
535 func(is_valleyview) sep \
536 func(is_haswell) sep \
537 func(is_preliminary) sep \
539 func(has_pipe_cxsr) sep \
540 func(has_hotplug) sep \
541 func(cursor_needs_physical) sep \
542 func(has_overlay) sep \
543 func(overlay_needs_physical) sep \
544 func(supports_tv) sep \
549 #define DEFINE_FLAG(name) u8 name:1
550 #define SEP_SEMICOLON ;
552 struct intel_device_info
{
553 u32 display_mmio_offset
;
555 u8 num_sprites
[I915_MAX_PIPES
];
557 u8 ring_mask
; /* Rings supported by the HW */
558 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG
, SEP_SEMICOLON
);
559 /* Register offsets for the various display pipes and transcoders */
560 int pipe_offsets
[I915_MAX_TRANSCODERS
];
561 int trans_offsets
[I915_MAX_TRANSCODERS
];
562 int palette_offsets
[I915_MAX_PIPES
];
563 int cursor_offsets
[I915_MAX_PIPES
];
569 enum i915_cache_level
{
571 I915_CACHE_LLC
, /* also used for snoopable memory on non-LLC */
572 I915_CACHE_L3_LLC
, /* gen7+, L3 sits between the domain specifc
573 caches, eg sampler/render caches, and the
574 large Last-Level-Cache. LLC is coherent with
575 the CPU, but L3 is only visible to the GPU. */
576 I915_CACHE_WT
, /* hsw:gt3e WriteThrough for scanouts */
579 struct i915_ctx_hang_stats
{
580 /* This context had batch pending when hang was declared */
581 unsigned batch_pending
;
583 /* This context had batch active when hang was declared */
584 unsigned batch_active
;
586 /* Time when this context was last blamed for a GPU reset */
587 unsigned long guilty_ts
;
589 /* This context is banned to submit more work */
593 /* This must match up with the value previously used for execbuf2.rsvd1. */
594 #define DEFAULT_CONTEXT_HANDLE 0
596 * struct intel_context - as the name implies, represents a context.
597 * @ref: reference count.
598 * @user_handle: userspace tracking identity for this context.
599 * @remap_slice: l3 row remapping information.
600 * @file_priv: filp associated with this context (NULL for global default
602 * @hang_stats: information about the role of this context in possible GPU
604 * @vm: virtual memory space used by this context.
605 * @legacy_hw_ctx: render context backing object and whether it is correctly
606 * initialized (legacy ring submission mechanism only).
607 * @link: link in the global list of contexts.
609 * Contexts are memory images used by the hardware to store copies of their
612 struct intel_context
{
616 struct drm_i915_file_private
*file_priv
;
617 struct i915_ctx_hang_stats hang_stats
;
618 struct i915_address_space
*vm
;
621 struct drm_i915_gem_object
*rcs_state
;
625 struct list_head link
;
635 struct drm_mm_node compressed_fb
;
636 struct drm_mm_node
*compressed_llb
;
638 struct intel_fbc_work
{
639 struct delayed_work work
;
640 struct drm_crtc
*crtc
;
641 struct drm_framebuffer
*fb
;
645 FBC_OK
, /* FBC is enabled */
646 FBC_UNSUPPORTED
, /* FBC is not supported by this chipset */
647 FBC_NO_OUTPUT
, /* no outputs enabled to compress */
648 FBC_STOLEN_TOO_SMALL
, /* not enough space for buffers */
649 FBC_UNSUPPORTED_MODE
, /* interlace or doublescanned mode */
650 FBC_MODE_TOO_LARGE
, /* mode too large for compression */
651 FBC_BAD_PLANE
, /* fbc not supported on plane */
652 FBC_NOT_TILED
, /* buffer not tiled */
653 FBC_MULTIPLE_PIPES
, /* more than one pipe active */
655 FBC_CHIP_DEFAULT
, /* disabled by default on this chip */
660 struct intel_connector
*connector
;
668 struct intel_dp
*enabled
;
670 struct delayed_work work
;
671 unsigned busy_frontbuffer_bits
;
675 PCH_NONE
= 0, /* No PCH present */
676 PCH_IBX
, /* Ibexpeak PCH */
677 PCH_CPT
, /* Cougarpoint PCH */
678 PCH_LPT
, /* Lynxpoint PCH */
682 enum intel_sbi_destination
{
687 #define QUIRK_PIPEA_FORCE (1<<0)
688 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
689 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
690 #define QUIRK_BACKLIGHT_PRESENT (1<<3)
693 struct intel_fbc_work
;
696 struct i2c_adapter adapter
;
700 struct i2c_algo_bit_data bit_algo
;
701 struct drm_i915_private
*dev_priv
;
704 struct i915_suspend_saved_registers
{
725 u32 saveTRANS_HTOTAL_A
;
726 u32 saveTRANS_HBLANK_A
;
727 u32 saveTRANS_HSYNC_A
;
728 u32 saveTRANS_VTOTAL_A
;
729 u32 saveTRANS_VBLANK_A
;
730 u32 saveTRANS_VSYNC_A
;
738 u32 savePFIT_PGM_RATIOS
;
739 u32 saveBLC_HIST_CTL
;
741 u32 saveBLC_PWM_CTL2
;
742 u32 saveBLC_HIST_CTL_B
;
743 u32 saveBLC_CPU_PWM_CTL
;
744 u32 saveBLC_CPU_PWM_CTL2
;
757 u32 saveTRANS_HTOTAL_B
;
758 u32 saveTRANS_HBLANK_B
;
759 u32 saveTRANS_HSYNC_B
;
760 u32 saveTRANS_VTOTAL_B
;
761 u32 saveTRANS_VBLANK_B
;
762 u32 saveTRANS_VSYNC_B
;
776 u32 savePP_ON_DELAYS
;
777 u32 savePP_OFF_DELAYS
;
785 u32 savePFIT_CONTROL
;
786 u32 save_palette_a
[256];
787 u32 save_palette_b
[256];
798 u32 saveCACHE_MODE_0
;
799 u32 saveMI_ARB_STATE
;
810 uint64_t saveFENCE
[I915_MAX_NUM_FENCES
];
821 u32 savePIPEA_GMCH_DATA_M
;
822 u32 savePIPEB_GMCH_DATA_M
;
823 u32 savePIPEA_GMCH_DATA_N
;
824 u32 savePIPEB_GMCH_DATA_N
;
825 u32 savePIPEA_DP_LINK_M
;
826 u32 savePIPEB_DP_LINK_M
;
827 u32 savePIPEA_DP_LINK_N
;
828 u32 savePIPEB_DP_LINK_N
;
839 u32 savePCH_DREF_CONTROL
;
840 u32 saveDISP_ARB_CTL
;
841 u32 savePIPEA_DATA_M1
;
842 u32 savePIPEA_DATA_N1
;
843 u32 savePIPEA_LINK_M1
;
844 u32 savePIPEA_LINK_N1
;
845 u32 savePIPEB_DATA_M1
;
846 u32 savePIPEB_DATA_N1
;
847 u32 savePIPEB_LINK_M1
;
848 u32 savePIPEB_LINK_N1
;
849 u32 saveMCHBAR_RENDER_STANDBY
;
850 u32 savePCH_PORT_HOTPLUG
;
853 struct vlv_s0ix_state
{
860 u32 lra_limits
[GEN7_LRA_LIMITS_REG_NUM
];
861 u32 media_max_req_count
;
862 u32 gfx_max_req_count
;
894 /* Display 1 CZ domain */
899 u32 gt_scratch
[GEN7_GT_SCRATCH_REG_NUM
];
901 /* GT SA CZ domain */
908 /* Display 2 CZ domain */
914 struct intel_rps_ei
{
920 struct intel_gen6_power_mgmt
{
921 /* work and pm_iir are protected by dev_priv->irq_lock */
922 struct work_struct work
;
925 /* Frequencies are stored in potentially platform dependent multiples.
926 * In other words, *_freq needs to be multiplied by X to be interesting.
927 * Soft limits are those which are used for the dynamic reclocking done
928 * by the driver (raise frequencies under heavy loads, and lower for
929 * lighter loads). Hard limits are those imposed by the hardware.
931 * A distinction is made for overclocking, which is never enabled by
932 * default, and is considered to be above the hard limit if it's
935 u8 cur_freq
; /* Current frequency (cached, may not == HW) */
936 u8 min_freq_softlimit
; /* Minimum frequency permitted by the driver */
937 u8 max_freq_softlimit
; /* Max frequency permitted by the driver */
938 u8 max_freq
; /* Maximum frequency, RP0 if not overclocking */
939 u8 min_freq
; /* AKA RPn. Minimum frequency */
940 u8 efficient_freq
; /* AKA RPe. Pre-determined balanced frequency */
941 u8 rp1_freq
; /* "less than" RP0 power/freqency */
942 u8 rp0_freq
; /* Non-overclocked max frequency. */
945 u32 ei_interrupt_count
;
948 enum { LOW_POWER
, BETWEEN
, HIGH_POWER
} power
;
951 struct delayed_work delayed_resume_work
;
953 /* manual wa residency calculations */
954 struct intel_rps_ei up_ei
, down_ei
;
957 * Protects RPS/RC6 register access and PCU communication.
958 * Must be taken after struct_mutex if nested.
960 struct mutex hw_lock
;
963 /* defined intel_pm.c */
964 extern spinlock_t mchdev_lock
;
966 struct intel_ilk_power_mgmt
{
974 unsigned long last_time1
;
975 unsigned long chipset_power
;
978 unsigned long gfx_power
;
984 struct drm_i915_gem_object
*pwrctx
;
985 struct drm_i915_gem_object
*renderctx
;
988 struct drm_i915_private
;
989 struct i915_power_well
;
991 struct i915_power_well_ops
{
993 * Synchronize the well's hw state to match the current sw state, for
994 * example enable/disable it based on the current refcount. Called
995 * during driver init and resume time, possibly after first calling
996 * the enable/disable handlers.
998 void (*sync_hw
)(struct drm_i915_private
*dev_priv
,
999 struct i915_power_well
*power_well
);
1001 * Enable the well and resources that depend on it (for example
1002 * interrupts located on the well). Called after the 0->1 refcount
1005 void (*enable
)(struct drm_i915_private
*dev_priv
,
1006 struct i915_power_well
*power_well
);
1008 * Disable the well and resources that depend on it. Called after
1009 * the 1->0 refcount transition.
1011 void (*disable
)(struct drm_i915_private
*dev_priv
,
1012 struct i915_power_well
*power_well
);
1013 /* Returns the hw enabled state. */
1014 bool (*is_enabled
)(struct drm_i915_private
*dev_priv
,
1015 struct i915_power_well
*power_well
);
1018 /* Power well structure for haswell */
1019 struct i915_power_well
{
1022 /* power well enable/disable usage count */
1024 /* cached hw enabled state */
1026 unsigned long domains
;
1028 const struct i915_power_well_ops
*ops
;
1031 struct i915_power_domains
{
1033 * Power wells needed for initialization at driver init and suspend
1034 * time are on. They are kept on until after the first modeset.
1038 int power_well_count
;
1041 int domain_use_count
[POWER_DOMAIN_NUM
];
1042 struct i915_power_well
*power_wells
;
1045 struct i915_dri1_state
{
1046 unsigned allow_batchbuffer
: 1;
1047 u32 __iomem
*gfx_hws_cpu_addr
;
1058 struct i915_ums_state
{
1060 * Flag if the X Server, and thus DRM, is not currently in
1061 * control of the device.
1063 * This is set between LeaveVT and EnterVT. It needs to be
1064 * replaced with a semaphore. It also needs to be
1065 * transitioned away from for kernel modesetting.
1070 #define MAX_L3_SLICES 2
1071 struct intel_l3_parity
{
1072 u32
*remap_info
[MAX_L3_SLICES
];
1073 struct work_struct error_work
;
1077 struct i915_gem_mm
{
1078 /** Memory allocator for GTT stolen memory */
1079 struct drm_mm stolen
;
1080 /** List of all objects in gtt_space. Used to restore gtt
1081 * mappings on resume */
1082 struct list_head bound_list
;
1084 * List of objects which are not bound to the GTT (thus
1085 * are idle and not used by the GPU) but still have
1086 * (presumably uncached) pages still attached.
1088 struct list_head unbound_list
;
1090 /** Usable portion of the GTT for GEM */
1091 unsigned long stolen_base
; /* limited to low memory (32-bit) */
1093 /** PPGTT used for aliasing the PPGTT with the GTT */
1094 struct i915_hw_ppgtt
*aliasing_ppgtt
;
1096 struct notifier_block oom_notifier
;
1097 struct shrinker shrinker
;
1098 bool shrinker_no_lock_stealing
;
1100 /** LRU list of objects with fence regs on them. */
1101 struct list_head fence_list
;
1104 * We leave the user IRQ off as much as possible,
1105 * but this means that requests will finish and never
1106 * be retired once the system goes idle. Set a timer to
1107 * fire periodically while the ring is running. When it
1108 * fires, go retire requests.
1110 struct delayed_work retire_work
;
1113 * When we detect an idle GPU, we want to turn on
1114 * powersaving features. So once we see that there
1115 * are no more requests outstanding and no more
1116 * arrive within a small period of time, we fire
1117 * off the idle_work.
1119 struct delayed_work idle_work
;
1122 * Are we in a non-interruptible section of code like
1128 * Is the GPU currently considered idle, or busy executing userspace
1129 * requests? Whilst idle, we attempt to power down the hardware and
1130 * display clocks. In order to reduce the effect on performance, there
1131 * is a slight delay before we do so.
1135 /* the indicator for dispatch video commands on two BSD rings */
1136 int bsd_ring_dispatch_index
;
1138 /** Bit 6 swizzling required for X tiling */
1139 uint32_t bit_6_swizzle_x
;
1140 /** Bit 6 swizzling required for Y tiling */
1141 uint32_t bit_6_swizzle_y
;
1143 /* accounting, useful for userland debugging */
1144 spinlock_t object_stat_lock
;
1145 size_t object_memory
;
1149 struct drm_i915_error_state_buf
{
1158 struct i915_error_state_file_priv
{
1159 struct drm_device
*dev
;
1160 struct drm_i915_error_state
*error
;
1163 struct i915_gpu_error
{
1164 /* For hangcheck timer */
1165 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1166 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1167 /* Hang gpu twice in this window and your context gets banned */
1168 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1170 struct timer_list hangcheck_timer
;
1172 /* For reset and error_state handling. */
1174 /* Protected by the above dev->gpu_error.lock. */
1175 struct drm_i915_error_state
*first_error
;
1176 struct work_struct work
;
1179 unsigned long missed_irq_rings
;
1182 * State variable controlling the reset flow and count
1184 * This is a counter which gets incremented when reset is triggered,
1185 * and again when reset has been handled. So odd values (lowest bit set)
1186 * means that reset is in progress and even values that
1187 * (reset_counter >> 1):th reset was successfully completed.
1189 * If reset is not completed succesfully, the I915_WEDGE bit is
1190 * set meaning that hardware is terminally sour and there is no
1191 * recovery. All waiters on the reset_queue will be woken when
1194 * This counter is used by the wait_seqno code to notice that reset
1195 * event happened and it needs to restart the entire ioctl (since most
1196 * likely the seqno it waited for won't ever signal anytime soon).
1198 * This is important for lock-free wait paths, where no contended lock
1199 * naturally enforces the correct ordering between the bail-out of the
1200 * waiter and the gpu reset work code.
1202 atomic_t reset_counter
;
1204 #define I915_RESET_IN_PROGRESS_FLAG 1
1205 #define I915_WEDGED (1 << 31)
1208 * Waitqueue to signal when the reset has completed. Used by clients
1209 * that wait for dev_priv->mm.wedged to settle.
1211 wait_queue_head_t reset_queue
;
1213 /* Userspace knobs for gpu hang simulation;
1214 * combines both a ring mask, and extra flags
1217 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1218 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1220 /* For missed irq/seqno simulation. */
1221 unsigned int test_irq_rings
;
1224 enum modeset_restore
{
1225 MODESET_ON_LID_OPEN
,
1230 struct ddi_vbt_port_info
{
1231 uint8_t hdmi_level_shift
;
1233 uint8_t supports_dvi
:1;
1234 uint8_t supports_hdmi
:1;
1235 uint8_t supports_dp
:1;
1238 enum drrs_support_type
{
1239 DRRS_NOT_SUPPORTED
= 0,
1240 STATIC_DRRS_SUPPORT
= 1,
1241 SEAMLESS_DRRS_SUPPORT
= 2
1244 struct intel_vbt_data
{
1245 struct drm_display_mode
*lfp_lvds_vbt_mode
; /* if any */
1246 struct drm_display_mode
*sdvo_lvds_vbt_mode
; /* if any */
1249 unsigned int int_tv_support
:1;
1250 unsigned int lvds_dither
:1;
1251 unsigned int lvds_vbt
:1;
1252 unsigned int int_crt_support
:1;
1253 unsigned int lvds_use_ssc
:1;
1254 unsigned int display_clock_mode
:1;
1255 unsigned int fdi_rx_polarity_inverted
:1;
1256 unsigned int has_mipi
:1;
1258 unsigned int bios_lvds_val
; /* initial [PCH_]LVDS reg val in VBIOS */
1260 enum drrs_support_type drrs_type
;
1265 int edp_preemphasis
;
1267 bool edp_initialized
;
1270 struct edp_power_seq edp_pps
;
1275 bool active_low_pwm
;
1276 u8 min_brightness
; /* min_brightness/255 of max */
1283 struct mipi_config
*config
;
1284 struct mipi_pps_data
*pps
;
1288 u8
*sequence
[MIPI_SEQ_MAX
];
1294 union child_device_config
*child_dev
;
1296 struct ddi_vbt_port_info ddi_port_info
[I915_MAX_PORTS
];
1299 enum intel_ddb_partitioning
{
1301 INTEL_DDB_PART_5_6
, /* IVB+ */
1304 struct intel_wm_level
{
1312 struct ilk_wm_values
{
1313 uint32_t wm_pipe
[3];
1315 uint32_t wm_lp_spr
[3];
1316 uint32_t wm_linetime
[3];
1318 enum intel_ddb_partitioning partitioning
;
1322 * This struct helps tracking the state needed for runtime PM, which puts the
1323 * device in PCI D3 state. Notice that when this happens, nothing on the
1324 * graphics device works, even register access, so we don't get interrupts nor
1327 * Every piece of our code that needs to actually touch the hardware needs to
1328 * either call intel_runtime_pm_get or call intel_display_power_get with the
1329 * appropriate power domain.
1331 * Our driver uses the autosuspend delay feature, which means we'll only really
1332 * suspend if we stay with zero refcount for a certain amount of time. The
1333 * default value is currently very conservative (see intel_init_runtime_pm), but
1334 * it can be changed with the standard runtime PM files from sysfs.
1336 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1337 * goes back to false exactly before we reenable the IRQs. We use this variable
1338 * to check if someone is trying to enable/disable IRQs while they're supposed
1339 * to be disabled. This shouldn't happen and we'll print some error messages in
1342 * For more, read the Documentation/power/runtime_pm.txt.
1344 struct i915_runtime_pm
{
1346 bool _irqs_disabled
;
1349 enum intel_pipe_crc_source
{
1350 INTEL_PIPE_CRC_SOURCE_NONE
,
1351 INTEL_PIPE_CRC_SOURCE_PLANE1
,
1352 INTEL_PIPE_CRC_SOURCE_PLANE2
,
1353 INTEL_PIPE_CRC_SOURCE_PF
,
1354 INTEL_PIPE_CRC_SOURCE_PIPE
,
1355 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1356 INTEL_PIPE_CRC_SOURCE_TV
,
1357 INTEL_PIPE_CRC_SOURCE_DP_B
,
1358 INTEL_PIPE_CRC_SOURCE_DP_C
,
1359 INTEL_PIPE_CRC_SOURCE_DP_D
,
1360 INTEL_PIPE_CRC_SOURCE_AUTO
,
1361 INTEL_PIPE_CRC_SOURCE_MAX
,
1364 struct intel_pipe_crc_entry
{
1369 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1370 struct intel_pipe_crc
{
1372 bool opened
; /* exclusive access to the result file */
1373 struct intel_pipe_crc_entry
*entries
;
1374 enum intel_pipe_crc_source source
;
1376 wait_queue_head_t wq
;
1379 struct i915_frontbuffer_tracking
{
1383 * Tracking bits for delayed frontbuffer flushing du to gpu activity or
1390 struct drm_i915_private
{
1391 struct drm_device
*dev
;
1392 struct kmem_cache
*slab
;
1394 const struct intel_device_info info
;
1396 int relative_constants_mode
;
1400 struct intel_uncore uncore
;
1402 struct intel_gmbus gmbus
[GMBUS_NUM_PORTS
];
1405 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1406 * controller on different i2c buses. */
1407 struct mutex gmbus_mutex
;
1410 * Base address of the gmbus and gpio block.
1412 uint32_t gpio_mmio_base
;
1414 /* MMIO base address for MIPI regs */
1415 uint32_t mipi_mmio_base
;
1417 wait_queue_head_t gmbus_wait_queue
;
1419 struct pci_dev
*bridge_dev
;
1420 struct intel_engine_cs ring
[I915_NUM_RINGS
];
1421 struct drm_i915_gem_object
*semaphore_obj
;
1422 uint32_t last_seqno
, next_seqno
;
1424 drm_dma_handle_t
*status_page_dmah
;
1425 struct resource mch_res
;
1427 /* protects the irq masks */
1428 spinlock_t irq_lock
;
1430 /* protects the mmio flip data */
1431 spinlock_t mmio_flip_lock
;
1433 bool display_irqs_enabled
;
1435 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1436 struct pm_qos_request pm_qos
;
1438 /* DPIO indirect register protection */
1439 struct mutex dpio_lock
;
1441 /** Cached value of IMR to avoid reads in updating the bitfield */
1444 u32 de_irq_mask
[I915_MAX_PIPES
];
1449 u32 pipestat_irq_mask
[I915_MAX_PIPES
];
1451 struct work_struct hotplug_work
;
1453 unsigned long hpd_last_jiffies
;
1458 HPD_MARK_DISABLED
= 2
1460 } hpd_stats
[HPD_NUM_PINS
];
1462 struct delayed_work hotplug_reenable_work
;
1464 struct i915_fbc fbc
;
1465 struct i915_drrs drrs
;
1466 struct intel_opregion opregion
;
1467 struct intel_vbt_data vbt
;
1470 struct intel_overlay
*overlay
;
1472 /* backlight registers and fields in struct intel_panel */
1473 spinlock_t backlight_lock
;
1476 bool no_aux_handshake
;
1478 struct drm_i915_fence_reg fence_regs
[I915_MAX_NUM_FENCES
]; /* assume 965 */
1479 int fence_reg_start
; /* 4 if userland hasn't ioctl'd us yet */
1480 int num_fence_regs
; /* 8 on pre-965, 16 otherwise */
1482 unsigned int fsb_freq
, mem_freq
, is_ddr3
;
1483 unsigned int vlv_cdclk_freq
;
1486 * wq - Driver workqueue for GEM.
1488 * NOTE: Work items scheduled here are not allowed to grab any modeset
1489 * locks, for otherwise the flushing done in the pageflip code will
1490 * result in deadlocks.
1492 struct workqueue_struct
*wq
;
1494 /* Display functions */
1495 struct drm_i915_display_funcs display
;
1497 /* PCH chipset type */
1498 enum intel_pch pch_type
;
1499 unsigned short pch_id
;
1501 unsigned long quirks
;
1503 enum modeset_restore modeset_restore
;
1504 struct mutex modeset_restore_lock
;
1506 struct list_head vm_list
; /* Global list of all address spaces */
1507 struct i915_gtt gtt
; /* VM representing the global address space */
1509 struct i915_gem_mm mm
;
1510 DECLARE_HASHTABLE(mm_structs
, 7);
1511 struct mutex mm_lock
;
1513 /* Kernel Modesetting */
1515 struct sdvo_device_mapping sdvo_mappings
[2];
1517 struct drm_crtc
*plane_to_crtc_mapping
[I915_MAX_PIPES
];
1518 struct drm_crtc
*pipe_to_crtc_mapping
[I915_MAX_PIPES
];
1519 wait_queue_head_t pending_flip_queue
;
1521 #ifdef CONFIG_DEBUG_FS
1522 struct intel_pipe_crc pipe_crc
[I915_MAX_PIPES
];
1525 int num_shared_dpll
;
1526 struct intel_shared_dpll shared_dplls
[I915_NUM_PLLS
];
1527 int dpio_phy_iosf_port
[I915_NUM_PHYS_VLV
];
1529 /* Reclocking support */
1530 bool render_reclock_avail
;
1531 bool lvds_downclock_avail
;
1532 /* indicates the reduced downclock for LVDS*/
1535 struct i915_frontbuffer_tracking fb_tracking
;
1539 bool mchbar_need_disable
;
1541 struct intel_l3_parity l3_parity
;
1543 /* Cannot be determined by PCIID. You must always read a register. */
1546 /* gen6+ rps state */
1547 struct intel_gen6_power_mgmt rps
;
1549 /* ilk-only ips/rps state. Everything in here is protected by the global
1550 * mchdev_lock in intel_pm.c */
1551 struct intel_ilk_power_mgmt ips
;
1553 struct i915_power_domains power_domains
;
1555 struct i915_psr psr
;
1557 struct i915_gpu_error gpu_error
;
1559 struct drm_i915_gem_object
*vlv_pctx
;
1561 #ifdef CONFIG_DRM_I915_FBDEV
1562 /* list of fbdev register on this device */
1563 struct intel_fbdev
*fbdev
;
1567 * The console may be contended at resume, but we don't
1568 * want it to block on it.
1570 struct work_struct console_resume_work
;
1572 struct drm_property
*broadcast_rgb_property
;
1573 struct drm_property
*force_audio_property
;
1575 uint32_t hw_context_size
;
1576 struct list_head context_list
;
1581 struct i915_suspend_saved_registers regfile
;
1582 struct vlv_s0ix_state vlv_s0ix_state
;
1586 * Raw watermark latency values:
1587 * in 0.1us units for WM0,
1588 * in 0.5us units for WM1+.
1591 uint16_t pri_latency
[5];
1593 uint16_t spr_latency
[5];
1595 uint16_t cur_latency
[5];
1597 /* current hardware state */
1598 struct ilk_wm_values hw
;
1601 struct i915_runtime_pm pm
;
1603 struct intel_digital_port
*hpd_irq_port
[I915_MAX_PORTS
];
1604 u32 long_hpd_port_mask
;
1605 u32 short_hpd_port_mask
;
1606 struct work_struct dig_port_work
;
1609 * if we get a HPD irq from DP and a HPD irq from non-DP
1610 * the non-DP HPD could block the workqueue on a mode config
1611 * mutex getting, that userspace may have taken. However
1612 * userspace is waiting on the DP workqueue to run which is
1613 * blocked behind the non-DP one.
1615 struct workqueue_struct
*dp_wq
;
1617 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1619 struct i915_dri1_state dri1
;
1620 /* Old ums support infrastructure, same warning applies. */
1621 struct i915_ums_state ums
;
1624 * NOTE: This is the dri1/ums dungeon, don't add stuff here. Your patch
1625 * will be rejected. Instead look for a better place.
1629 static inline struct drm_i915_private
*to_i915(const struct drm_device
*dev
)
1631 return dev
->dev_private
;
1634 /* Iterate over initialised rings */
1635 #define for_each_ring(ring__, dev_priv__, i__) \
1636 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1637 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1639 enum hdmi_force_audio
{
1640 HDMI_AUDIO_OFF_DVI
= -2, /* no aux data for HDMI-DVI converter */
1641 HDMI_AUDIO_OFF
, /* force turn off HDMI audio */
1642 HDMI_AUDIO_AUTO
, /* trust EDID */
1643 HDMI_AUDIO_ON
, /* force turn on HDMI audio */
1646 #define I915_GTT_OFFSET_NONE ((u32)-1)
1648 struct drm_i915_gem_object_ops
{
1649 /* Interface between the GEM object and its backing storage.
1650 * get_pages() is called once prior to the use of the associated set
1651 * of pages before to binding them into the GTT, and put_pages() is
1652 * called after we no longer need them. As we expect there to be
1653 * associated cost with migrating pages between the backing storage
1654 * and making them available for the GPU (e.g. clflush), we may hold
1655 * onto the pages after they are no longer referenced by the GPU
1656 * in case they may be used again shortly (for example migrating the
1657 * pages to a different memory domain within the GTT). put_pages()
1658 * will therefore most likely be called when the object itself is
1659 * being released or under memory pressure (where we attempt to
1660 * reap pages for the shrinker).
1662 int (*get_pages
)(struct drm_i915_gem_object
*);
1663 void (*put_pages
)(struct drm_i915_gem_object
*);
1664 int (*dmabuf_export
)(struct drm_i915_gem_object
*);
1665 void (*release
)(struct drm_i915_gem_object
*);
1669 * Frontbuffer tracking bits. Set in obj->frontbuffer_bits while a gem bo is
1670 * considered to be the frontbuffer for the given plane interface-vise. This
1671 * doesn't mean that the hw necessarily already scans it out, but that any
1672 * rendering (by the cpu or gpu) will land in the frontbuffer eventually.
1674 * We have one bit per pipe and per scanout plane type.
1676 #define INTEL_FRONTBUFFER_BITS_PER_PIPE 4
1677 #define INTEL_FRONTBUFFER_BITS \
1678 (INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES)
1679 #define INTEL_FRONTBUFFER_PRIMARY(pipe) \
1680 (1 << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1681 #define INTEL_FRONTBUFFER_CURSOR(pipe) \
1682 (1 << (1 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1683 #define INTEL_FRONTBUFFER_SPRITE(pipe) \
1684 (1 << (2 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1685 #define INTEL_FRONTBUFFER_OVERLAY(pipe) \
1686 (1 << (3 +(INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe))))
1687 #define INTEL_FRONTBUFFER_ALL_MASK(pipe) \
1688 (0xf << (INTEL_FRONTBUFFER_BITS_PER_PIPE * (pipe)))
1690 struct drm_i915_gem_object
{
1691 struct drm_gem_object base
;
1693 const struct drm_i915_gem_object_ops
*ops
;
1695 /** List of VMAs backed by this object */
1696 struct list_head vma_list
;
1698 /** Stolen memory for this object, instead of being backed by shmem. */
1699 struct drm_mm_node
*stolen
;
1700 struct list_head global_list
;
1702 struct list_head ring_list
;
1703 /** Used in execbuf to temporarily hold a ref */
1704 struct list_head obj_exec_link
;
1707 * This is set if the object is on the active lists (has pending
1708 * rendering and so a non-zero seqno), and is not set if it i s on
1709 * inactive (ready to be unbound) list.
1711 unsigned int active
:1;
1714 * This is set if the object has been written to since last bound
1717 unsigned int dirty
:1;
1720 * Fence register bits (if any) for this object. Will be set
1721 * as needed when mapped into the GTT.
1722 * Protected by dev->struct_mutex.
1724 signed int fence_reg
:I915_MAX_NUM_FENCE_BITS
;
1727 * Advice: are the backing pages purgeable?
1729 unsigned int madv
:2;
1732 * Current tiling mode for the object.
1734 unsigned int tiling_mode
:2;
1736 * Whether the tiling parameters for the currently associated fence
1737 * register have changed. Note that for the purposes of tracking
1738 * tiling changes we also treat the unfenced register, the register
1739 * slot that the object occupies whilst it executes a fenced
1740 * command (such as BLT on gen2/3), as a "fence".
1742 unsigned int fence_dirty
:1;
1745 * Is the object at the current location in the gtt mappable and
1746 * fenceable? Used to avoid costly recalculations.
1748 unsigned int map_and_fenceable
:1;
1751 * Whether the current gtt mapping needs to be mappable (and isn't just
1752 * mappable by accident). Track pin and fault separate for a more
1753 * accurate mappable working set.
1755 unsigned int fault_mappable
:1;
1756 unsigned int pin_mappable
:1;
1757 unsigned int pin_display
:1;
1760 * Is the object to be mapped as read-only to the GPU
1761 * Only honoured if hardware has relevant pte bit
1763 unsigned long gt_ro
:1;
1766 * Is the GPU currently using a fence to access this buffer,
1768 unsigned int pending_fenced_gpu_access
:1;
1769 unsigned int fenced_gpu_access
:1;
1771 unsigned int cache_level
:3;
1773 unsigned int has_aliasing_ppgtt_mapping
:1;
1774 unsigned int has_global_gtt_mapping
:1;
1775 unsigned int has_dma_mapping
:1;
1777 unsigned int frontbuffer_bits
:INTEL_FRONTBUFFER_BITS
;
1779 struct sg_table
*pages
;
1780 int pages_pin_count
;
1782 /* prime dma-buf support */
1783 void *dma_buf_vmapping
;
1786 struct intel_engine_cs
*ring
;
1788 /** Breadcrumb of last rendering to the buffer. */
1789 uint32_t last_read_seqno
;
1790 uint32_t last_write_seqno
;
1791 /** Breadcrumb of last fenced GPU access to the buffer. */
1792 uint32_t last_fenced_seqno
;
1794 /** Current tiling stride for the object, if it's tiled. */
1797 /** References from framebuffers, locks out tiling changes. */
1798 unsigned long framebuffer_references
;
1800 /** Record of address bit 17 of each page at last unbind. */
1801 unsigned long *bit_17
;
1803 /** User space pin count and filp owning the pin */
1804 unsigned long user_pin_count
;
1805 struct drm_file
*pin_filp
;
1807 /** for phy allocated objects */
1808 drm_dma_handle_t
*phys_handle
;
1811 struct i915_gem_userptr
{
1813 unsigned read_only
:1;
1814 unsigned workers
:4;
1815 #define I915_GEM_USERPTR_MAX_WORKERS 15
1817 struct i915_mm_struct
*mm
;
1818 struct i915_mmu_object
*mmu_object
;
1819 struct work_struct
*work
;
1823 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1825 void i915_gem_track_fb(struct drm_i915_gem_object
*old
,
1826 struct drm_i915_gem_object
*new,
1827 unsigned frontbuffer_bits
);
1830 * Request queue structure.
1832 * The request queue allows us to note sequence numbers that have been emitted
1833 * and may be associated with active buffers to be retired.
1835 * By keeping this list, we can avoid having to do questionable
1836 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1837 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1839 struct drm_i915_gem_request
{
1840 /** On Which ring this request was generated */
1841 struct intel_engine_cs
*ring
;
1843 /** GEM sequence number associated with this request. */
1846 /** Position in the ringbuffer of the start of the request */
1849 /** Position in the ringbuffer of the end of the request */
1852 /** Context related to this request */
1853 struct intel_context
*ctx
;
1855 /** Batch buffer related to this request if any */
1856 struct drm_i915_gem_object
*batch_obj
;
1858 /** Time at which this request was emitted, in jiffies. */
1859 unsigned long emitted_jiffies
;
1861 /** global list entry for this request */
1862 struct list_head list
;
1864 struct drm_i915_file_private
*file_priv
;
1865 /** file_priv list entry for this request */
1866 struct list_head client_list
;
1869 struct drm_i915_file_private
{
1870 struct drm_i915_private
*dev_priv
;
1871 struct drm_file
*file
;
1875 struct list_head request_list
;
1876 struct delayed_work idle_work
;
1878 struct idr context_idr
;
1880 atomic_t rps_wait_boost
;
1881 struct intel_engine_cs
*bsd_ring
;
1885 * A command that requires special handling by the command parser.
1887 struct drm_i915_cmd_descriptor
{
1889 * Flags describing how the command parser processes the command.
1891 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1892 * a length mask if not set
1893 * CMD_DESC_SKIP: The command is allowed but does not follow the
1894 * standard length encoding for the opcode range in
1896 * CMD_DESC_REJECT: The command is never allowed
1897 * CMD_DESC_REGISTER: The command should be checked against the
1898 * register whitelist for the appropriate ring
1899 * CMD_DESC_MASTER: The command is allowed if the submitting process
1903 #define CMD_DESC_FIXED (1<<0)
1904 #define CMD_DESC_SKIP (1<<1)
1905 #define CMD_DESC_REJECT (1<<2)
1906 #define CMD_DESC_REGISTER (1<<3)
1907 #define CMD_DESC_BITMASK (1<<4)
1908 #define CMD_DESC_MASTER (1<<5)
1911 * The command's unique identification bits and the bitmask to get them.
1912 * This isn't strictly the opcode field as defined in the spec and may
1913 * also include type, subtype, and/or subop fields.
1921 * The command's length. The command is either fixed length (i.e. does
1922 * not include a length field) or has a length field mask. The flag
1923 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1924 * a length mask. All command entries in a command table must include
1925 * length information.
1933 * Describes where to find a register address in the command to check
1934 * against the ring's register whitelist. Only valid if flags has the
1935 * CMD_DESC_REGISTER bit set.
1942 #define MAX_CMD_DESC_BITMASKS 3
1944 * Describes command checks where a particular dword is masked and
1945 * compared against an expected value. If the command does not match
1946 * the expected value, the parser rejects it. Only valid if flags has
1947 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1950 * If the check specifies a non-zero condition_mask then the parser
1951 * only performs the check when the bits specified by condition_mask
1958 u32 condition_offset
;
1960 } bits
[MAX_CMD_DESC_BITMASKS
];
1964 * A table of commands requiring special handling by the command parser.
1966 * Each ring has an array of tables. Each table consists of an array of command
1967 * descriptors, which must be sorted with command opcodes in ascending order.
1969 struct drm_i915_cmd_table
{
1970 const struct drm_i915_cmd_descriptor
*table
;
1974 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1976 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1977 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1978 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1979 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1980 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1981 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1982 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1983 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1984 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1985 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1986 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1987 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1988 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1989 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1990 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1991 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1992 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1993 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1994 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1995 (dev)->pdev->device == 0x0152 || \
1996 (dev)->pdev->device == 0x015a)
1997 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1998 (dev)->pdev->device == 0x0106 || \
1999 (dev)->pdev->device == 0x010A)
2000 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
2001 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2002 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
2003 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
2004 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
2005 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
2006 ((dev)->pdev->device & 0xFF00) == 0x0C00)
2007 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
2008 (((dev)->pdev->device & 0xf) == 0x2 || \
2009 ((dev)->pdev->device & 0xf) == 0x6 || \
2010 ((dev)->pdev->device & 0xf) == 0xe))
2011 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
2012 ((dev)->pdev->device & 0xFF00) == 0x0A00)
2013 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
2014 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
2015 ((dev)->pdev->device & 0x00F0) == 0x0020)
2016 /* ULX machines are also considered ULT. */
2017 #define IS_HSW_ULX(dev) ((dev)->pdev->device == 0x0A0E || \
2018 (dev)->pdev->device == 0x0A1E)
2019 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
2022 * The genX designation typically refers to the render engine, so render
2023 * capability related checks should use IS_GEN, while display and other checks
2024 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
2027 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
2028 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
2029 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
2030 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
2031 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
2032 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
2033 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
2035 #define RENDER_RING (1<<RCS)
2036 #define BSD_RING (1<<VCS)
2037 #define BLT_RING (1<<BCS)
2038 #define VEBOX_RING (1<<VECS)
2039 #define BSD2_RING (1<<VCS2)
2040 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
2041 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
2042 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
2043 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
2044 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
2045 #define HAS_WT(dev) ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && \
2046 to_i915(dev)->ellc_size)
2047 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
2049 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
2050 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6)
2051 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_GEN8(dev))
2052 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
2053 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
2055 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
2056 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
2058 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
2059 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
2061 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
2062 * even when in MSI mode. This results in spurious interrupt warnings if the
2063 * legacy irq no. is shared with another device. The kernel then disables that
2064 * interrupt source and so prevents the other device from working properly.
2066 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2067 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
2069 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
2070 * rows, which changed the alignment requirements and fence programming.
2072 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
2074 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
2075 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
2076 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
2077 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
2078 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
2080 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
2081 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
2082 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
2084 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
2086 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
2087 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
2088 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
2089 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
2090 IS_BROADWELL(dev) || IS_VALLEYVIEW(dev))
2092 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
2093 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
2094 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
2095 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
2096 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
2097 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
2099 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
2100 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
2101 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
2102 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
2103 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
2104 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
2106 #define HAS_GMCH_DISPLAY(dev) (INTEL_INFO(dev)->gen < 5 || IS_VALLEYVIEW(dev))
2108 /* DPF == dynamic parity feature */
2109 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
2110 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
2112 #define GT_FREQUENCY_MULTIPLIER 50
2114 #include "i915_trace.h"
2116 extern const struct drm_ioctl_desc i915_ioctls
[];
2117 extern int i915_max_ioctl
;
2119 extern int i915_suspend(struct drm_device
*dev
, pm_message_t state
);
2120 extern int i915_resume(struct drm_device
*dev
);
2121 extern int i915_master_create(struct drm_device
*dev
, struct drm_master
*master
);
2122 extern void i915_master_destroy(struct drm_device
*dev
, struct drm_master
*master
);
2125 struct i915_params
{
2127 int panel_ignore_lid
;
2128 unsigned int powersave
;
2130 unsigned int lvds_downclock
;
2131 int lvds_channel_mode
;
2133 int vbt_sdvo_panel_type
;
2138 unsigned int preliminary_hw_support
;
2139 int disable_power_well
;
2141 int invert_brightness
;
2142 int enable_cmd_parser
;
2143 /* leave bools at the end to not create holes */
2144 bool enable_hangcheck
;
2146 bool prefault_disable
;
2148 bool disable_display
;
2149 bool disable_vtd_wa
;
2153 extern struct i915_params i915 __read_mostly
;
2156 void i915_update_dri1_breadcrumb(struct drm_device
*dev
);
2157 extern void i915_kernel_lost_context(struct drm_device
* dev
);
2158 extern int i915_driver_load(struct drm_device
*, unsigned long flags
);
2159 extern int i915_driver_unload(struct drm_device
*);
2160 extern int i915_driver_open(struct drm_device
*dev
, struct drm_file
*file
);
2161 extern void i915_driver_lastclose(struct drm_device
* dev
);
2162 extern void i915_driver_preclose(struct drm_device
*dev
,
2163 struct drm_file
*file
);
2164 extern void i915_driver_postclose(struct drm_device
*dev
,
2165 struct drm_file
*file
);
2166 extern int i915_driver_device_is_agp(struct drm_device
* dev
);
2167 #ifdef CONFIG_COMPAT
2168 extern long i915_compat_ioctl(struct file
*filp
, unsigned int cmd
,
2171 extern int i915_emit_box(struct drm_device
*dev
,
2172 struct drm_clip_rect
*box
,
2174 extern int intel_gpu_reset(struct drm_device
*dev
);
2175 extern int i915_reset(struct drm_device
*dev
);
2176 extern unsigned long i915_chipset_val(struct drm_i915_private
*dev_priv
);
2177 extern unsigned long i915_mch_val(struct drm_i915_private
*dev_priv
);
2178 extern unsigned long i915_gfx_val(struct drm_i915_private
*dev_priv
);
2179 extern void i915_update_gfx_val(struct drm_i915_private
*dev_priv
);
2180 int vlv_force_gfx_clock(struct drm_i915_private
*dev_priv
, bool on
);
2181 void intel_hpd_cancel_work(struct drm_i915_private
*dev_priv
);
2183 extern void intel_console_resume(struct work_struct
*work
);
2186 void i915_queue_hangcheck(struct drm_device
*dev
);
2188 void i915_handle_error(struct drm_device
*dev
, bool wedged
,
2189 const char *fmt
, ...);
2191 void gen6_set_pm_mask(struct drm_i915_private
*dev_priv
, u32 pm_iir
,
2193 extern void intel_irq_init(struct drm_device
*dev
);
2194 extern void intel_hpd_init(struct drm_device
*dev
);
2196 extern void intel_uncore_sanitize(struct drm_device
*dev
);
2197 extern void intel_uncore_early_sanitize(struct drm_device
*dev
,
2198 bool restore_forcewake
);
2199 extern void intel_uncore_init(struct drm_device
*dev
);
2200 extern void intel_uncore_check_errors(struct drm_device
*dev
);
2201 extern void intel_uncore_fini(struct drm_device
*dev
);
2202 extern void intel_uncore_forcewake_reset(struct drm_device
*dev
, bool restore
);
2205 i915_enable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2209 i915_disable_pipestat(struct drm_i915_private
*dev_priv
, enum pipe pipe
,
2212 void valleyview_enable_display_irqs(struct drm_i915_private
*dev_priv
);
2213 void valleyview_disable_display_irqs(struct drm_i915_private
*dev_priv
);
2216 int i915_gem_init_ioctl(struct drm_device
*dev
, void *data
,
2217 struct drm_file
*file_priv
);
2218 int i915_gem_create_ioctl(struct drm_device
*dev
, void *data
,
2219 struct drm_file
*file_priv
);
2220 int i915_gem_pread_ioctl(struct drm_device
*dev
, void *data
,
2221 struct drm_file
*file_priv
);
2222 int i915_gem_pwrite_ioctl(struct drm_device
*dev
, void *data
,
2223 struct drm_file
*file_priv
);
2224 int i915_gem_mmap_ioctl(struct drm_device
*dev
, void *data
,
2225 struct drm_file
*file_priv
);
2226 int i915_gem_mmap_gtt_ioctl(struct drm_device
*dev
, void *data
,
2227 struct drm_file
*file_priv
);
2228 int i915_gem_set_domain_ioctl(struct drm_device
*dev
, void *data
,
2229 struct drm_file
*file_priv
);
2230 int i915_gem_sw_finish_ioctl(struct drm_device
*dev
, void *data
,
2231 struct drm_file
*file_priv
);
2232 int i915_gem_execbuffer(struct drm_device
*dev
, void *data
,
2233 struct drm_file
*file_priv
);
2234 int i915_gem_execbuffer2(struct drm_device
*dev
, void *data
,
2235 struct drm_file
*file_priv
);
2236 int i915_gem_pin_ioctl(struct drm_device
*dev
, void *data
,
2237 struct drm_file
*file_priv
);
2238 int i915_gem_unpin_ioctl(struct drm_device
*dev
, void *data
,
2239 struct drm_file
*file_priv
);
2240 int i915_gem_busy_ioctl(struct drm_device
*dev
, void *data
,
2241 struct drm_file
*file_priv
);
2242 int i915_gem_get_caching_ioctl(struct drm_device
*dev
, void *data
,
2243 struct drm_file
*file
);
2244 int i915_gem_set_caching_ioctl(struct drm_device
*dev
, void *data
,
2245 struct drm_file
*file
);
2246 int i915_gem_throttle_ioctl(struct drm_device
*dev
, void *data
,
2247 struct drm_file
*file_priv
);
2248 int i915_gem_madvise_ioctl(struct drm_device
*dev
, void *data
,
2249 struct drm_file
*file_priv
);
2250 int i915_gem_entervt_ioctl(struct drm_device
*dev
, void *data
,
2251 struct drm_file
*file_priv
);
2252 int i915_gem_leavevt_ioctl(struct drm_device
*dev
, void *data
,
2253 struct drm_file
*file_priv
);
2254 int i915_gem_set_tiling(struct drm_device
*dev
, void *data
,
2255 struct drm_file
*file_priv
);
2256 int i915_gem_get_tiling(struct drm_device
*dev
, void *data
,
2257 struct drm_file
*file_priv
);
2258 int i915_gem_init_userptr(struct drm_device
*dev
);
2259 int i915_gem_userptr_ioctl(struct drm_device
*dev
, void *data
,
2260 struct drm_file
*file
);
2261 int i915_gem_get_aperture_ioctl(struct drm_device
*dev
, void *data
,
2262 struct drm_file
*file_priv
);
2263 int i915_gem_wait_ioctl(struct drm_device
*dev
, void *data
,
2264 struct drm_file
*file_priv
);
2265 void i915_gem_load(struct drm_device
*dev
);
2266 void *i915_gem_object_alloc(struct drm_device
*dev
);
2267 void i915_gem_object_free(struct drm_i915_gem_object
*obj
);
2268 void i915_gem_object_init(struct drm_i915_gem_object
*obj
,
2269 const struct drm_i915_gem_object_ops
*ops
);
2270 struct drm_i915_gem_object
*i915_gem_alloc_object(struct drm_device
*dev
,
2272 void i915_init_vm(struct drm_i915_private
*dev_priv
,
2273 struct i915_address_space
*vm
);
2274 void i915_gem_free_object(struct drm_gem_object
*obj
);
2275 void i915_gem_vma_destroy(struct i915_vma
*vma
);
2277 #define PIN_MAPPABLE 0x1
2278 #define PIN_NONBLOCK 0x2
2279 #define PIN_GLOBAL 0x4
2280 #define PIN_OFFSET_BIAS 0x8
2281 #define PIN_OFFSET_MASK (~4095)
2282 int __must_check
i915_gem_object_pin(struct drm_i915_gem_object
*obj
,
2283 struct i915_address_space
*vm
,
2286 int __must_check
i915_vma_unbind(struct i915_vma
*vma
);
2287 int i915_gem_object_put_pages(struct drm_i915_gem_object
*obj
);
2288 void i915_gem_release_all_mmaps(struct drm_i915_private
*dev_priv
);
2289 void i915_gem_release_mmap(struct drm_i915_gem_object
*obj
);
2290 void i915_gem_lastclose(struct drm_device
*dev
);
2292 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object
*obj
,
2293 int *needs_clflush
);
2295 int __must_check
i915_gem_object_get_pages(struct drm_i915_gem_object
*obj
);
2296 static inline struct page
*i915_gem_object_get_page(struct drm_i915_gem_object
*obj
, int n
)
2298 struct sg_page_iter sg_iter
;
2300 for_each_sg_page(obj
->pages
->sgl
, &sg_iter
, obj
->pages
->nents
, n
)
2301 return sg_page_iter_page(&sg_iter
);
2305 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object
*obj
)
2307 BUG_ON(obj
->pages
== NULL
);
2308 obj
->pages_pin_count
++;
2310 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object
*obj
)
2312 BUG_ON(obj
->pages_pin_count
== 0);
2313 obj
->pages_pin_count
--;
2316 int __must_check
i915_mutex_lock_interruptible(struct drm_device
*dev
);
2317 int i915_gem_object_sync(struct drm_i915_gem_object
*obj
,
2318 struct intel_engine_cs
*to
);
2319 void i915_vma_move_to_active(struct i915_vma
*vma
,
2320 struct intel_engine_cs
*ring
);
2321 int i915_gem_dumb_create(struct drm_file
*file_priv
,
2322 struct drm_device
*dev
,
2323 struct drm_mode_create_dumb
*args
);
2324 int i915_gem_mmap_gtt(struct drm_file
*file_priv
, struct drm_device
*dev
,
2325 uint32_t handle
, uint64_t *offset
);
2327 * Returns true if seq1 is later than seq2.
2330 i915_seqno_passed(uint32_t seq1
, uint32_t seq2
)
2332 return (int32_t)(seq1
- seq2
) >= 0;
2335 int __must_check
i915_gem_get_seqno(struct drm_device
*dev
, u32
*seqno
);
2336 int __must_check
i915_gem_set_seqno(struct drm_device
*dev
, u32 seqno
);
2337 int __must_check
i915_gem_object_get_fence(struct drm_i915_gem_object
*obj
);
2338 int __must_check
i915_gem_object_put_fence(struct drm_i915_gem_object
*obj
);
2340 bool i915_gem_object_pin_fence(struct drm_i915_gem_object
*obj
);
2341 void i915_gem_object_unpin_fence(struct drm_i915_gem_object
*obj
);
2343 struct drm_i915_gem_request
*
2344 i915_gem_find_active_request(struct intel_engine_cs
*ring
);
2346 bool i915_gem_retire_requests(struct drm_device
*dev
);
2347 void i915_gem_retire_requests_ring(struct intel_engine_cs
*ring
);
2348 int __must_check
i915_gem_check_wedge(struct i915_gpu_error
*error
,
2349 bool interruptible
);
2350 int __must_check
i915_gem_check_olr(struct intel_engine_cs
*ring
, u32 seqno
);
2352 static inline bool i915_reset_in_progress(struct i915_gpu_error
*error
)
2354 return unlikely(atomic_read(&error
->reset_counter
)
2355 & (I915_RESET_IN_PROGRESS_FLAG
| I915_WEDGED
));
2358 static inline bool i915_terminally_wedged(struct i915_gpu_error
*error
)
2360 return atomic_read(&error
->reset_counter
) & I915_WEDGED
;
2363 static inline u32
i915_reset_count(struct i915_gpu_error
*error
)
2365 return ((atomic_read(&error
->reset_counter
) & ~I915_WEDGED
) + 1) / 2;
2368 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private
*dev_priv
)
2370 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2371 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_BAN
;
2374 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private
*dev_priv
)
2376 return dev_priv
->gpu_error
.stop_rings
== 0 ||
2377 dev_priv
->gpu_error
.stop_rings
& I915_STOP_RING_ALLOW_WARN
;
2380 void i915_gem_reset(struct drm_device
*dev
);
2381 bool i915_gem_clflush_object(struct drm_i915_gem_object
*obj
, bool force
);
2382 int __must_check
i915_gem_object_finish_gpu(struct drm_i915_gem_object
*obj
);
2383 int __must_check
i915_gem_init(struct drm_device
*dev
);
2384 int __must_check
i915_gem_init_hw(struct drm_device
*dev
);
2385 int i915_gem_l3_remap(struct intel_engine_cs
*ring
, int slice
);
2386 void i915_gem_init_swizzling(struct drm_device
*dev
);
2387 void i915_gem_cleanup_ringbuffer(struct drm_device
*dev
);
2388 int __must_check
i915_gpu_idle(struct drm_device
*dev
);
2389 int __must_check
i915_gem_suspend(struct drm_device
*dev
);
2390 int __i915_add_request(struct intel_engine_cs
*ring
,
2391 struct drm_file
*file
,
2392 struct drm_i915_gem_object
*batch_obj
,
2394 #define i915_add_request(ring, seqno) \
2395 __i915_add_request(ring, NULL, NULL, seqno)
2396 int __must_check
i915_wait_seqno(struct intel_engine_cs
*ring
,
2398 int i915_gem_fault(struct vm_area_struct
*vma
, struct vm_fault
*vmf
);
2400 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object
*obj
,
2403 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object
*obj
, bool write
);
2405 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object
*obj
,
2407 struct intel_engine_cs
*pipelined
);
2408 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object
*obj
);
2409 int i915_gem_object_attach_phys(struct drm_i915_gem_object
*obj
,
2411 int i915_gem_open(struct drm_device
*dev
, struct drm_file
*file
);
2412 void i915_gem_release(struct drm_device
*dev
, struct drm_file
*file
);
2415 i915_gem_get_gtt_size(struct drm_device
*dev
, uint32_t size
, int tiling_mode
);
2417 i915_gem_get_gtt_alignment(struct drm_device
*dev
, uint32_t size
,
2418 int tiling_mode
, bool fenced
);
2420 int i915_gem_object_set_cache_level(struct drm_i915_gem_object
*obj
,
2421 enum i915_cache_level cache_level
);
2423 struct drm_gem_object
*i915_gem_prime_import(struct drm_device
*dev
,
2424 struct dma_buf
*dma_buf
);
2426 struct dma_buf
*i915_gem_prime_export(struct drm_device
*dev
,
2427 struct drm_gem_object
*gem_obj
, int flags
);
2429 void i915_gem_restore_fences(struct drm_device
*dev
);
2431 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object
*o
,
2432 struct i915_address_space
*vm
);
2433 bool i915_gem_obj_bound_any(struct drm_i915_gem_object
*o
);
2434 bool i915_gem_obj_bound(struct drm_i915_gem_object
*o
,
2435 struct i915_address_space
*vm
);
2436 unsigned long i915_gem_obj_size(struct drm_i915_gem_object
*o
,
2437 struct i915_address_space
*vm
);
2438 struct i915_vma
*i915_gem_obj_to_vma(struct drm_i915_gem_object
*obj
,
2439 struct i915_address_space
*vm
);
2441 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object
*obj
,
2442 struct i915_address_space
*vm
);
2444 struct i915_vma
*i915_gem_obj_to_ggtt(struct drm_i915_gem_object
*obj
);
2445 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object
*obj
) {
2446 struct i915_vma
*vma
;
2447 list_for_each_entry(vma
, &obj
->vma_list
, vma_link
)
2448 if (vma
->pin_count
> 0)
2453 /* Some GGTT VM helpers */
2454 #define obj_to_ggtt(obj) \
2455 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2456 static inline bool i915_is_ggtt(struct i915_address_space
*vm
)
2458 struct i915_address_space
*ggtt
=
2459 &((struct drm_i915_private
*)(vm
)->dev
->dev_private
)->gtt
.base
;
2463 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object
*obj
)
2465 return i915_gem_obj_bound(obj
, obj_to_ggtt(obj
));
2468 static inline unsigned long
2469 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object
*obj
)
2471 return i915_gem_obj_offset(obj
, obj_to_ggtt(obj
));
2474 static inline unsigned long
2475 i915_gem_obj_ggtt_size(struct drm_i915_gem_object
*obj
)
2477 return i915_gem_obj_size(obj
, obj_to_ggtt(obj
));
2480 static inline int __must_check
2481 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object
*obj
,
2485 return i915_gem_object_pin(obj
, obj_to_ggtt(obj
), alignment
, flags
| PIN_GLOBAL
);
2489 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object
*obj
)
2491 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj
));
2494 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object
*obj
);
2496 /* i915_gem_context.c */
2497 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2498 int __must_check
i915_gem_context_init(struct drm_device
*dev
);
2499 void i915_gem_context_fini(struct drm_device
*dev
);
2500 void i915_gem_context_reset(struct drm_device
*dev
);
2501 int i915_gem_context_open(struct drm_device
*dev
, struct drm_file
*file
);
2502 int i915_gem_context_enable(struct drm_i915_private
*dev_priv
);
2503 void i915_gem_context_close(struct drm_device
*dev
, struct drm_file
*file
);
2504 int i915_switch_context(struct intel_engine_cs
*ring
,
2505 struct intel_context
*to
);
2506 struct intel_context
*
2507 i915_gem_context_get(struct drm_i915_file_private
*file_priv
, u32 id
);
2508 void i915_gem_context_free(struct kref
*ctx_ref
);
2509 static inline void i915_gem_context_reference(struct intel_context
*ctx
)
2511 kref_get(&ctx
->ref
);
2514 static inline void i915_gem_context_unreference(struct intel_context
*ctx
)
2516 kref_put(&ctx
->ref
, i915_gem_context_free
);
2519 static inline bool i915_gem_context_is_default(const struct intel_context
*c
)
2521 return c
->user_handle
== DEFAULT_CONTEXT_HANDLE
;
2524 int i915_gem_context_create_ioctl(struct drm_device
*dev
, void *data
,
2525 struct drm_file
*file
);
2526 int i915_gem_context_destroy_ioctl(struct drm_device
*dev
, void *data
,
2527 struct drm_file
*file
);
2529 /* i915_gem_render_state.c */
2530 int i915_gem_render_state_init(struct intel_engine_cs
*ring
);
2531 /* i915_gem_evict.c */
2532 int __must_check
i915_gem_evict_something(struct drm_device
*dev
,
2533 struct i915_address_space
*vm
,
2536 unsigned cache_level
,
2537 unsigned long start
,
2540 int i915_gem_evict_vm(struct i915_address_space
*vm
, bool do_idle
);
2541 int i915_gem_evict_everything(struct drm_device
*dev
);
2543 /* belongs in i915_gem_gtt.h */
2544 static inline void i915_gem_chipset_flush(struct drm_device
*dev
)
2546 if (INTEL_INFO(dev
)->gen
< 6)
2547 intel_gtt_chipset_flush();
2550 /* i915_gem_stolen.c */
2551 int i915_gem_init_stolen(struct drm_device
*dev
);
2552 int i915_gem_stolen_setup_compression(struct drm_device
*dev
, int size
, int fb_cpp
);
2553 void i915_gem_stolen_cleanup_compression(struct drm_device
*dev
);
2554 void i915_gem_cleanup_stolen(struct drm_device
*dev
);
2555 struct drm_i915_gem_object
*
2556 i915_gem_object_create_stolen(struct drm_device
*dev
, u32 size
);
2557 struct drm_i915_gem_object
*
2558 i915_gem_object_create_stolen_for_preallocated(struct drm_device
*dev
,
2563 /* i915_gem_tiling.c */
2564 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object
*obj
)
2566 struct drm_i915_private
*dev_priv
= obj
->base
.dev
->dev_private
;
2568 return dev_priv
->mm
.bit_6_swizzle_x
== I915_BIT_6_SWIZZLE_9_10_17
&&
2569 obj
->tiling_mode
!= I915_TILING_NONE
;
2572 void i915_gem_detect_bit_6_swizzle(struct drm_device
*dev
);
2573 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2574 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object
*obj
);
2576 /* i915_gem_debug.c */
2578 int i915_verify_lists(struct drm_device
*dev
);
2580 #define i915_verify_lists(dev) 0
2583 /* i915_debugfs.c */
2584 int i915_debugfs_init(struct drm_minor
*minor
);
2585 void i915_debugfs_cleanup(struct drm_minor
*minor
);
2586 #ifdef CONFIG_DEBUG_FS
2587 void intel_display_crc_init(struct drm_device
*dev
);
2589 static inline void intel_display_crc_init(struct drm_device
*dev
) {}
2592 /* i915_gpu_error.c */
2594 void i915_error_printf(struct drm_i915_error_state_buf
*e
, const char *f
, ...);
2595 int i915_error_state_to_str(struct drm_i915_error_state_buf
*estr
,
2596 const struct i915_error_state_file_priv
*error
);
2597 int i915_error_state_buf_init(struct drm_i915_error_state_buf
*eb
,
2598 size_t count
, loff_t pos
);
2599 static inline void i915_error_state_buf_release(
2600 struct drm_i915_error_state_buf
*eb
)
2604 void i915_capture_error_state(struct drm_device
*dev
, bool wedge
,
2605 const char *error_msg
);
2606 void i915_error_state_get(struct drm_device
*dev
,
2607 struct i915_error_state_file_priv
*error_priv
);
2608 void i915_error_state_put(struct i915_error_state_file_priv
*error_priv
);
2609 void i915_destroy_error_state(struct drm_device
*dev
);
2611 void i915_get_extra_instdone(struct drm_device
*dev
, uint32_t *instdone
);
2612 const char *i915_cache_level_str(int type
);
2614 /* i915_cmd_parser.c */
2615 int i915_cmd_parser_get_version(void);
2616 int i915_cmd_parser_init_ring(struct intel_engine_cs
*ring
);
2617 void i915_cmd_parser_fini_ring(struct intel_engine_cs
*ring
);
2618 bool i915_needs_cmd_parser(struct intel_engine_cs
*ring
);
2619 int i915_parse_cmds(struct intel_engine_cs
*ring
,
2620 struct drm_i915_gem_object
*batch_obj
,
2621 u32 batch_start_offset
,
2624 /* i915_suspend.c */
2625 extern int i915_save_state(struct drm_device
*dev
);
2626 extern int i915_restore_state(struct drm_device
*dev
);
2629 void i915_save_display_reg(struct drm_device
*dev
);
2630 void i915_restore_display_reg(struct drm_device
*dev
);
2633 void i915_setup_sysfs(struct drm_device
*dev_priv
);
2634 void i915_teardown_sysfs(struct drm_device
*dev_priv
);
2637 extern int intel_setup_gmbus(struct drm_device
*dev
);
2638 extern void intel_teardown_gmbus(struct drm_device
*dev
);
2639 static inline bool intel_gmbus_is_port_valid(unsigned port
)
2641 return (port
>= GMBUS_PORT_SSC
&& port
<= GMBUS_PORT_DPD
);
2644 extern struct i2c_adapter
*intel_gmbus_get_adapter(
2645 struct drm_i915_private
*dev_priv
, unsigned port
);
2646 extern void intel_gmbus_set_speed(struct i2c_adapter
*adapter
, int speed
);
2647 extern void intel_gmbus_force_bit(struct i2c_adapter
*adapter
, bool force_bit
);
2648 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter
*adapter
)
2650 return container_of(adapter
, struct intel_gmbus
, adapter
)->force_bit
;
2652 extern void intel_i2c_reset(struct drm_device
*dev
);
2654 /* intel_opregion.c */
2655 struct intel_encoder
;
2657 extern int intel_opregion_setup(struct drm_device
*dev
);
2658 extern void intel_opregion_init(struct drm_device
*dev
);
2659 extern void intel_opregion_fini(struct drm_device
*dev
);
2660 extern void intel_opregion_asle_intr(struct drm_device
*dev
);
2661 extern int intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
,
2663 extern int intel_opregion_notify_adapter(struct drm_device
*dev
,
2666 static inline int intel_opregion_setup(struct drm_device
*dev
) { return 0; }
2667 static inline void intel_opregion_init(struct drm_device
*dev
) { return; }
2668 static inline void intel_opregion_fini(struct drm_device
*dev
) { return; }
2669 static inline void intel_opregion_asle_intr(struct drm_device
*dev
) { return; }
2671 intel_opregion_notify_encoder(struct intel_encoder
*intel_encoder
, bool enable
)
2676 intel_opregion_notify_adapter(struct drm_device
*dev
, pci_power_t state
)
2684 extern void intel_register_dsm_handler(void);
2685 extern void intel_unregister_dsm_handler(void);
2687 static inline void intel_register_dsm_handler(void) { return; }
2688 static inline void intel_unregister_dsm_handler(void) { return; }
2689 #endif /* CONFIG_ACPI */
2692 extern void intel_modeset_init_hw(struct drm_device
*dev
);
2693 extern void intel_modeset_suspend_hw(struct drm_device
*dev
);
2694 extern void intel_modeset_init(struct drm_device
*dev
);
2695 extern void intel_modeset_gem_init(struct drm_device
*dev
);
2696 extern void intel_modeset_cleanup(struct drm_device
*dev
);
2697 extern void intel_connector_unregister(struct intel_connector
*);
2698 extern int intel_modeset_vga_set_state(struct drm_device
*dev
, bool state
);
2699 extern void intel_modeset_setup_hw_state(struct drm_device
*dev
,
2700 bool force_restore
);
2701 extern void i915_redisable_vga(struct drm_device
*dev
);
2702 extern void i915_redisable_vga_power_on(struct drm_device
*dev
);
2703 extern bool intel_fbc_enabled(struct drm_device
*dev
);
2704 extern void intel_disable_fbc(struct drm_device
*dev
);
2705 extern bool ironlake_set_drps(struct drm_device
*dev
, u8 val
);
2706 extern void intel_init_pch_refclk(struct drm_device
*dev
);
2707 extern void gen6_set_rps(struct drm_device
*dev
, u8 val
);
2708 extern void valleyview_set_rps(struct drm_device
*dev
, u8 val
);
2709 extern void intel_set_memory_cxsr(struct drm_i915_private
*dev_priv
,
2711 extern void intel_detect_pch(struct drm_device
*dev
);
2712 extern int intel_trans_dp_port_sel(struct drm_crtc
*crtc
);
2713 extern int intel_enable_rc6(const struct drm_device
*dev
);
2715 extern bool i915_semaphore_is_enabled(struct drm_device
*dev
);
2716 int i915_reg_read_ioctl(struct drm_device
*dev
, void *data
,
2717 struct drm_file
*file
);
2718 int i915_get_reset_stats_ioctl(struct drm_device
*dev
, void *data
,
2719 struct drm_file
*file
);
2721 void intel_notify_mmio_flip(struct intel_engine_cs
*ring
);
2724 extern struct intel_overlay_error_state
*intel_overlay_capture_error_state(struct drm_device
*dev
);
2725 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf
*e
,
2726 struct intel_overlay_error_state
*error
);
2728 extern struct intel_display_error_state
*intel_display_capture_error_state(struct drm_device
*dev
);
2729 extern void intel_display_print_error_state(struct drm_i915_error_state_buf
*e
,
2730 struct drm_device
*dev
,
2731 struct intel_display_error_state
*error
);
2733 /* On SNB platform, before reading ring registers forcewake bit
2734 * must be set to prevent GT core from power down and stale values being
2737 void gen6_gt_force_wake_get(struct drm_i915_private
*dev_priv
, int fw_engine
);
2738 void gen6_gt_force_wake_put(struct drm_i915_private
*dev_priv
, int fw_engine
);
2739 void assert_force_wake_inactive(struct drm_i915_private
*dev_priv
);
2741 int sandybridge_pcode_read(struct drm_i915_private
*dev_priv
, u8 mbox
, u32
*val
);
2742 int sandybridge_pcode_write(struct drm_i915_private
*dev_priv
, u8 mbox
, u32 val
);
2744 /* intel_sideband.c */
2745 u32
vlv_punit_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2746 void vlv_punit_write(struct drm_i915_private
*dev_priv
, u8 addr
, u32 val
);
2747 u32
vlv_nc_read(struct drm_i915_private
*dev_priv
, u8 addr
);
2748 u32
vlv_gpio_nc_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2749 void vlv_gpio_nc_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2750 u32
vlv_cck_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2751 void vlv_cck_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2752 u32
vlv_ccu_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2753 void vlv_ccu_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2754 u32
vlv_bunit_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2755 void vlv_bunit_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2756 u32
vlv_gps_core_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2757 void vlv_gps_core_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2758 u32
vlv_dpio_read(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
);
2759 void vlv_dpio_write(struct drm_i915_private
*dev_priv
, enum pipe pipe
, int reg
, u32 val
);
2760 u32
intel_sbi_read(struct drm_i915_private
*dev_priv
, u16 reg
,
2761 enum intel_sbi_destination destination
);
2762 void intel_sbi_write(struct drm_i915_private
*dev_priv
, u16 reg
, u32 value
,
2763 enum intel_sbi_destination destination
);
2764 u32
vlv_flisdsi_read(struct drm_i915_private
*dev_priv
, u32 reg
);
2765 void vlv_flisdsi_write(struct drm_i915_private
*dev_priv
, u32 reg
, u32 val
);
2767 int vlv_gpu_freq(struct drm_i915_private
*dev_priv
, int val
);
2768 int vlv_freq_opcode(struct drm_i915_private
*dev_priv
, int val
);
2770 #define FORCEWAKE_RENDER (1 << 0)
2771 #define FORCEWAKE_MEDIA (1 << 1)
2772 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2775 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2776 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2778 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2779 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2780 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2781 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2783 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2784 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2785 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2786 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2788 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2789 * will be implemented using 2 32-bit writes in an arbitrary order with
2790 * an arbitrary delay between them. This can cause the hardware to
2791 * act upon the intermediate value, possibly leading to corruption and
2792 * machine death. You have been warned.
2794 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2795 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2797 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2798 u32 upper = I915_READ(upper_reg); \
2799 u32 lower = I915_READ(lower_reg); \
2800 u32 tmp = I915_READ(upper_reg); \
2801 if (upper != tmp) { \
2803 lower = I915_READ(lower_reg); \
2804 WARN_ON(I915_READ(upper_reg) != upper); \
2806 (u64)upper << 32 | lower; })
2808 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2809 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2811 /* "Broadcast RGB" property */
2812 #define INTEL_BROADCAST_RGB_AUTO 0
2813 #define INTEL_BROADCAST_RGB_FULL 1
2814 #define INTEL_BROADCAST_RGB_LIMITED 2
2816 static inline uint32_t i915_vgacntrl_reg(struct drm_device
*dev
)
2818 if (IS_VALLEYVIEW(dev
))
2819 return VLV_VGACNTRL
;
2820 else if (INTEL_INFO(dev
)->gen
>= 5)
2821 return CPU_VGACNTRL
;
2826 static inline void __user
*to_user_ptr(u64 address
)
2828 return (void __user
*)(uintptr_t)address
;
2831 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m
)
2833 unsigned long j
= msecs_to_jiffies(m
);
2835 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2838 static inline unsigned long
2839 timespec_to_jiffies_timeout(const struct timespec
*value
)
2841 unsigned long j
= timespec_to_jiffies(value
);
2843 return min_t(unsigned long, MAX_JIFFY_OFFSET
, j
+ 1);
2847 * If you need to wait X milliseconds between events A and B, but event B
2848 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2849 * when event A happened, then just before event B you call this function and
2850 * pass the timestamp as the first argument, and X as the second argument.
2853 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies
, int to_wait_ms
)
2855 unsigned long target_jiffies
, tmp_jiffies
, remaining_jiffies
;
2858 * Don't re-read the value of "jiffies" every time since it may change
2859 * behind our back and break the math.
2861 tmp_jiffies
= jiffies
;
2862 target_jiffies
= timestamp_jiffies
+
2863 msecs_to_jiffies_timeout(to_wait_ms
);
2865 if (time_after(target_jiffies
, tmp_jiffies
)) {
2866 remaining_jiffies
= target_jiffies
- tmp_jiffies
;
2867 while (remaining_jiffies
)
2869 schedule_timeout_uninterruptible(remaining_jiffies
);