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drm/i915:Initialize the second BSD ring on BDW GT3 machine
[deliverable/linux.git] / drivers / gpu / drm / i915 / i915_drv.h
1 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*-
2 */
3 /*
4 *
5 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
6 * All Rights Reserved.
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the
10 * "Software"), to deal in the Software without restriction, including
11 * without limitation the rights to use, copy, modify, merge, publish,
12 * distribute, sub license, and/or sell copies of the Software, and to
13 * permit persons to whom the Software is furnished to do so, subject to
14 * the following conditions:
15 *
16 * The above copyright notice and this permission notice (including the
17 * next paragraph) shall be included in all copies or substantial portions
18 * of the Software.
19 *
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
21 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
22 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
23 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
24 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
25 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
26 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 *
28 */
29
30 #ifndef _I915_DRV_H_
31 #define _I915_DRV_H_
32
33 #include <uapi/drm/i915_drm.h>
34
35 #include "i915_reg.h"
36 #include "intel_bios.h"
37 #include "intel_ringbuffer.h"
38 #include "i915_gem_gtt.h"
39 #include <linux/io-mapping.h>
40 #include <linux/i2c.h>
41 #include <linux/i2c-algo-bit.h>
42 #include <drm/intel-gtt.h>
43 #include <linux/backlight.h>
44 #include <linux/intel-iommu.h>
45 #include <linux/kref.h>
46 #include <linux/pm_qos.h>
47
48 /* General customization:
49 */
50
51 #define DRIVER_AUTHOR "Tungsten Graphics, Inc."
52
53 #define DRIVER_NAME "i915"
54 #define DRIVER_DESC "Intel Graphics"
55 #define DRIVER_DATE "20080730"
56
57 enum pipe {
58 INVALID_PIPE = -1,
59 PIPE_A = 0,
60 PIPE_B,
61 PIPE_C,
62 _PIPE_EDP,
63 I915_MAX_PIPES = _PIPE_EDP
64 };
65 #define pipe_name(p) ((p) + 'A')
66
67 enum transcoder {
68 TRANSCODER_A = 0,
69 TRANSCODER_B,
70 TRANSCODER_C,
71 TRANSCODER_EDP,
72 I915_MAX_TRANSCODERS
73 };
74 #define transcoder_name(t) ((t) + 'A')
75
76 enum plane {
77 PLANE_A = 0,
78 PLANE_B,
79 PLANE_C,
80 };
81 #define plane_name(p) ((p) + 'A')
82
83 #define sprite_name(p, s) ((p) * INTEL_INFO(dev)->num_sprites[(p)] + (s) + 'A')
84
85 enum port {
86 PORT_A = 0,
87 PORT_B,
88 PORT_C,
89 PORT_D,
90 PORT_E,
91 I915_MAX_PORTS
92 };
93 #define port_name(p) ((p) + 'A')
94
95 #define I915_NUM_PHYS_VLV 1
96
97 enum dpio_channel {
98 DPIO_CH0,
99 DPIO_CH1
100 };
101
102 enum dpio_phy {
103 DPIO_PHY0,
104 DPIO_PHY1
105 };
106
107 enum intel_display_power_domain {
108 POWER_DOMAIN_PIPE_A,
109 POWER_DOMAIN_PIPE_B,
110 POWER_DOMAIN_PIPE_C,
111 POWER_DOMAIN_PIPE_A_PANEL_FITTER,
112 POWER_DOMAIN_PIPE_B_PANEL_FITTER,
113 POWER_DOMAIN_PIPE_C_PANEL_FITTER,
114 POWER_DOMAIN_TRANSCODER_A,
115 POWER_DOMAIN_TRANSCODER_B,
116 POWER_DOMAIN_TRANSCODER_C,
117 POWER_DOMAIN_TRANSCODER_EDP,
118 POWER_DOMAIN_PORT_DDI_A_2_LANES,
119 POWER_DOMAIN_PORT_DDI_A_4_LANES,
120 POWER_DOMAIN_PORT_DDI_B_2_LANES,
121 POWER_DOMAIN_PORT_DDI_B_4_LANES,
122 POWER_DOMAIN_PORT_DDI_C_2_LANES,
123 POWER_DOMAIN_PORT_DDI_C_4_LANES,
124 POWER_DOMAIN_PORT_DDI_D_2_LANES,
125 POWER_DOMAIN_PORT_DDI_D_4_LANES,
126 POWER_DOMAIN_PORT_DSI,
127 POWER_DOMAIN_PORT_CRT,
128 POWER_DOMAIN_PORT_OTHER,
129 POWER_DOMAIN_VGA,
130 POWER_DOMAIN_AUDIO,
131 POWER_DOMAIN_INIT,
132
133 POWER_DOMAIN_NUM,
134 };
135
136 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
137 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
138 ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
139 #define POWER_DOMAIN_TRANSCODER(tran) \
140 ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
141 (tran) + POWER_DOMAIN_TRANSCODER_A)
142
143 enum hpd_pin {
144 HPD_NONE = 0,
145 HPD_PORT_A = HPD_NONE, /* PORT_A is internal */
146 HPD_TV = HPD_NONE, /* TV is known to be unreliable */
147 HPD_CRT,
148 HPD_SDVO_B,
149 HPD_SDVO_C,
150 HPD_PORT_B,
151 HPD_PORT_C,
152 HPD_PORT_D,
153 HPD_NUM_PINS
154 };
155
156 #define I915_GEM_GPU_DOMAINS \
157 (I915_GEM_DOMAIN_RENDER | \
158 I915_GEM_DOMAIN_SAMPLER | \
159 I915_GEM_DOMAIN_COMMAND | \
160 I915_GEM_DOMAIN_INSTRUCTION | \
161 I915_GEM_DOMAIN_VERTEX)
162
163 #define for_each_pipe(p) for ((p) = 0; (p) < INTEL_INFO(dev)->num_pipes; (p)++)
164 #define for_each_sprite(p, s) for ((s) = 0; (s) < INTEL_INFO(dev)->num_sprites[(p)]; (s)++)
165
166 #define for_each_encoder_on_crtc(dev, __crtc, intel_encoder) \
167 list_for_each_entry((intel_encoder), &(dev)->mode_config.encoder_list, base.head) \
168 if ((intel_encoder)->base.crtc == (__crtc))
169
170 #define for_each_connector_on_encoder(dev, __encoder, intel_connector) \
171 list_for_each_entry((intel_connector), &(dev)->mode_config.connector_list, base.head) \
172 if ((intel_connector)->base.encoder == (__encoder))
173
174 struct drm_i915_private;
175
176 enum intel_dpll_id {
177 DPLL_ID_PRIVATE = -1, /* non-shared dpll in use */
178 /* real shared dpll ids must be >= 0 */
179 DPLL_ID_PCH_PLL_A,
180 DPLL_ID_PCH_PLL_B,
181 };
182 #define I915_NUM_PLLS 2
183
184 struct intel_dpll_hw_state {
185 uint32_t dpll;
186 uint32_t dpll_md;
187 uint32_t fp0;
188 uint32_t fp1;
189 };
190
191 struct intel_shared_dpll {
192 int refcount; /* count of number of CRTCs sharing this PLL */
193 int active; /* count of number of active CRTCs (i.e. DPMS on) */
194 bool on; /* is the PLL actually active? Disabled during modeset */
195 const char *name;
196 /* should match the index in the dev_priv->shared_dplls array */
197 enum intel_dpll_id id;
198 struct intel_dpll_hw_state hw_state;
199 void (*mode_set)(struct drm_i915_private *dev_priv,
200 struct intel_shared_dpll *pll);
201 void (*enable)(struct drm_i915_private *dev_priv,
202 struct intel_shared_dpll *pll);
203 void (*disable)(struct drm_i915_private *dev_priv,
204 struct intel_shared_dpll *pll);
205 bool (*get_hw_state)(struct drm_i915_private *dev_priv,
206 struct intel_shared_dpll *pll,
207 struct intel_dpll_hw_state *hw_state);
208 };
209
210 /* Used by dp and fdi links */
211 struct intel_link_m_n {
212 uint32_t tu;
213 uint32_t gmch_m;
214 uint32_t gmch_n;
215 uint32_t link_m;
216 uint32_t link_n;
217 };
218
219 void intel_link_compute_m_n(int bpp, int nlanes,
220 int pixel_clock, int link_clock,
221 struct intel_link_m_n *m_n);
222
223 struct intel_ddi_plls {
224 int spll_refcount;
225 int wrpll1_refcount;
226 int wrpll2_refcount;
227 };
228
229 /* Interface history:
230 *
231 * 1.1: Original.
232 * 1.2: Add Power Management
233 * 1.3: Add vblank support
234 * 1.4: Fix cmdbuffer path, add heap destroy
235 * 1.5: Add vblank pipe configuration
236 * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
237 * - Support vertical blank on secondary display pipe
238 */
239 #define DRIVER_MAJOR 1
240 #define DRIVER_MINOR 6
241 #define DRIVER_PATCHLEVEL 0
242
243 #define WATCH_LISTS 0
244 #define WATCH_GTT 0
245
246 #define I915_GEM_PHYS_CURSOR_0 1
247 #define I915_GEM_PHYS_CURSOR_1 2
248 #define I915_GEM_PHYS_OVERLAY_REGS 3
249 #define I915_MAX_PHYS_OBJECT (I915_GEM_PHYS_OVERLAY_REGS)
250
251 struct drm_i915_gem_phys_object {
252 int id;
253 struct page **page_list;
254 drm_dma_handle_t *handle;
255 struct drm_i915_gem_object *cur_obj;
256 };
257
258 struct opregion_header;
259 struct opregion_acpi;
260 struct opregion_swsci;
261 struct opregion_asle;
262
263 struct intel_opregion {
264 struct opregion_header __iomem *header;
265 struct opregion_acpi __iomem *acpi;
266 struct opregion_swsci __iomem *swsci;
267 u32 swsci_gbda_sub_functions;
268 u32 swsci_sbcb_sub_functions;
269 struct opregion_asle __iomem *asle;
270 void __iomem *vbt;
271 u32 __iomem *lid_state;
272 struct work_struct asle_work;
273 };
274 #define OPREGION_SIZE (8*1024)
275
276 struct intel_overlay;
277 struct intel_overlay_error_state;
278
279 struct drm_i915_master_private {
280 drm_local_map_t *sarea;
281 struct _drm_i915_sarea *sarea_priv;
282 };
283 #define I915_FENCE_REG_NONE -1
284 #define I915_MAX_NUM_FENCES 32
285 /* 32 fences + sign bit for FENCE_REG_NONE */
286 #define I915_MAX_NUM_FENCE_BITS 6
287
288 struct drm_i915_fence_reg {
289 struct list_head lru_list;
290 struct drm_i915_gem_object *obj;
291 int pin_count;
292 };
293
294 struct sdvo_device_mapping {
295 u8 initialized;
296 u8 dvo_port;
297 u8 slave_addr;
298 u8 dvo_wiring;
299 u8 i2c_pin;
300 u8 ddc_pin;
301 };
302
303 struct intel_display_error_state;
304
305 struct drm_i915_error_state {
306 struct kref ref;
307 struct timeval time;
308
309 char error_msg[128];
310 u32 reset_count;
311 u32 suspend_count;
312
313 /* Generic register state */
314 u32 eir;
315 u32 pgtbl_er;
316 u32 ier;
317 u32 ccid;
318 u32 derrmr;
319 u32 forcewake;
320 u32 error; /* gen6+ */
321 u32 err_int; /* gen7 */
322 u32 done_reg;
323 u32 gac_eco;
324 u32 gam_ecochk;
325 u32 gab_ctl;
326 u32 gfx_mode;
327 u32 extra_instdone[I915_NUM_INSTDONE_REG];
328 u32 pipestat[I915_MAX_PIPES];
329 u64 fence[I915_MAX_NUM_FENCES];
330 struct intel_overlay_error_state *overlay;
331 struct intel_display_error_state *display;
332
333 struct drm_i915_error_ring {
334 bool valid;
335 /* Software tracked state */
336 bool waiting;
337 int hangcheck_score;
338 enum intel_ring_hangcheck_action hangcheck_action;
339 int num_requests;
340
341 /* our own tracking of ring head and tail */
342 u32 cpu_ring_head;
343 u32 cpu_ring_tail;
344
345 u32 semaphore_seqno[I915_NUM_RINGS - 1];
346
347 /* Register state */
348 u32 tail;
349 u32 head;
350 u32 ctl;
351 u32 hws;
352 u32 ipeir;
353 u32 ipehr;
354 u32 instdone;
355 u32 bbstate;
356 u32 instpm;
357 u32 instps;
358 u32 seqno;
359 u64 bbaddr;
360 u64 acthd;
361 u32 fault_reg;
362 u64 faddr;
363 u32 rc_psmi; /* sleep state */
364 u32 semaphore_mboxes[I915_NUM_RINGS - 1];
365
366 struct drm_i915_error_object {
367 int page_count;
368 u32 gtt_offset;
369 u32 *pages[0];
370 } *ringbuffer, *batchbuffer, *wa_batchbuffer, *ctx, *hws_page;
371
372 struct drm_i915_error_request {
373 long jiffies;
374 u32 seqno;
375 u32 tail;
376 } *requests;
377
378 struct {
379 u32 gfx_mode;
380 union {
381 u64 pdp[4];
382 u32 pp_dir_base;
383 };
384 } vm_info;
385
386 pid_t pid;
387 char comm[TASK_COMM_LEN];
388 } ring[I915_NUM_RINGS];
389 struct drm_i915_error_buffer {
390 u32 size;
391 u32 name;
392 u32 rseqno, wseqno;
393 u32 gtt_offset;
394 u32 read_domains;
395 u32 write_domain;
396 s32 fence_reg:I915_MAX_NUM_FENCE_BITS;
397 s32 pinned:2;
398 u32 tiling:2;
399 u32 dirty:1;
400 u32 purgeable:1;
401 s32 ring:4;
402 u32 cache_level:3;
403 } **active_bo, **pinned_bo;
404
405 u32 *active_bo_count, *pinned_bo_count;
406 };
407
408 struct intel_connector;
409 struct intel_crtc_config;
410 struct intel_plane_config;
411 struct intel_crtc;
412 struct intel_limit;
413 struct dpll;
414
415 struct drm_i915_display_funcs {
416 bool (*fbc_enabled)(struct drm_device *dev);
417 void (*enable_fbc)(struct drm_crtc *crtc);
418 void (*disable_fbc)(struct drm_device *dev);
419 int (*get_display_clock_speed)(struct drm_device *dev);
420 int (*get_fifo_size)(struct drm_device *dev, int plane);
421 /**
422 * find_dpll() - Find the best values for the PLL
423 * @limit: limits for the PLL
424 * @crtc: current CRTC
425 * @target: target frequency in kHz
426 * @refclk: reference clock frequency in kHz
427 * @match_clock: if provided, @best_clock P divider must
428 * match the P divider from @match_clock
429 * used for LVDS downclocking
430 * @best_clock: best PLL values found
431 *
432 * Returns true on success, false on failure.
433 */
434 bool (*find_dpll)(const struct intel_limit *limit,
435 struct drm_crtc *crtc,
436 int target, int refclk,
437 struct dpll *match_clock,
438 struct dpll *best_clock);
439 void (*update_wm)(struct drm_crtc *crtc);
440 void (*update_sprite_wm)(struct drm_plane *plane,
441 struct drm_crtc *crtc,
442 uint32_t sprite_width, int pixel_size,
443 bool enable, bool scaled);
444 void (*modeset_global_resources)(struct drm_device *dev);
445 /* Returns the active state of the crtc, and if the crtc is active,
446 * fills out the pipe-config with the hw state. */
447 bool (*get_pipe_config)(struct intel_crtc *,
448 struct intel_crtc_config *);
449 void (*get_plane_config)(struct intel_crtc *,
450 struct intel_plane_config *);
451 int (*crtc_mode_set)(struct drm_crtc *crtc,
452 int x, int y,
453 struct drm_framebuffer *old_fb);
454 void (*crtc_enable)(struct drm_crtc *crtc);
455 void (*crtc_disable)(struct drm_crtc *crtc);
456 void (*off)(struct drm_crtc *crtc);
457 void (*write_eld)(struct drm_connector *connector,
458 struct drm_crtc *crtc,
459 struct drm_display_mode *mode);
460 void (*fdi_link_train)(struct drm_crtc *crtc);
461 void (*init_clock_gating)(struct drm_device *dev);
462 int (*queue_flip)(struct drm_device *dev, struct drm_crtc *crtc,
463 struct drm_framebuffer *fb,
464 struct drm_i915_gem_object *obj,
465 uint32_t flags);
466 int (*update_primary_plane)(struct drm_crtc *crtc,
467 struct drm_framebuffer *fb,
468 int x, int y);
469 void (*hpd_irq_setup)(struct drm_device *dev);
470 /* clock updates for mode set */
471 /* cursor updates */
472 /* render clock increase/decrease */
473 /* display clock increase/decrease */
474 /* pll clock increase/decrease */
475
476 int (*setup_backlight)(struct intel_connector *connector);
477 uint32_t (*get_backlight)(struct intel_connector *connector);
478 void (*set_backlight)(struct intel_connector *connector,
479 uint32_t level);
480 void (*disable_backlight)(struct intel_connector *connector);
481 void (*enable_backlight)(struct intel_connector *connector);
482 };
483
484 struct intel_uncore_funcs {
485 void (*force_wake_get)(struct drm_i915_private *dev_priv,
486 int fw_engine);
487 void (*force_wake_put)(struct drm_i915_private *dev_priv,
488 int fw_engine);
489
490 uint8_t (*mmio_readb)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
491 uint16_t (*mmio_readw)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
492 uint32_t (*mmio_readl)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
493 uint64_t (*mmio_readq)(struct drm_i915_private *dev_priv, off_t offset, bool trace);
494
495 void (*mmio_writeb)(struct drm_i915_private *dev_priv, off_t offset,
496 uint8_t val, bool trace);
497 void (*mmio_writew)(struct drm_i915_private *dev_priv, off_t offset,
498 uint16_t val, bool trace);
499 void (*mmio_writel)(struct drm_i915_private *dev_priv, off_t offset,
500 uint32_t val, bool trace);
501 void (*mmio_writeq)(struct drm_i915_private *dev_priv, off_t offset,
502 uint64_t val, bool trace);
503 };
504
505 struct intel_uncore {
506 spinlock_t lock; /** lock is also taken in irq contexts. */
507
508 struct intel_uncore_funcs funcs;
509
510 unsigned fifo_count;
511 unsigned forcewake_count;
512
513 unsigned fw_rendercount;
514 unsigned fw_mediacount;
515
516 struct timer_list force_wake_timer;
517 };
518
519 #define DEV_INFO_FOR_EACH_FLAG(func, sep) \
520 func(is_mobile) sep \
521 func(is_i85x) sep \
522 func(is_i915g) sep \
523 func(is_i945gm) sep \
524 func(is_g33) sep \
525 func(need_gfx_hws) sep \
526 func(is_g4x) sep \
527 func(is_pineview) sep \
528 func(is_broadwater) sep \
529 func(is_crestline) sep \
530 func(is_ivybridge) sep \
531 func(is_valleyview) sep \
532 func(is_haswell) sep \
533 func(is_preliminary) sep \
534 func(has_fbc) sep \
535 func(has_pipe_cxsr) sep \
536 func(has_hotplug) sep \
537 func(cursor_needs_physical) sep \
538 func(has_overlay) sep \
539 func(overlay_needs_physical) sep \
540 func(supports_tv) sep \
541 func(has_llc) sep \
542 func(has_ddi) sep \
543 func(has_fpga_dbg)
544
545 #define DEFINE_FLAG(name) u8 name:1
546 #define SEP_SEMICOLON ;
547
548 struct intel_device_info {
549 u32 display_mmio_offset;
550 u8 num_pipes:3;
551 u8 num_sprites[I915_MAX_PIPES];
552 u8 gen;
553 u8 ring_mask; /* Rings supported by the HW */
554 DEV_INFO_FOR_EACH_FLAG(DEFINE_FLAG, SEP_SEMICOLON);
555 /* Register offsets for the various display pipes and transcoders */
556 int pipe_offsets[I915_MAX_TRANSCODERS];
557 int trans_offsets[I915_MAX_TRANSCODERS];
558 int dpll_offsets[I915_MAX_PIPES];
559 int dpll_md_offsets[I915_MAX_PIPES];
560 int palette_offsets[I915_MAX_PIPES];
561 };
562
563 #undef DEFINE_FLAG
564 #undef SEP_SEMICOLON
565
566 enum i915_cache_level {
567 I915_CACHE_NONE = 0,
568 I915_CACHE_LLC, /* also used for snoopable memory on non-LLC */
569 I915_CACHE_L3_LLC, /* gen7+, L3 sits between the domain specifc
570 caches, eg sampler/render caches, and the
571 large Last-Level-Cache. LLC is coherent with
572 the CPU, but L3 is only visible to the GPU. */
573 I915_CACHE_WT, /* hsw:gt3e WriteThrough for scanouts */
574 };
575
576 struct i915_ctx_hang_stats {
577 /* This context had batch pending when hang was declared */
578 unsigned batch_pending;
579
580 /* This context had batch active when hang was declared */
581 unsigned batch_active;
582
583 /* Time when this context was last blamed for a GPU reset */
584 unsigned long guilty_ts;
585
586 /* This context is banned to submit more work */
587 bool banned;
588 };
589
590 /* This must match up with the value previously used for execbuf2.rsvd1. */
591 #define DEFAULT_CONTEXT_ID 0
592 struct i915_hw_context {
593 struct kref ref;
594 int id;
595 bool is_initialized;
596 uint8_t remap_slice;
597 struct drm_i915_file_private *file_priv;
598 struct intel_ring_buffer *last_ring;
599 struct drm_i915_gem_object *obj;
600 struct i915_ctx_hang_stats hang_stats;
601 struct i915_address_space *vm;
602
603 struct list_head link;
604 };
605
606 struct i915_fbc {
607 unsigned long size;
608 unsigned int fb_id;
609 enum plane plane;
610 int y;
611
612 struct drm_mm_node *compressed_fb;
613 struct drm_mm_node *compressed_llb;
614
615 struct intel_fbc_work {
616 struct delayed_work work;
617 struct drm_crtc *crtc;
618 struct drm_framebuffer *fb;
619 } *fbc_work;
620
621 enum no_fbc_reason {
622 FBC_OK, /* FBC is enabled */
623 FBC_UNSUPPORTED, /* FBC is not supported by this chipset */
624 FBC_NO_OUTPUT, /* no outputs enabled to compress */
625 FBC_STOLEN_TOO_SMALL, /* not enough space for buffers */
626 FBC_UNSUPPORTED_MODE, /* interlace or doublescanned mode */
627 FBC_MODE_TOO_LARGE, /* mode too large for compression */
628 FBC_BAD_PLANE, /* fbc not supported on plane */
629 FBC_NOT_TILED, /* buffer not tiled */
630 FBC_MULTIPLE_PIPES, /* more than one pipe active */
631 FBC_MODULE_PARAM,
632 FBC_CHIP_DEFAULT, /* disabled by default on this chip */
633 } no_fbc_reason;
634 };
635
636 struct i915_drrs {
637 struct intel_connector *connector;
638 };
639
640 struct i915_psr {
641 bool sink_support;
642 bool source_ok;
643 };
644
645 enum intel_pch {
646 PCH_NONE = 0, /* No PCH present */
647 PCH_IBX, /* Ibexpeak PCH */
648 PCH_CPT, /* Cougarpoint PCH */
649 PCH_LPT, /* Lynxpoint PCH */
650 PCH_NOP,
651 };
652
653 enum intel_sbi_destination {
654 SBI_ICLK,
655 SBI_MPHY,
656 };
657
658 #define QUIRK_PIPEA_FORCE (1<<0)
659 #define QUIRK_LVDS_SSC_DISABLE (1<<1)
660 #define QUIRK_INVERT_BRIGHTNESS (1<<2)
661
662 struct intel_fbdev;
663 struct intel_fbc_work;
664
665 struct intel_gmbus {
666 struct i2c_adapter adapter;
667 u32 force_bit;
668 u32 reg0;
669 u32 gpio_reg;
670 struct i2c_algo_bit_data bit_algo;
671 struct drm_i915_private *dev_priv;
672 };
673
674 struct i915_suspend_saved_registers {
675 u8 saveLBB;
676 u32 saveDSPACNTR;
677 u32 saveDSPBCNTR;
678 u32 saveDSPARB;
679 u32 savePIPEACONF;
680 u32 savePIPEBCONF;
681 u32 savePIPEASRC;
682 u32 savePIPEBSRC;
683 u32 saveFPA0;
684 u32 saveFPA1;
685 u32 saveDPLL_A;
686 u32 saveDPLL_A_MD;
687 u32 saveHTOTAL_A;
688 u32 saveHBLANK_A;
689 u32 saveHSYNC_A;
690 u32 saveVTOTAL_A;
691 u32 saveVBLANK_A;
692 u32 saveVSYNC_A;
693 u32 saveBCLRPAT_A;
694 u32 saveTRANSACONF;
695 u32 saveTRANS_HTOTAL_A;
696 u32 saveTRANS_HBLANK_A;
697 u32 saveTRANS_HSYNC_A;
698 u32 saveTRANS_VTOTAL_A;
699 u32 saveTRANS_VBLANK_A;
700 u32 saveTRANS_VSYNC_A;
701 u32 savePIPEASTAT;
702 u32 saveDSPASTRIDE;
703 u32 saveDSPASIZE;
704 u32 saveDSPAPOS;
705 u32 saveDSPAADDR;
706 u32 saveDSPASURF;
707 u32 saveDSPATILEOFF;
708 u32 savePFIT_PGM_RATIOS;
709 u32 saveBLC_HIST_CTL;
710 u32 saveBLC_PWM_CTL;
711 u32 saveBLC_PWM_CTL2;
712 u32 saveBLC_HIST_CTL_B;
713 u32 saveBLC_CPU_PWM_CTL;
714 u32 saveBLC_CPU_PWM_CTL2;
715 u32 saveFPB0;
716 u32 saveFPB1;
717 u32 saveDPLL_B;
718 u32 saveDPLL_B_MD;
719 u32 saveHTOTAL_B;
720 u32 saveHBLANK_B;
721 u32 saveHSYNC_B;
722 u32 saveVTOTAL_B;
723 u32 saveVBLANK_B;
724 u32 saveVSYNC_B;
725 u32 saveBCLRPAT_B;
726 u32 saveTRANSBCONF;
727 u32 saveTRANS_HTOTAL_B;
728 u32 saveTRANS_HBLANK_B;
729 u32 saveTRANS_HSYNC_B;
730 u32 saveTRANS_VTOTAL_B;
731 u32 saveTRANS_VBLANK_B;
732 u32 saveTRANS_VSYNC_B;
733 u32 savePIPEBSTAT;
734 u32 saveDSPBSTRIDE;
735 u32 saveDSPBSIZE;
736 u32 saveDSPBPOS;
737 u32 saveDSPBADDR;
738 u32 saveDSPBSURF;
739 u32 saveDSPBTILEOFF;
740 u32 saveVGA0;
741 u32 saveVGA1;
742 u32 saveVGA_PD;
743 u32 saveVGACNTRL;
744 u32 saveADPA;
745 u32 saveLVDS;
746 u32 savePP_ON_DELAYS;
747 u32 savePP_OFF_DELAYS;
748 u32 saveDVOA;
749 u32 saveDVOB;
750 u32 saveDVOC;
751 u32 savePP_ON;
752 u32 savePP_OFF;
753 u32 savePP_CONTROL;
754 u32 savePP_DIVISOR;
755 u32 savePFIT_CONTROL;
756 u32 save_palette_a[256];
757 u32 save_palette_b[256];
758 u32 saveFBC_CONTROL;
759 u32 saveIER;
760 u32 saveIIR;
761 u32 saveIMR;
762 u32 saveDEIER;
763 u32 saveDEIMR;
764 u32 saveGTIER;
765 u32 saveGTIMR;
766 u32 saveFDI_RXA_IMR;
767 u32 saveFDI_RXB_IMR;
768 u32 saveCACHE_MODE_0;
769 u32 saveMI_ARB_STATE;
770 u32 saveSWF0[16];
771 u32 saveSWF1[16];
772 u32 saveSWF2[3];
773 u8 saveMSR;
774 u8 saveSR[8];
775 u8 saveGR[25];
776 u8 saveAR_INDEX;
777 u8 saveAR[21];
778 u8 saveDACMASK;
779 u8 saveCR[37];
780 uint64_t saveFENCE[I915_MAX_NUM_FENCES];
781 u32 saveCURACNTR;
782 u32 saveCURAPOS;
783 u32 saveCURABASE;
784 u32 saveCURBCNTR;
785 u32 saveCURBPOS;
786 u32 saveCURBBASE;
787 u32 saveCURSIZE;
788 u32 saveDP_B;
789 u32 saveDP_C;
790 u32 saveDP_D;
791 u32 savePIPEA_GMCH_DATA_M;
792 u32 savePIPEB_GMCH_DATA_M;
793 u32 savePIPEA_GMCH_DATA_N;
794 u32 savePIPEB_GMCH_DATA_N;
795 u32 savePIPEA_DP_LINK_M;
796 u32 savePIPEB_DP_LINK_M;
797 u32 savePIPEA_DP_LINK_N;
798 u32 savePIPEB_DP_LINK_N;
799 u32 saveFDI_RXA_CTL;
800 u32 saveFDI_TXA_CTL;
801 u32 saveFDI_RXB_CTL;
802 u32 saveFDI_TXB_CTL;
803 u32 savePFA_CTL_1;
804 u32 savePFB_CTL_1;
805 u32 savePFA_WIN_SZ;
806 u32 savePFB_WIN_SZ;
807 u32 savePFA_WIN_POS;
808 u32 savePFB_WIN_POS;
809 u32 savePCH_DREF_CONTROL;
810 u32 saveDISP_ARB_CTL;
811 u32 savePIPEA_DATA_M1;
812 u32 savePIPEA_DATA_N1;
813 u32 savePIPEA_LINK_M1;
814 u32 savePIPEA_LINK_N1;
815 u32 savePIPEB_DATA_M1;
816 u32 savePIPEB_DATA_N1;
817 u32 savePIPEB_LINK_M1;
818 u32 savePIPEB_LINK_N1;
819 u32 saveMCHBAR_RENDER_STANDBY;
820 u32 savePCH_PORT_HOTPLUG;
821 };
822
823 struct intel_gen6_power_mgmt {
824 /* work and pm_iir are protected by dev_priv->irq_lock */
825 struct work_struct work;
826 u32 pm_iir;
827
828 /* Frequencies are stored in potentially platform dependent multiples.
829 * In other words, *_freq needs to be multiplied by X to be interesting.
830 * Soft limits are those which are used for the dynamic reclocking done
831 * by the driver (raise frequencies under heavy loads, and lower for
832 * lighter loads). Hard limits are those imposed by the hardware.
833 *
834 * A distinction is made for overclocking, which is never enabled by
835 * default, and is considered to be above the hard limit if it's
836 * possible at all.
837 */
838 u8 cur_freq; /* Current frequency (cached, may not == HW) */
839 u8 min_freq_softlimit; /* Minimum frequency permitted by the driver */
840 u8 max_freq_softlimit; /* Max frequency permitted by the driver */
841 u8 max_freq; /* Maximum frequency, RP0 if not overclocking */
842 u8 min_freq; /* AKA RPn. Minimum frequency */
843 u8 efficient_freq; /* AKA RPe. Pre-determined balanced frequency */
844 u8 rp1_freq; /* "less than" RP0 power/freqency */
845 u8 rp0_freq; /* Non-overclocked max frequency. */
846
847 int last_adj;
848 enum { LOW_POWER, BETWEEN, HIGH_POWER } power;
849
850 bool enabled;
851 struct delayed_work delayed_resume_work;
852
853 /*
854 * Protects RPS/RC6 register access and PCU communication.
855 * Must be taken after struct_mutex if nested.
856 */
857 struct mutex hw_lock;
858 };
859
860 /* defined intel_pm.c */
861 extern spinlock_t mchdev_lock;
862
863 struct intel_ilk_power_mgmt {
864 u8 cur_delay;
865 u8 min_delay;
866 u8 max_delay;
867 u8 fmax;
868 u8 fstart;
869
870 u64 last_count1;
871 unsigned long last_time1;
872 unsigned long chipset_power;
873 u64 last_count2;
874 struct timespec last_time2;
875 unsigned long gfx_power;
876 u8 corr;
877
878 int c_m;
879 int r_t;
880
881 struct drm_i915_gem_object *pwrctx;
882 struct drm_i915_gem_object *renderctx;
883 };
884
885 struct drm_i915_private;
886 struct i915_power_well;
887
888 struct i915_power_well_ops {
889 /*
890 * Synchronize the well's hw state to match the current sw state, for
891 * example enable/disable it based on the current refcount. Called
892 * during driver init and resume time, possibly after first calling
893 * the enable/disable handlers.
894 */
895 void (*sync_hw)(struct drm_i915_private *dev_priv,
896 struct i915_power_well *power_well);
897 /*
898 * Enable the well and resources that depend on it (for example
899 * interrupts located on the well). Called after the 0->1 refcount
900 * transition.
901 */
902 void (*enable)(struct drm_i915_private *dev_priv,
903 struct i915_power_well *power_well);
904 /*
905 * Disable the well and resources that depend on it. Called after
906 * the 1->0 refcount transition.
907 */
908 void (*disable)(struct drm_i915_private *dev_priv,
909 struct i915_power_well *power_well);
910 /* Returns the hw enabled state. */
911 bool (*is_enabled)(struct drm_i915_private *dev_priv,
912 struct i915_power_well *power_well);
913 };
914
915 /* Power well structure for haswell */
916 struct i915_power_well {
917 const char *name;
918 bool always_on;
919 /* power well enable/disable usage count */
920 int count;
921 unsigned long domains;
922 unsigned long data;
923 const struct i915_power_well_ops *ops;
924 };
925
926 struct i915_power_domains {
927 /*
928 * Power wells needed for initialization at driver init and suspend
929 * time are on. They are kept on until after the first modeset.
930 */
931 bool init_power_on;
932 int power_well_count;
933
934 struct mutex lock;
935 int domain_use_count[POWER_DOMAIN_NUM];
936 struct i915_power_well *power_wells;
937 };
938
939 struct i915_dri1_state {
940 unsigned allow_batchbuffer : 1;
941 u32 __iomem *gfx_hws_cpu_addr;
942
943 unsigned int cpp;
944 int back_offset;
945 int front_offset;
946 int current_page;
947 int page_flipping;
948
949 uint32_t counter;
950 };
951
952 struct i915_ums_state {
953 /**
954 * Flag if the X Server, and thus DRM, is not currently in
955 * control of the device.
956 *
957 * This is set between LeaveVT and EnterVT. It needs to be
958 * replaced with a semaphore. It also needs to be
959 * transitioned away from for kernel modesetting.
960 */
961 int mm_suspended;
962 };
963
964 #define MAX_L3_SLICES 2
965 struct intel_l3_parity {
966 u32 *remap_info[MAX_L3_SLICES];
967 struct work_struct error_work;
968 int which_slice;
969 };
970
971 struct i915_gem_mm {
972 /** Memory allocator for GTT stolen memory */
973 struct drm_mm stolen;
974 /** List of all objects in gtt_space. Used to restore gtt
975 * mappings on resume */
976 struct list_head bound_list;
977 /**
978 * List of objects which are not bound to the GTT (thus
979 * are idle and not used by the GPU) but still have
980 * (presumably uncached) pages still attached.
981 */
982 struct list_head unbound_list;
983
984 /** Usable portion of the GTT for GEM */
985 unsigned long stolen_base; /* limited to low memory (32-bit) */
986
987 /** PPGTT used for aliasing the PPGTT with the GTT */
988 struct i915_hw_ppgtt *aliasing_ppgtt;
989
990 struct shrinker inactive_shrinker;
991 bool shrinker_no_lock_stealing;
992
993 /** LRU list of objects with fence regs on them. */
994 struct list_head fence_list;
995
996 /**
997 * We leave the user IRQ off as much as possible,
998 * but this means that requests will finish and never
999 * be retired once the system goes idle. Set a timer to
1000 * fire periodically while the ring is running. When it
1001 * fires, go retire requests.
1002 */
1003 struct delayed_work retire_work;
1004
1005 /**
1006 * When we detect an idle GPU, we want to turn on
1007 * powersaving features. So once we see that there
1008 * are no more requests outstanding and no more
1009 * arrive within a small period of time, we fire
1010 * off the idle_work.
1011 */
1012 struct delayed_work idle_work;
1013
1014 /**
1015 * Are we in a non-interruptible section of code like
1016 * modesetting?
1017 */
1018 bool interruptible;
1019
1020 /**
1021 * Is the GPU currently considered idle, or busy executing userspace
1022 * requests? Whilst idle, we attempt to power down the hardware and
1023 * display clocks. In order to reduce the effect on performance, there
1024 * is a slight delay before we do so.
1025 */
1026 bool busy;
1027
1028 /** Bit 6 swizzling required for X tiling */
1029 uint32_t bit_6_swizzle_x;
1030 /** Bit 6 swizzling required for Y tiling */
1031 uint32_t bit_6_swizzle_y;
1032
1033 /* storage for physical objects */
1034 struct drm_i915_gem_phys_object *phys_objs[I915_MAX_PHYS_OBJECT];
1035
1036 /* accounting, useful for userland debugging */
1037 spinlock_t object_stat_lock;
1038 size_t object_memory;
1039 u32 object_count;
1040 };
1041
1042 struct drm_i915_error_state_buf {
1043 unsigned bytes;
1044 unsigned size;
1045 int err;
1046 u8 *buf;
1047 loff_t start;
1048 loff_t pos;
1049 };
1050
1051 struct i915_error_state_file_priv {
1052 struct drm_device *dev;
1053 struct drm_i915_error_state *error;
1054 };
1055
1056 struct i915_gpu_error {
1057 /* For hangcheck timer */
1058 #define DRM_I915_HANGCHECK_PERIOD 1500 /* in ms */
1059 #define DRM_I915_HANGCHECK_JIFFIES msecs_to_jiffies(DRM_I915_HANGCHECK_PERIOD)
1060 /* Hang gpu twice in this window and your context gets banned */
1061 #define DRM_I915_CTX_BAN_PERIOD DIV_ROUND_UP(8*DRM_I915_HANGCHECK_PERIOD, 1000)
1062
1063 struct timer_list hangcheck_timer;
1064
1065 /* For reset and error_state handling. */
1066 spinlock_t lock;
1067 /* Protected by the above dev->gpu_error.lock. */
1068 struct drm_i915_error_state *first_error;
1069 struct work_struct work;
1070
1071
1072 unsigned long missed_irq_rings;
1073
1074 /**
1075 * State variable controlling the reset flow and count
1076 *
1077 * This is a counter which gets incremented when reset is triggered,
1078 * and again when reset has been handled. So odd values (lowest bit set)
1079 * means that reset is in progress and even values that
1080 * (reset_counter >> 1):th reset was successfully completed.
1081 *
1082 * If reset is not completed succesfully, the I915_WEDGE bit is
1083 * set meaning that hardware is terminally sour and there is no
1084 * recovery. All waiters on the reset_queue will be woken when
1085 * that happens.
1086 *
1087 * This counter is used by the wait_seqno code to notice that reset
1088 * event happened and it needs to restart the entire ioctl (since most
1089 * likely the seqno it waited for won't ever signal anytime soon).
1090 *
1091 * This is important for lock-free wait paths, where no contended lock
1092 * naturally enforces the correct ordering between the bail-out of the
1093 * waiter and the gpu reset work code.
1094 */
1095 atomic_t reset_counter;
1096
1097 #define I915_RESET_IN_PROGRESS_FLAG 1
1098 #define I915_WEDGED (1 << 31)
1099
1100 /**
1101 * Waitqueue to signal when the reset has completed. Used by clients
1102 * that wait for dev_priv->mm.wedged to settle.
1103 */
1104 wait_queue_head_t reset_queue;
1105
1106 /* Userspace knobs for gpu hang simulation;
1107 * combines both a ring mask, and extra flags
1108 */
1109 u32 stop_rings;
1110 #define I915_STOP_RING_ALLOW_BAN (1 << 31)
1111 #define I915_STOP_RING_ALLOW_WARN (1 << 30)
1112
1113 /* For missed irq/seqno simulation. */
1114 unsigned int test_irq_rings;
1115 };
1116
1117 enum modeset_restore {
1118 MODESET_ON_LID_OPEN,
1119 MODESET_DONE,
1120 MODESET_SUSPENDED,
1121 };
1122
1123 struct ddi_vbt_port_info {
1124 uint8_t hdmi_level_shift;
1125
1126 uint8_t supports_dvi:1;
1127 uint8_t supports_hdmi:1;
1128 uint8_t supports_dp:1;
1129 };
1130
1131 enum drrs_support_type {
1132 DRRS_NOT_SUPPORTED = 0,
1133 STATIC_DRRS_SUPPORT = 1,
1134 SEAMLESS_DRRS_SUPPORT = 2
1135 };
1136
1137 struct intel_vbt_data {
1138 struct drm_display_mode *lfp_lvds_vbt_mode; /* if any */
1139 struct drm_display_mode *sdvo_lvds_vbt_mode; /* if any */
1140
1141 /* Feature bits */
1142 unsigned int int_tv_support:1;
1143 unsigned int lvds_dither:1;
1144 unsigned int lvds_vbt:1;
1145 unsigned int int_crt_support:1;
1146 unsigned int lvds_use_ssc:1;
1147 unsigned int display_clock_mode:1;
1148 unsigned int fdi_rx_polarity_inverted:1;
1149 int lvds_ssc_freq;
1150 unsigned int bios_lvds_val; /* initial [PCH_]LVDS reg val in VBIOS */
1151
1152 enum drrs_support_type drrs_type;
1153
1154 /* eDP */
1155 int edp_rate;
1156 int edp_lanes;
1157 int edp_preemphasis;
1158 int edp_vswing;
1159 bool edp_initialized;
1160 bool edp_support;
1161 int edp_bpp;
1162 struct edp_power_seq edp_pps;
1163
1164 struct {
1165 u16 pwm_freq_hz;
1166 bool present;
1167 bool active_low_pwm;
1168 } backlight;
1169
1170 /* MIPI DSI */
1171 struct {
1172 u16 panel_id;
1173 struct mipi_config *config;
1174 struct mipi_pps_data *pps;
1175 u8 seq_version;
1176 u32 size;
1177 u8 *data;
1178 u8 *sequence[MIPI_SEQ_MAX];
1179 } dsi;
1180
1181 int crt_ddc_pin;
1182
1183 int child_dev_num;
1184 union child_device_config *child_dev;
1185
1186 struct ddi_vbt_port_info ddi_port_info[I915_MAX_PORTS];
1187 };
1188
1189 enum intel_ddb_partitioning {
1190 INTEL_DDB_PART_1_2,
1191 INTEL_DDB_PART_5_6, /* IVB+ */
1192 };
1193
1194 struct intel_wm_level {
1195 bool enable;
1196 uint32_t pri_val;
1197 uint32_t spr_val;
1198 uint32_t cur_val;
1199 uint32_t fbc_val;
1200 };
1201
1202 struct ilk_wm_values {
1203 uint32_t wm_pipe[3];
1204 uint32_t wm_lp[3];
1205 uint32_t wm_lp_spr[3];
1206 uint32_t wm_linetime[3];
1207 bool enable_fbc_wm;
1208 enum intel_ddb_partitioning partitioning;
1209 };
1210
1211 /*
1212 * This struct helps tracking the state needed for runtime PM, which puts the
1213 * device in PCI D3 state. Notice that when this happens, nothing on the
1214 * graphics device works, even register access, so we don't get interrupts nor
1215 * anything else.
1216 *
1217 * Every piece of our code that needs to actually touch the hardware needs to
1218 * either call intel_runtime_pm_get or call intel_display_power_get with the
1219 * appropriate power domain.
1220 *
1221 * Our driver uses the autosuspend delay feature, which means we'll only really
1222 * suspend if we stay with zero refcount for a certain amount of time. The
1223 * default value is currently very conservative (see intel_init_runtime_pm), but
1224 * it can be changed with the standard runtime PM files from sysfs.
1225 *
1226 * The irqs_disabled variable becomes true exactly after we disable the IRQs and
1227 * goes back to false exactly before we reenable the IRQs. We use this variable
1228 * to check if someone is trying to enable/disable IRQs while they're supposed
1229 * to be disabled. This shouldn't happen and we'll print some error messages in
1230 * case it happens.
1231 *
1232 * For more, read the Documentation/power/runtime_pm.txt.
1233 */
1234 struct i915_runtime_pm {
1235 bool suspended;
1236 bool irqs_disabled;
1237 };
1238
1239 enum intel_pipe_crc_source {
1240 INTEL_PIPE_CRC_SOURCE_NONE,
1241 INTEL_PIPE_CRC_SOURCE_PLANE1,
1242 INTEL_PIPE_CRC_SOURCE_PLANE2,
1243 INTEL_PIPE_CRC_SOURCE_PF,
1244 INTEL_PIPE_CRC_SOURCE_PIPE,
1245 /* TV/DP on pre-gen5/vlv can't use the pipe source. */
1246 INTEL_PIPE_CRC_SOURCE_TV,
1247 INTEL_PIPE_CRC_SOURCE_DP_B,
1248 INTEL_PIPE_CRC_SOURCE_DP_C,
1249 INTEL_PIPE_CRC_SOURCE_DP_D,
1250 INTEL_PIPE_CRC_SOURCE_AUTO,
1251 INTEL_PIPE_CRC_SOURCE_MAX,
1252 };
1253
1254 struct intel_pipe_crc_entry {
1255 uint32_t frame;
1256 uint32_t crc[5];
1257 };
1258
1259 #define INTEL_PIPE_CRC_ENTRIES_NR 128
1260 struct intel_pipe_crc {
1261 spinlock_t lock;
1262 bool opened; /* exclusive access to the result file */
1263 struct intel_pipe_crc_entry *entries;
1264 enum intel_pipe_crc_source source;
1265 int head, tail;
1266 wait_queue_head_t wq;
1267 };
1268
1269 struct drm_i915_private {
1270 struct drm_device *dev;
1271 struct kmem_cache *slab;
1272
1273 const struct intel_device_info info;
1274
1275 int relative_constants_mode;
1276
1277 void __iomem *regs;
1278
1279 struct intel_uncore uncore;
1280
1281 struct intel_gmbus gmbus[GMBUS_NUM_PORTS];
1282
1283
1284 /** gmbus_mutex protects against concurrent usage of the single hw gmbus
1285 * controller on different i2c buses. */
1286 struct mutex gmbus_mutex;
1287
1288 /**
1289 * Base address of the gmbus and gpio block.
1290 */
1291 uint32_t gpio_mmio_base;
1292
1293 wait_queue_head_t gmbus_wait_queue;
1294
1295 struct pci_dev *bridge_dev;
1296 struct intel_ring_buffer ring[I915_NUM_RINGS];
1297 uint32_t last_seqno, next_seqno;
1298
1299 drm_dma_handle_t *status_page_dmah;
1300 struct resource mch_res;
1301
1302 /* protects the irq masks */
1303 spinlock_t irq_lock;
1304
1305 bool display_irqs_enabled;
1306
1307 /* To control wakeup latency, e.g. for irq-driven dp aux transfers. */
1308 struct pm_qos_request pm_qos;
1309
1310 /* DPIO indirect register protection */
1311 struct mutex dpio_lock;
1312
1313 /** Cached value of IMR to avoid reads in updating the bitfield */
1314 union {
1315 u32 irq_mask;
1316 u32 de_irq_mask[I915_MAX_PIPES];
1317 };
1318 u32 gt_irq_mask;
1319 u32 pm_irq_mask;
1320 u32 pm_rps_events;
1321 u32 pipestat_irq_mask[I915_MAX_PIPES];
1322
1323 struct work_struct hotplug_work;
1324 bool enable_hotplug_processing;
1325 struct {
1326 unsigned long hpd_last_jiffies;
1327 int hpd_cnt;
1328 enum {
1329 HPD_ENABLED = 0,
1330 HPD_DISABLED = 1,
1331 HPD_MARK_DISABLED = 2
1332 } hpd_mark;
1333 } hpd_stats[HPD_NUM_PINS];
1334 u32 hpd_event_bits;
1335 struct timer_list hotplug_reenable_timer;
1336
1337 struct i915_fbc fbc;
1338 struct i915_drrs drrs;
1339 struct intel_opregion opregion;
1340 struct intel_vbt_data vbt;
1341
1342 /* overlay */
1343 struct intel_overlay *overlay;
1344
1345 /* backlight registers and fields in struct intel_panel */
1346 spinlock_t backlight_lock;
1347
1348 /* LVDS info */
1349 bool no_aux_handshake;
1350
1351 struct drm_i915_fence_reg fence_regs[I915_MAX_NUM_FENCES]; /* assume 965 */
1352 int fence_reg_start; /* 4 if userland hasn't ioctl'd us yet */
1353 int num_fence_regs; /* 8 on pre-965, 16 otherwise */
1354
1355 unsigned int fsb_freq, mem_freq, is_ddr3;
1356 unsigned int vlv_cdclk_freq;
1357
1358 /**
1359 * wq - Driver workqueue for GEM.
1360 *
1361 * NOTE: Work items scheduled here are not allowed to grab any modeset
1362 * locks, for otherwise the flushing done in the pageflip code will
1363 * result in deadlocks.
1364 */
1365 struct workqueue_struct *wq;
1366
1367 /* Display functions */
1368 struct drm_i915_display_funcs display;
1369
1370 /* PCH chipset type */
1371 enum intel_pch pch_type;
1372 unsigned short pch_id;
1373
1374 unsigned long quirks;
1375
1376 enum modeset_restore modeset_restore;
1377 struct mutex modeset_restore_lock;
1378
1379 struct list_head vm_list; /* Global list of all address spaces */
1380 struct i915_gtt gtt; /* VM representing the global address space */
1381
1382 struct i915_gem_mm mm;
1383
1384 /* Kernel Modesetting */
1385
1386 struct sdvo_device_mapping sdvo_mappings[2];
1387
1388 struct drm_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];
1389 struct drm_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];
1390 wait_queue_head_t pending_flip_queue;
1391
1392 #ifdef CONFIG_DEBUG_FS
1393 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];
1394 #endif
1395
1396 int num_shared_dpll;
1397 struct intel_shared_dpll shared_dplls[I915_NUM_PLLS];
1398 struct intel_ddi_plls ddi_plls;
1399 int dpio_phy_iosf_port[I915_NUM_PHYS_VLV];
1400
1401 /* Reclocking support */
1402 bool render_reclock_avail;
1403 bool lvds_downclock_avail;
1404 /* indicates the reduced downclock for LVDS*/
1405 int lvds_downclock;
1406 u16 orig_clock;
1407
1408 bool mchbar_need_disable;
1409
1410 struct intel_l3_parity l3_parity;
1411
1412 /* Cannot be determined by PCIID. You must always read a register. */
1413 size_t ellc_size;
1414
1415 /* gen6+ rps state */
1416 struct intel_gen6_power_mgmt rps;
1417
1418 /* ilk-only ips/rps state. Everything in here is protected by the global
1419 * mchdev_lock in intel_pm.c */
1420 struct intel_ilk_power_mgmt ips;
1421
1422 struct i915_power_domains power_domains;
1423
1424 struct i915_psr psr;
1425
1426 struct i915_gpu_error gpu_error;
1427
1428 struct drm_i915_gem_object *vlv_pctx;
1429
1430 #ifdef CONFIG_DRM_I915_FBDEV
1431 /* list of fbdev register on this device */
1432 struct intel_fbdev *fbdev;
1433 #endif
1434
1435 /*
1436 * The console may be contended at resume, but we don't
1437 * want it to block on it.
1438 */
1439 struct work_struct console_resume_work;
1440
1441 struct drm_property *broadcast_rgb_property;
1442 struct drm_property *force_audio_property;
1443
1444 uint32_t hw_context_size;
1445 struct list_head context_list;
1446
1447 u32 fdi_rx_config;
1448
1449 u32 suspend_count;
1450 struct i915_suspend_saved_registers regfile;
1451
1452 struct {
1453 /*
1454 * Raw watermark latency values:
1455 * in 0.1us units for WM0,
1456 * in 0.5us units for WM1+.
1457 */
1458 /* primary */
1459 uint16_t pri_latency[5];
1460 /* sprite */
1461 uint16_t spr_latency[5];
1462 /* cursor */
1463 uint16_t cur_latency[5];
1464
1465 /* current hardware state */
1466 struct ilk_wm_values hw;
1467 } wm;
1468
1469 struct i915_runtime_pm pm;
1470
1471 /* Old dri1 support infrastructure, beware the dragons ya fools entering
1472 * here! */
1473 struct i915_dri1_state dri1;
1474 /* Old ums support infrastructure, same warning applies. */
1475 struct i915_ums_state ums;
1476 };
1477
1478 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
1479 {
1480 return dev->dev_private;
1481 }
1482
1483 /* Iterate over initialised rings */
1484 #define for_each_ring(ring__, dev_priv__, i__) \
1485 for ((i__) = 0; (i__) < I915_NUM_RINGS; (i__)++) \
1486 if (((ring__) = &(dev_priv__)->ring[(i__)]), intel_ring_initialized((ring__)))
1487
1488 enum hdmi_force_audio {
1489 HDMI_AUDIO_OFF_DVI = -2, /* no aux data for HDMI-DVI converter */
1490 HDMI_AUDIO_OFF, /* force turn off HDMI audio */
1491 HDMI_AUDIO_AUTO, /* trust EDID */
1492 HDMI_AUDIO_ON, /* force turn on HDMI audio */
1493 };
1494
1495 #define I915_GTT_OFFSET_NONE ((u32)-1)
1496
1497 struct drm_i915_gem_object_ops {
1498 /* Interface between the GEM object and its backing storage.
1499 * get_pages() is called once prior to the use of the associated set
1500 * of pages before to binding them into the GTT, and put_pages() is
1501 * called after we no longer need them. As we expect there to be
1502 * associated cost with migrating pages between the backing storage
1503 * and making them available for the GPU (e.g. clflush), we may hold
1504 * onto the pages after they are no longer referenced by the GPU
1505 * in case they may be used again shortly (for example migrating the
1506 * pages to a different memory domain within the GTT). put_pages()
1507 * will therefore most likely be called when the object itself is
1508 * being released or under memory pressure (where we attempt to
1509 * reap pages for the shrinker).
1510 */
1511 int (*get_pages)(struct drm_i915_gem_object *);
1512 void (*put_pages)(struct drm_i915_gem_object *);
1513 };
1514
1515 struct drm_i915_gem_object {
1516 struct drm_gem_object base;
1517
1518 const struct drm_i915_gem_object_ops *ops;
1519
1520 /** List of VMAs backed by this object */
1521 struct list_head vma_list;
1522
1523 /** Stolen memory for this object, instead of being backed by shmem. */
1524 struct drm_mm_node *stolen;
1525 struct list_head global_list;
1526
1527 struct list_head ring_list;
1528 /** Used in execbuf to temporarily hold a ref */
1529 struct list_head obj_exec_link;
1530
1531 /**
1532 * This is set if the object is on the active lists (has pending
1533 * rendering and so a non-zero seqno), and is not set if it i s on
1534 * inactive (ready to be unbound) list.
1535 */
1536 unsigned int active:1;
1537
1538 /**
1539 * This is set if the object has been written to since last bound
1540 * to the GTT
1541 */
1542 unsigned int dirty:1;
1543
1544 /**
1545 * Fence register bits (if any) for this object. Will be set
1546 * as needed when mapped into the GTT.
1547 * Protected by dev->struct_mutex.
1548 */
1549 signed int fence_reg:I915_MAX_NUM_FENCE_BITS;
1550
1551 /**
1552 * Advice: are the backing pages purgeable?
1553 */
1554 unsigned int madv:2;
1555
1556 /**
1557 * Current tiling mode for the object.
1558 */
1559 unsigned int tiling_mode:2;
1560 /**
1561 * Whether the tiling parameters for the currently associated fence
1562 * register have changed. Note that for the purposes of tracking
1563 * tiling changes we also treat the unfenced register, the register
1564 * slot that the object occupies whilst it executes a fenced
1565 * command (such as BLT on gen2/3), as a "fence".
1566 */
1567 unsigned int fence_dirty:1;
1568
1569 /**
1570 * Is the object at the current location in the gtt mappable and
1571 * fenceable? Used to avoid costly recalculations.
1572 */
1573 unsigned int map_and_fenceable:1;
1574
1575 /**
1576 * Whether the current gtt mapping needs to be mappable (and isn't just
1577 * mappable by accident). Track pin and fault separate for a more
1578 * accurate mappable working set.
1579 */
1580 unsigned int fault_mappable:1;
1581 unsigned int pin_mappable:1;
1582 unsigned int pin_display:1;
1583
1584 /*
1585 * Is the GPU currently using a fence to access this buffer,
1586 */
1587 unsigned int pending_fenced_gpu_access:1;
1588 unsigned int fenced_gpu_access:1;
1589
1590 unsigned int cache_level:3;
1591
1592 unsigned int has_aliasing_ppgtt_mapping:1;
1593 unsigned int has_global_gtt_mapping:1;
1594 unsigned int has_dma_mapping:1;
1595
1596 struct sg_table *pages;
1597 int pages_pin_count;
1598
1599 /* prime dma-buf support */
1600 void *dma_buf_vmapping;
1601 int vmapping_count;
1602
1603 struct intel_ring_buffer *ring;
1604
1605 /** Breadcrumb of last rendering to the buffer. */
1606 uint32_t last_read_seqno;
1607 uint32_t last_write_seqno;
1608 /** Breadcrumb of last fenced GPU access to the buffer. */
1609 uint32_t last_fenced_seqno;
1610
1611 /** Current tiling stride for the object, if it's tiled. */
1612 uint32_t stride;
1613
1614 /** References from framebuffers, locks out tiling changes. */
1615 unsigned long framebuffer_references;
1616
1617 /** Record of address bit 17 of each page at last unbind. */
1618 unsigned long *bit_17;
1619
1620 /** User space pin count and filp owning the pin */
1621 unsigned long user_pin_count;
1622 struct drm_file *pin_filp;
1623
1624 /** for phy allocated objects */
1625 struct drm_i915_gem_phys_object *phys_obj;
1626 };
1627
1628 #define to_intel_bo(x) container_of(x, struct drm_i915_gem_object, base)
1629
1630 /**
1631 * Request queue structure.
1632 *
1633 * The request queue allows us to note sequence numbers that have been emitted
1634 * and may be associated with active buffers to be retired.
1635 *
1636 * By keeping this list, we can avoid having to do questionable
1637 * sequence-number comparisons on buffer last_rendering_seqnos, and associate
1638 * an emission time with seqnos for tracking how far ahead of the GPU we are.
1639 */
1640 struct drm_i915_gem_request {
1641 /** On Which ring this request was generated */
1642 struct intel_ring_buffer *ring;
1643
1644 /** GEM sequence number associated with this request. */
1645 uint32_t seqno;
1646
1647 /** Position in the ringbuffer of the start of the request */
1648 u32 head;
1649
1650 /** Position in the ringbuffer of the end of the request */
1651 u32 tail;
1652
1653 /** Context related to this request */
1654 struct i915_hw_context *ctx;
1655
1656 /** Batch buffer related to this request if any */
1657 struct drm_i915_gem_object *batch_obj;
1658
1659 /** Time at which this request was emitted, in jiffies. */
1660 unsigned long emitted_jiffies;
1661
1662 /** global list entry for this request */
1663 struct list_head list;
1664
1665 struct drm_i915_file_private *file_priv;
1666 /** file_priv list entry for this request */
1667 struct list_head client_list;
1668 };
1669
1670 struct drm_i915_file_private {
1671 struct drm_i915_private *dev_priv;
1672 struct drm_file *file;
1673
1674 struct {
1675 spinlock_t lock;
1676 struct list_head request_list;
1677 struct delayed_work idle_work;
1678 } mm;
1679 struct idr context_idr;
1680
1681 struct i915_hw_context *private_default_ctx;
1682 atomic_t rps_wait_boost;
1683 };
1684
1685 /*
1686 * A command that requires special handling by the command parser.
1687 */
1688 struct drm_i915_cmd_descriptor {
1689 /*
1690 * Flags describing how the command parser processes the command.
1691 *
1692 * CMD_DESC_FIXED: The command has a fixed length if this is set,
1693 * a length mask if not set
1694 * CMD_DESC_SKIP: The command is allowed but does not follow the
1695 * standard length encoding for the opcode range in
1696 * which it falls
1697 * CMD_DESC_REJECT: The command is never allowed
1698 * CMD_DESC_REGISTER: The command should be checked against the
1699 * register whitelist for the appropriate ring
1700 * CMD_DESC_MASTER: The command is allowed if the submitting process
1701 * is the DRM master
1702 */
1703 u32 flags;
1704 #define CMD_DESC_FIXED (1<<0)
1705 #define CMD_DESC_SKIP (1<<1)
1706 #define CMD_DESC_REJECT (1<<2)
1707 #define CMD_DESC_REGISTER (1<<3)
1708 #define CMD_DESC_BITMASK (1<<4)
1709 #define CMD_DESC_MASTER (1<<5)
1710
1711 /*
1712 * The command's unique identification bits and the bitmask to get them.
1713 * This isn't strictly the opcode field as defined in the spec and may
1714 * also include type, subtype, and/or subop fields.
1715 */
1716 struct {
1717 u32 value;
1718 u32 mask;
1719 } cmd;
1720
1721 /*
1722 * The command's length. The command is either fixed length (i.e. does
1723 * not include a length field) or has a length field mask. The flag
1724 * CMD_DESC_FIXED indicates a fixed length. Otherwise, the command has
1725 * a length mask. All command entries in a command table must include
1726 * length information.
1727 */
1728 union {
1729 u32 fixed;
1730 u32 mask;
1731 } length;
1732
1733 /*
1734 * Describes where to find a register address in the command to check
1735 * against the ring's register whitelist. Only valid if flags has the
1736 * CMD_DESC_REGISTER bit set.
1737 */
1738 struct {
1739 u32 offset;
1740 u32 mask;
1741 } reg;
1742
1743 #define MAX_CMD_DESC_BITMASKS 3
1744 /*
1745 * Describes command checks where a particular dword is masked and
1746 * compared against an expected value. If the command does not match
1747 * the expected value, the parser rejects it. Only valid if flags has
1748 * the CMD_DESC_BITMASK bit set. Only entries where mask is non-zero
1749 * are valid.
1750 *
1751 * If the check specifies a non-zero condition_mask then the parser
1752 * only performs the check when the bits specified by condition_mask
1753 * are non-zero.
1754 */
1755 struct {
1756 u32 offset;
1757 u32 mask;
1758 u32 expected;
1759 u32 condition_offset;
1760 u32 condition_mask;
1761 } bits[MAX_CMD_DESC_BITMASKS];
1762 };
1763
1764 /*
1765 * A table of commands requiring special handling by the command parser.
1766 *
1767 * Each ring has an array of tables. Each table consists of an array of command
1768 * descriptors, which must be sorted with command opcodes in ascending order.
1769 */
1770 struct drm_i915_cmd_table {
1771 const struct drm_i915_cmd_descriptor *table;
1772 int count;
1773 };
1774
1775 #define INTEL_INFO(dev) (&to_i915(dev)->info)
1776
1777 #define IS_I830(dev) ((dev)->pdev->device == 0x3577)
1778 #define IS_845G(dev) ((dev)->pdev->device == 0x2562)
1779 #define IS_I85X(dev) (INTEL_INFO(dev)->is_i85x)
1780 #define IS_I865G(dev) ((dev)->pdev->device == 0x2572)
1781 #define IS_I915G(dev) (INTEL_INFO(dev)->is_i915g)
1782 #define IS_I915GM(dev) ((dev)->pdev->device == 0x2592)
1783 #define IS_I945G(dev) ((dev)->pdev->device == 0x2772)
1784 #define IS_I945GM(dev) (INTEL_INFO(dev)->is_i945gm)
1785 #define IS_BROADWATER(dev) (INTEL_INFO(dev)->is_broadwater)
1786 #define IS_CRESTLINE(dev) (INTEL_INFO(dev)->is_crestline)
1787 #define IS_GM45(dev) ((dev)->pdev->device == 0x2A42)
1788 #define IS_G4X(dev) (INTEL_INFO(dev)->is_g4x)
1789 #define IS_PINEVIEW_G(dev) ((dev)->pdev->device == 0xa001)
1790 #define IS_PINEVIEW_M(dev) ((dev)->pdev->device == 0xa011)
1791 #define IS_PINEVIEW(dev) (INTEL_INFO(dev)->is_pineview)
1792 #define IS_G33(dev) (INTEL_INFO(dev)->is_g33)
1793 #define IS_IRONLAKE_M(dev) ((dev)->pdev->device == 0x0046)
1794 #define IS_IVYBRIDGE(dev) (INTEL_INFO(dev)->is_ivybridge)
1795 #define IS_IVB_GT1(dev) ((dev)->pdev->device == 0x0156 || \
1796 (dev)->pdev->device == 0x0152 || \
1797 (dev)->pdev->device == 0x015a)
1798 #define IS_SNB_GT1(dev) ((dev)->pdev->device == 0x0102 || \
1799 (dev)->pdev->device == 0x0106 || \
1800 (dev)->pdev->device == 0x010A)
1801 #define IS_VALLEYVIEW(dev) (INTEL_INFO(dev)->is_valleyview)
1802 #define IS_CHERRYVIEW(dev) (INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1803 #define IS_HASWELL(dev) (INTEL_INFO(dev)->is_haswell)
1804 #define IS_BROADWELL(dev) (!INTEL_INFO(dev)->is_valleyview && IS_GEN8(dev))
1805 #define IS_MOBILE(dev) (INTEL_INFO(dev)->is_mobile)
1806 #define IS_HSW_EARLY_SDV(dev) (IS_HASWELL(dev) && \
1807 ((dev)->pdev->device & 0xFF00) == 0x0C00)
1808 #define IS_BDW_ULT(dev) (IS_BROADWELL(dev) && \
1809 (((dev)->pdev->device & 0xf) == 0x2 || \
1810 ((dev)->pdev->device & 0xf) == 0x6 || \
1811 ((dev)->pdev->device & 0xf) == 0xe))
1812 #define IS_HSW_ULT(dev) (IS_HASWELL(dev) && \
1813 ((dev)->pdev->device & 0xFF00) == 0x0A00)
1814 #define IS_ULT(dev) (IS_HSW_ULT(dev) || IS_BDW_ULT(dev))
1815 #define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
1816 ((dev)->pdev->device & 0x00F0) == 0x0020)
1817 #define IS_PRELIMINARY_HW(intel_info) ((intel_info)->is_preliminary)
1818
1819 /*
1820 * The genX designation typically refers to the render engine, so render
1821 * capability related checks should use IS_GEN, while display and other checks
1822 * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
1823 * chips, etc.).
1824 */
1825 #define IS_GEN2(dev) (INTEL_INFO(dev)->gen == 2)
1826 #define IS_GEN3(dev) (INTEL_INFO(dev)->gen == 3)
1827 #define IS_GEN4(dev) (INTEL_INFO(dev)->gen == 4)
1828 #define IS_GEN5(dev) (INTEL_INFO(dev)->gen == 5)
1829 #define IS_GEN6(dev) (INTEL_INFO(dev)->gen == 6)
1830 #define IS_GEN7(dev) (INTEL_INFO(dev)->gen == 7)
1831 #define IS_GEN8(dev) (INTEL_INFO(dev)->gen == 8)
1832
1833 #define RENDER_RING (1<<RCS)
1834 #define BSD_RING (1<<VCS)
1835 #define BLT_RING (1<<BCS)
1836 #define VEBOX_RING (1<<VECS)
1837 #define BSD2_RING (1<<VCS2)
1838 #define HAS_BSD(dev) (INTEL_INFO(dev)->ring_mask & BSD_RING)
1839 #define HAS_BSD2(dev) (INTEL_INFO(dev)->ring_mask & BSD2_RING)
1840 #define HAS_BLT(dev) (INTEL_INFO(dev)->ring_mask & BLT_RING)
1841 #define HAS_VEBOX(dev) (INTEL_INFO(dev)->ring_mask & VEBOX_RING)
1842 #define HAS_LLC(dev) (INTEL_INFO(dev)->has_llc)
1843 #define HAS_WT(dev) (IS_HASWELL(dev) && to_i915(dev)->ellc_size)
1844 #define I915_NEED_GFX_HWS(dev) (INTEL_INFO(dev)->need_gfx_hws)
1845
1846 #define HAS_HW_CONTEXTS(dev) (INTEL_INFO(dev)->gen >= 6)
1847 #define HAS_ALIASING_PPGTT(dev) (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev))
1848 #define HAS_PPGTT(dev) (INTEL_INFO(dev)->gen >= 7 && !IS_VALLEYVIEW(dev) \
1849 && !IS_BROADWELL(dev))
1850 #define USES_PPGTT(dev) intel_enable_ppgtt(dev, false)
1851 #define USES_FULL_PPGTT(dev) intel_enable_ppgtt(dev, true)
1852
1853 #define HAS_OVERLAY(dev) (INTEL_INFO(dev)->has_overlay)
1854 #define OVERLAY_NEEDS_PHYSICAL(dev) (INTEL_INFO(dev)->overlay_needs_physical)
1855
1856 /* Early gen2 have a totally busted CS tlb and require pinned batches. */
1857 #define HAS_BROKEN_CS_TLB(dev) (IS_I830(dev) || IS_845G(dev))
1858 /*
1859 * dp aux and gmbus irq on gen4 seems to be able to generate legacy interrupts
1860 * even when in MSI mode. This results in spurious interrupt warnings if the
1861 * legacy irq no. is shared with another device. The kernel then disables that
1862 * interrupt source and so prevents the other device from working properly.
1863 */
1864 #define HAS_AUX_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1865 #define HAS_GMBUS_IRQ(dev) (INTEL_INFO(dev)->gen >= 5)
1866
1867 /* With the 945 and later, Y tiling got adjusted so that it was 32 128-byte
1868 * rows, which changed the alignment requirements and fence programming.
1869 */
1870 #define HAS_128_BYTE_Y_TILING(dev) (!IS_GEN2(dev) && !(IS_I915G(dev) || \
1871 IS_I915GM(dev)))
1872 #define SUPPORTS_DIGITAL_OUTPUTS(dev) (!IS_GEN2(dev) && !IS_PINEVIEW(dev))
1873 #define SUPPORTS_INTEGRATED_HDMI(dev) (IS_G4X(dev) || IS_GEN5(dev))
1874 #define SUPPORTS_INTEGRATED_DP(dev) (IS_G4X(dev) || IS_GEN5(dev))
1875 #define SUPPORTS_TV(dev) (INTEL_INFO(dev)->supports_tv)
1876 #define I915_HAS_HOTPLUG(dev) (INTEL_INFO(dev)->has_hotplug)
1877
1878 #define HAS_FW_BLC(dev) (INTEL_INFO(dev)->gen > 2)
1879 #define HAS_PIPE_CXSR(dev) (INTEL_INFO(dev)->has_pipe_cxsr)
1880 #define HAS_FBC(dev) (INTEL_INFO(dev)->has_fbc)
1881
1882 #define HAS_IPS(dev) (IS_ULT(dev) || IS_BROADWELL(dev))
1883
1884 #define HAS_DDI(dev) (INTEL_INFO(dev)->has_ddi)
1885 #define HAS_FPGA_DBG_UNCLAIMED(dev) (INTEL_INFO(dev)->has_fpga_dbg)
1886 #define HAS_PSR(dev) (IS_HASWELL(dev) || IS_BROADWELL(dev))
1887 #define HAS_RUNTIME_PM(dev) (IS_GEN6(dev) || IS_HASWELL(dev) || \
1888 IS_BROADWELL(dev))
1889
1890 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
1891 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
1892 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
1893 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
1894 #define INTEL_PCH_LPT_DEVICE_ID_TYPE 0x8c00
1895 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE 0x9c00
1896
1897 #define INTEL_PCH_TYPE(dev) (to_i915(dev)->pch_type)
1898 #define HAS_PCH_LPT(dev) (INTEL_PCH_TYPE(dev) == PCH_LPT)
1899 #define HAS_PCH_CPT(dev) (INTEL_PCH_TYPE(dev) == PCH_CPT)
1900 #define HAS_PCH_IBX(dev) (INTEL_PCH_TYPE(dev) == PCH_IBX)
1901 #define HAS_PCH_NOP(dev) (INTEL_PCH_TYPE(dev) == PCH_NOP)
1902 #define HAS_PCH_SPLIT(dev) (INTEL_PCH_TYPE(dev) != PCH_NONE)
1903
1904 /* DPF == dynamic parity feature */
1905 #define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
1906 #define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev))
1907
1908 #define GT_FREQUENCY_MULTIPLIER 50
1909
1910 #include "i915_trace.h"
1911
1912 extern const struct drm_ioctl_desc i915_ioctls[];
1913 extern int i915_max_ioctl;
1914
1915 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
1916 extern int i915_resume(struct drm_device *dev);
1917 extern int i915_master_create(struct drm_device *dev, struct drm_master *master);
1918 extern void i915_master_destroy(struct drm_device *dev, struct drm_master *master);
1919
1920 /* i915_params.c */
1921 struct i915_params {
1922 int modeset;
1923 int panel_ignore_lid;
1924 unsigned int powersave;
1925 int semaphores;
1926 unsigned int lvds_downclock;
1927 int lvds_channel_mode;
1928 int panel_use_ssc;
1929 int vbt_sdvo_panel_type;
1930 int enable_rc6;
1931 int enable_fbc;
1932 int enable_ppgtt;
1933 int enable_psr;
1934 unsigned int preliminary_hw_support;
1935 int disable_power_well;
1936 int enable_ips;
1937 int invert_brightness;
1938 int enable_cmd_parser;
1939 /* leave bools at the end to not create holes */
1940 bool enable_hangcheck;
1941 bool fastboot;
1942 bool prefault_disable;
1943 bool reset;
1944 bool disable_display;
1945 bool disable_vtd_wa;
1946 };
1947 extern struct i915_params i915 __read_mostly;
1948
1949 /* i915_dma.c */
1950 void i915_update_dri1_breadcrumb(struct drm_device *dev);
1951 extern void i915_kernel_lost_context(struct drm_device * dev);
1952 extern int i915_driver_load(struct drm_device *, unsigned long flags);
1953 extern int i915_driver_unload(struct drm_device *);
1954 extern int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv);
1955 extern void i915_driver_lastclose(struct drm_device * dev);
1956 extern void i915_driver_preclose(struct drm_device *dev,
1957 struct drm_file *file_priv);
1958 extern void i915_driver_postclose(struct drm_device *dev,
1959 struct drm_file *file_priv);
1960 extern int i915_driver_device_is_agp(struct drm_device * dev);
1961 #ifdef CONFIG_COMPAT
1962 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
1963 unsigned long arg);
1964 #endif
1965 extern int i915_emit_box(struct drm_device *dev,
1966 struct drm_clip_rect *box,
1967 int DR1, int DR4);
1968 extern int intel_gpu_reset(struct drm_device *dev);
1969 extern int i915_reset(struct drm_device *dev);
1970 extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
1971 extern unsigned long i915_mch_val(struct drm_i915_private *dev_priv);
1972 extern unsigned long i915_gfx_val(struct drm_i915_private *dev_priv);
1973 extern void i915_update_gfx_val(struct drm_i915_private *dev_priv);
1974
1975 extern void intel_console_resume(struct work_struct *work);
1976
1977 /* i915_irq.c */
1978 void i915_queue_hangcheck(struct drm_device *dev);
1979 __printf(3, 4)
1980 void i915_handle_error(struct drm_device *dev, bool wedged,
1981 const char *fmt, ...);
1982
1983 void gen6_set_pm_mask(struct drm_i915_private *dev_priv, u32 pm_iir,
1984 int new_delay);
1985 extern void intel_irq_init(struct drm_device *dev);
1986 extern void intel_hpd_init(struct drm_device *dev);
1987
1988 extern void intel_uncore_sanitize(struct drm_device *dev);
1989 extern void intel_uncore_early_sanitize(struct drm_device *dev);
1990 extern void intel_uncore_init(struct drm_device *dev);
1991 extern void intel_uncore_check_errors(struct drm_device *dev);
1992 extern void intel_uncore_fini(struct drm_device *dev);
1993
1994 void
1995 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
1996 u32 status_mask);
1997
1998 void
1999 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
2000 u32 status_mask);
2001
2002 void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv);
2003 void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv);
2004
2005 /* i915_gem.c */
2006 int i915_gem_init_ioctl(struct drm_device *dev, void *data,
2007 struct drm_file *file_priv);
2008 int i915_gem_create_ioctl(struct drm_device *dev, void *data,
2009 struct drm_file *file_priv);
2010 int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
2011 struct drm_file *file_priv);
2012 int i915_gem_pwrite_ioctl(struct drm_device *dev, void *data,
2013 struct drm_file *file_priv);
2014 int i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
2015 struct drm_file *file_priv);
2016 int i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data,
2017 struct drm_file *file_priv);
2018 int i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
2019 struct drm_file *file_priv);
2020 int i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
2021 struct drm_file *file_priv);
2022 int i915_gem_execbuffer(struct drm_device *dev, void *data,
2023 struct drm_file *file_priv);
2024 int i915_gem_execbuffer2(struct drm_device *dev, void *data,
2025 struct drm_file *file_priv);
2026 int i915_gem_pin_ioctl(struct drm_device *dev, void *data,
2027 struct drm_file *file_priv);
2028 int i915_gem_unpin_ioctl(struct drm_device *dev, void *data,
2029 struct drm_file *file_priv);
2030 int i915_gem_busy_ioctl(struct drm_device *dev, void *data,
2031 struct drm_file *file_priv);
2032 int i915_gem_get_caching_ioctl(struct drm_device *dev, void *data,
2033 struct drm_file *file);
2034 int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
2035 struct drm_file *file);
2036 int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
2037 struct drm_file *file_priv);
2038 int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
2039 struct drm_file *file_priv);
2040 int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
2041 struct drm_file *file_priv);
2042 int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
2043 struct drm_file *file_priv);
2044 int i915_gem_set_tiling(struct drm_device *dev, void *data,
2045 struct drm_file *file_priv);
2046 int i915_gem_get_tiling(struct drm_device *dev, void *data,
2047 struct drm_file *file_priv);
2048 int i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data,
2049 struct drm_file *file_priv);
2050 int i915_gem_wait_ioctl(struct drm_device *dev, void *data,
2051 struct drm_file *file_priv);
2052 void i915_gem_load(struct drm_device *dev);
2053 void *i915_gem_object_alloc(struct drm_device *dev);
2054 void i915_gem_object_free(struct drm_i915_gem_object *obj);
2055 void i915_gem_object_init(struct drm_i915_gem_object *obj,
2056 const struct drm_i915_gem_object_ops *ops);
2057 struct drm_i915_gem_object *i915_gem_alloc_object(struct drm_device *dev,
2058 size_t size);
2059 void i915_init_vm(struct drm_i915_private *dev_priv,
2060 struct i915_address_space *vm);
2061 void i915_gem_free_object(struct drm_gem_object *obj);
2062 void i915_gem_vma_destroy(struct i915_vma *vma);
2063
2064 #define PIN_MAPPABLE 0x1
2065 #define PIN_NONBLOCK 0x2
2066 #define PIN_GLOBAL 0x4
2067 int __must_check i915_gem_object_pin(struct drm_i915_gem_object *obj,
2068 struct i915_address_space *vm,
2069 uint32_t alignment,
2070 unsigned flags);
2071 int __must_check i915_vma_unbind(struct i915_vma *vma);
2072 int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
2073 void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
2074 void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
2075 void i915_gem_lastclose(struct drm_device *dev);
2076
2077 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
2078 int *needs_clflush);
2079
2080 int __must_check i915_gem_object_get_pages(struct drm_i915_gem_object *obj);
2081 static inline struct page *i915_gem_object_get_page(struct drm_i915_gem_object *obj, int n)
2082 {
2083 struct sg_page_iter sg_iter;
2084
2085 for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, n)
2086 return sg_page_iter_page(&sg_iter);
2087
2088 return NULL;
2089 }
2090 static inline void i915_gem_object_pin_pages(struct drm_i915_gem_object *obj)
2091 {
2092 BUG_ON(obj->pages == NULL);
2093 obj->pages_pin_count++;
2094 }
2095 static inline void i915_gem_object_unpin_pages(struct drm_i915_gem_object *obj)
2096 {
2097 BUG_ON(obj->pages_pin_count == 0);
2098 obj->pages_pin_count--;
2099 }
2100
2101 int __must_check i915_mutex_lock_interruptible(struct drm_device *dev);
2102 int i915_gem_object_sync(struct drm_i915_gem_object *obj,
2103 struct intel_ring_buffer *to);
2104 void i915_vma_move_to_active(struct i915_vma *vma,
2105 struct intel_ring_buffer *ring);
2106 int i915_gem_dumb_create(struct drm_file *file_priv,
2107 struct drm_device *dev,
2108 struct drm_mode_create_dumb *args);
2109 int i915_gem_mmap_gtt(struct drm_file *file_priv, struct drm_device *dev,
2110 uint32_t handle, uint64_t *offset);
2111 /**
2112 * Returns true if seq1 is later than seq2.
2113 */
2114 static inline bool
2115 i915_seqno_passed(uint32_t seq1, uint32_t seq2)
2116 {
2117 return (int32_t)(seq1 - seq2) >= 0;
2118 }
2119
2120 int __must_check i915_gem_get_seqno(struct drm_device *dev, u32 *seqno);
2121 int __must_check i915_gem_set_seqno(struct drm_device *dev, u32 seqno);
2122 int __must_check i915_gem_object_get_fence(struct drm_i915_gem_object *obj);
2123 int __must_check i915_gem_object_put_fence(struct drm_i915_gem_object *obj);
2124
2125 static inline bool
2126 i915_gem_object_pin_fence(struct drm_i915_gem_object *obj)
2127 {
2128 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2129 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2130 dev_priv->fence_regs[obj->fence_reg].pin_count++;
2131 return true;
2132 } else
2133 return false;
2134 }
2135
2136 static inline void
2137 i915_gem_object_unpin_fence(struct drm_i915_gem_object *obj)
2138 {
2139 if (obj->fence_reg != I915_FENCE_REG_NONE) {
2140 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2141 WARN_ON(dev_priv->fence_regs[obj->fence_reg].pin_count <= 0);
2142 dev_priv->fence_regs[obj->fence_reg].pin_count--;
2143 }
2144 }
2145
2146 struct drm_i915_gem_request *
2147 i915_gem_find_active_request(struct intel_ring_buffer *ring);
2148
2149 bool i915_gem_retire_requests(struct drm_device *dev);
2150 int __must_check i915_gem_check_wedge(struct i915_gpu_error *error,
2151 bool interruptible);
2152 static inline bool i915_reset_in_progress(struct i915_gpu_error *error)
2153 {
2154 return unlikely(atomic_read(&error->reset_counter)
2155 & (I915_RESET_IN_PROGRESS_FLAG | I915_WEDGED));
2156 }
2157
2158 static inline bool i915_terminally_wedged(struct i915_gpu_error *error)
2159 {
2160 return atomic_read(&error->reset_counter) & I915_WEDGED;
2161 }
2162
2163 static inline u32 i915_reset_count(struct i915_gpu_error *error)
2164 {
2165 return ((atomic_read(&error->reset_counter) & ~I915_WEDGED) + 1) / 2;
2166 }
2167
2168 static inline bool i915_stop_ring_allow_ban(struct drm_i915_private *dev_priv)
2169 {
2170 return dev_priv->gpu_error.stop_rings == 0 ||
2171 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_BAN;
2172 }
2173
2174 static inline bool i915_stop_ring_allow_warn(struct drm_i915_private *dev_priv)
2175 {
2176 return dev_priv->gpu_error.stop_rings == 0 ||
2177 dev_priv->gpu_error.stop_rings & I915_STOP_RING_ALLOW_WARN;
2178 }
2179
2180 void i915_gem_reset(struct drm_device *dev);
2181 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, bool force);
2182 int __must_check i915_gem_object_finish_gpu(struct drm_i915_gem_object *obj);
2183 int __must_check i915_gem_init(struct drm_device *dev);
2184 int __must_check i915_gem_init_hw(struct drm_device *dev);
2185 int i915_gem_l3_remap(struct intel_ring_buffer *ring, int slice);
2186 void i915_gem_init_swizzling(struct drm_device *dev);
2187 void i915_gem_cleanup_ringbuffer(struct drm_device *dev);
2188 int __must_check i915_gpu_idle(struct drm_device *dev);
2189 int __must_check i915_gem_suspend(struct drm_device *dev);
2190 int __i915_add_request(struct intel_ring_buffer *ring,
2191 struct drm_file *file,
2192 struct drm_i915_gem_object *batch_obj,
2193 u32 *seqno);
2194 #define i915_add_request(ring, seqno) \
2195 __i915_add_request(ring, NULL, NULL, seqno)
2196 int __must_check i915_wait_seqno(struct intel_ring_buffer *ring,
2197 uint32_t seqno);
2198 int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf);
2199 int __must_check
2200 i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj,
2201 bool write);
2202 int __must_check
2203 i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write);
2204 int __must_check
2205 i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj,
2206 u32 alignment,
2207 struct intel_ring_buffer *pipelined);
2208 void i915_gem_object_unpin_from_display_plane(struct drm_i915_gem_object *obj);
2209 int i915_gem_attach_phys_object(struct drm_device *dev,
2210 struct drm_i915_gem_object *obj,
2211 int id,
2212 int align);
2213 void i915_gem_detach_phys_object(struct drm_device *dev,
2214 struct drm_i915_gem_object *obj);
2215 void i915_gem_free_all_phys_object(struct drm_device *dev);
2216 int i915_gem_open(struct drm_device *dev, struct drm_file *file);
2217 void i915_gem_release(struct drm_device *dev, struct drm_file *file);
2218
2219 uint32_t
2220 i915_gem_get_gtt_size(struct drm_device *dev, uint32_t size, int tiling_mode);
2221 uint32_t
2222 i915_gem_get_gtt_alignment(struct drm_device *dev, uint32_t size,
2223 int tiling_mode, bool fenced);
2224
2225 int i915_gem_object_set_cache_level(struct drm_i915_gem_object *obj,
2226 enum i915_cache_level cache_level);
2227
2228 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev,
2229 struct dma_buf *dma_buf);
2230
2231 struct dma_buf *i915_gem_prime_export(struct drm_device *dev,
2232 struct drm_gem_object *gem_obj, int flags);
2233
2234 void i915_gem_restore_fences(struct drm_device *dev);
2235
2236 unsigned long i915_gem_obj_offset(struct drm_i915_gem_object *o,
2237 struct i915_address_space *vm);
2238 bool i915_gem_obj_bound_any(struct drm_i915_gem_object *o);
2239 bool i915_gem_obj_bound(struct drm_i915_gem_object *o,
2240 struct i915_address_space *vm);
2241 unsigned long i915_gem_obj_size(struct drm_i915_gem_object *o,
2242 struct i915_address_space *vm);
2243 struct i915_vma *i915_gem_obj_to_vma(struct drm_i915_gem_object *obj,
2244 struct i915_address_space *vm);
2245 struct i915_vma *
2246 i915_gem_obj_lookup_or_create_vma(struct drm_i915_gem_object *obj,
2247 struct i915_address_space *vm);
2248
2249 struct i915_vma *i915_gem_obj_to_ggtt(struct drm_i915_gem_object *obj);
2250 static inline bool i915_gem_obj_is_pinned(struct drm_i915_gem_object *obj) {
2251 struct i915_vma *vma;
2252 list_for_each_entry(vma, &obj->vma_list, vma_link)
2253 if (vma->pin_count > 0)
2254 return true;
2255 return false;
2256 }
2257
2258 /* Some GGTT VM helpers */
2259 #define obj_to_ggtt(obj) \
2260 (&((struct drm_i915_private *)(obj)->base.dev->dev_private)->gtt.base)
2261 static inline bool i915_is_ggtt(struct i915_address_space *vm)
2262 {
2263 struct i915_address_space *ggtt =
2264 &((struct drm_i915_private *)(vm)->dev->dev_private)->gtt.base;
2265 return vm == ggtt;
2266 }
2267
2268 static inline bool i915_gem_obj_ggtt_bound(struct drm_i915_gem_object *obj)
2269 {
2270 return i915_gem_obj_bound(obj, obj_to_ggtt(obj));
2271 }
2272
2273 static inline unsigned long
2274 i915_gem_obj_ggtt_offset(struct drm_i915_gem_object *obj)
2275 {
2276 return i915_gem_obj_offset(obj, obj_to_ggtt(obj));
2277 }
2278
2279 static inline unsigned long
2280 i915_gem_obj_ggtt_size(struct drm_i915_gem_object *obj)
2281 {
2282 return i915_gem_obj_size(obj, obj_to_ggtt(obj));
2283 }
2284
2285 static inline int __must_check
2286 i915_gem_obj_ggtt_pin(struct drm_i915_gem_object *obj,
2287 uint32_t alignment,
2288 unsigned flags)
2289 {
2290 return i915_gem_object_pin(obj, obj_to_ggtt(obj), alignment, flags | PIN_GLOBAL);
2291 }
2292
2293 static inline int
2294 i915_gem_object_ggtt_unbind(struct drm_i915_gem_object *obj)
2295 {
2296 return i915_vma_unbind(i915_gem_obj_to_ggtt(obj));
2297 }
2298
2299 void i915_gem_object_ggtt_unpin(struct drm_i915_gem_object *obj);
2300
2301 /* i915_gem_context.c */
2302 #define ctx_to_ppgtt(ctx) container_of((ctx)->vm, struct i915_hw_ppgtt, base)
2303 int __must_check i915_gem_context_init(struct drm_device *dev);
2304 void i915_gem_context_fini(struct drm_device *dev);
2305 void i915_gem_context_reset(struct drm_device *dev);
2306 int i915_gem_context_open(struct drm_device *dev, struct drm_file *file);
2307 int i915_gem_context_enable(struct drm_i915_private *dev_priv);
2308 void i915_gem_context_close(struct drm_device *dev, struct drm_file *file);
2309 int i915_switch_context(struct intel_ring_buffer *ring,
2310 struct i915_hw_context *to);
2311 struct i915_hw_context *
2312 i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
2313 void i915_gem_context_free(struct kref *ctx_ref);
2314 static inline void i915_gem_context_reference(struct i915_hw_context *ctx)
2315 {
2316 kref_get(&ctx->ref);
2317 }
2318
2319 static inline void i915_gem_context_unreference(struct i915_hw_context *ctx)
2320 {
2321 kref_put(&ctx->ref, i915_gem_context_free);
2322 }
2323
2324 static inline bool i915_gem_context_is_default(const struct i915_hw_context *c)
2325 {
2326 return c->id == DEFAULT_CONTEXT_ID;
2327 }
2328
2329 int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
2330 struct drm_file *file);
2331 int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
2332 struct drm_file *file);
2333
2334 /* i915_gem_evict.c */
2335 int __must_check i915_gem_evict_something(struct drm_device *dev,
2336 struct i915_address_space *vm,
2337 int min_size,
2338 unsigned alignment,
2339 unsigned cache_level,
2340 unsigned flags);
2341 int i915_gem_evict_vm(struct i915_address_space *vm, bool do_idle);
2342 int i915_gem_evict_everything(struct drm_device *dev);
2343
2344 /* belongs in i915_gem_gtt.h */
2345 static inline void i915_gem_chipset_flush(struct drm_device *dev)
2346 {
2347 if (INTEL_INFO(dev)->gen < 6)
2348 intel_gtt_chipset_flush();
2349 }
2350
2351 /* i915_gem_stolen.c */
2352 int i915_gem_init_stolen(struct drm_device *dev);
2353 int i915_gem_stolen_setup_compression(struct drm_device *dev, int size);
2354 void i915_gem_stolen_cleanup_compression(struct drm_device *dev);
2355 void i915_gem_cleanup_stolen(struct drm_device *dev);
2356 struct drm_i915_gem_object *
2357 i915_gem_object_create_stolen(struct drm_device *dev, u32 size);
2358 struct drm_i915_gem_object *
2359 i915_gem_object_create_stolen_for_preallocated(struct drm_device *dev,
2360 u32 stolen_offset,
2361 u32 gtt_offset,
2362 u32 size);
2363 void i915_gem_object_release_stolen(struct drm_i915_gem_object *obj);
2364
2365 /* i915_gem_tiling.c */
2366 static inline bool i915_gem_object_needs_bit17_swizzle(struct drm_i915_gem_object *obj)
2367 {
2368 struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2369
2370 return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 &&
2371 obj->tiling_mode != I915_TILING_NONE;
2372 }
2373
2374 void i915_gem_detect_bit_6_swizzle(struct drm_device *dev);
2375 void i915_gem_object_do_bit_17_swizzle(struct drm_i915_gem_object *obj);
2376 void i915_gem_object_save_bit_17_swizzle(struct drm_i915_gem_object *obj);
2377
2378 /* i915_gem_debug.c */
2379 #if WATCH_LISTS
2380 int i915_verify_lists(struct drm_device *dev);
2381 #else
2382 #define i915_verify_lists(dev) 0
2383 #endif
2384
2385 /* i915_debugfs.c */
2386 int i915_debugfs_init(struct drm_minor *minor);
2387 void i915_debugfs_cleanup(struct drm_minor *minor);
2388 #ifdef CONFIG_DEBUG_FS
2389 void intel_display_crc_init(struct drm_device *dev);
2390 #else
2391 static inline void intel_display_crc_init(struct drm_device *dev) {}
2392 #endif
2393
2394 /* i915_gpu_error.c */
2395 __printf(2, 3)
2396 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
2397 int i915_error_state_to_str(struct drm_i915_error_state_buf *estr,
2398 const struct i915_error_state_file_priv *error);
2399 int i915_error_state_buf_init(struct drm_i915_error_state_buf *eb,
2400 size_t count, loff_t pos);
2401 static inline void i915_error_state_buf_release(
2402 struct drm_i915_error_state_buf *eb)
2403 {
2404 kfree(eb->buf);
2405 }
2406 void i915_capture_error_state(struct drm_device *dev, bool wedge,
2407 const char *error_msg);
2408 void i915_error_state_get(struct drm_device *dev,
2409 struct i915_error_state_file_priv *error_priv);
2410 void i915_error_state_put(struct i915_error_state_file_priv *error_priv);
2411 void i915_destroy_error_state(struct drm_device *dev);
2412
2413 void i915_get_extra_instdone(struct drm_device *dev, uint32_t *instdone);
2414 const char *i915_cache_level_str(int type);
2415
2416 /* i915_cmd_parser.c */
2417 int i915_cmd_parser_get_version(void);
2418 void i915_cmd_parser_init_ring(struct intel_ring_buffer *ring);
2419 bool i915_needs_cmd_parser(struct intel_ring_buffer *ring);
2420 int i915_parse_cmds(struct intel_ring_buffer *ring,
2421 struct drm_i915_gem_object *batch_obj,
2422 u32 batch_start_offset,
2423 bool is_master);
2424
2425 /* i915_suspend.c */
2426 extern int i915_save_state(struct drm_device *dev);
2427 extern int i915_restore_state(struct drm_device *dev);
2428
2429 /* i915_ums.c */
2430 void i915_save_display_reg(struct drm_device *dev);
2431 void i915_restore_display_reg(struct drm_device *dev);
2432
2433 /* i915_sysfs.c */
2434 void i915_setup_sysfs(struct drm_device *dev_priv);
2435 void i915_teardown_sysfs(struct drm_device *dev_priv);
2436
2437 /* intel_i2c.c */
2438 extern int intel_setup_gmbus(struct drm_device *dev);
2439 extern void intel_teardown_gmbus(struct drm_device *dev);
2440 static inline bool intel_gmbus_is_port_valid(unsigned port)
2441 {
2442 return (port >= GMBUS_PORT_SSC && port <= GMBUS_PORT_DPD);
2443 }
2444
2445 extern struct i2c_adapter *intel_gmbus_get_adapter(
2446 struct drm_i915_private *dev_priv, unsigned port);
2447 extern void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
2448 extern void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
2449 static inline bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
2450 {
2451 return container_of(adapter, struct intel_gmbus, adapter)->force_bit;
2452 }
2453 extern void intel_i2c_reset(struct drm_device *dev);
2454
2455 /* intel_opregion.c */
2456 struct intel_encoder;
2457 #ifdef CONFIG_ACPI
2458 extern int intel_opregion_setup(struct drm_device *dev);
2459 extern void intel_opregion_init(struct drm_device *dev);
2460 extern void intel_opregion_fini(struct drm_device *dev);
2461 extern void intel_opregion_asle_intr(struct drm_device *dev);
2462 extern int intel_opregion_notify_encoder(struct intel_encoder *intel_encoder,
2463 bool enable);
2464 extern int intel_opregion_notify_adapter(struct drm_device *dev,
2465 pci_power_t state);
2466 #else
2467 static inline int intel_opregion_setup(struct drm_device *dev) { return 0; }
2468 static inline void intel_opregion_init(struct drm_device *dev) { return; }
2469 static inline void intel_opregion_fini(struct drm_device *dev) { return; }
2470 static inline void intel_opregion_asle_intr(struct drm_device *dev) { return; }
2471 static inline int
2472 intel_opregion_notify_encoder(struct intel_encoder *intel_encoder, bool enable)
2473 {
2474 return 0;
2475 }
2476 static inline int
2477 intel_opregion_notify_adapter(struct drm_device *dev, pci_power_t state)
2478 {
2479 return 0;
2480 }
2481 #endif
2482
2483 /* intel_acpi.c */
2484 #ifdef CONFIG_ACPI
2485 extern void intel_register_dsm_handler(void);
2486 extern void intel_unregister_dsm_handler(void);
2487 #else
2488 static inline void intel_register_dsm_handler(void) { return; }
2489 static inline void intel_unregister_dsm_handler(void) { return; }
2490 #endif /* CONFIG_ACPI */
2491
2492 /* modesetting */
2493 extern void intel_modeset_init_hw(struct drm_device *dev);
2494 extern void intel_modeset_suspend_hw(struct drm_device *dev);
2495 extern void intel_modeset_init(struct drm_device *dev);
2496 extern void intel_modeset_gem_init(struct drm_device *dev);
2497 extern void intel_modeset_cleanup(struct drm_device *dev);
2498 extern void intel_connector_unregister(struct intel_connector *);
2499 extern int intel_modeset_vga_set_state(struct drm_device *dev, bool state);
2500 extern void intel_modeset_setup_hw_state(struct drm_device *dev,
2501 bool force_restore);
2502 extern void i915_redisable_vga(struct drm_device *dev);
2503 extern void i915_redisable_vga_power_on(struct drm_device *dev);
2504 extern bool intel_fbc_enabled(struct drm_device *dev);
2505 extern void intel_disable_fbc(struct drm_device *dev);
2506 extern bool ironlake_set_drps(struct drm_device *dev, u8 val);
2507 extern void intel_init_pch_refclk(struct drm_device *dev);
2508 extern void gen6_set_rps(struct drm_device *dev, u8 val);
2509 extern void valleyview_set_rps(struct drm_device *dev, u8 val);
2510 extern int valleyview_rps_max_freq(struct drm_i915_private *dev_priv);
2511 extern int valleyview_rps_min_freq(struct drm_i915_private *dev_priv);
2512 extern void intel_detect_pch(struct drm_device *dev);
2513 extern int intel_trans_dp_port_sel(struct drm_crtc *crtc);
2514 extern int intel_enable_rc6(const struct drm_device *dev);
2515
2516 extern bool i915_semaphore_is_enabled(struct drm_device *dev);
2517 int i915_reg_read_ioctl(struct drm_device *dev, void *data,
2518 struct drm_file *file);
2519 int i915_get_reset_stats_ioctl(struct drm_device *dev, void *data,
2520 struct drm_file *file);
2521
2522 /* overlay */
2523 extern struct intel_overlay_error_state *intel_overlay_capture_error_state(struct drm_device *dev);
2524 extern void intel_overlay_print_error_state(struct drm_i915_error_state_buf *e,
2525 struct intel_overlay_error_state *error);
2526
2527 extern struct intel_display_error_state *intel_display_capture_error_state(struct drm_device *dev);
2528 extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
2529 struct drm_device *dev,
2530 struct intel_display_error_state *error);
2531
2532 /* On SNB platform, before reading ring registers forcewake bit
2533 * must be set to prevent GT core from power down and stale values being
2534 * returned.
2535 */
2536 void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
2537 void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
2538 void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
2539
2540 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val);
2541 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val);
2542
2543 /* intel_sideband.c */
2544 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
2545 void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val);
2546 u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
2547 u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg);
2548 void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2549 u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
2550 void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2551 u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
2552 void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2553 u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
2554 void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2555 u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg);
2556 void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2557 u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
2558 void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
2559 u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
2560 enum intel_sbi_destination destination);
2561 void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
2562 enum intel_sbi_destination destination);
2563 u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
2564 void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
2565
2566 int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val);
2567 int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val);
2568
2569 #define FORCEWAKE_RENDER (1 << 0)
2570 #define FORCEWAKE_MEDIA (1 << 1)
2571 #define FORCEWAKE_ALL (FORCEWAKE_RENDER | FORCEWAKE_MEDIA)
2572
2573
2574 #define I915_READ8(reg) dev_priv->uncore.funcs.mmio_readb(dev_priv, (reg), true)
2575 #define I915_WRITE8(reg, val) dev_priv->uncore.funcs.mmio_writeb(dev_priv, (reg), (val), true)
2576
2577 #define I915_READ16(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), true)
2578 #define I915_WRITE16(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), true)
2579 #define I915_READ16_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readw(dev_priv, (reg), false)
2580 #define I915_WRITE16_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writew(dev_priv, (reg), (val), false)
2581
2582 #define I915_READ(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), true)
2583 #define I915_WRITE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), true)
2584 #define I915_READ_NOTRACE(reg) dev_priv->uncore.funcs.mmio_readl(dev_priv, (reg), false)
2585 #define I915_WRITE_NOTRACE(reg, val) dev_priv->uncore.funcs.mmio_writel(dev_priv, (reg), (val), false)
2586
2587 /* Be very careful with read/write 64-bit values. On 32-bit machines, they
2588 * will be implemented using 2 32-bit writes in an arbitrary order with
2589 * an arbitrary delay between them. This can cause the hardware to
2590 * act upon the intermediate value, possibly leading to corruption and
2591 * machine death. You have been warned.
2592 */
2593 #define I915_WRITE64(reg, val) dev_priv->uncore.funcs.mmio_writeq(dev_priv, (reg), (val), true)
2594 #define I915_READ64(reg) dev_priv->uncore.funcs.mmio_readq(dev_priv, (reg), true)
2595
2596 #define I915_READ64_2x32(lower_reg, upper_reg) ({ \
2597 u32 upper = I915_READ(upper_reg); \
2598 u32 lower = I915_READ(lower_reg); \
2599 u32 tmp = I915_READ(upper_reg); \
2600 if (upper != tmp) { \
2601 upper = tmp; \
2602 lower = I915_READ(lower_reg); \
2603 WARN_ON(I915_READ(upper_reg) != upper); \
2604 } \
2605 (u64)upper << 32 | lower; })
2606
2607 #define POSTING_READ(reg) (void)I915_READ_NOTRACE(reg)
2608 #define POSTING_READ16(reg) (void)I915_READ16_NOTRACE(reg)
2609
2610 /* "Broadcast RGB" property */
2611 #define INTEL_BROADCAST_RGB_AUTO 0
2612 #define INTEL_BROADCAST_RGB_FULL 1
2613 #define INTEL_BROADCAST_RGB_LIMITED 2
2614
2615 static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
2616 {
2617 if (HAS_PCH_SPLIT(dev))
2618 return CPU_VGACNTRL;
2619 else if (IS_VALLEYVIEW(dev))
2620 return VLV_VGACNTRL;
2621 else
2622 return VGACNTRL;
2623 }
2624
2625 static inline void __user *to_user_ptr(u64 address)
2626 {
2627 return (void __user *)(uintptr_t)address;
2628 }
2629
2630 static inline unsigned long msecs_to_jiffies_timeout(const unsigned int m)
2631 {
2632 unsigned long j = msecs_to_jiffies(m);
2633
2634 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2635 }
2636
2637 static inline unsigned long
2638 timespec_to_jiffies_timeout(const struct timespec *value)
2639 {
2640 unsigned long j = timespec_to_jiffies(value);
2641
2642 return min_t(unsigned long, MAX_JIFFY_OFFSET, j + 1);
2643 }
2644
2645 /*
2646 * If you need to wait X milliseconds between events A and B, but event B
2647 * doesn't happen exactly after event A, you record the timestamp (jiffies) of
2648 * when event A happened, then just before event B you call this function and
2649 * pass the timestamp as the first argument, and X as the second argument.
2650 */
2651 static inline void
2652 wait_remaining_ms_from_jiffies(unsigned long timestamp_jiffies, int to_wait_ms)
2653 {
2654 unsigned long target_jiffies, tmp_jiffies, remaining_jiffies;
2655
2656 /*
2657 * Don't re-read the value of "jiffies" every time since it may change
2658 * behind our back and break the math.
2659 */
2660 tmp_jiffies = jiffies;
2661 target_jiffies = timestamp_jiffies +
2662 msecs_to_jiffies_timeout(to_wait_ms);
2663
2664 if (time_after(target_jiffies, tmp_jiffies)) {
2665 remaining_jiffies = target_jiffies - tmp_jiffies;
2666 while (remaining_jiffies)
2667 remaining_jiffies =
2668 schedule_timeout_uninterruptible(remaining_jiffies);
2669 }
2670 }
2671
2672 #endif
Linux kernel - Deliverables
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